HexagonSubtarget.h revision 344779 
1//===- HexagonSubtarget.h - Define Subtarget for the Hexagon ----*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file declares the Hexagon specific subclass of TargetSubtarget.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef LLVM_LIB_TARGET_HEXAGON_HEXAGONSUBTARGET_H
15#define LLVM_LIB_TARGET_HEXAGON_HEXAGONSUBTARGET_H
16
17#include "HexagonDepArch.h"
18#include "HexagonFrameLowering.h"
19#include "HexagonISelLowering.h"
20#include "HexagonInstrInfo.h"
21#include "HexagonRegisterInfo.h"
22#include "HexagonSelectionDAGInfo.h"
23#include "llvm/ADT/SmallSet.h"
24#include "llvm/ADT/StringRef.h"
25#include "llvm/CodeGen/ScheduleDAGMutation.h"
26#include "llvm/CodeGen/TargetSubtargetInfo.h"
27#include "llvm/MC/MCInstrItineraries.h"
28#include <memory>
29#include <string>
30#include <vector>
31
32#define GET_SUBTARGETINFO_HEADER
33#include "HexagonGenSubtargetInfo.inc"
34
35namespace llvm {
36
37class MachineInstr;
38class SDep;
39class SUnit;
40class TargetMachine;
41class Triple;
42
43class HexagonSubtarget : public HexagonGenSubtargetInfo {
44  virtual void anchor();
45
46  bool UseHVX64BOps = false;
47  bool UseHVX128BOps = false;
48
49  bool UseLongCalls = false;
50  bool UseMemops = false;
51  bool UsePackets = false;
52  bool UseNewValueJumps = false;
53  bool UseNewValueStores = false;
54  bool UseSmallData = false;
55  bool UseZRegOps = false;
56
57  bool HasMemNoShuf = false;
58  bool EnableDuplex = false;
59  bool ReservedR19 = false;
60  bool NoreturnStackElim = false;
61
62public:
63  Hexagon::ArchEnum HexagonArchVersion;
64  Hexagon::ArchEnum HexagonHVXVersion = Hexagon::ArchEnum::NoArch;
65  CodeGenOpt::Level OptLevel;
66  /// True if the target should use Back-Skip-Back scheduling. This is the
67  /// default for V60.
68  bool UseBSBScheduling;
69
70  struct UsrOverflowMutation : public ScheduleDAGMutation {
71    void apply(ScheduleDAGInstrs *DAG) override;
72  };
73  struct HVXMemLatencyMutation : public ScheduleDAGMutation {
74    void apply(ScheduleDAGInstrs *DAG) override;
75  };
76  struct CallMutation : public ScheduleDAGMutation {
77    void apply(ScheduleDAGInstrs *DAG) override;
78  private:
79    bool shouldTFRICallBind(const HexagonInstrInfo &HII,
80          const SUnit &Inst1, const SUnit &Inst2) const;
81  };
82  struct BankConflictMutation : public ScheduleDAGMutation {
83    void apply(ScheduleDAGInstrs *DAG) override;
84  };
85
86private:
87  std::string CPUString;
88  HexagonInstrInfo InstrInfo;
89  HexagonRegisterInfo RegInfo;
90  HexagonTargetLowering TLInfo;
91  HexagonSelectionDAGInfo TSInfo;
92  HexagonFrameLowering FrameLowering;
93  InstrItineraryData InstrItins;
94
95public:
96  HexagonSubtarget(const Triple &TT, StringRef CPU, StringRef FS,
97                   const TargetMachine &TM);
98
99  /// getInstrItins - Return the instruction itineraries based on subtarget
100  /// selection.
101  const InstrItineraryData *getInstrItineraryData() const override {
102    return &InstrItins;
103  }
104  const HexagonInstrInfo *getInstrInfo() const override { return &InstrInfo; }
105  const HexagonRegisterInfo *getRegisterInfo() const override {
106    return &RegInfo;
107  }
108  const HexagonTargetLowering *getTargetLowering() const override {
109    return &TLInfo;
110  }
111  const HexagonFrameLowering *getFrameLowering() const override {
112    return &FrameLowering;
113  }
114  const HexagonSelectionDAGInfo *getSelectionDAGInfo() const override {
115    return &TSInfo;
116  }
117
118  HexagonSubtarget &initializeSubtargetDependencies(StringRef CPU,
119                                                    StringRef FS);
120
121  /// ParseSubtargetFeatures - Parses features string setting specified
122  /// subtarget options.  Definition of function is auto generated by tblgen.
123  void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
124
125  bool hasV5Ops() const {
126    return getHexagonArchVersion() >= Hexagon::ArchEnum::V5;
127  }
128  bool hasV5OpsOnly() const {
129    return getHexagonArchVersion() == Hexagon::ArchEnum::V5;
130  }
131  bool hasV55Ops() const {
132    return getHexagonArchVersion() >= Hexagon::ArchEnum::V55;
133  }
134  bool hasV55OpsOnly() const {
135    return getHexagonArchVersion() == Hexagon::ArchEnum::V55;
136  }
137  bool hasV60Ops() const {
138    return getHexagonArchVersion() >= Hexagon::ArchEnum::V60;
139  }
140  bool hasV60OpsOnly() const {
141    return getHexagonArchVersion() == Hexagon::ArchEnum::V60;
142  }
143  bool hasV62Ops() const {
144    return getHexagonArchVersion() >= Hexagon::ArchEnum::V62;
145  }
146  bool hasV62OpsOnly() const {
147    return getHexagonArchVersion() == Hexagon::ArchEnum::V62;
148  }
149  bool hasV65Ops() const {
150    return getHexagonArchVersion() >= Hexagon::ArchEnum::V65;
151  }
152  bool hasV65OpsOnly() const {
153    return getHexagonArchVersion() == Hexagon::ArchEnum::V65;
154  }
155  bool hasV66Ops() const {
156    return getHexagonArchVersion() >= Hexagon::ArchEnum::V66;
157  }
158  bool hasV66OpsOnly() const {
159    return getHexagonArchVersion() == Hexagon::ArchEnum::V66;
160  }
161
162  bool useLongCalls() const { return UseLongCalls; }
163  bool useMemops() const { return UseMemops; }
164  bool usePackets() const { return UsePackets; }
165  bool useNewValueJumps() const { return UseNewValueJumps; }
166  bool useNewValueStores() const { return UseNewValueStores; }
167  bool useSmallData() const { return UseSmallData; }
168  bool useZRegOps() const { return UseZRegOps; }
169
170  bool useHVXOps() const {
171    return HexagonHVXVersion > Hexagon::ArchEnum::NoArch;
172  }
173  bool useHVX128BOps() const { return useHVXOps() && UseHVX128BOps; }
174  bool useHVX64BOps() const { return useHVXOps() && UseHVX64BOps; }
175
176  bool hasMemNoShuf() const { return HasMemNoShuf; }
177  bool hasReservedR19() const { return ReservedR19; }
178  bool usePredicatedCalls() const;
179
180  bool noreturnStackElim() const { return NoreturnStackElim; }
181
182  bool useBSBScheduling() const { return UseBSBScheduling; }
183  bool enableMachineScheduler() const override;
184
185  // Always use the TargetLowering default scheduler.
186  // FIXME: This will use the vliw scheduler which is probably just hurting
187  // compiler time and will be removed eventually anyway.
188  bool enableMachineSchedDefaultSched() const override { return false; }
189
190  AntiDepBreakMode getAntiDepBreakMode() const override { return ANTIDEP_ALL; }
191  bool enablePostRAScheduler() const override { return true; }
192
193  bool enableSubRegLiveness() const override;
194
195  const std::string &getCPUString () const { return CPUString; }
196
197  const Hexagon::ArchEnum &getHexagonArchVersion() const {
198    return HexagonArchVersion;
199  }
200
201  void getPostRAMutations(
202      std::vector<std::unique_ptr<ScheduleDAGMutation>> &Mutations)
203      const override;
204
205  void getSMSMutations(
206      std::vector<std::unique_ptr<ScheduleDAGMutation>> &Mutations)
207      const override;
208
209  /// Enable use of alias analysis during code generation (during MI
210  /// scheduling, DAGCombine, etc.).
211  bool useAA() const override;
212
213  /// Perform target specific adjustments to the latency of a schedule
214  /// dependency.
215  void adjustSchedDependency(SUnit *def, SUnit *use, SDep& dep) const override;
216
217  unsigned getVectorLength() const {
218    assert(useHVXOps());
219    if (useHVX64BOps())
220      return 64;
221    if (useHVX128BOps())
222      return 128;
223    llvm_unreachable("Invalid HVX vector length settings");
224  }
225
226  ArrayRef<MVT> getHVXElementTypes() const {
227    static MVT Types[] = { MVT::i8, MVT::i16, MVT::i32 };
228    return makeArrayRef(Types);
229  }
230
231  bool isHVXVectorType(MVT VecTy, bool IncludeBool = false) const {
232    if (!VecTy.isVector() || !useHVXOps())
233      return false;
234    MVT ElemTy = VecTy.getVectorElementType();
235    if (!IncludeBool && ElemTy == MVT::i1)
236      return false;
237
238    unsigned HwLen = getVectorLength();
239    unsigned NumElems = VecTy.getVectorNumElements();
240    ArrayRef<MVT> ElemTypes = getHVXElementTypes();
241
242    if (IncludeBool && ElemTy == MVT::i1) {
243      // Special case for the v512i1, etc.
244      if (8*HwLen == NumElems)
245        return true;
246      // Boolean HVX vector types are formed from regular HVX vector types
247      // by replacing the element type with i1.
248      for (MVT T : ElemTypes)
249        if (NumElems * T.getSizeInBits() == 8*HwLen)
250          return true;
251      return false;
252    }
253
254    unsigned VecWidth = VecTy.getSizeInBits();
255    if (VecWidth != 8*HwLen && VecWidth != 16*HwLen)
256      return false;
257    return llvm::any_of(ElemTypes, [ElemTy] (MVT T) { return ElemTy == T; });
258  }
259
260  unsigned getTypeAlignment(MVT Ty) const {
261    if (isHVXVectorType(Ty, true))
262      return getVectorLength();
263    return Ty.getSizeInBits() / 8;
264  }
265
266  unsigned getL1CacheLineSize() const;
267  unsigned getL1PrefetchDistance() const;
268
269private:
270  // Helper function responsible for increasing the latency only.
271  void updateLatency(MachineInstr &SrcInst, MachineInstr &DstInst, SDep &Dep)
272      const;
273  void restoreLatency(SUnit *Src, SUnit *Dst) const;
274  void changeLatency(SUnit *Src, SUnit *Dst, unsigned Lat) const;
275  bool isBestZeroLatency(SUnit *Src, SUnit *Dst, const HexagonInstrInfo *TII,
276      SmallSet<SUnit*, 4> &ExclSrc, SmallSet<SUnit*, 4> &ExclDst) const;
277};
278
279} // end namespace llvm
280
281#endif // LLVM_LIB_TARGET_HEXAGON_HEXAGONSUBTARGET_H
282