HexagonNewValueJump.cpp revision 327952
1//===- HexagonNewValueJump.cpp - Hexagon Backend New Value Jump -----------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This implements NewValueJump pass in Hexagon. 11// Ideally, we should merge this as a Peephole pass prior to register 12// allocation, but because we have a spill in between the feeder and new value 13// jump instructions, we are forced to write after register allocation. 14// Having said that, we should re-attempt to pull this earlier at some point 15// in future. 16 17// The basic approach looks for sequence of predicated jump, compare instruciton 18// that genereates the predicate and, the feeder to the predicate. Once it finds 19// all, it collapses compare and jump instruction into a new valu jump 20// intstructions. 21// 22//===----------------------------------------------------------------------===// 23 24#include "Hexagon.h" 25#include "HexagonInstrInfo.h" 26#include "HexagonRegisterInfo.h" 27#include "llvm/ADT/Statistic.h" 28#include "llvm/CodeGen/MachineBasicBlock.h" 29#include "llvm/CodeGen/MachineBranchProbabilityInfo.h" 30#include "llvm/CodeGen/MachineFunction.h" 31#include "llvm/CodeGen/MachineFunctionPass.h" 32#include "llvm/CodeGen/MachineInstr.h" 33#include "llvm/CodeGen/MachineInstrBuilder.h" 34#include "llvm/CodeGen/MachineOperand.h" 35#include "llvm/CodeGen/MachineRegisterInfo.h" 36#include "llvm/CodeGen/TargetOpcodes.h" 37#include "llvm/CodeGen/TargetRegisterInfo.h" 38#include "llvm/CodeGen/TargetSubtargetInfo.h" 39#include "llvm/IR/DebugLoc.h" 40#include "llvm/MC/MCInstrDesc.h" 41#include "llvm/Pass.h" 42#include "llvm/Support/BranchProbability.h" 43#include "llvm/Support/CommandLine.h" 44#include "llvm/Support/Debug.h" 45#include "llvm/Support/ErrorHandling.h" 46#include "llvm/Support/MathExtras.h" 47#include "llvm/Support/raw_ostream.h" 48#include <cassert> 49#include <cstdint> 50#include <iterator> 51 52using namespace llvm; 53 54#define DEBUG_TYPE "hexagon-nvj" 55 56STATISTIC(NumNVJGenerated, "Number of New Value Jump Instructions created"); 57 58static cl::opt<int> DbgNVJCount("nvj-count", cl::init(-1), cl::Hidden, 59 cl::desc("Maximum number of predicated jumps to be converted to " 60 "New Value Jump")); 61 62static cl::opt<bool> DisableNewValueJumps("disable-nvjump", cl::Hidden, 63 cl::ZeroOrMore, cl::init(false), 64 cl::desc("Disable New Value Jumps")); 65 66namespace llvm { 67 68FunctionPass *createHexagonNewValueJump(); 69void initializeHexagonNewValueJumpPass(PassRegistry&); 70 71} // end namespace llvm 72 73namespace { 74 75 struct HexagonNewValueJump : public MachineFunctionPass { 76 static char ID; 77 78 HexagonNewValueJump() : MachineFunctionPass(ID) {} 79 80 void getAnalysisUsage(AnalysisUsage &AU) const override { 81 AU.addRequired<MachineBranchProbabilityInfo>(); 82 MachineFunctionPass::getAnalysisUsage(AU); 83 } 84 85 StringRef getPassName() const override { return "Hexagon NewValueJump"; } 86 87 bool runOnMachineFunction(MachineFunction &Fn) override; 88 89 MachineFunctionProperties getRequiredProperties() const override { 90 return MachineFunctionProperties().set( 91 MachineFunctionProperties::Property::NoVRegs); 92 } 93 94 private: 95 const HexagonInstrInfo *QII; 96 const HexagonRegisterInfo *QRI; 97 98 /// \brief A handle to the branch probability pass. 99 const MachineBranchProbabilityInfo *MBPI; 100 101 bool isNewValueJumpCandidate(const MachineInstr &MI) const; 102 }; 103 104} // end anonymous namespace 105 106char HexagonNewValueJump::ID = 0; 107 108INITIALIZE_PASS_BEGIN(HexagonNewValueJump, "hexagon-nvj", 109 "Hexagon NewValueJump", false, false) 110INITIALIZE_PASS_DEPENDENCY(MachineBranchProbabilityInfo) 111INITIALIZE_PASS_END(HexagonNewValueJump, "hexagon-nvj", 112 "Hexagon NewValueJump", false, false) 113 114// We have identified this II could be feeder to NVJ, 115// verify that it can be. 116static bool canBeFeederToNewValueJump(const HexagonInstrInfo *QII, 117 const TargetRegisterInfo *TRI, 118 MachineBasicBlock::iterator II, 119 MachineBasicBlock::iterator end, 120 MachineBasicBlock::iterator skip, 121 MachineFunction &MF) { 122 // Predicated instruction can not be feeder to NVJ. 123 if (QII->isPredicated(*II)) 124 return false; 125 126 // Bail out if feederReg is a paired register (double regs in 127 // our case). One would think that we can check to see if a given 128 // register cmpReg1 or cmpReg2 is a sub register of feederReg 129 // using -- if (QRI->isSubRegister(feederReg, cmpReg1) logic 130 // before the callsite of this function 131 // But we can not as it comes in the following fashion. 132 // %d0 = Hexagon_S2_lsr_r_p killed %d0, killed %r2 133 // %r0 = KILL %r0, implicit killed %d0 134 // %p0 = CMPEQri killed %r0, 0 135 // Hence, we need to check if it's a KILL instruction. 136 if (II->getOpcode() == TargetOpcode::KILL) 137 return false; 138 139 if (II->isImplicitDef()) 140 return false; 141 142 if (QII->isSolo(*II)) 143 return false; 144 145 // Make sure there there is no 'def' or 'use' of any of the uses of 146 // feeder insn between it's definition, this MI and jump, jmpInst 147 // skipping compare, cmpInst. 148 // Here's the example. 149 // r21=memub(r22+r24<<#0) 150 // p0 = cmp.eq(r21, #0) 151 // r4=memub(r3+r21<<#0) 152 // if (p0.new) jump:t .LBB29_45 153 // Without this check, it will be converted into 154 // r4=memub(r3+r21<<#0) 155 // r21=memub(r22+r24<<#0) 156 // p0 = cmp.eq(r21, #0) 157 // if (p0.new) jump:t .LBB29_45 158 // and result WAR hazards if converted to New Value Jump. 159 for (unsigned i = 0; i < II->getNumOperands(); ++i) { 160 if (II->getOperand(i).isReg() && 161 (II->getOperand(i).isUse() || II->getOperand(i).isDef())) { 162 MachineBasicBlock::iterator localII = II; 163 ++localII; 164 unsigned Reg = II->getOperand(i).getReg(); 165 for (MachineBasicBlock::iterator localBegin = localII; localBegin != end; 166 ++localBegin) { 167 if (localBegin == skip) 168 continue; 169 // Check for Subregisters too. 170 if (localBegin->modifiesRegister(Reg, TRI) || 171 localBegin->readsRegister(Reg, TRI)) 172 return false; 173 } 174 } 175 } 176 return true; 177} 178 179// These are the common checks that need to performed 180// to determine if 181// 1. compare instruction can be moved before jump. 182// 2. feeder to the compare instruction can be moved before jump. 183static bool commonChecksToProhibitNewValueJump(bool afterRA, 184 MachineBasicBlock::iterator MII) { 185 // If store in path, bail out. 186 if (MII->mayStore()) 187 return false; 188 189 // if call in path, bail out. 190 if (MII->isCall()) 191 return false; 192 193 // if NVJ is running prior to RA, do the following checks. 194 if (!afterRA) { 195 // The following Target Opcode instructions are spurious 196 // to new value jump. If they are in the path, bail out. 197 // KILL sets kill flag on the opcode. It also sets up a 198 // single register, out of pair. 199 // %d0 = S2_lsr_r_p killed %d0, killed %r2 200 // %r0 = KILL %r0, implicit killed %d0 201 // %p0 = C2_cmpeqi killed %r0, 0 202 // PHI can be anything after RA. 203 // COPY can remateriaze things in between feeder, compare and nvj. 204 if (MII->getOpcode() == TargetOpcode::KILL || 205 MII->getOpcode() == TargetOpcode::PHI || 206 MII->getOpcode() == TargetOpcode::COPY) 207 return false; 208 209 // The following pseudo Hexagon instructions sets "use" and "def" 210 // of registers by individual passes in the backend. At this time, 211 // we don't know the scope of usage and definitions of these 212 // instructions. 213 if (MII->getOpcode() == Hexagon::LDriw_pred || 214 MII->getOpcode() == Hexagon::STriw_pred) 215 return false; 216 } 217 218 return true; 219} 220 221static bool canCompareBeNewValueJump(const HexagonInstrInfo *QII, 222 const TargetRegisterInfo *TRI, 223 MachineBasicBlock::iterator II, 224 unsigned pReg, 225 bool secondReg, 226 bool optLocation, 227 MachineBasicBlock::iterator end, 228 MachineFunction &MF) { 229 MachineInstr &MI = *II; 230 231 // If the second operand of the compare is an imm, make sure it's in the 232 // range specified by the arch. 233 if (!secondReg) { 234 const MachineOperand &Op2 = MI.getOperand(2); 235 if (!Op2.isImm()) 236 return false; 237 238 int64_t v = Op2.getImm(); 239 bool Valid = false; 240 241 switch (MI.getOpcode()) { 242 case Hexagon::C2_cmpeqi: 243 case Hexagon::C4_cmpneqi: 244 case Hexagon::C2_cmpgti: 245 case Hexagon::C4_cmpltei: 246 Valid = (isUInt<5>(v) || v == -1); 247 break; 248 case Hexagon::C2_cmpgtui: 249 case Hexagon::C4_cmplteui: 250 Valid = isUInt<5>(v); 251 break; 252 case Hexagon::S2_tstbit_i: 253 case Hexagon::S4_ntstbit_i: 254 Valid = (v == 0); 255 break; 256 } 257 258 if (!Valid) 259 return false; 260 } 261 262 unsigned cmpReg1, cmpOp2 = 0; // cmpOp2 assignment silences compiler warning. 263 cmpReg1 = MI.getOperand(1).getReg(); 264 265 if (secondReg) { 266 cmpOp2 = MI.getOperand(2).getReg(); 267 268 // If the same register appears as both operands, we cannot generate a new 269 // value compare. Only one operand may use the .new suffix. 270 if (cmpReg1 == cmpOp2) 271 return false; 272 273 // Make sure that that second register is not from COPY 274 // At machine code level, we don't need this, but if we decide 275 // to move new value jump prior to RA, we would be needing this. 276 MachineRegisterInfo &MRI = MF.getRegInfo(); 277 if (secondReg && !TargetRegisterInfo::isPhysicalRegister(cmpOp2)) { 278 MachineInstr *def = MRI.getVRegDef(cmpOp2); 279 if (def->getOpcode() == TargetOpcode::COPY) 280 return false; 281 } 282 } 283 284 // Walk the instructions after the compare (predicate def) to the jump, 285 // and satisfy the following conditions. 286 ++II; 287 for (MachineBasicBlock::iterator localII = II; localII != end; ++localII) { 288 if (localII->isDebugValue()) 289 continue; 290 291 // Check 1. 292 // If "common" checks fail, bail out. 293 if (!commonChecksToProhibitNewValueJump(optLocation, localII)) 294 return false; 295 296 // Check 2. 297 // If there is a def or use of predicate (result of compare), bail out. 298 if (localII->modifiesRegister(pReg, TRI) || 299 localII->readsRegister(pReg, TRI)) 300 return false; 301 302 // Check 3. 303 // If there is a def of any of the use of the compare (operands of compare), 304 // bail out. 305 // Eg. 306 // p0 = cmp.eq(r2, r0) 307 // r2 = r4 308 // if (p0.new) jump:t .LBB28_3 309 if (localII->modifiesRegister(cmpReg1, TRI) || 310 (secondReg && localII->modifiesRegister(cmpOp2, TRI))) 311 return false; 312 } 313 return true; 314} 315 316// Given a compare operator, return a matching New Value Jump compare operator. 317// Make sure that MI here is included in isNewValueJumpCandidate. 318static unsigned getNewValueJumpOpcode(MachineInstr *MI, int reg, 319 bool secondRegNewified, 320 MachineBasicBlock *jmpTarget, 321 const MachineBranchProbabilityInfo 322 *MBPI) { 323 bool taken = false; 324 MachineBasicBlock *Src = MI->getParent(); 325 const BranchProbability Prediction = 326 MBPI->getEdgeProbability(Src, jmpTarget); 327 328 if (Prediction >= BranchProbability(1,2)) 329 taken = true; 330 331 switch (MI->getOpcode()) { 332 case Hexagon::C2_cmpeq: 333 return taken ? Hexagon::J4_cmpeq_t_jumpnv_t 334 : Hexagon::J4_cmpeq_t_jumpnv_nt; 335 336 case Hexagon::C2_cmpeqi: 337 if (reg >= 0) 338 return taken ? Hexagon::J4_cmpeqi_t_jumpnv_t 339 : Hexagon::J4_cmpeqi_t_jumpnv_nt; 340 return taken ? Hexagon::J4_cmpeqn1_t_jumpnv_t 341 : Hexagon::J4_cmpeqn1_t_jumpnv_nt; 342 343 case Hexagon::C4_cmpneqi: 344 if (reg >= 0) 345 return taken ? Hexagon::J4_cmpeqi_f_jumpnv_t 346 : Hexagon::J4_cmpeqi_f_jumpnv_nt; 347 return taken ? Hexagon::J4_cmpeqn1_f_jumpnv_t : 348 Hexagon::J4_cmpeqn1_f_jumpnv_nt; 349 350 case Hexagon::C2_cmpgt: 351 if (secondRegNewified) 352 return taken ? Hexagon::J4_cmplt_t_jumpnv_t 353 : Hexagon::J4_cmplt_t_jumpnv_nt; 354 return taken ? Hexagon::J4_cmpgt_t_jumpnv_t 355 : Hexagon::J4_cmpgt_t_jumpnv_nt; 356 357 case Hexagon::C2_cmpgti: 358 if (reg >= 0) 359 return taken ? Hexagon::J4_cmpgti_t_jumpnv_t 360 : Hexagon::J4_cmpgti_t_jumpnv_nt; 361 return taken ? Hexagon::J4_cmpgtn1_t_jumpnv_t 362 : Hexagon::J4_cmpgtn1_t_jumpnv_nt; 363 364 case Hexagon::C2_cmpgtu: 365 if (secondRegNewified) 366 return taken ? Hexagon::J4_cmpltu_t_jumpnv_t 367 : Hexagon::J4_cmpltu_t_jumpnv_nt; 368 return taken ? Hexagon::J4_cmpgtu_t_jumpnv_t 369 : Hexagon::J4_cmpgtu_t_jumpnv_nt; 370 371 case Hexagon::C2_cmpgtui: 372 return taken ? Hexagon::J4_cmpgtui_t_jumpnv_t 373 : Hexagon::J4_cmpgtui_t_jumpnv_nt; 374 375 case Hexagon::C4_cmpneq: 376 return taken ? Hexagon::J4_cmpeq_f_jumpnv_t 377 : Hexagon::J4_cmpeq_f_jumpnv_nt; 378 379 case Hexagon::C4_cmplte: 380 if (secondRegNewified) 381 return taken ? Hexagon::J4_cmplt_f_jumpnv_t 382 : Hexagon::J4_cmplt_f_jumpnv_nt; 383 return taken ? Hexagon::J4_cmpgt_f_jumpnv_t 384 : Hexagon::J4_cmpgt_f_jumpnv_nt; 385 386 case Hexagon::C4_cmplteu: 387 if (secondRegNewified) 388 return taken ? Hexagon::J4_cmpltu_f_jumpnv_t 389 : Hexagon::J4_cmpltu_f_jumpnv_nt; 390 return taken ? Hexagon::J4_cmpgtu_f_jumpnv_t 391 : Hexagon::J4_cmpgtu_f_jumpnv_nt; 392 393 case Hexagon::C4_cmpltei: 394 if (reg >= 0) 395 return taken ? Hexagon::J4_cmpgti_f_jumpnv_t 396 : Hexagon::J4_cmpgti_f_jumpnv_nt; 397 return taken ? Hexagon::J4_cmpgtn1_f_jumpnv_t 398 : Hexagon::J4_cmpgtn1_f_jumpnv_nt; 399 400 case Hexagon::C4_cmplteui: 401 return taken ? Hexagon::J4_cmpgtui_f_jumpnv_t 402 : Hexagon::J4_cmpgtui_f_jumpnv_nt; 403 404 default: 405 llvm_unreachable("Could not find matching New Value Jump instruction."); 406 } 407 // return *some value* to avoid compiler warning 408 return 0; 409} 410 411bool HexagonNewValueJump::isNewValueJumpCandidate( 412 const MachineInstr &MI) const { 413 switch (MI.getOpcode()) { 414 case Hexagon::C2_cmpeq: 415 case Hexagon::C2_cmpeqi: 416 case Hexagon::C2_cmpgt: 417 case Hexagon::C2_cmpgti: 418 case Hexagon::C2_cmpgtu: 419 case Hexagon::C2_cmpgtui: 420 case Hexagon::C4_cmpneq: 421 case Hexagon::C4_cmpneqi: 422 case Hexagon::C4_cmplte: 423 case Hexagon::C4_cmplteu: 424 case Hexagon::C4_cmpltei: 425 case Hexagon::C4_cmplteui: 426 return true; 427 428 default: 429 return false; 430 } 431} 432 433bool HexagonNewValueJump::runOnMachineFunction(MachineFunction &MF) { 434 DEBUG(dbgs() << "********** Hexagon New Value Jump **********\n" 435 << "********** Function: " << MF.getName() << "\n"); 436 437 if (skipFunction(MF.getFunction())) 438 return false; 439 440 // If we move NewValueJump before register allocation we'll need live variable 441 // analysis here too. 442 443 QII = static_cast<const HexagonInstrInfo *>(MF.getSubtarget().getInstrInfo()); 444 QRI = static_cast<const HexagonRegisterInfo *>( 445 MF.getSubtarget().getRegisterInfo()); 446 MBPI = &getAnalysis<MachineBranchProbabilityInfo>(); 447 448 if (DisableNewValueJumps) { 449 return false; 450 } 451 452 int nvjCount = DbgNVJCount; 453 int nvjGenerated = 0; 454 455 // Loop through all the bb's of the function 456 for (MachineFunction::iterator MBBb = MF.begin(), MBBe = MF.end(); 457 MBBb != MBBe; ++MBBb) { 458 MachineBasicBlock *MBB = &*MBBb; 459 460 DEBUG(dbgs() << "** dumping bb ** " << MBB->getNumber() << "\n"); 461 DEBUG(MBB->dump()); 462 DEBUG(dbgs() << "\n" << "********** dumping instr bottom up **********\n"); 463 bool foundJump = false; 464 bool foundCompare = false; 465 bool invertPredicate = false; 466 unsigned predReg = 0; // predicate reg of the jump. 467 unsigned cmpReg1 = 0; 468 int cmpOp2 = 0; 469 MachineBasicBlock::iterator jmpPos; 470 MachineBasicBlock::iterator cmpPos; 471 MachineInstr *cmpInstr = nullptr, *jmpInstr = nullptr; 472 MachineBasicBlock *jmpTarget = nullptr; 473 bool afterRA = false; 474 bool isSecondOpReg = false; 475 bool isSecondOpNewified = false; 476 // Traverse the basic block - bottom up 477 for (MachineBasicBlock::iterator MII = MBB->end(), E = MBB->begin(); 478 MII != E;) { 479 MachineInstr &MI = *--MII; 480 if (MI.isDebugValue()) { 481 continue; 482 } 483 484 if ((nvjCount == 0) || (nvjCount > -1 && nvjCount <= nvjGenerated)) 485 break; 486 487 DEBUG(dbgs() << "Instr: "; MI.dump(); dbgs() << "\n"); 488 489 if (!foundJump && (MI.getOpcode() == Hexagon::J2_jumpt || 490 MI.getOpcode() == Hexagon::J2_jumptpt || 491 MI.getOpcode() == Hexagon::J2_jumpf || 492 MI.getOpcode() == Hexagon::J2_jumpfpt || 493 MI.getOpcode() == Hexagon::J2_jumptnewpt || 494 MI.getOpcode() == Hexagon::J2_jumptnew || 495 MI.getOpcode() == Hexagon::J2_jumpfnewpt || 496 MI.getOpcode() == Hexagon::J2_jumpfnew)) { 497 // This is where you would insert your compare and 498 // instr that feeds compare 499 jmpPos = MII; 500 jmpInstr = &MI; 501 predReg = MI.getOperand(0).getReg(); 502 afterRA = TargetRegisterInfo::isPhysicalRegister(predReg); 503 504 // If ifconverter had not messed up with the kill flags of the 505 // operands, the following check on the kill flag would suffice. 506 // if(!jmpInstr->getOperand(0).isKill()) break; 507 508 // This predicate register is live out out of BB 509 // this would only work if we can actually use Live 510 // variable analysis on phy regs - but LLVM does not 511 // provide LV analysis on phys regs. 512 //if(LVs.isLiveOut(predReg, *MBB)) break; 513 514 // Get all the successors of this block - which will always 515 // be 2. Check if the predicate register is live-in in those 516 // successor. If yes, we can not delete the predicate - 517 // I am doing this only because LLVM does not provide LiveOut 518 // at the BB level. 519 bool predLive = false; 520 for (MachineBasicBlock::const_succ_iterator SI = MBB->succ_begin(), 521 SIE = MBB->succ_end(); 522 SI != SIE; ++SI) { 523 MachineBasicBlock *succMBB = *SI; 524 if (succMBB->isLiveIn(predReg)) 525 predLive = true; 526 } 527 if (predLive) 528 break; 529 530 if (!MI.getOperand(1).isMBB()) 531 continue; 532 jmpTarget = MI.getOperand(1).getMBB(); 533 foundJump = true; 534 if (MI.getOpcode() == Hexagon::J2_jumpf || 535 MI.getOpcode() == Hexagon::J2_jumpfnewpt || 536 MI.getOpcode() == Hexagon::J2_jumpfnew) { 537 invertPredicate = true; 538 } 539 continue; 540 } 541 542 // No new value jump if there is a barrier. A barrier has to be in its 543 // own packet. A barrier has zero operands. We conservatively bail out 544 // here if we see any instruction with zero operands. 545 if (foundJump && MI.getNumOperands() == 0) 546 break; 547 548 if (foundJump && !foundCompare && MI.getOperand(0).isReg() && 549 MI.getOperand(0).getReg() == predReg) { 550 // Not all compares can be new value compare. Arch Spec: 7.6.1.1 551 if (isNewValueJumpCandidate(MI)) { 552 assert( 553 (MI.getDesc().isCompare()) && 554 "Only compare instruction can be collapsed into New Value Jump"); 555 isSecondOpReg = MI.getOperand(2).isReg(); 556 557 if (!canCompareBeNewValueJump(QII, QRI, MII, predReg, isSecondOpReg, 558 afterRA, jmpPos, MF)) 559 break; 560 561 cmpInstr = &MI; 562 cmpPos = MII; 563 foundCompare = true; 564 565 // We need cmpReg1 and cmpOp2(imm or reg) while building 566 // new value jump instruction. 567 cmpReg1 = MI.getOperand(1).getReg(); 568 569 if (isSecondOpReg) 570 cmpOp2 = MI.getOperand(2).getReg(); 571 else 572 cmpOp2 = MI.getOperand(2).getImm(); 573 continue; 574 } 575 } 576 577 if (foundCompare && foundJump) { 578 // If "common" checks fail, bail out on this BB. 579 if (!commonChecksToProhibitNewValueJump(afterRA, MII)) 580 break; 581 582 bool foundFeeder = false; 583 MachineBasicBlock::iterator feederPos = MII; 584 if (MI.getOperand(0).isReg() && MI.getOperand(0).isDef() && 585 (MI.getOperand(0).getReg() == cmpReg1 || 586 (isSecondOpReg && 587 MI.getOperand(0).getReg() == (unsigned)cmpOp2))) { 588 589 unsigned feederReg = MI.getOperand(0).getReg(); 590 591 // First try to see if we can get the feeder from the first operand 592 // of the compare. If we can not, and if secondOpReg is true 593 // (second operand of the compare is also register), try that one. 594 // TODO: Try to come up with some heuristic to figure out which 595 // feeder would benefit. 596 597 if (feederReg == cmpReg1) { 598 if (!canBeFeederToNewValueJump(QII, QRI, MII, jmpPos, cmpPos, MF)) { 599 if (!isSecondOpReg) 600 break; 601 else 602 continue; 603 } else 604 foundFeeder = true; 605 } 606 607 if (!foundFeeder && isSecondOpReg && feederReg == (unsigned)cmpOp2) 608 if (!canBeFeederToNewValueJump(QII, QRI, MII, jmpPos, cmpPos, MF)) 609 break; 610 611 if (isSecondOpReg) { 612 // In case of CMPLT, or CMPLTU, or EQ with the second register 613 // to newify, swap the operands. 614 unsigned COp = cmpInstr->getOpcode(); 615 if ((COp == Hexagon::C2_cmpeq || COp == Hexagon::C4_cmpneq) && 616 (feederReg == (unsigned)cmpOp2)) { 617 unsigned tmp = cmpReg1; 618 cmpReg1 = cmpOp2; 619 cmpOp2 = tmp; 620 } 621 622 // Now we have swapped the operands, all we need to check is, 623 // if the second operand (after swap) is the feeder. 624 // And if it is, make a note. 625 if (feederReg == (unsigned)cmpOp2) 626 isSecondOpNewified = true; 627 } 628 629 // Now that we are moving feeder close the jump, 630 // make sure we are respecting the kill values of 631 // the operands of the feeder. 632 633 auto TransferKills = [jmpPos,cmpPos] (MachineInstr &MI) { 634 for (MachineOperand &MO : MI.operands()) { 635 if (!MO.isReg() || !MO.isUse()) 636 continue; 637 unsigned UseR = MO.getReg(); 638 for (auto I = std::next(MI.getIterator()); I != jmpPos; ++I) { 639 if (I == cmpPos) 640 continue; 641 for (MachineOperand &Op : I->operands()) { 642 if (!Op.isReg() || !Op.isUse() || !Op.isKill()) 643 continue; 644 if (Op.getReg() != UseR) 645 continue; 646 // We found that there is kill of a use register 647 // Set up a kill flag on the register 648 Op.setIsKill(false); 649 MO.setIsKill(true); 650 return; 651 } 652 } 653 } 654 }; 655 656 TransferKills(*feederPos); 657 TransferKills(*cmpPos); 658 bool MO1IsKill = cmpPos->killsRegister(cmpReg1, QRI); 659 bool MO2IsKill = isSecondOpReg && cmpPos->killsRegister(cmpOp2, QRI); 660 661 MBB->splice(jmpPos, MI.getParent(), MI); 662 MBB->splice(jmpPos, MI.getParent(), cmpInstr); 663 DebugLoc dl = MI.getDebugLoc(); 664 MachineInstr *NewMI; 665 666 assert((isNewValueJumpCandidate(*cmpInstr)) && 667 "This compare is not a New Value Jump candidate."); 668 unsigned opc = getNewValueJumpOpcode(cmpInstr, cmpOp2, 669 isSecondOpNewified, 670 jmpTarget, MBPI); 671 if (invertPredicate) 672 opc = QII->getInvertedPredicatedOpcode(opc); 673 674 if (isSecondOpReg) 675 NewMI = BuildMI(*MBB, jmpPos, dl, QII->get(opc)) 676 .addReg(cmpReg1, getKillRegState(MO1IsKill)) 677 .addReg(cmpOp2, getKillRegState(MO2IsKill)) 678 .addMBB(jmpTarget); 679 680 else 681 NewMI = BuildMI(*MBB, jmpPos, dl, QII->get(opc)) 682 .addReg(cmpReg1, getKillRegState(MO1IsKill)) 683 .addImm(cmpOp2) 684 .addMBB(jmpTarget); 685 686 assert(NewMI && "New Value Jump Instruction Not created!"); 687 (void)NewMI; 688 if (cmpInstr->getOperand(0).isReg() && 689 cmpInstr->getOperand(0).isKill()) 690 cmpInstr->getOperand(0).setIsKill(false); 691 if (cmpInstr->getOperand(1).isReg() && 692 cmpInstr->getOperand(1).isKill()) 693 cmpInstr->getOperand(1).setIsKill(false); 694 cmpInstr->eraseFromParent(); 695 jmpInstr->eraseFromParent(); 696 ++nvjGenerated; 697 ++NumNVJGenerated; 698 break; 699 } 700 } 701 } 702 } 703 704 return true; 705} 706 707FunctionPass *llvm::createHexagonNewValueJump() { 708 return new HexagonNewValueJump(); 709} 710