HexagonNewValueJump.cpp revision 280031
1//===----- HexagonNewValueJump.cpp - Hexagon Backend New Value Jump -------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This implements NewValueJump pass in Hexagon. 11// Ideally, we should merge this as a Peephole pass prior to register 12// allocation, but because we have a spill in between the feeder and new value 13// jump instructions, we are forced to write after register allocation. 14// Having said that, we should re-attempt to pull this earlier at some point 15// in future. 16 17// The basic approach looks for sequence of predicated jump, compare instruciton 18// that genereates the predicate and, the feeder to the predicate. Once it finds 19// all, it collapses compare and jump instruction into a new valu jump 20// intstructions. 21// 22// 23//===----------------------------------------------------------------------===// 24#include "llvm/PassSupport.h" 25#include "Hexagon.h" 26#include "HexagonInstrInfo.h" 27#include "HexagonMachineFunctionInfo.h" 28#include "HexagonRegisterInfo.h" 29#include "HexagonSubtarget.h" 30#include "HexagonTargetMachine.h" 31#include "llvm/ADT/DenseMap.h" 32#include "llvm/ADT/Statistic.h" 33#include "llvm/CodeGen/LiveVariables.h" 34#include "llvm/CodeGen/MachineFunctionAnalysis.h" 35#include "llvm/CodeGen/MachineFunctionPass.h" 36#include "llvm/CodeGen/MachineInstrBuilder.h" 37#include "llvm/CodeGen/MachineRegisterInfo.h" 38#include "llvm/CodeGen/Passes.h" 39#include "llvm/CodeGen/ScheduleDAGInstrs.h" 40#include "llvm/Support/CommandLine.h" 41#include "llvm/Support/Compiler.h" 42#include "llvm/Support/Debug.h" 43#include "llvm/Target/TargetInstrInfo.h" 44#include "llvm/Target/TargetMachine.h" 45#include "llvm/Target/TargetRegisterInfo.h" 46#include <map> 47using namespace llvm; 48 49#define DEBUG_TYPE "hexagon-nvj" 50 51STATISTIC(NumNVJGenerated, "Number of New Value Jump Instructions created"); 52 53static cl::opt<int> 54DbgNVJCount("nvj-count", cl::init(-1), cl::Hidden, cl::desc( 55 "Maximum number of predicated jumps to be converted to New Value Jump")); 56 57static cl::opt<bool> DisableNewValueJumps("disable-nvjump", cl::Hidden, 58 cl::ZeroOrMore, cl::init(false), 59 cl::desc("Disable New Value Jumps")); 60 61namespace llvm { 62 void initializeHexagonNewValueJumpPass(PassRegistry&); 63} 64 65 66namespace { 67 struct HexagonNewValueJump : public MachineFunctionPass { 68 const HexagonInstrInfo *QII; 69 const HexagonRegisterInfo *QRI; 70 71 public: 72 static char ID; 73 74 HexagonNewValueJump() : MachineFunctionPass(ID) { 75 initializeHexagonNewValueJumpPass(*PassRegistry::getPassRegistry()); 76 } 77 78 void getAnalysisUsage(AnalysisUsage &AU) const override { 79 AU.addRequired<MachineBranchProbabilityInfo>(); 80 MachineFunctionPass::getAnalysisUsage(AU); 81 } 82 83 const char *getPassName() const override { 84 return "Hexagon NewValueJump"; 85 } 86 87 bool runOnMachineFunction(MachineFunction &Fn) override; 88 89 private: 90 /// \brief A handle to the branch probability pass. 91 const MachineBranchProbabilityInfo *MBPI; 92 93 }; 94 95} // end of anonymous namespace 96 97char HexagonNewValueJump::ID = 0; 98 99INITIALIZE_PASS_BEGIN(HexagonNewValueJump, "hexagon-nvj", 100 "Hexagon NewValueJump", false, false) 101INITIALIZE_PASS_DEPENDENCY(MachineBranchProbabilityInfo) 102INITIALIZE_PASS_END(HexagonNewValueJump, "hexagon-nvj", 103 "Hexagon NewValueJump", false, false) 104 105 106// We have identified this II could be feeder to NVJ, 107// verify that it can be. 108static bool canBeFeederToNewValueJump(const HexagonInstrInfo *QII, 109 const TargetRegisterInfo *TRI, 110 MachineBasicBlock::iterator II, 111 MachineBasicBlock::iterator end, 112 MachineBasicBlock::iterator skip, 113 MachineFunction &MF) { 114 115 // Predicated instruction can not be feeder to NVJ. 116 if (QII->isPredicated(II)) 117 return false; 118 119 // Bail out if feederReg is a paired register (double regs in 120 // our case). One would think that we can check to see if a given 121 // register cmpReg1 or cmpReg2 is a sub register of feederReg 122 // using -- if (QRI->isSubRegister(feederReg, cmpReg1) logic 123 // before the callsite of this function 124 // But we can not as it comes in the following fashion. 125 // %D0<def> = Hexagon_S2_lsr_r_p %D0<kill>, %R2<kill> 126 // %R0<def> = KILL %R0, %D0<imp-use,kill> 127 // %P0<def> = CMPEQri %R0<kill>, 0 128 // Hence, we need to check if it's a KILL instruction. 129 if (II->getOpcode() == TargetOpcode::KILL) 130 return false; 131 132 133 // Make sure there there is no 'def' or 'use' of any of the uses of 134 // feeder insn between it's definition, this MI and jump, jmpInst 135 // skipping compare, cmpInst. 136 // Here's the example. 137 // r21=memub(r22+r24<<#0) 138 // p0 = cmp.eq(r21, #0) 139 // r4=memub(r3+r21<<#0) 140 // if (p0.new) jump:t .LBB29_45 141 // Without this check, it will be converted into 142 // r4=memub(r3+r21<<#0) 143 // r21=memub(r22+r24<<#0) 144 // p0 = cmp.eq(r21, #0) 145 // if (p0.new) jump:t .LBB29_45 146 // and result WAR hazards if converted to New Value Jump. 147 148 for (unsigned i = 0; i < II->getNumOperands(); ++i) { 149 if (II->getOperand(i).isReg() && 150 (II->getOperand(i).isUse() || II->getOperand(i).isDef())) { 151 MachineBasicBlock::iterator localII = II; 152 ++localII; 153 unsigned Reg = II->getOperand(i).getReg(); 154 for (MachineBasicBlock::iterator localBegin = localII; 155 localBegin != end; ++localBegin) { 156 if (localBegin == skip ) continue; 157 // Check for Subregisters too. 158 if (localBegin->modifiesRegister(Reg, TRI) || 159 localBegin->readsRegister(Reg, TRI)) 160 return false; 161 } 162 } 163 } 164 return true; 165} 166 167// These are the common checks that need to performed 168// to determine if 169// 1. compare instruction can be moved before jump. 170// 2. feeder to the compare instruction can be moved before jump. 171static bool commonChecksToProhibitNewValueJump(bool afterRA, 172 MachineBasicBlock::iterator MII) { 173 174 // If store in path, bail out. 175 if (MII->getDesc().mayStore()) 176 return false; 177 178 // if call in path, bail out. 179 if (MII->getOpcode() == Hexagon::J2_call) 180 return false; 181 182 // if NVJ is running prior to RA, do the following checks. 183 if (!afterRA) { 184 // The following Target Opcode instructions are spurious 185 // to new value jump. If they are in the path, bail out. 186 // KILL sets kill flag on the opcode. It also sets up a 187 // single register, out of pair. 188 // %D0<def> = Hexagon_S2_lsr_r_p %D0<kill>, %R2<kill> 189 // %R0<def> = KILL %R0, %D0<imp-use,kill> 190 // %P0<def> = CMPEQri %R0<kill>, 0 191 // PHI can be anything after RA. 192 // COPY can remateriaze things in between feeder, compare and nvj. 193 if (MII->getOpcode() == TargetOpcode::KILL || 194 MII->getOpcode() == TargetOpcode::PHI || 195 MII->getOpcode() == TargetOpcode::COPY) 196 return false; 197 198 // The following pseudo Hexagon instructions sets "use" and "def" 199 // of registers by individual passes in the backend. At this time, 200 // we don't know the scope of usage and definitions of these 201 // instructions. 202 if (MII->getOpcode() == Hexagon::TFR_condset_ii || 203 MII->getOpcode() == Hexagon::TFR_condset_ri || 204 MII->getOpcode() == Hexagon::TFR_condset_ir || 205 MII->getOpcode() == Hexagon::LDriw_pred || 206 MII->getOpcode() == Hexagon::STriw_pred) 207 return false; 208 } 209 210 return true; 211} 212 213static bool canCompareBeNewValueJump(const HexagonInstrInfo *QII, 214 const TargetRegisterInfo *TRI, 215 MachineBasicBlock::iterator II, 216 unsigned pReg, 217 bool secondReg, 218 bool optLocation, 219 MachineBasicBlock::iterator end, 220 MachineFunction &MF) { 221 222 MachineInstr *MI = II; 223 224 // If the second operand of the compare is an imm, make sure it's in the 225 // range specified by the arch. 226 if (!secondReg) { 227 int64_t v = MI->getOperand(2).getImm(); 228 229 if (!(isUInt<5>(v) || 230 ((MI->getOpcode() == Hexagon::C2_cmpeqi || 231 MI->getOpcode() == Hexagon::C2_cmpgti) && 232 (v == -1)))) 233 return false; 234 } 235 236 unsigned cmpReg1, cmpOp2 = 0; // cmpOp2 assignment silences compiler warning. 237 cmpReg1 = MI->getOperand(1).getReg(); 238 239 if (secondReg) { 240 cmpOp2 = MI->getOperand(2).getReg(); 241 242 // Make sure that that second register is not from COPY 243 // At machine code level, we don't need this, but if we decide 244 // to move new value jump prior to RA, we would be needing this. 245 MachineRegisterInfo &MRI = MF.getRegInfo(); 246 if (secondReg && !TargetRegisterInfo::isPhysicalRegister(cmpOp2)) { 247 MachineInstr *def = MRI.getVRegDef(cmpOp2); 248 if (def->getOpcode() == TargetOpcode::COPY) 249 return false; 250 } 251 } 252 253 // Walk the instructions after the compare (predicate def) to the jump, 254 // and satisfy the following conditions. 255 ++II ; 256 for (MachineBasicBlock::iterator localII = II; localII != end; 257 ++localII) { 258 259 // Check 1. 260 // If "common" checks fail, bail out. 261 if (!commonChecksToProhibitNewValueJump(optLocation, localII)) 262 return false; 263 264 // Check 2. 265 // If there is a def or use of predicate (result of compare), bail out. 266 if (localII->modifiesRegister(pReg, TRI) || 267 localII->readsRegister(pReg, TRI)) 268 return false; 269 270 // Check 3. 271 // If there is a def of any of the use of the compare (operands of compare), 272 // bail out. 273 // Eg. 274 // p0 = cmp.eq(r2, r0) 275 // r2 = r4 276 // if (p0.new) jump:t .LBB28_3 277 if (localII->modifiesRegister(cmpReg1, TRI) || 278 (secondReg && localII->modifiesRegister(cmpOp2, TRI))) 279 return false; 280 } 281 return true; 282} 283 284// Given a compare operator, return a matching New Value Jump 285// compare operator. Make sure that MI here is included in 286// HexagonInstrInfo.cpp::isNewValueJumpCandidate 287static unsigned getNewValueJumpOpcode(MachineInstr *MI, int reg, 288 bool secondRegNewified, 289 MachineBasicBlock *jmpTarget, 290 const MachineBranchProbabilityInfo 291 *MBPI) { 292 bool taken = false; 293 MachineBasicBlock *Src = MI->getParent(); 294 const BranchProbability Prediction = 295 MBPI->getEdgeProbability(Src, jmpTarget); 296 297 if (Prediction >= BranchProbability(1,2)) 298 taken = true; 299 300 switch (MI->getOpcode()) { 301 case Hexagon::C2_cmpeq: 302 return taken ? Hexagon::CMPEQrr_t_Jumpnv_t_V4 303 : Hexagon::CMPEQrr_t_Jumpnv_nt_V4; 304 305 case Hexagon::C2_cmpeqi: { 306 if (reg >= 0) 307 return taken ? Hexagon::CMPEQri_t_Jumpnv_t_V4 308 : Hexagon::CMPEQri_t_Jumpnv_nt_V4; 309 else 310 return taken ? Hexagon::CMPEQn1_t_Jumpnv_t_V4 311 : Hexagon::CMPEQn1_t_Jumpnv_nt_V4; 312 } 313 314 case Hexagon::C2_cmpgt: { 315 if (secondRegNewified) 316 return taken ? Hexagon::CMPLTrr_t_Jumpnv_t_V4 317 : Hexagon::CMPLTrr_t_Jumpnv_nt_V4; 318 else 319 return taken ? Hexagon::CMPGTrr_t_Jumpnv_t_V4 320 : Hexagon::CMPGTrr_t_Jumpnv_nt_V4; 321 } 322 323 case Hexagon::C2_cmpgti: { 324 if (reg >= 0) 325 return taken ? Hexagon::CMPGTri_t_Jumpnv_t_V4 326 : Hexagon::CMPGTri_t_Jumpnv_nt_V4; 327 else 328 return taken ? Hexagon::CMPGTn1_t_Jumpnv_t_V4 329 : Hexagon::CMPGTn1_t_Jumpnv_nt_V4; 330 } 331 332 case Hexagon::C2_cmpgtu: { 333 if (secondRegNewified) 334 return taken ? Hexagon::CMPLTUrr_t_Jumpnv_t_V4 335 : Hexagon::CMPLTUrr_t_Jumpnv_nt_V4; 336 else 337 return taken ? Hexagon::CMPGTUrr_t_Jumpnv_t_V4 338 : Hexagon::CMPGTUrr_t_Jumpnv_nt_V4; 339 } 340 341 case Hexagon::C2_cmpgtui: 342 return taken ? Hexagon::CMPGTUri_t_Jumpnv_t_V4 343 : Hexagon::CMPGTUri_t_Jumpnv_nt_V4; 344 345 default: 346 llvm_unreachable("Could not find matching New Value Jump instruction."); 347 } 348 // return *some value* to avoid compiler warning 349 return 0; 350} 351 352bool HexagonNewValueJump::runOnMachineFunction(MachineFunction &MF) { 353 354 DEBUG(dbgs() << "********** Hexagon New Value Jump **********\n" 355 << "********** Function: " 356 << MF.getName() << "\n"); 357 358#if 0 359 // for now disable this, if we move NewValueJump before register 360 // allocation we need this information. 361 LiveVariables &LVs = getAnalysis<LiveVariables>(); 362#endif 363 364 QII = static_cast<const HexagonInstrInfo *>(MF.getSubtarget().getInstrInfo()); 365 QRI = static_cast<const HexagonRegisterInfo *>( 366 MF.getSubtarget().getRegisterInfo()); 367 MBPI = &getAnalysis<MachineBranchProbabilityInfo>(); 368 369 if (!QRI->Subtarget.hasV4TOps() || 370 DisableNewValueJumps) { 371 return false; 372 } 373 374 int nvjCount = DbgNVJCount; 375 int nvjGenerated = 0; 376 377 // Loop through all the bb's of the function 378 for (MachineFunction::iterator MBBb = MF.begin(), MBBe = MF.end(); 379 MBBb != MBBe; ++MBBb) { 380 MachineBasicBlock* MBB = MBBb; 381 382 DEBUG(dbgs() << "** dumping bb ** " 383 << MBB->getNumber() << "\n"); 384 DEBUG(MBB->dump()); 385 DEBUG(dbgs() << "\n" << "********** dumping instr bottom up **********\n"); 386 bool foundJump = false; 387 bool foundCompare = false; 388 bool invertPredicate = false; 389 unsigned predReg = 0; // predicate reg of the jump. 390 unsigned cmpReg1 = 0; 391 int cmpOp2 = 0; 392 bool MO1IsKill = false; 393 bool MO2IsKill = false; 394 MachineBasicBlock::iterator jmpPos; 395 MachineBasicBlock::iterator cmpPos; 396 MachineInstr *cmpInstr = nullptr, *jmpInstr = nullptr; 397 MachineBasicBlock *jmpTarget = nullptr; 398 bool afterRA = false; 399 bool isSecondOpReg = false; 400 bool isSecondOpNewified = false; 401 // Traverse the basic block - bottom up 402 for (MachineBasicBlock::iterator MII = MBB->end(), E = MBB->begin(); 403 MII != E;) { 404 MachineInstr *MI = --MII; 405 if (MI->isDebugValue()) { 406 continue; 407 } 408 409 if ((nvjCount == 0) || (nvjCount > -1 && nvjCount <= nvjGenerated)) 410 break; 411 412 DEBUG(dbgs() << "Instr: "; MI->dump(); dbgs() << "\n"); 413 414 if (!foundJump && 415 (MI->getOpcode() == Hexagon::J2_jumpt || 416 MI->getOpcode() == Hexagon::J2_jumpf || 417 MI->getOpcode() == Hexagon::J2_jumptnewpt || 418 MI->getOpcode() == Hexagon::J2_jumptnew || 419 MI->getOpcode() == Hexagon::J2_jumpfnewpt || 420 MI->getOpcode() == Hexagon::J2_jumpfnew)) { 421 // This is where you would insert your compare and 422 // instr that feeds compare 423 jmpPos = MII; 424 jmpInstr = MI; 425 predReg = MI->getOperand(0).getReg(); 426 afterRA = TargetRegisterInfo::isPhysicalRegister(predReg); 427 428 // If ifconverter had not messed up with the kill flags of the 429 // operands, the following check on the kill flag would suffice. 430 // if(!jmpInstr->getOperand(0).isKill()) break; 431 432 // This predicate register is live out out of BB 433 // this would only work if we can actually use Live 434 // variable analysis on phy regs - but LLVM does not 435 // provide LV analysis on phys regs. 436 //if(LVs.isLiveOut(predReg, *MBB)) break; 437 438 // Get all the successors of this block - which will always 439 // be 2. Check if the predicate register is live in in those 440 // successor. If yes, we can not delete the predicate - 441 // I am doing this only because LLVM does not provide LiveOut 442 // at the BB level. 443 bool predLive = false; 444 for (MachineBasicBlock::const_succ_iterator SI = MBB->succ_begin(), 445 SIE = MBB->succ_end(); SI != SIE; ++SI) { 446 MachineBasicBlock* succMBB = *SI; 447 if (succMBB->isLiveIn(predReg)) { 448 predLive = true; 449 } 450 } 451 if (predLive) 452 break; 453 454 jmpTarget = MI->getOperand(1).getMBB(); 455 foundJump = true; 456 if (MI->getOpcode() == Hexagon::J2_jumpf || 457 MI->getOpcode() == Hexagon::J2_jumpfnewpt || 458 MI->getOpcode() == Hexagon::J2_jumpfnew) { 459 invertPredicate = true; 460 } 461 continue; 462 } 463 464 // No new value jump if there is a barrier. A barrier has to be in its 465 // own packet. A barrier has zero operands. We conservatively bail out 466 // here if we see any instruction with zero operands. 467 if (foundJump && MI->getNumOperands() == 0) 468 break; 469 470 if (foundJump && 471 !foundCompare && 472 MI->getOperand(0).isReg() && 473 MI->getOperand(0).getReg() == predReg) { 474 475 // Not all compares can be new value compare. Arch Spec: 7.6.1.1 476 if (QII->isNewValueJumpCandidate(MI)) { 477 478 assert((MI->getDesc().isCompare()) && 479 "Only compare instruction can be collapsed into New Value Jump"); 480 isSecondOpReg = MI->getOperand(2).isReg(); 481 482 if (!canCompareBeNewValueJump(QII, QRI, MII, predReg, isSecondOpReg, 483 afterRA, jmpPos, MF)) 484 break; 485 486 cmpInstr = MI; 487 cmpPos = MII; 488 foundCompare = true; 489 490 // We need cmpReg1 and cmpOp2(imm or reg) while building 491 // new value jump instruction. 492 cmpReg1 = MI->getOperand(1).getReg(); 493 if (MI->getOperand(1).isKill()) 494 MO1IsKill = true; 495 496 if (isSecondOpReg) { 497 cmpOp2 = MI->getOperand(2).getReg(); 498 if (MI->getOperand(2).isKill()) 499 MO2IsKill = true; 500 } else 501 cmpOp2 = MI->getOperand(2).getImm(); 502 continue; 503 } 504 } 505 506 if (foundCompare && foundJump) { 507 508 // If "common" checks fail, bail out on this BB. 509 if (!commonChecksToProhibitNewValueJump(afterRA, MII)) 510 break; 511 512 bool foundFeeder = false; 513 MachineBasicBlock::iterator feederPos = MII; 514 if (MI->getOperand(0).isReg() && 515 MI->getOperand(0).isDef() && 516 (MI->getOperand(0).getReg() == cmpReg1 || 517 (isSecondOpReg && 518 MI->getOperand(0).getReg() == (unsigned) cmpOp2))) { 519 520 unsigned feederReg = MI->getOperand(0).getReg(); 521 522 // First try to see if we can get the feeder from the first operand 523 // of the compare. If we can not, and if secondOpReg is true 524 // (second operand of the compare is also register), try that one. 525 // TODO: Try to come up with some heuristic to figure out which 526 // feeder would benefit. 527 528 if (feederReg == cmpReg1) { 529 if (!canBeFeederToNewValueJump(QII, QRI, MII, jmpPos, cmpPos, MF)) { 530 if (!isSecondOpReg) 531 break; 532 else 533 continue; 534 } else 535 foundFeeder = true; 536 } 537 538 if (!foundFeeder && 539 isSecondOpReg && 540 feederReg == (unsigned) cmpOp2) 541 if (!canBeFeederToNewValueJump(QII, QRI, MII, jmpPos, cmpPos, MF)) 542 break; 543 544 if (isSecondOpReg) { 545 // In case of CMPLT, or CMPLTU, or EQ with the second register 546 // to newify, swap the operands. 547 if (cmpInstr->getOpcode() == Hexagon::C2_cmpeq && 548 feederReg == (unsigned) cmpOp2) { 549 unsigned tmp = cmpReg1; 550 bool tmpIsKill = MO1IsKill; 551 cmpReg1 = cmpOp2; 552 MO1IsKill = MO2IsKill; 553 cmpOp2 = tmp; 554 MO2IsKill = tmpIsKill; 555 } 556 557 // Now we have swapped the operands, all we need to check is, 558 // if the second operand (after swap) is the feeder. 559 // And if it is, make a note. 560 if (feederReg == (unsigned)cmpOp2) 561 isSecondOpNewified = true; 562 } 563 564 // Now that we are moving feeder close the jump, 565 // make sure we are respecting the kill values of 566 // the operands of the feeder. 567 568 bool updatedIsKill = false; 569 for (unsigned i = 0; i < MI->getNumOperands(); i++) { 570 MachineOperand &MO = MI->getOperand(i); 571 if (MO.isReg() && MO.isUse()) { 572 unsigned feederReg = MO.getReg(); 573 for (MachineBasicBlock::iterator localII = feederPos, 574 end = jmpPos; localII != end; localII++) { 575 MachineInstr *localMI = localII; 576 for (unsigned j = 0; j < localMI->getNumOperands(); j++) { 577 MachineOperand &localMO = localMI->getOperand(j); 578 if (localMO.isReg() && localMO.isUse() && 579 localMO.isKill() && feederReg == localMO.getReg()) { 580 // We found that there is kill of a use register 581 // Set up a kill flag on the register 582 localMO.setIsKill(false); 583 MO.setIsKill(); 584 updatedIsKill = true; 585 break; 586 } 587 } 588 if (updatedIsKill) break; 589 } 590 } 591 if (updatedIsKill) break; 592 } 593 594 MBB->splice(jmpPos, MI->getParent(), MI); 595 MBB->splice(jmpPos, MI->getParent(), cmpInstr); 596 DebugLoc dl = MI->getDebugLoc(); 597 MachineInstr *NewMI; 598 599 assert((QII->isNewValueJumpCandidate(cmpInstr)) && 600 "This compare is not a New Value Jump candidate."); 601 unsigned opc = getNewValueJumpOpcode(cmpInstr, cmpOp2, 602 isSecondOpNewified, 603 jmpTarget, MBPI); 604 if (invertPredicate) 605 opc = QII->getInvertedPredicatedOpcode(opc); 606 607 if (isSecondOpReg) 608 NewMI = BuildMI(*MBB, jmpPos, dl, 609 QII->get(opc)) 610 .addReg(cmpReg1, getKillRegState(MO1IsKill)) 611 .addReg(cmpOp2, getKillRegState(MO2IsKill)) 612 .addMBB(jmpTarget); 613 614 else if ((cmpInstr->getOpcode() == Hexagon::C2_cmpeqi || 615 cmpInstr->getOpcode() == Hexagon::C2_cmpgti) && 616 cmpOp2 == -1 ) 617 // Corresponding new-value compare jump instructions don't have the 618 // operand for -1 immediate value. 619 NewMI = BuildMI(*MBB, jmpPos, dl, 620 QII->get(opc)) 621 .addReg(cmpReg1, getKillRegState(MO1IsKill)) 622 .addMBB(jmpTarget); 623 624 else 625 NewMI = BuildMI(*MBB, jmpPos, dl, 626 QII->get(opc)) 627 .addReg(cmpReg1, getKillRegState(MO1IsKill)) 628 .addImm(cmpOp2) 629 .addMBB(jmpTarget); 630 631 assert(NewMI && "New Value Jump Instruction Not created!"); 632 (void)NewMI; 633 if (cmpInstr->getOperand(0).isReg() && 634 cmpInstr->getOperand(0).isKill()) 635 cmpInstr->getOperand(0).setIsKill(false); 636 if (cmpInstr->getOperand(1).isReg() && 637 cmpInstr->getOperand(1).isKill()) 638 cmpInstr->getOperand(1).setIsKill(false); 639 cmpInstr->eraseFromParent(); 640 jmpInstr->eraseFromParent(); 641 ++nvjGenerated; 642 ++NumNVJGenerated; 643 break; 644 } 645 } 646 } 647 } 648 649 return true; 650 651} 652 653FunctionPass *llvm::createHexagonNewValueJump() { 654 return new HexagonNewValueJump(); 655} 656