Thumb2ITBlockPass.cpp revision 360660 
1//===-- Thumb2ITBlockPass.cpp - Insert Thumb-2 IT blocks ------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
9#include "ARM.h"
10#include "ARMMachineFunctionInfo.h"
11#include "ARMSubtarget.h"
12#include "MCTargetDesc/ARMBaseInfo.h"
13#include "Thumb2InstrInfo.h"
14#include "llvm/ADT/SmallSet.h"
15#include "llvm/ADT/SmallVector.h"
16#include "llvm/ADT/Statistic.h"
17#include "llvm/ADT/StringRef.h"
18#include "llvm/CodeGen/MachineBasicBlock.h"
19#include "llvm/CodeGen/MachineFunction.h"
20#include "llvm/CodeGen/MachineFunctionPass.h"
21#include "llvm/CodeGen/MachineInstr.h"
22#include "llvm/CodeGen/MachineInstrBuilder.h"
23#include "llvm/CodeGen/MachineInstrBundle.h"
24#include "llvm/CodeGen/MachineOperand.h"
25#include "llvm/IR/DebugLoc.h"
26#include "llvm/MC/MCInstrDesc.h"
27#include "llvm/MC/MCRegisterInfo.h"
28#include <cassert>
29#include <new>
30
31using namespace llvm;
32
33#define DEBUG_TYPE "thumb2-it"
34#define PASS_NAME "Thumb IT blocks insertion pass"
35
36STATISTIC(NumITs,        "Number of IT blocks inserted");
37STATISTIC(NumMovedInsts, "Number of predicated instructions moved");
38
39using RegisterSet = SmallSet<unsigned, 4>;
40
41namespace {
42
43  class Thumb2ITBlock : public MachineFunctionPass {
44  public:
45    static char ID;
46
47    bool restrictIT;
48    const Thumb2InstrInfo *TII;
49    const TargetRegisterInfo *TRI;
50    ARMFunctionInfo *AFI;
51
52    Thumb2ITBlock() : MachineFunctionPass(ID) {}
53
54    bool runOnMachineFunction(MachineFunction &Fn) override;
55
56    MachineFunctionProperties getRequiredProperties() const override {
57      return MachineFunctionProperties().set(
58          MachineFunctionProperties::Property::NoVRegs);
59    }
60
61    StringRef getPassName() const override {
62      return PASS_NAME;
63    }
64
65  private:
66    bool MoveCopyOutOfITBlock(MachineInstr *MI,
67                              ARMCC::CondCodes CC, ARMCC::CondCodes OCC,
68                              RegisterSet &Defs, RegisterSet &Uses);
69    bool InsertITInstructions(MachineBasicBlock &Block);
70  };
71
72  char Thumb2ITBlock::ID = 0;
73
74} // end anonymous namespace
75
76INITIALIZE_PASS(Thumb2ITBlock, DEBUG_TYPE, PASS_NAME, false, false)
77
78/// TrackDefUses - Tracking what registers are being defined and used by
79/// instructions in the IT block. This also tracks "dependencies", i.e. uses
80/// in the IT block that are defined before the IT instruction.
81static void TrackDefUses(MachineInstr *MI, RegisterSet &Defs, RegisterSet &Uses,
82                         const TargetRegisterInfo *TRI) {
83  using RegList = SmallVector<unsigned, 4>;
84  RegList LocalDefs;
85  RegList LocalUses;
86
87  for (auto &MO : MI->operands()) {
88    if (!MO.isReg())
89      continue;
90    unsigned Reg = MO.getReg();
91    if (!Reg || Reg == ARM::ITSTATE || Reg == ARM::SP)
92      continue;
93    if (MO.isUse())
94      LocalUses.push_back(Reg);
95    else
96      LocalDefs.push_back(Reg);
97  }
98
99  auto InsertUsesDefs = [&](RegList &Regs, RegisterSet &UsesDefs) {
100    for (unsigned Reg : Regs)
101      for (MCSubRegIterator Subreg(Reg, TRI, /*IncludeSelf=*/true);
102           Subreg.isValid(); ++Subreg)
103        UsesDefs.insert(*Subreg);
104  };
105
106  InsertUsesDefs(LocalDefs, Defs);
107  InsertUsesDefs(LocalUses, Uses);
108}
109
110/// Clear kill flags for any uses in the given set.  This will likely
111/// conservatively remove more kill flags than are necessary, but removing them
112/// is safer than incorrect kill flags remaining on instructions.
113static void ClearKillFlags(MachineInstr *MI, RegisterSet &Uses) {
114  for (MachineOperand &MO : MI->operands()) {
115    if (!MO.isReg() || MO.isDef() || !MO.isKill())
116      continue;
117    if (!Uses.count(MO.getReg()))
118      continue;
119    MO.setIsKill(false);
120  }
121}
122
123static bool isCopy(MachineInstr *MI) {
124  switch (MI->getOpcode()) {
125  default:
126    return false;
127  case ARM::MOVr:
128  case ARM::MOVr_TC:
129  case ARM::tMOVr:
130  case ARM::t2MOVr:
131    return true;
132  }
133}
134
135bool
136Thumb2ITBlock::MoveCopyOutOfITBlock(MachineInstr *MI,
137                                    ARMCC::CondCodes CC, ARMCC::CondCodes OCC,
138                                    RegisterSet &Defs, RegisterSet &Uses) {
139  if (!isCopy(MI))
140    return false;
141  // llvm models select's as two-address instructions. That means a copy
142  // is inserted before a t2MOVccr, etc. If the copy is scheduled in
143  // between selects we would end up creating multiple IT blocks.
144  assert(MI->getOperand(0).getSubReg() == 0 &&
145         MI->getOperand(1).getSubReg() == 0 &&
146         "Sub-register indices still around?");
147
148  unsigned DstReg = MI->getOperand(0).getReg();
149  unsigned SrcReg = MI->getOperand(1).getReg();
150
151  // First check if it's safe to move it.
152  if (Uses.count(DstReg) || Defs.count(SrcReg))
153    return false;
154
155  // If the CPSR is defined by this copy, then we don't want to move it. E.g.,
156  // if we have:
157  //
158  //   movs  r1, r1
159  //   rsb   r1, 0
160  //   movs  r2, r2
161  //   rsb   r2, 0
162  //
163  // we don't want this to be converted to:
164  //
165  //   movs  r1, r1
166  //   movs  r2, r2
167  //   itt   mi
168  //   rsb   r1, 0
169  //   rsb   r2, 0
170  //
171  const MCInstrDesc &MCID = MI->getDesc();
172  if (MI->hasOptionalDef() &&
173      MI->getOperand(MCID.getNumOperands() - 1).getReg() == ARM::CPSR)
174    return false;
175
176  // Then peek at the next instruction to see if it's predicated on CC or OCC.
177  // If not, then there is nothing to be gained by moving the copy.
178  MachineBasicBlock::iterator I = MI;
179  ++I;
180  MachineBasicBlock::iterator E = MI->getParent()->end();
181
182  while (I != E && I->isDebugInstr())
183    ++I;
184
185  if (I != E) {
186    unsigned NPredReg = 0;
187    ARMCC::CondCodes NCC = getITInstrPredicate(*I, NPredReg);
188    if (NCC == CC || NCC == OCC)
189      return true;
190  }
191  return false;
192}
193
194bool Thumb2ITBlock::InsertITInstructions(MachineBasicBlock &MBB) {
195  bool Modified = false;
196  RegisterSet Defs, Uses;
197  MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end();
198
199  while (MBBI != E) {
200    MachineInstr *MI = &*MBBI;
201    DebugLoc dl = MI->getDebugLoc();
202    unsigned PredReg = 0;
203    ARMCC::CondCodes CC = getITInstrPredicate(*MI, PredReg);
204    if (CC == ARMCC::AL) {
205      ++MBBI;
206      continue;
207    }
208
209    Defs.clear();
210    Uses.clear();
211    TrackDefUses(MI, Defs, Uses, TRI);
212
213    // Insert an IT instruction.
214    MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII->get(ARM::t2IT))
215      .addImm(CC);
216
217    // Add implicit use of ITSTATE to IT block instructions.
218    MI->addOperand(MachineOperand::CreateReg(ARM::ITSTATE, false/*ifDef*/,
219                                             true/*isImp*/, false/*isKill*/));
220
221    MachineInstr *LastITMI = MI;
222    MachineBasicBlock::iterator InsertPos = MIB.getInstr();
223    ++MBBI;
224
225    // Form IT block.
226    ARMCC::CondCodes OCC = ARMCC::getOppositeCondition(CC);
227    unsigned Mask = 0, Pos = 3;
228
229    // v8 IT blocks are limited to one conditional op unless -arm-no-restrict-it
230    // is set: skip the loop
231    if (!restrictIT) {
232      // Branches, including tricky ones like LDM_RET, need to end an IT
233      // block so check the instruction we just put in the block.
234      for (; MBBI != E && Pos &&
235             (!MI->isBranch() && !MI->isReturn()) ; ++MBBI) {
236        if (MBBI->isDebugInstr())
237          continue;
238
239        MachineInstr *NMI = &*MBBI;
240        MI = NMI;
241
242        unsigned NPredReg = 0;
243        ARMCC::CondCodes NCC = getITInstrPredicate(*NMI, NPredReg);
244        if (NCC == CC || NCC == OCC) {
245          Mask |= ((NCC ^ CC) & 1) << Pos;
246          // Add implicit use of ITSTATE.
247          NMI->addOperand(MachineOperand::CreateReg(ARM::ITSTATE, false/*ifDef*/,
248                                                 true/*isImp*/, false/*isKill*/));
249          LastITMI = NMI;
250        } else {
251          if (NCC == ARMCC::AL &&
252              MoveCopyOutOfITBlock(NMI, CC, OCC, Defs, Uses)) {
253            --MBBI;
254            MBB.remove(NMI);
255            MBB.insert(InsertPos, NMI);
256            ClearKillFlags(MI, Uses);
257            ++NumMovedInsts;
258            continue;
259          }
260          break;
261        }
262        TrackDefUses(NMI, Defs, Uses, TRI);
263        --Pos;
264      }
265    }
266
267    // Finalize IT mask.
268    Mask |= (1 << Pos);
269    MIB.addImm(Mask);
270
271    // Last instruction in IT block kills ITSTATE.
272    LastITMI->findRegisterUseOperand(ARM::ITSTATE)->setIsKill();
273
274    // Finalize the bundle.
275    finalizeBundle(MBB, InsertPos.getInstrIterator(),
276                   ++LastITMI->getIterator());
277
278    Modified = true;
279    ++NumITs;
280  }
281
282  return Modified;
283}
284
285bool Thumb2ITBlock::runOnMachineFunction(MachineFunction &Fn) {
286  const ARMSubtarget &STI =
287      static_cast<const ARMSubtarget &>(Fn.getSubtarget());
288  if (!STI.isThumb2())
289    return false;
290  AFI = Fn.getInfo<ARMFunctionInfo>();
291  TII = static_cast<const Thumb2InstrInfo *>(STI.getInstrInfo());
292  TRI = STI.getRegisterInfo();
293  restrictIT = STI.restrictIT();
294
295  if (!AFI->isThumbFunction())
296    return false;
297
298  bool Modified = false;
299  for (auto &MBB : Fn )
300    Modified |= InsertITInstructions(MBB);
301
302  if (Modified)
303    AFI->setHasITBlocks(true);
304
305  return Modified;
306}
307
308/// createThumb2ITBlockPass - Returns an instance of the Thumb2 IT blocks
309/// insertion pass.
310FunctionPass *llvm::createThumb2ITBlockPass() { return new Thumb2ITBlock(); }
311
312#undef DEBUG_TYPE
313#define DEBUG_TYPE "arm-mve-vpt"
314
315namespace {
316  class MVEVPTBlock : public MachineFunctionPass {
317  public:
318    static char ID;
319    const Thumb2InstrInfo *TII;
320    const TargetRegisterInfo *TRI;
321
322    MVEVPTBlock() : MachineFunctionPass(ID) {}
323
324    bool runOnMachineFunction(MachineFunction &Fn) override;
325
326    MachineFunctionProperties getRequiredProperties() const override {
327      return MachineFunctionProperties().set(
328          MachineFunctionProperties::Property::NoVRegs);
329    }
330
331    StringRef getPassName() const override {
332      return "MVE VPT block insertion pass";
333    }
334
335  private:
336    bool InsertVPTBlocks(MachineBasicBlock &MBB);
337  };
338
339  char MVEVPTBlock::ID = 0;
340
341} // end anonymous namespace
342
343INITIALIZE_PASS(MVEVPTBlock, DEBUG_TYPE, "ARM MVE VPT block pass", false, false)
344
345enum VPTMaskValue {
346  T     =  8, // 0b1000
347  TT    =  4, // 0b0100
348  TE    = 12, // 0b1100
349  TTT   =  2, // 0b0010
350  TTE   =  6, // 0b0110
351  TEE   = 10, // 0b1010
352  TET   = 14, // 0b1110
353  TTTT  =  1, // 0b0001
354  TTTE  =  3, // 0b0011
355  TTEE  =  5, // 0b0101
356  TTET  =  7, // 0b0111
357  TEEE  =  9, // 0b1001
358  TEET  = 11, // 0b1011
359  TETT  = 13, // 0b1101
360  TETE  = 15  // 0b1111
361};
362
363bool MVEVPTBlock::InsertVPTBlocks(MachineBasicBlock &Block) {
364  bool Modified = false;
365  MachineBasicBlock::iterator MBIter = Block.begin();
366  MachineBasicBlock::iterator EndIter = Block.end();
367
368  while (MBIter != EndIter) {
369    MachineInstr *MI = &*MBIter;
370    unsigned PredReg = 0;
371    DebugLoc dl = MI->getDebugLoc();
372
373    ARMVCC::VPTCodes Pred = getVPTInstrPredicate(*MI, PredReg);
374
375    // The idea of the predicate is that None, Then and Else are for use when
376    // handling assembly language: they correspond to the three possible
377    // suffixes "", "t" and "e" on the mnemonic. So when instructions are read
378    // from assembly source or disassembled from object code, you expect to see
379    // a mixture whenever there's a long VPT block. But in code generation, we
380    // hope we'll never generate an Else as input to this pass.
381
382    assert(Pred != ARMVCC::Else && "VPT block pass does not expect Else preds");
383
384    if (Pred == ARMVCC::None) {
385      ++MBIter;
386      continue;
387    }
388
389    MachineInstrBuilder MIBuilder =
390        BuildMI(Block, MBIter, dl, TII->get(ARM::MVE_VPST));
391    // The mask value for the VPST instruction is T = 0b1000 = 8
392    MIBuilder.addImm(VPTMaskValue::T);
393
394    MachineBasicBlock::iterator VPSTInsertPos = MIBuilder.getInstr();
395    int VPTInstCnt = 1;
396    ARMVCC::VPTCodes NextPred;
397
398    do {
399      ++MBIter;
400      NextPred = getVPTInstrPredicate(*MBIter, PredReg);
401    } while (NextPred != ARMVCC::None && NextPred == Pred && ++VPTInstCnt < 4);
402
403    MachineInstr *LastMI = &*MBIter;
404    finalizeBundle(Block, VPSTInsertPos.getInstrIterator(),
405                   ++LastMI->getIterator());
406
407    Modified = true;
408    LLVM_DEBUG(dbgs() << "VPT block created for: "; MI->dump(););
409
410    ++MBIter;
411  }
412  return Modified;
413}
414
415bool MVEVPTBlock::runOnMachineFunction(MachineFunction &Fn) {
416  const ARMSubtarget &STI =
417      static_cast<const ARMSubtarget &>(Fn.getSubtarget());
418
419  if (!STI.isThumb2() || !STI.hasMVEIntegerOps())
420    return false;
421
422  TII = static_cast<const Thumb2InstrInfo *>(STI.getInstrInfo());
423  TRI = STI.getRegisterInfo();
424
425  LLVM_DEBUG(dbgs() << "********** ARM MVE VPT BLOCKS **********\n"
426                    << "********** Function: " << Fn.getName() << '\n');
427
428  bool Modified = false;
429  for (MachineBasicBlock &MBB : Fn)
430    Modified |= InsertVPTBlocks(MBB);
431
432  LLVM_DEBUG(dbgs() << "**************************************\n");
433  return Modified;
434}
435
436/// createMVEVPTBlock - Returns an instance of the MVE VPT block
437/// insertion pass.
438FunctionPass *llvm::createMVEVPTBlockPass() { return new MVEVPTBlock(); }
439