Thumb2ITBlockPass.cpp revision 276479
11590Srgrimes//===-- Thumb2ITBlockPass.cpp - Insert Thumb-2 IT blocks ------------------===// 21590Srgrimes// 31590Srgrimes// The LLVM Compiler Infrastructure 41590Srgrimes// 51590Srgrimes// This file is distributed under the University of Illinois Open Source 61590Srgrimes// License. See LICENSE.TXT for details. 71590Srgrimes// 81590Srgrimes//===----------------------------------------------------------------------===// 91590Srgrimes 101590Srgrimes#include "ARM.h" 111590Srgrimes#include "ARMMachineFunctionInfo.h" 121590Srgrimes#include "Thumb2InstrInfo.h" 131590Srgrimes#include "llvm/ADT/SmallSet.h" 141590Srgrimes#include "llvm/ADT/Statistic.h" 151590Srgrimes#include "llvm/CodeGen/MachineFunctionPass.h" 161590Srgrimes#include "llvm/CodeGen/MachineInstr.h" 171590Srgrimes#include "llvm/CodeGen/MachineInstrBuilder.h" 181590Srgrimes#include "llvm/CodeGen/MachineInstrBundle.h" 191590Srgrimesusing namespace llvm; 201590Srgrimes 211590Srgrimes#define DEBUG_TYPE "thumb2-it" 221590Srgrimes 231590SrgrimesSTATISTIC(NumITs, "Number of IT blocks inserted"); 241590SrgrimesSTATISTIC(NumMovedInsts, "Number of predicated instructions moved"); 251590Srgrimes 261590Srgrimesnamespace { 271590Srgrimes class Thumb2ITBlockPass : public MachineFunctionPass { 281590Srgrimes public: 291590Srgrimes static char ID; 301590Srgrimes Thumb2ITBlockPass() : MachineFunctionPass(ID) {} 311590Srgrimes 321590Srgrimes bool restrictIT; 331590Srgrimes const Thumb2InstrInfo *TII; 341590Srgrimes const TargetRegisterInfo *TRI; 3527647Scharnier ARMFunctionInfo *AFI; 361590Srgrimes 371590Srgrimes bool runOnMachineFunction(MachineFunction &Fn) override; 381590Srgrimes 391590Srgrimes const char *getPassName() const override { 401590Srgrimes return "Thumb IT blocks insertion pass"; 4127647Scharnier } 421590Srgrimes 4327647Scharnier private: 441590Srgrimes bool MoveCopyOutOfITBlock(MachineInstr *MI, 4599112Sobrien ARMCC::CondCodes CC, ARMCC::CondCodes OCC, 4699112Sobrien SmallSet<unsigned, 4> &Defs, 471590Srgrimes SmallSet<unsigned, 4> &Uses); 481590Srgrimes bool InsertITInstructions(MachineBasicBlock &MBB); 491590Srgrimes }; 501590Srgrimes char Thumb2ITBlockPass::ID = 0; 5127647Scharnier} 5250452Ssheldonh 531590Srgrimes/// TrackDefUses - Tracking what registers are being defined and used by 5478717Sdd/// instructions in the IT block. This also tracks "dependencies", i.e. uses 551590Srgrimes/// in the IT block that are defined before the IT instruction. 5627647Scharnierstatic void TrackDefUses(MachineInstr *MI, 571590Srgrimes SmallSet<unsigned, 4> &Defs, 5850452Ssheldonh SmallSet<unsigned, 4> &Uses, 5950452Ssheldonh const TargetRegisterInfo *TRI) { 6050452Ssheldonh SmallVector<unsigned, 4> LocalDefs; 6192921Simp SmallVector<unsigned, 4> LocalUses; 6227647Scharnier 6350452Ssheldonh for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 6450452Ssheldonh MachineOperand &MO = MI->getOperand(i); 651590Srgrimes if (!MO.isReg()) 66102944Sdwmalone continue; 671590Srgrimes unsigned Reg = MO.getReg(); 6850452Ssheldonh if (!Reg || Reg == ARM::ITSTATE || Reg == ARM::SP) 6950452Ssheldonh continue; 7050452Ssheldonh if (MO.isUse()) 711590Srgrimes LocalUses.push_back(Reg); 721590Srgrimes else 7350452Ssheldonh LocalDefs.push_back(Reg); 741590Srgrimes } 7550452Ssheldonh 7650452Ssheldonh for (unsigned i = 0, e = LocalUses.size(); i != e; ++i) { 7750452Ssheldonh unsigned Reg = LocalUses[i]; 7850452Ssheldonh for (MCSubRegIterator Subreg(Reg, TRI, /*IncludeSelf=*/true); 791590Srgrimes Subreg.isValid(); ++Subreg) 801590Srgrimes Uses.insert(*Subreg); 811590Srgrimes } 821590Srgrimes 831590Srgrimes for (unsigned i = 0, e = LocalDefs.size(); i != e; ++i) { 841590Srgrimes unsigned Reg = LocalDefs[i]; 851590Srgrimes for (MCSubRegIterator Subreg(Reg, TRI, /*IncludeSelf=*/true); 861590Srgrimes Subreg.isValid(); ++Subreg) 871590Srgrimes Defs.insert(*Subreg); 8850452Ssheldonh if (Reg == ARM::CPSR) 8950452Ssheldonh continue; 9050452Ssheldonh } 9150452Ssheldonh} 9250452Ssheldonh 9350452Ssheldonhstatic bool isCopy(MachineInstr *MI) { 9450452Ssheldonh switch (MI->getOpcode()) { 9550452Ssheldonh default: 9650452Ssheldonh return false; 9750452Ssheldonh case ARM::MOVr: 9850452Ssheldonh case ARM::MOVr_TC: 9950452Ssheldonh case ARM::tMOVr: 10050452Ssheldonh case ARM::t2MOVr: 1011590Srgrimes return true; 10250452Ssheldonh } 1031590Srgrimes} 1041590Srgrimes 1051590Srgrimesbool 1061590SrgrimesThumb2ITBlockPass::MoveCopyOutOfITBlock(MachineInstr *MI, 1071590Srgrimes ARMCC::CondCodes CC, ARMCC::CondCodes OCC, 1081590Srgrimes SmallSet<unsigned, 4> &Defs, 10927647Scharnier SmallSet<unsigned, 4> &Uses) { 110102944Sdwmalone if (!isCopy(MI)) 1111590Srgrimes return false; 11250452Ssheldonh // llvm models select's as two-address instructions. That means a copy 1131590Srgrimes // is inserted before a t2MOVccr, etc. If the copy is scheduled in 1141590Srgrimes // between selects we would end up creating multiple IT blocks. 115 assert(MI->getOperand(0).getSubReg() == 0 && 116 MI->getOperand(1).getSubReg() == 0 && 117 "Sub-register indices still around?"); 118 119 unsigned DstReg = MI->getOperand(0).getReg(); 120 unsigned SrcReg = MI->getOperand(1).getReg(); 121 122 // First check if it's safe to move it. 123 if (Uses.count(DstReg) || Defs.count(SrcReg)) 124 return false; 125 126 // If the CPSR is defined by this copy, then we don't want to move it. E.g., 127 // if we have: 128 // 129 // movs r1, r1 130 // rsb r1, 0 131 // movs r2, r2 132 // rsb r2, 0 133 // 134 // we don't want this to be converted to: 135 // 136 // movs r1, r1 137 // movs r2, r2 138 // itt mi 139 // rsb r1, 0 140 // rsb r2, 0 141 // 142 const MCInstrDesc &MCID = MI->getDesc(); 143 if (MI->hasOptionalDef() && 144 MI->getOperand(MCID.getNumOperands() - 1).getReg() == ARM::CPSR) 145 return false; 146 147 // Then peek at the next instruction to see if it's predicated on CC or OCC. 148 // If not, then there is nothing to be gained by moving the copy. 149 MachineBasicBlock::iterator I = MI; ++I; 150 MachineBasicBlock::iterator E = MI->getParent()->end(); 151 while (I != E && I->isDebugValue()) 152 ++I; 153 if (I != E) { 154 unsigned NPredReg = 0; 155 ARMCC::CondCodes NCC = getITInstrPredicate(I, NPredReg); 156 if (NCC == CC || NCC == OCC) 157 return true; 158 } 159 return false; 160} 161 162bool Thumb2ITBlockPass::InsertITInstructions(MachineBasicBlock &MBB) { 163 bool Modified = false; 164 165 SmallSet<unsigned, 4> Defs; 166 SmallSet<unsigned, 4> Uses; 167 MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end(); 168 while (MBBI != E) { 169 MachineInstr *MI = &*MBBI; 170 DebugLoc dl = MI->getDebugLoc(); 171 unsigned PredReg = 0; 172 ARMCC::CondCodes CC = getITInstrPredicate(MI, PredReg); 173 if (CC == ARMCC::AL) { 174 ++MBBI; 175 continue; 176 } 177 178 Defs.clear(); 179 Uses.clear(); 180 TrackDefUses(MI, Defs, Uses, TRI); 181 182 // Insert an IT instruction. 183 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII->get(ARM::t2IT)) 184 .addImm(CC); 185 186 // Add implicit use of ITSTATE to IT block instructions. 187 MI->addOperand(MachineOperand::CreateReg(ARM::ITSTATE, false/*ifDef*/, 188 true/*isImp*/, false/*isKill*/)); 189 190 MachineInstr *LastITMI = MI; 191 MachineBasicBlock::iterator InsertPos = MIB; 192 ++MBBI; 193 194 // Form IT block. 195 ARMCC::CondCodes OCC = ARMCC::getOppositeCondition(CC); 196 unsigned Mask = 0, Pos = 3; 197 198 // v8 IT blocks are limited to one conditional op unless -arm-no-restrict-it 199 // is set: skip the loop 200 if (!restrictIT) { 201 // Branches, including tricky ones like LDM_RET, need to end an IT 202 // block so check the instruction we just put in the block. 203 for (; MBBI != E && Pos && 204 (!MI->isBranch() && !MI->isReturn()) ; ++MBBI) { 205 if (MBBI->isDebugValue()) 206 continue; 207 208 MachineInstr *NMI = &*MBBI; 209 MI = NMI; 210 211 unsigned NPredReg = 0; 212 ARMCC::CondCodes NCC = getITInstrPredicate(NMI, NPredReg); 213 if (NCC == CC || NCC == OCC) { 214 Mask |= (NCC & 1) << Pos; 215 // Add implicit use of ITSTATE. 216 NMI->addOperand(MachineOperand::CreateReg(ARM::ITSTATE, false/*ifDef*/, 217 true/*isImp*/, false/*isKill*/)); 218 LastITMI = NMI; 219 } else { 220 if (NCC == ARMCC::AL && 221 MoveCopyOutOfITBlock(NMI, CC, OCC, Defs, Uses)) { 222 --MBBI; 223 MBB.remove(NMI); 224 MBB.insert(InsertPos, NMI); 225 ++NumMovedInsts; 226 continue; 227 } 228 break; 229 } 230 TrackDefUses(NMI, Defs, Uses, TRI); 231 --Pos; 232 } 233 } 234 235 // Finalize IT mask. 236 Mask |= (1 << Pos); 237 // Tag along (firstcond[0] << 4) with the mask. 238 Mask |= (CC & 1) << 4; 239 MIB.addImm(Mask); 240 241 // Last instruction in IT block kills ITSTATE. 242 LastITMI->findRegisterUseOperand(ARM::ITSTATE)->setIsKill(); 243 244 // Finalize the bundle. 245 MachineBasicBlock::instr_iterator LI = LastITMI; 246 finalizeBundle(MBB, InsertPos.getInstrIterator(), std::next(LI)); 247 248 Modified = true; 249 ++NumITs; 250 } 251 252 return Modified; 253} 254 255bool Thumb2ITBlockPass::runOnMachineFunction(MachineFunction &Fn) { 256 const TargetMachine &TM = Fn.getTarget(); 257 AFI = Fn.getInfo<ARMFunctionInfo>(); 258 TII = static_cast<const Thumb2InstrInfo*>(TM.getInstrInfo()); 259 TRI = TM.getRegisterInfo(); 260 restrictIT = TM.getSubtarget<ARMSubtarget>().restrictIT(); 261 262 if (!AFI->isThumbFunction()) 263 return false; 264 265 bool Modified = false; 266 for (MachineFunction::iterator MFI = Fn.begin(), E = Fn.end(); MFI != E; ) { 267 MachineBasicBlock &MBB = *MFI; 268 ++MFI; 269 Modified |= InsertITInstructions(MBB); 270 } 271 272 if (Modified) 273 AFI->setHasITBlocks(true); 274 275 return Modified; 276} 277 278/// createThumb2ITBlockPass - Returns an instance of the Thumb2 IT blocks 279/// insertion pass. 280FunctionPass *llvm::createThumb2ITBlockPass() { 281 return new Thumb2ITBlockPass(); 282} 283