Thumb1FrameLowering.cpp revision 221345 
1//======- Thumb1FrameLowering.cpp - Thumb1 Frame Information ---*- C++ -*-====//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the Thumb1 implementation of TargetFrameLowering class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "Thumb1FrameLowering.h"
15#include "ARMBaseInstrInfo.h"
16#include "ARMMachineFunctionInfo.h"
17#include "llvm/CodeGen/MachineFrameInfo.h"
18#include "llvm/CodeGen/MachineFunction.h"
19#include "llvm/CodeGen/MachineInstrBuilder.h"
20#include "llvm/CodeGen/MachineRegisterInfo.h"
21
22using namespace llvm;
23
24bool Thumb1FrameLowering::hasReservedCallFrame(const MachineFunction &MF) const {
25  const MachineFrameInfo *FFI = MF.getFrameInfo();
26  unsigned CFSize = FFI->getMaxCallFrameSize();
27  // It's not always a good idea to include the call frame as part of the
28  // stack frame. ARM (especially Thumb) has small immediate offset to
29  // address the stack frame. So a large call frame can cause poor codegen
30  // and may even makes it impossible to scavenge a register.
31  if (CFSize >= ((1 << 8) - 1) * 4 / 2) // Half of imm8 * 4
32    return false;
33
34  return !MF.getFrameInfo()->hasVarSizedObjects();
35}
36
37static void
38emitSPUpdate(MachineBasicBlock &MBB,
39             MachineBasicBlock::iterator &MBBI,
40             const TargetInstrInfo &TII, DebugLoc dl,
41             const Thumb1RegisterInfo &MRI,
42             int NumBytes, unsigned MIFlags = MachineInstr::NoFlags)  {
43  emitThumbRegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes, TII,
44                            MRI, MIFlags);
45}
46
47void Thumb1FrameLowering::emitPrologue(MachineFunction &MF) const {
48  MachineBasicBlock &MBB = MF.front();
49  MachineBasicBlock::iterator MBBI = MBB.begin();
50  MachineFrameInfo  *MFI = MF.getFrameInfo();
51  ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
52  const Thumb1RegisterInfo *RegInfo =
53    static_cast<const Thumb1RegisterInfo*>(MF.getTarget().getRegisterInfo());
54  const Thumb1InstrInfo &TII =
55    *static_cast<const Thumb1InstrInfo*>(MF.getTarget().getInstrInfo());
56
57  unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize();
58  unsigned NumBytes = MFI->getStackSize();
59  const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
60  DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
61  unsigned FramePtr = RegInfo->getFrameRegister(MF);
62  unsigned BasePtr = RegInfo->getBaseRegister();
63
64  // Thumb add/sub sp, imm8 instructions implicitly multiply the offset by 4.
65  NumBytes = (NumBytes + 3) & ~3;
66  MFI->setStackSize(NumBytes);
67
68  // Determine the sizes of each callee-save spill areas and record which frame
69  // belongs to which callee-save spill areas.
70  unsigned GPRCS1Size = 0, GPRCS2Size = 0, DPRCSSize = 0;
71  int FramePtrSpillFI = 0;
72
73  if (VARegSaveSize)
74    emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, -VARegSaveSize,
75                 MachineInstr::FrameSetup);
76
77  if (!AFI->hasStackFrame()) {
78    if (NumBytes != 0)
79      emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, -NumBytes,
80                   MachineInstr::FrameSetup);
81    return;
82  }
83
84  for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
85    unsigned Reg = CSI[i].getReg();
86    int FI = CSI[i].getFrameIdx();
87    switch (Reg) {
88    case ARM::R4:
89    case ARM::R5:
90    case ARM::R6:
91    case ARM::R7:
92    case ARM::LR:
93      if (Reg == FramePtr)
94        FramePtrSpillFI = FI;
95      AFI->addGPRCalleeSavedArea1Frame(FI);
96      GPRCS1Size += 4;
97      break;
98    case ARM::R8:
99    case ARM::R9:
100    case ARM::R10:
101    case ARM::R11:
102      if (Reg == FramePtr)
103        FramePtrSpillFI = FI;
104      if (STI.isTargetDarwin()) {
105        AFI->addGPRCalleeSavedArea2Frame(FI);
106        GPRCS2Size += 4;
107      } else {
108        AFI->addGPRCalleeSavedArea1Frame(FI);
109        GPRCS1Size += 4;
110      }
111      break;
112    default:
113      AFI->addDPRCalleeSavedAreaFrame(FI);
114      DPRCSSize += 8;
115    }
116  }
117
118  if (MBBI != MBB.end() && MBBI->getOpcode() == ARM::tPUSH) {
119    ++MBBI;
120    if (MBBI != MBB.end())
121      dl = MBBI->getDebugLoc();
122  }
123
124  // Determine starting offsets of spill areas.
125  unsigned DPRCSOffset  = NumBytes - (GPRCS1Size + GPRCS2Size + DPRCSSize);
126  unsigned GPRCS2Offset = DPRCSOffset + DPRCSSize;
127  unsigned GPRCS1Offset = GPRCS2Offset + GPRCS2Size;
128  AFI->setFramePtrSpillOffset(MFI->getObjectOffset(FramePtrSpillFI) + NumBytes);
129  AFI->setGPRCalleeSavedArea1Offset(GPRCS1Offset);
130  AFI->setGPRCalleeSavedArea2Offset(GPRCS2Offset);
131  AFI->setDPRCalleeSavedAreaOffset(DPRCSOffset);
132  NumBytes = DPRCSOffset;
133
134  // Adjust FP so it point to the stack slot that contains the previous FP.
135  if (hasFP(MF)) {
136    BuildMI(MBB, MBBI, dl, TII.get(ARM::tADDrSPi), FramePtr)
137      .addFrameIndex(FramePtrSpillFI).addImm(0)
138      .setMIFlags(MachineInstr::FrameSetup);
139    if (NumBytes > 7)
140      // If offset is > 7 then sp cannot be adjusted in a single instruction,
141      // try restoring from fp instead.
142      AFI->setShouldRestoreSPFromFP(true);
143  }
144
145  if (NumBytes)
146    // Insert it after all the callee-save spills.
147    emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, -NumBytes,
148                 MachineInstr::FrameSetup);
149
150  if (STI.isTargetELF() && hasFP(MF))
151    MFI->setOffsetAdjustment(MFI->getOffsetAdjustment() -
152                             AFI->getFramePtrSpillOffset());
153
154  AFI->setGPRCalleeSavedArea1Size(GPRCS1Size);
155  AFI->setGPRCalleeSavedArea2Size(GPRCS2Size);
156  AFI->setDPRCalleeSavedAreaSize(DPRCSSize);
157
158  // If we need a base pointer, set it up here. It's whatever the value
159  // of the stack pointer is at this point. Any variable size objects
160  // will be allocated after this, so we can still use the base pointer
161  // to reference locals.
162  if (RegInfo->hasBasePointer(MF))
163    BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVgpr2gpr), BasePtr).addReg(ARM::SP);
164
165  // If the frame has variable sized objects then the epilogue must restore
166  // the sp from fp. We can assume there's an FP here since hasFP already
167  // checks for hasVarSizedObjects.
168  if (MFI->hasVarSizedObjects())
169    AFI->setShouldRestoreSPFromFP(true);
170}
171
172static bool isCalleeSavedRegister(unsigned Reg, const unsigned *CSRegs) {
173  for (unsigned i = 0; CSRegs[i]; ++i)
174    if (Reg == CSRegs[i])
175      return true;
176  return false;
177}
178
179static bool isCSRestore(MachineInstr *MI, const unsigned *CSRegs) {
180  if (MI->getOpcode() == ARM::tRestore &&
181      MI->getOperand(1).isFI() &&
182      isCalleeSavedRegister(MI->getOperand(0).getReg(), CSRegs))
183    return true;
184  else if (MI->getOpcode() == ARM::tPOP) {
185    // The first two operands are predicates. The last two are
186    // imp-def and imp-use of SP. Check everything in between.
187    for (int i = 2, e = MI->getNumOperands() - 2; i != e; ++i)
188      if (!isCalleeSavedRegister(MI->getOperand(i).getReg(), CSRegs))
189        return false;
190    return true;
191  }
192  return false;
193}
194
195void Thumb1FrameLowering::emitEpilogue(MachineFunction &MF,
196                                   MachineBasicBlock &MBB) const {
197  MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr();
198  assert((MBBI->getOpcode() == ARM::tBX_RET ||
199          MBBI->getOpcode() == ARM::tPOP_RET) &&
200         "Can only insert epilog into returning blocks");
201  DebugLoc dl = MBBI->getDebugLoc();
202  MachineFrameInfo *MFI = MF.getFrameInfo();
203  ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
204  const Thumb1RegisterInfo *RegInfo =
205    static_cast<const Thumb1RegisterInfo*>(MF.getTarget().getRegisterInfo());
206  const Thumb1InstrInfo &TII =
207    *static_cast<const Thumb1InstrInfo*>(MF.getTarget().getInstrInfo());
208
209  unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize();
210  int NumBytes = (int)MFI->getStackSize();
211  const unsigned *CSRegs = RegInfo->getCalleeSavedRegs();
212  unsigned FramePtr = RegInfo->getFrameRegister(MF);
213
214  if (!AFI->hasStackFrame()) {
215    if (NumBytes != 0)
216      emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, NumBytes);
217  } else {
218    // Unwind MBBI to point to first LDR / VLDRD.
219    if (MBBI != MBB.begin()) {
220      do
221        --MBBI;
222      while (MBBI != MBB.begin() && isCSRestore(MBBI, CSRegs));
223      if (!isCSRestore(MBBI, CSRegs))
224        ++MBBI;
225    }
226
227    // Move SP to start of FP callee save spill area.
228    NumBytes -= (AFI->getGPRCalleeSavedArea1Size() +
229                 AFI->getGPRCalleeSavedArea2Size() +
230                 AFI->getDPRCalleeSavedAreaSize());
231
232    if (AFI->shouldRestoreSPFromFP()) {
233      NumBytes = AFI->getFramePtrSpillOffset() - NumBytes;
234      // Reset SP based on frame pointer only if the stack frame extends beyond
235      // frame pointer stack slot, the target is ELF and the function has FP, or
236      // the target uses var sized objects.
237      if (NumBytes) {
238        assert(MF.getRegInfo().isPhysRegUsed(ARM::R4) &&
239               "No scratch register to restore SP from FP!");
240        emitThumbRegPlusImmediate(MBB, MBBI, dl, ARM::R4, FramePtr, -NumBytes,
241                                  TII, *RegInfo);
242        BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVtgpr2gpr), ARM::SP)
243          .addReg(ARM::R4);
244      } else
245        BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVtgpr2gpr), ARM::SP)
246          .addReg(FramePtr);
247    } else {
248      if (MBBI->getOpcode() == ARM::tBX_RET &&
249          &MBB.front() != MBBI &&
250          prior(MBBI)->getOpcode() == ARM::tPOP) {
251        MachineBasicBlock::iterator PMBBI = prior(MBBI);
252        emitSPUpdate(MBB, PMBBI, TII, dl, *RegInfo, NumBytes);
253      } else
254        emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, NumBytes);
255    }
256  }
257
258  if (VARegSaveSize) {
259    // Unlike T2 and ARM mode, the T1 pop instruction cannot restore
260    // to LR, and we can't pop the value directly to the PC since
261    // we need to update the SP after popping the value. Therefore, we
262    // pop the old LR into R3 as a temporary.
263
264    // Move back past the callee-saved register restoration
265    while (MBBI != MBB.end() && isCSRestore(MBBI, CSRegs))
266      ++MBBI;
267    // Epilogue for vararg functions: pop LR to R3 and branch off it.
268    AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tPOP)))
269      .addReg(ARM::R3, RegState::Define);
270
271    emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, VARegSaveSize);
272
273    BuildMI(MBB, MBBI, dl, TII.get(ARM::tBX_RET_vararg))
274      .addReg(ARM::R3, RegState::Kill);
275    // erase the old tBX_RET instruction
276    MBB.erase(MBBI);
277  }
278}
279
280bool Thumb1FrameLowering::
281spillCalleeSavedRegisters(MachineBasicBlock &MBB,
282                          MachineBasicBlock::iterator MI,
283                          const std::vector<CalleeSavedInfo> &CSI,
284                          const TargetRegisterInfo *TRI) const {
285  if (CSI.empty())
286    return false;
287
288  DebugLoc DL;
289  MachineFunction &MF = *MBB.getParent();
290  const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
291
292  if (MI != MBB.end()) DL = MI->getDebugLoc();
293
294  MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(ARM::tPUSH));
295  AddDefaultPred(MIB);
296  for (unsigned i = CSI.size(); i != 0; --i) {
297    unsigned Reg = CSI[i-1].getReg();
298    bool isKill = true;
299
300    // Add the callee-saved register as live-in unless it's LR and
301    // @llvm.returnaddress is called. If LR is returned for @llvm.returnaddress
302    // then it's already added to the function and entry block live-in sets.
303    if (Reg == ARM::LR) {
304      MachineFunction &MF = *MBB.getParent();
305      if (MF.getFrameInfo()->isReturnAddressTaken() &&
306          MF.getRegInfo().isLiveIn(Reg))
307        isKill = false;
308    }
309
310    if (isKill)
311      MBB.addLiveIn(Reg);
312
313    MIB.addReg(Reg, getKillRegState(isKill));
314  }
315  MIB.setMIFlags(MachineInstr::FrameSetup);
316  return true;
317}
318
319bool Thumb1FrameLowering::
320restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
321                            MachineBasicBlock::iterator MI,
322                            const std::vector<CalleeSavedInfo> &CSI,
323                            const TargetRegisterInfo *TRI) const {
324  if (CSI.empty())
325    return false;
326
327  MachineFunction &MF = *MBB.getParent();
328  ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
329  const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
330
331  bool isVarArg = AFI->getVarArgsRegSaveSize() > 0;
332  DebugLoc DL = MI->getDebugLoc();
333  MachineInstrBuilder MIB = BuildMI(MF, DL, TII.get(ARM::tPOP));
334  AddDefaultPred(MIB);
335
336  bool NumRegs = false;
337  for (unsigned i = CSI.size(); i != 0; --i) {
338    unsigned Reg = CSI[i-1].getReg();
339    if (Reg == ARM::LR) {
340      // Special epilogue for vararg functions. See emitEpilogue
341      if (isVarArg)
342        continue;
343      Reg = ARM::PC;
344      (*MIB).setDesc(TII.get(ARM::tPOP_RET));
345      MI = MBB.erase(MI);
346    }
347    MIB.addReg(Reg, getDefRegState(true));
348    NumRegs = true;
349  }
350
351  // It's illegal to emit pop instruction without operands.
352  if (NumRegs)
353    MBB.insert(MI, &*MIB);
354  else
355    MF.DeleteMachineInstr(MIB);
356
357  return true;
358}
359