1311116Sdim//==- ARMScheduleR52.td - Cortex-R52 Scheduling Definitions -*- tablegen -*-=// 2311116Sdim// 3353358Sdim// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4353358Sdim// See https://llvm.org/LICENSE.txt for license information. 5353358Sdim// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6311116Sdim// 7311116Sdim//===----------------------------------------------------------------------===// 8311116Sdim// 9311116Sdim// This file defines the SchedRead/Write data for the ARM Cortex-R52 processor. 10311116Sdim// 11311116Sdim//===----------------------------------------------------------------------===// 12311116Sdim 13311116Sdim// ===---------------------------------------------------------------------===// 14311116Sdim// The Cortex-R52 is an in-order pipelined superscalar microprocessor with 15311116Sdim// a 8 stage pipeline. It can issue maximum two instructions in each cycle. 16311116Sdim// There are two ALUs, one LDST, one MUL and a non-pipelined integer DIV. 17311116Sdim// A number of forwarding paths enable results of computations to be input 18311116Sdim// to subsequent operations before they are written to registers. 19311116Sdim// This scheduler is a MachineScheduler. See TargetSchedule.td for details. 20311116Sdim 21311116Sdimdef CortexR52Model : SchedMachineModel { 22311116Sdim let MicroOpBufferSize = 0; // R52 is in-order processor 23311116Sdim let IssueWidth = 2; // 2 micro-ops dispatched per cycle 24311116Sdim let LoadLatency = 1; // Optimistic, assuming no misses 25311116Sdim let MispredictPenalty = 8; // A branch direction mispredict, including PFU 26311116Sdim let CompleteModel = 0; // Covers instructions applicable to cortex-r52. 27311116Sdim} 28311116Sdim 29311116Sdim 30311116Sdim//===----------------------------------------------------------------------===// 31311116Sdim// Define each kind of processor resource and number available. 32311116Sdim 33311116Sdim// Modeling each pipeline as a ProcResource using the BufferSize = 0 since 34311116Sdim// Cortex-R52 is an in-order processor. 35311116Sdim 36311116Sdimdef R52UnitALU : ProcResource<2> { let BufferSize = 0; } // Int ALU 37311116Sdimdef R52UnitMAC : ProcResource<1> { let BufferSize = 0; } // Int MAC 38311116Sdimdef R52UnitDiv : ProcResource<1> { let BufferSize = 0; } // Int Division 39311116Sdimdef R52UnitLd : ProcResource<1> { let BufferSize = 0; } // Load/Store 40311116Sdimdef R52UnitB : ProcResource<1> { let BufferSize = 0; } // Branch 41311116Sdimdef R52UnitFPALU : ProcResource<2> { let BufferSize = 0; } // FP ALU 42311116Sdimdef R52UnitFPMUL : ProcResource<2> { let BufferSize = 0; } // FP MUL 43311116Sdimdef R52UnitFPDIV : ProcResource<1> { let BufferSize = 0; } // FP DIV 44311116Sdim 45311116Sdim// Cortex-R52 specific SchedReads 46311116Sdimdef R52Read_ISS : SchedRead; 47311116Sdimdef R52Read_EX1 : SchedRead; 48311116Sdimdef R52Read_EX2 : SchedRead; 49311116Sdimdef R52Read_WRI : SchedRead; 50311116Sdimdef R52Read_F0 : SchedRead; // F0 maps to ISS stage of integer pipe 51311116Sdimdef R52Read_F1 : SchedRead; 52311116Sdimdef R52Read_F2 : SchedRead; 53311116Sdim 54311116Sdim 55311116Sdim//===----------------------------------------------------------------------===// 56311116Sdim// Subtarget-specific SchedWrite types which map ProcResources and set latency. 57311116Sdim 58311116Sdimlet SchedModel = CortexR52Model in { 59311116Sdim 60311116Sdim// ALU - Write occurs in Late EX2 (independent of whether shift was required) 61311116Sdimdef : WriteRes<WriteALU, [R52UnitALU]> { let Latency = 3; } 62311116Sdimdef : WriteRes<WriteALUsi, [R52UnitALU]> { let Latency = 3; } 63311116Sdimdef : WriteRes<WriteALUsr, [R52UnitALU]> { let Latency = 3; } 64311116Sdimdef : WriteRes<WriteALUSsr, [R52UnitALU]> { let Latency = 3; } 65311116Sdim 66311116Sdim// Compares 67311116Sdimdef : WriteRes<WriteCMP, [R52UnitALU]> { let Latency = 0; } 68311116Sdimdef : WriteRes<WriteCMPsi, [R52UnitALU]> { let Latency = 0; } 69311116Sdimdef : WriteRes<WriteCMPsr, [R52UnitALU]> { let Latency = 0; } 70311116Sdim 71321369Sdim// Multiply - aliased to sub-target specific later 72321369Sdim 73311116Sdim// Div - may stall 0-9 cycles depending on input (i.e. WRI+(0-9)/2) 74321369Sdimdef : WriteRes<WriteDIV, [R52UnitDiv]> { 75321369Sdim let Latency = 8; let ResourceCycles = [8]; // non-pipelined 76311116Sdim} 77311116Sdim 78311116Sdim// Branches - LR written in Late EX2 79311116Sdimdef : WriteRes<WriteBr, [R52UnitB]> { let Latency = 0; } 80311116Sdimdef : WriteRes<WriteBrL, [R52UnitB]> { let Latency = 0; } 81311116Sdimdef : WriteRes<WriteBrTbl, [R52UnitALU]> { let Latency = 0; } 82311116Sdim 83311116Sdim// Misc 84311116Sdimdef : WriteRes<WriteNoop, []> { let Latency = 0; let NumMicroOps = 0; } 85311116Sdim 86321369Sdim// Integer pipeline by-passes 87311116Sdimdef : ReadAdvance<ReadALU, 1>; // Operand needed in EX1 stage 88311116Sdimdef : ReadAdvance<ReadALUsr, 0>; // Shift operands needed in ISS 89321369Sdimdef : ReadAdvance<ReadMUL, 0>; 90321369Sdimdef : ReadAdvance<ReadMAC, 0>; 91311116Sdim 92321369Sdim// Floating-point. Map target-defined SchedReadWrites to subtarget 93321369Sdimdef : WriteRes<WriteFPMUL32, [R52UnitFPMUL]> { let Latency = 6; } 94311116Sdim 95321369Sdimdef : WriteRes<WriteFPMUL64, [R52UnitFPMUL, R52UnitFPMUL]> { 96321369Sdim let Latency = 6; 97321369Sdim} 98321369Sdim 99321369Sdimdef : WriteRes<WriteFPMAC32, [R52UnitFPMUL, R52UnitFPALU]> { 100321369Sdim let Latency = 11; // as it is internally two insns (MUL then ADD) 101321369Sdim} 102321369Sdim 103321369Sdimdef : WriteRes<WriteFPMAC64, [R52UnitFPMUL, R52UnitFPMUL, 104321369Sdim R52UnitFPALU, R52UnitFPALU]> { 105321369Sdim let Latency = 11; 106321369Sdim} 107321369Sdim 108321369Sdimdef : WriteRes<WriteFPDIV32, [R52UnitDiv]> { 109321369Sdim let Latency = 7; // FP div takes fixed #cycles 110321369Sdim let ResourceCycles = [7]; // is not pipelined 111321369Sdim} 112321369Sdim 113321369Sdimdef : WriteRes<WriteFPDIV64, [R52UnitDiv]> { 114321369Sdim let Latency = 17; 115321369Sdim let ResourceCycles = [17]; 116321369Sdim} 117321369Sdim 118321369Sdimdef : WriteRes<WriteFPSQRT32, [R52UnitDiv]> { let Latency = 7; } 119321369Sdimdef : WriteRes<WriteFPSQRT64, [R52UnitDiv]> { let Latency = 17; } 120321369Sdim 121321369Sdim// Overriden via InstRW for this processor. 122321369Sdimdef : WriteRes<WriteVST1, []>; 123321369Sdimdef : WriteRes<WriteVST2, []>; 124321369Sdimdef : WriteRes<WriteVST3, []>; 125321369Sdimdef : WriteRes<WriteVST4, []>; 126321369Sdim 127321369Sdimdef : ReadAdvance<ReadFPMUL, 1>; // mul operand read in F1 128321369Sdimdef : ReadAdvance<ReadFPMAC, 1>; // fp-mac operand read in F1 129321369Sdim 130311116Sdim//===----------------------------------------------------------------------===// 131311116Sdim// Subtarget-specific SchedReadWrites. 132311116Sdim 133311116Sdim// Forwarding information - based on when an operand is read 134311116Sdimdef : ReadAdvance<R52Read_ISS, 0>; 135311116Sdimdef : ReadAdvance<R52Read_EX1, 1>; 136311116Sdimdef : ReadAdvance<R52Read_EX2, 2>; 137311116Sdimdef : ReadAdvance<R52Read_F0, 0>; 138311116Sdimdef : ReadAdvance<R52Read_F1, 1>; 139311116Sdimdef : ReadAdvance<R52Read_F2, 2>; 140311116Sdim 141311116Sdim 142311116Sdim// Cortex-R52 specific SchedWrites for use with InstRW 143311116Sdimdef R52WriteMAC : SchedWriteRes<[R52UnitMAC]> { let Latency = 4; } 144321369Sdimdef R52WriteMACHi : SchedWriteRes<[R52UnitMAC]> { 145321369Sdim let Latency = 4; let NumMicroOps = 0; 146321369Sdim} 147311116Sdimdef R52WriteDIV : SchedWriteRes<[R52UnitDiv]> { 148311116Sdim let Latency = 8; let ResourceCycles = [8]; // not pipelined 149311116Sdim} 150311116Sdimdef R52WriteLd : SchedWriteRes<[R52UnitLd]> { let Latency = 4; } 151311116Sdimdef R52WriteST : SchedWriteRes<[R52UnitLd]> { let Latency = 4; } 152311116Sdimdef R52WriteAdr : SchedWriteRes<[]> { let Latency = 0; } 153311116Sdimdef R52WriteCC : SchedWriteRes<[]> { let Latency = 0; } 154311116Sdimdef R52WriteALU_EX1 : SchedWriteRes<[R52UnitALU]> { let Latency = 2; } 155311116Sdimdef R52WriteALU_EX2 : SchedWriteRes<[R52UnitALU]> { let Latency = 3; } 156311116Sdimdef R52WriteALU_WRI : SchedWriteRes<[R52UnitALU]> { let Latency = 4; } 157311116Sdim 158311116Sdimdef R52WriteNoRSRC_EX2 : SchedWriteRes<[]> { let Latency = 3; } 159311116Sdimdef R52WriteNoRSRC_WRI : SchedWriteRes<[]> { let Latency = 4; } 160311116Sdim 161321369Sdim// Alias generics to sub-target specific 162321369Sdimdef : SchedAlias<WriteMUL16, R52WriteMAC>; 163321369Sdimdef : SchedAlias<WriteMUL32, R52WriteMAC>; 164321369Sdimdef : SchedAlias<WriteMUL64Lo, R52WriteMAC>; 165321369Sdimdef : SchedAlias<WriteMUL64Hi, R52WriteMACHi>; 166321369Sdimdef : SchedAlias<WriteMAC16, R52WriteMAC>; 167321369Sdimdef : SchedAlias<WriteMAC32, R52WriteMAC>; 168321369Sdimdef : SchedAlias<WriteMAC64Lo, R52WriteMAC>; 169321369Sdimdef : SchedAlias<WriteMAC64Hi, R52WriteMACHi>; 170321369Sdimdef : SchedAlias<WritePreLd, R52WriteLd>; 171321369Sdimdef : SchedAlias<WriteLd, R52WriteLd>; 172321369Sdimdef : SchedAlias<WriteST, R52WriteST>; 173321369Sdim 174311116Sdimdef R52WriteFPALU_F3 : SchedWriteRes<[R52UnitFPALU]> { let Latency = 4; } 175311116Sdimdef R52Write2FPALU_F3 : SchedWriteRes<[R52UnitFPALU, R52UnitFPALU]> { 176311116Sdim let Latency = 4; 177311116Sdim} 178311116Sdimdef R52WriteFPALU_F4 : SchedWriteRes<[R52UnitFPALU]> { let Latency = 5; } 179311116Sdimdef R52Write2FPALU_F4 : SchedWriteRes<[R52UnitFPALU, R52UnitFPALU]> { 180311116Sdim let Latency = 5; 181311116Sdim} 182311116Sdimdef R52WriteFPALU_F5 : SchedWriteRes<[R52UnitFPALU]> { let Latency = 6; } 183311116Sdimdef R52Write2FPALU_F5 : SchedWriteRes<[R52UnitFPALU, R52UnitFPALU]> { 184311116Sdim let Latency = 6; 185311116Sdim} 186311116Sdimdef R52WriteFPMUL_F5 : SchedWriteRes<[R52UnitFPMUL]> { let Latency = 6; } 187311116Sdimdef R52Write2FPMUL_F5 : SchedWriteRes<[R52UnitFPMUL, R52UnitFPMUL]> { 188311116Sdim let Latency = 6; 189311116Sdim} 190311116Sdimdef R52WriteFPMAC_F5 : SchedWriteRes<[R52UnitFPMUL, R52UnitFPALU]> { 191311116Sdim let Latency = 11; // as it is internally two insns (MUL then ADD) 192311116Sdim} 193311116Sdimdef R52Write2FPMAC_F5 : SchedWriteRes<[R52UnitFPMUL, R52UnitFPMUL, 194311116Sdim R52UnitFPALU, R52UnitFPALU]> { 195311116Sdim let Latency = 11; 196311116Sdim} 197311116Sdim 198311116Sdimdef R52WriteFPLd_F4 : SchedWriteRes<[R52UnitLd]> { let Latency = 5; } 199311116Sdimdef R52WriteFPST_F4 : SchedWriteRes<[R52UnitLd]> { let Latency = 5; } 200311116Sdim 201321369Sdim//===----------------------------------------------------------------------===// 202321369Sdim// Floating-point. Map target defined SchedReadWrites to processor specific ones 203321369Sdim// 204321369Sdimdef : SchedAlias<WriteFPCVT, R52WriteFPALU_F5>; 205321369Sdimdef : SchedAlias<WriteFPMOV, R52WriteFPALU_F3>; 206321369Sdimdef : SchedAlias<WriteFPALU32, R52WriteFPALU_F5>; 207321369Sdimdef : SchedAlias<WriteFPALU64, R52WriteFPALU_F5>; 208311116Sdim 209311116Sdim//===----------------------------------------------------------------------===// 210321369Sdim// Subtarget-specific overrides. Map opcodes to list of SchedReadWrites types. 211321369Sdim// 212311116Sdimdef : InstRW<[WriteALU], (instrs COPY)>; 213311116Sdim 214311116Sdimdef : InstRW<[R52WriteALU_EX2, R52Read_EX1, R52Read_ISS], 215311116Sdim (instregex "SXTB", "SXTH", "SXTB16", "UXTB", "UXTH", "UXTB16", 216311116Sdim "t2SXTB", "t2SXTH", "t2SXTB16", "t2UXTB", "t2UXTH", "t2UXTB16")>; 217311116Sdim 218311116Sdimdef : InstRW<[R52WriteALU_EX1, R52Read_ISS], 219341825Sdim (instregex "MOVCCi32imm", "MOVi32imm", "t2MOVCCi", "t2MOVi")>; 220311116Sdimdef : InstRW<[R52WriteALU_EX2, R52Read_EX1], 221341825Sdim (instregex "MOV_ga_pcrel$")>; 222311116Sdimdef : InstRW<[R52WriteLd,R52Read_ISS], 223341825Sdim (instregex "MOV_ga_pcrel_ldr")>; 224311116Sdim 225311116Sdimdef : InstRW<[R52WriteALU_EX2, R52Read_EX1, R52Read_EX1], (instregex "SEL", "t2SEL")>; 226311116Sdim 227311116Sdimdef : InstRW< [R52WriteALU_EX2, R52Read_ISS, R52Read_ISS], 228311116Sdim (instregex "BFC", "BFI", "UBFX", "SBFX", "(t|t2)BFC", "(t|t2)BFI", 229311116Sdim "(t|t2)UBFX", "(t|t2)SBFX")>; 230311116Sdim 231311116Sdim// Saturating arithmetic 232311116Sdimdef : InstRW< [R52WriteALU_WRI, R52Read_EX1, R52Read_EX1], 233311116Sdim (instregex "QADD", "QSUB", "QDADD", "QDSUB", "SSAT", "SSAT16", "USAT", 234311116Sdim "QADD8", "QADD16", "QSUB8", "QSUB16", "QASX", "QSAX", 235311116Sdim "UQADD8", "UQADD16","UQSUB8","UQSUB16","UQASX","UQSAX", "t2QADD", 236311116Sdim "t2QSUB", "t2QDADD", "t2QDSUB", "t2SSAT", "t2SSAT16", "t2USAT", 237311116Sdim "t2QADD8", "t2QADD16", "t2QSUB8", "t2QSUB16", "t2QASX", "t2QSAX", 238311116Sdim "t2UQADD8", "t2UQADD16","t2UQSUB8","t2UQSUB16","t2UQASX","t2UQSAX","t2ABS")>; 239311116Sdim 240311116Sdim// Parallel arithmetic 241311116Sdimdef : InstRW< [R52WriteALU_EX2, R52Read_EX1, R52Read_EX1], 242311116Sdim (instregex "SADD8", "SADD16", "SSUB8", "SSUB16", "SASX", "SSAX", 243311116Sdim "UADD8", "UADD16", "USUB8", "USUB16", "UASX", "USAX", "t2SADD8", 244311116Sdim "t2SADD16", "t2SSUB8", "t2SSUB16", "t2SASX", "t2SSAX", "t2UADD8", 245311116Sdim "t2UADD16", "t2USUB8", "t2USUB16", "t2UASX", "t2USAX")>; 246311116Sdim 247311116Sdim// Flag setting. 248311116Sdimdef : InstRW< [R52WriteALU_EX2, R52Read_EX1, R52Read_EX1], 249311116Sdim (instregex "SHADD8", "SHADD16", "SHSUB8", "SHSUB16", "SHASX", "SHSAX", 250311116Sdim "SXTAB", "SXTAB16", "SXTAH", "UHADD8", "UHADD16", "UHSUB8", "UHSUB16", 251311116Sdim "UHASX", "UHSAX", "UXTAB", "UXTAB16", "UXTAH", "t2SHADD8", "t2SHADD16", 252311116Sdim "t2SHSUB8", "t2SHSUB16", "t2SHASX", "t2SHSAX", "t2SXTAB", "t2SXTAB16", 253311116Sdim "t2SXTAH", "t2UHADD8", "t2UHADD16", "t2UHSUB8", "t2UHSUB16", "t2UHASX", 254311116Sdim "t2UHSAX", "t2UXTAB", "t2UXTAB16", "t2UXTAH")>; 255311116Sdim 256311116Sdim// Sum of Absolute Difference 257311116Sdimdef : InstRW< [R52WriteALU_WRI, R52Read_ISS, R52Read_ISS, R52Read_ISS], 258341825Sdim (instregex "USAD8", "t2USAD8", "USADA8", "t2USADA8") >; 259311116Sdim 260311116Sdim// Integer Multiply 261311116Sdimdef : InstRW<[R52WriteMAC, R52Read_ISS, R52Read_ISS], 262341825Sdim (instregex "MUL", "SMMUL", "SMMULR", "SMULBB", "SMULBT", 263341825Sdim "SMULTB", "SMULTT", "SMULWB", "SMULWT", "SMUSD", "SMUSDX", "t2MUL", 264311116Sdim "t2SMMUL", "t2SMMULR", "t2SMULBB", "t2SMULBT", "t2SMULTB", "t2SMULTT", 265311116Sdim "t2SMULWB", "t2SMULWT", "t2SMUSD")>; 266311116Sdim 267311116Sdim// Multiply Accumulate 268311116Sdim// Even for 64-bit accumulation (or Long), the single MAC is used (not ALUs). 269311116Sdim// The store pipeline is used partly for 64-bit operations. 270311116Sdimdef : InstRW<[R52WriteMAC, R52Read_ISS, R52Read_ISS, R52Read_ISS], 271341825Sdim (instregex "MLA", "MLS", "SMMLA", "SMMLAR", "SMMLS", "SMMLSR", 272341825Sdim "t2MLA", "t2MLS", "t2SMMLA", "t2SMMLAR", "t2SMMLS", "t2SMMLSR", 273311116Sdim "SMUAD", "SMUADX", "t2SMUAD", "t2SMUADX", 274311116Sdim "SMLABB", "SMLABT", "SMLATB", "SMLATT", "SMLSD", "SMLSDX", 275311116Sdim "SMLAWB", "SMLAWT", "t2SMLABB", "t2SMLABT", "t2SMLATB", "t2SMLATT", 276311116Sdim "t2SMLSD", "t2SMLSDX", "t2SMLAWB", "t2SMLAWT", 277311116Sdim "SMLAD", "SMLADX", "t2SMLAD", "t2SMLADX", 278311116Sdim "SMULL$", "UMULL$", "t2SMULL$", "t2UMULL$", 279341825Sdim "SMLAL", "UMLAL", "SMLALBT", 280311116Sdim "SMLALTB", "SMLALTT", "SMLALD", "SMLALDX", "SMLSLD", "SMLSLDX", 281341825Sdim "UMAAL", "t2SMLAL", "t2UMLAL", 282311116Sdim "t2SMLALBT", "t2SMLALTB", "t2SMLALTT", "t2SMLALD", "t2SMLALDX", 283311116Sdim "t2SMLSLD", "t2SMLSLDX", "t2UMAAL")>; 284311116Sdim 285311116Sdimdef : InstRW <[R52WriteDIV, R52Read_ISS, R52Read_ISS], 286321369Sdim (instregex "t2SDIV", "t2UDIV")>; 287311116Sdim 288311116Sdim// Loads (except POST) with SHL > 2, or ror, require 2 extra cycles. 289311116Sdim// However, that's non-trivial to specify, so we keep it uniform 290311116Sdimdef : InstRW<[R52WriteLd, R52Read_ISS, R52Read_ISS], 291311116Sdim (instregex "LDR(i12|rs)$", "LDRB(i12|rs)$", "t2LDR(i8|i12|s|pci)", 292311116Sdim "t2LDR(H|B)(i8|i12|s|pci)", "LDREX", "t2LDREX", 293311116Sdim "tLDR[BH](r|i|spi|pci|pciASM)", "tLDR(r|i|spi|pci|pciASM)", 294311116Sdim "LDRH$", "PICLDR$", "PICLDR(H|B)$", "LDRcp$", 295311116Sdim "PICLDRS(H|B)$", "t2LDRS(H|B)(i|r|p|s)", "LDRS(H|B)$", 296311116Sdim "t2LDRpci_pic", "tLDRS(B|H)", "t2LDRDi8", "LDRD$", "LDA", "t2LDA")>; 297311116Sdimdef : InstRW<[R52WriteLd, R52WriteAdr, R52Read_ISS, R52Read_ISS], 298311116Sdim (instregex "LD(RB|R)(_|T_)(POST|PRE)_(IMM|REG)", "LDRH(_PRE|_POST)", 299311116Sdim "LDRBT_POST$", "LDR(T|BT)_POST_(REG|IMM)", "LDRHT(i|r)", 300311116Sdim "t2LD(R|RB|RH)_(PRE|POST)", "t2LD(R|RB|RH)T", 301311116Sdim "LDR(SH|SB)(_POST|_PRE)", "t2LDR(SH|SB)(_POST|_PRE)", 302341825Sdim "LDRS(B|H)T(i|r)", "t2LDRS(B|H)T(i|r)?", 303311116Sdim "LDRD_(POST|PRE)", "t2LDRD_(POST|PRE)")>; 304311116Sdim 305311116Sdimdef : InstRW<[R52WriteALU_EX2, R52Read_EX1], (instregex "MOVS?sr", "t2MOVS?sr")>; 306311116Sdimdef : InstRW<[R52WriteALU_WRI, R52Read_EX2], (instregex "MOVT", "t2MOVT")>; 307311116Sdim 308341825Sdimdef : InstRW<[R52WriteALU_EX2, R52Read_EX1], (instregex "AD(C|D)S?ri", "ANDS?ri", 309311116Sdim "BICS?ri", "CLZ", "EORri", "MVNS?r", "ORRri", "RSBS?ri", "RSCri", "SBCri", 310311116Sdim "t2AD(C|D)S?ri", "t2ANDS?ri", "t2BICS?ri","t2CLZ", "t2EORri", "t2MVN", 311311116Sdim "t2ORRri", "t2RSBS?ri", "t2SBCri")>; 312311116Sdim 313311116Sdimdef : InstRW<[R52WriteALU_EX2, R52Read_EX1, R52Read_EX1], (instregex "AD(C|D)S?rr", 314341825Sdim "ANDS?rr", "BICS?rr", "CRC", "EORrr", "ORRrr", "RSBrr", "RSCrr", "SBCrr", 315311116Sdim "t2AD(C|D)S?rr", "t2ANDS?rr", "t2BICS?rr", "t2CRC", "t2EORrr", "t2SBCrr")>; 316311116Sdim 317311116Sdimdef : InstRW<[R52WriteALU_EX2, R52Read_EX1, R52Read_ISS], (instregex "AD(C|D)S?rsi", 318311116Sdim "ANDS?rsi", "BICS?rsi", "EORrsi", "ORRrsi", "RSBrsi", "RSCrsi", "SBCrsi", 319341825Sdim "t2AD(C|D)S?rs", "t2ANDS?rs", "t2BICS?rs", "t2EORrs", "t2ORRrs", "t2RSBrs", "t2SBCrs")>; 320311116Sdim 321311116Sdimdef : InstRW<[R52WriteALU_EX2, R52Read_EX1, R52Read_ISS, R52Read_ISS], 322311116Sdim (instregex "AD(C|D)S?rsr", "ANDS?rsr", "BICS?rsr", "EORrsr", "MVNS?sr", 323341825Sdim "ORRrsr", "RSBrsr", "RSCrsr", "SBCrsr")>; 324311116Sdim 325311116Sdimdef : InstRW<[R52WriteALU_EX1], 326341825Sdim (instregex "ADR", "MOVsi", "MVNS?s?i", "t2MOVS?si")>; 327311116Sdim 328311116Sdimdef : InstRW<[R52WriteALU_EX1, R52Read_ISS], (instregex "ASRi", "RORS?i")>; 329311116Sdimdef : InstRW<[R52WriteALU_EX1, R52Read_ISS, R52Read_ISS], 330311116Sdim (instregex "ASRr", "RORS?r", "LSR", "LSL")>; 331311116Sdim 332311116Sdimdef : InstRW<[R52WriteCC, R52Read_EX1], (instregex "CMPri", "CMNri")>; 333311116Sdimdef : InstRW<[R52WriteCC, R52Read_EX1, R52Read_EX1], (instregex "CMPrr", "CMNzrr")>; 334311116Sdimdef : InstRW<[R52WriteCC, R52Read_EX1, R52Read_ISS], (instregex "CMPrsi", "CMNzrsi")>; 335311116Sdimdef : InstRW<[R52WriteCC, R52Read_EX1, R52Read_ISS, R52Read_ISS], (instregex "CMPrsr", "CMNzrsr")>; 336311116Sdim 337311116Sdimdef : InstRW<[R52WriteALU_EX2, R52Read_ISS], 338311116Sdim (instregex "t2LDC", "RBIT", "REV", "REV16", "REVSH", "RRX")>; 339311116Sdim 340311116Sdimdef : InstRW<[R52WriteCC, R52Read_ISS], (instregex "TST")>; 341311116Sdim 342311116Sdimdef : InstRW<[R52WriteLd], (instregex "MRS", "MRSbanked")>; 343311116Sdimdef : InstRW<[R52WriteLd, R52Read_EX1], (instregex "MSR", "MSRbanked")>; 344311116Sdim 345311116Sdim// Integer Load, Multiple. 346311116Sdimforeach Lat = 3-25 in { 347311116Sdim def R52WriteILDM#Lat#Cy : SchedWriteRes<[R52UnitLd]> { 348311116Sdim let Latency = Lat; 349311116Sdim } 350311116Sdim def R52WriteILDM#Lat#CyNo : SchedWriteRes<[]> { 351311116Sdim let Latency = Lat; 352311116Sdim let NumMicroOps = 0; 353311116Sdim } 354311116Sdim} 355311116Sdimforeach NAddr = 1-16 in { 356311116Sdim def R52ILDMAddr#NAddr#Pred : SchedPredicate<"TII->getNumLDMAddresses(*MI) == "#NAddr>; 357311116Sdim} 358311116Sdimdef R52WriteILDMAddrNoWB : SchedWriteRes<[R52UnitLd]> { let Latency = 0; } 359311116Sdimdef R52WriteILDMAddrWB : SchedWriteRes<[R52UnitLd]>; 360311116Sdimdef R52WriteILDM : SchedWriteVariant<[ 361311116Sdim SchedVar<R52ILDMAddr2Pred, [R52WriteILDM4Cy, R52WriteILDM5Cy]>, 362311116Sdim 363311116Sdim SchedVar<R52ILDMAddr3Pred, [R52WriteILDM4Cy, R52WriteILDM5Cy, 364311116Sdim R52WriteILDM6Cy]>, 365311116Sdim SchedVar<R52ILDMAddr4Pred, [R52WriteILDM4Cy, R52WriteILDM5Cy, 366311116Sdim R52WriteILDM6Cy, R52WriteILDM7Cy]>, 367311116Sdim 368311116Sdim SchedVar<R52ILDMAddr5Pred, [R52WriteILDM4Cy, R52WriteILDM5Cy, 369311116Sdim R52WriteILDM6Cy, R52WriteILDM7Cy, 370311116Sdim R52WriteILDM8Cy]>, 371311116Sdim SchedVar<R52ILDMAddr6Pred, [R52WriteILDM4Cy, R52WriteILDM5Cy, 372311116Sdim R52WriteILDM6Cy, R52WriteILDM7Cy, 373311116Sdim R52WriteILDM8Cy, R52WriteILDM9Cy]>, 374311116Sdim 375311116Sdim SchedVar<R52ILDMAddr7Pred, [R52WriteILDM4Cy, R52WriteILDM5Cy, 376311116Sdim R52WriteILDM6Cy, R52WriteILDM7Cy, 377311116Sdim R52WriteILDM8Cy, R52WriteILDM9Cy, 378311116Sdim R52WriteILDM10Cy]>, 379311116Sdim SchedVar<R52ILDMAddr8Pred, [R52WriteILDM4Cy, R52WriteILDM5Cy, 380311116Sdim R52WriteILDM6Cy, R52WriteILDM7Cy, 381311116Sdim R52WriteILDM8Cy, R52WriteILDM9Cy, 382311116Sdim R52WriteILDM10Cy, R52WriteILDM11Cy]>, 383311116Sdim 384311116Sdim SchedVar<R52ILDMAddr9Pred, [R52WriteILDM4Cy, R52WriteILDM5Cy, 385311116Sdim R52WriteILDM6Cy, R52WriteILDM7Cy, 386311116Sdim R52WriteILDM8Cy, R52WriteILDM9Cy, 387311116Sdim R52WriteILDM10Cy, R52WriteILDM11Cy, 388311116Sdim R52WriteILDM12Cy]>, 389311116Sdim SchedVar<R52ILDMAddr10Pred,[R52WriteILDM4Cy, R52WriteILDM5Cy, 390311116Sdim R52WriteILDM6Cy, R52WriteILDM7Cy, 391311116Sdim R52WriteILDM8Cy, R52WriteILDM9Cy, 392311116Sdim R52WriteILDM10Cy, R52WriteILDM11Cy, 393311116Sdim R52WriteILDM12Cy, R52WriteILDM13Cy]>, 394311116Sdim 395311116Sdim SchedVar<R52ILDMAddr11Pred,[R52WriteILDM4Cy, R52WriteILDM5Cy, 396311116Sdim R52WriteILDM6Cy, R52WriteILDM7Cy, 397311116Sdim R52WriteILDM8Cy, R52WriteILDM9Cy, 398311116Sdim R52WriteILDM10Cy, R52WriteILDM11Cy, 399311116Sdim R52WriteILDM12Cy, R52WriteILDM13Cy, 400311116Sdim R52WriteILDM14Cy]>, 401311116Sdim SchedVar<R52ILDMAddr12Pred,[R52WriteILDM4Cy, R52WriteILDM5Cy, 402311116Sdim R52WriteILDM6Cy, R52WriteILDM7Cy, 403311116Sdim R52WriteILDM8Cy, R52WriteILDM9Cy, 404311116Sdim R52WriteILDM10Cy, R52WriteILDM11Cy, 405311116Sdim R52WriteILDM12Cy, R52WriteILDM13Cy, 406311116Sdim R52WriteILDM14Cy, R52WriteILDM15Cy]>, 407311116Sdim 408311116Sdim SchedVar<R52ILDMAddr13Pred,[R52WriteILDM4Cy, R52WriteILDM5Cy, 409311116Sdim R52WriteILDM6Cy, R52WriteILDM7Cy, 410311116Sdim R52WriteILDM8Cy, R52WriteILDM9Cy, 411311116Sdim R52WriteILDM10Cy, R52WriteILDM11Cy, 412311116Sdim R52WriteILDM12Cy, R52WriteILDM13Cy, 413311116Sdim R52WriteILDM14Cy, R52WriteILDM15Cy, 414311116Sdim R52WriteILDM16Cy]>, 415311116Sdim SchedVar<R52ILDMAddr14Pred,[R52WriteILDM4Cy, R52WriteILDM5Cy, 416311116Sdim R52WriteILDM6Cy, R52WriteILDM7Cy, 417311116Sdim R52WriteILDM8Cy, R52WriteILDM9Cy, 418311116Sdim R52WriteILDM10Cy, R52WriteILDM11Cy, 419311116Sdim R52WriteILDM12Cy, R52WriteILDM13Cy, 420311116Sdim R52WriteILDM14Cy, R52WriteILDM15Cy, 421311116Sdim R52WriteILDM16Cy, R52WriteILDM17Cy]>, 422311116Sdim 423311116Sdim SchedVar<R52ILDMAddr15Pred,[R52WriteILDM4Cy, R52WriteILDM5Cy, 424311116Sdim R52WriteILDM6Cy, R52WriteILDM7Cy, 425311116Sdim R52WriteILDM8Cy, R52WriteILDM9Cy, 426311116Sdim R52WriteILDM10Cy, R52WriteILDM11Cy, 427311116Sdim R52WriteILDM12Cy, R52WriteILDM13Cy, 428311116Sdim R52WriteILDM14Cy, R52WriteILDM15Cy, 429311116Sdim R52WriteILDM16Cy, R52WriteILDM17Cy, 430311116Sdim R52WriteILDM18Cy]>, 431311116Sdim SchedVar<R52ILDMAddr15Pred,[R52WriteILDM4Cy, R52WriteILDM5Cy, 432311116Sdim R52WriteILDM6Cy, R52WriteILDM7Cy, 433311116Sdim R52WriteILDM8Cy, R52WriteILDM9Cy, 434311116Sdim R52WriteILDM10Cy, R52WriteILDM11Cy, 435311116Sdim R52WriteILDM12Cy, R52WriteILDM13Cy, 436311116Sdim R52WriteILDM14Cy, R52WriteILDM15Cy, 437311116Sdim R52WriteILDM16Cy, R52WriteILDM17Cy, 438311116Sdim R52WriteILDM18Cy, R52WriteILDM19Cy]>, 439311116Sdim 440311116Sdim// Unknown number of registers, just use resources for two registers. 441311116Sdim SchedVar<NoSchedPred, [R52WriteILDM4Cy, R52WriteILDM5Cy, 442311116Sdim R52WriteILDM6CyNo, R52WriteILDM7CyNo, 443311116Sdim R52WriteILDM8CyNo, R52WriteILDM9CyNo, 444311116Sdim R52WriteILDM10CyNo, R52WriteILDM11CyNo, 445311116Sdim R52WriteILDM12CyNo, R52WriteILDM13CyNo, 446311116Sdim R52WriteILDM14CyNo, R52WriteILDM15CyNo, 447311116Sdim R52WriteILDM16CyNo, R52WriteILDM17CyNo, 448311116Sdim R52WriteILDM18Cy, R52WriteILDM19Cy]> 449311116Sdim]> { let Variadic=1; } 450311116Sdim 451311116Sdim// Integer Store, Multiple 452311116Sdimdef R52WriteIStIncAddr : SchedWriteRes<[R52UnitLd]> { 453311116Sdim let Latency = 4; 454311116Sdim let NumMicroOps = 2; 455311116Sdim} 456311116Sdimforeach NumAddr = 1-16 in { 457311116Sdim def R52WriteISTM#NumAddr : WriteSequence<[R52WriteIStIncAddr], NumAddr>; 458311116Sdim} 459311116Sdimdef R52WriteISTM : SchedWriteVariant<[ 460311116Sdim SchedVar<R52ILDMAddr2Pred, [R52WriteISTM2]>, 461311116Sdim SchedVar<R52ILDMAddr3Pred, [R52WriteISTM3]>, 462311116Sdim SchedVar<R52ILDMAddr4Pred, [R52WriteISTM4]>, 463311116Sdim SchedVar<R52ILDMAddr5Pred, [R52WriteISTM5]>, 464311116Sdim SchedVar<R52ILDMAddr6Pred, [R52WriteISTM6]>, 465311116Sdim SchedVar<R52ILDMAddr7Pred, [R52WriteISTM7]>, 466311116Sdim SchedVar<R52ILDMAddr8Pred, [R52WriteISTM8]>, 467311116Sdim SchedVar<R52ILDMAddr9Pred, [R52WriteISTM9]>, 468311116Sdim SchedVar<R52ILDMAddr10Pred,[R52WriteISTM10]>, 469311116Sdim SchedVar<R52ILDMAddr11Pred,[R52WriteISTM11]>, 470311116Sdim SchedVar<R52ILDMAddr12Pred,[R52WriteISTM12]>, 471311116Sdim SchedVar<R52ILDMAddr13Pred,[R52WriteISTM13]>, 472311116Sdim SchedVar<R52ILDMAddr14Pred,[R52WriteISTM14]>, 473311116Sdim SchedVar<R52ILDMAddr15Pred,[R52WriteISTM15]>, 474311116Sdim SchedVar<R52ILDMAddr16Pred,[R52WriteISTM16]>, 475311116Sdim // Unknow number of registers, just use resources for two registers. 476311116Sdim SchedVar<NoSchedPred, [R52WriteISTM2]> 477311116Sdim]>; 478311116Sdim 479311116Sdimdef : InstRW<[R52WriteILDM, R52Read_ISS], 480311116Sdim (instregex "LDM(IA|DA|DB|IB)$", "t2LDM(IA|DA|DB|IB)$", 481311116Sdim "(t|sys)LDM(IA|DA|DB|IB)$")>; 482311116Sdimdef : InstRW<[R52WriteILDM, R52WriteAdr, R52Read_ISS], 483311116Sdim (instregex "LDM(IA|DA|DB|IB)_UPD", "(t2|sys|t)LDM(IA|DA|DB|IB)_UPD")>; 484311116Sdimdef : InstRW<[R52WriteILDM, R52WriteAdr, R52Read_ISS], 485341825Sdim (instregex "LDMIA_RET", "(t|t2)LDMIA_RET", "tPOP")>; 486311116Sdim 487311116Sdim// Integer Store, Single Element 488311116Sdimdef : InstRW<[R52WriteLd, R52Read_ISS, R52Read_EX2], 489311116Sdim (instregex "PICSTR", "STR(i12|rs)", "STRB(i12|rs)", "STRH$", "STREX", "SRS", "t2SRS", 490311116Sdim "t2SRSDB", "t2STREX", "t2STREXB", "t2STREXD", "t2STREXH", "t2STR(i12|i8|s)$", 491311116Sdim "RFE", "t2RFE", "t2STR[BH](i12|i8|s)$", "tSTR[BH](i|r)", "tSTR(i|r)", "tSTRspi")>; 492311116Sdim 493311116Sdimdef : InstRW<[R52WriteLd, R52WriteAdr, R52Read_ISS, R52Read_EX2], 494311116Sdim (instregex "STR(B_|_|BT_|T_)(PRE_IMM|PRE_REG|POST_REG|POST_IMM)", 495311116Sdim "STR(i|r)_preidx", "STRB(i|r)_preidx", "STRH_preidx", "STR(H_|HT_)(PRE|POST)", 496311116Sdim "STR(BT|HT|T)", "t2STR_(PRE|POST)", "t2STR[BH]_(PRE|POST)", 497311116Sdim "t2STR_preidx", "t2STR[BH]_preidx", "t2ST(RB|RH|R)T")>; 498311116Sdim 499311116Sdim// Integer Store, Dual 500311116Sdimdef : InstRW<[R52WriteLd, R52Read_ISS, R52Read_EX2], 501341825Sdim (instregex "STRD$", "t2STRDi8", "STL", "t2STL")>; 502311116Sdimdef : InstRW<[R52WriteLd, R52WriteAdr, R52Read_ISS, R52Read_EX2], 503311116Sdim (instregex "(t2|t)STRD_(POST|PRE)", "STRD_(POST|PRE)")>; 504311116Sdim 505311116Sdimdef : InstRW<[R52WriteISTM, R52Read_ISS, R52Read_EX2], 506311116Sdim (instregex "STM(IB|IA|DB|DA)$", "(t2|sys|t)STM(IB|IA|DB|DA)$")>; 507311116Sdimdef : InstRW<[R52WriteISTM, R52WriteAdr, R52Read_ISS, R52Read_EX2], 508311116Sdim (instregex "STM(IB|IA|DB|DA)_UPD", "(t2|sys|t)STM(IB|IA|DB|DA)_UPD", 509341825Sdim "tPUSH")>; 510311116Sdim 511311116Sdim// LDRLIT pseudo instructions, they expand to LDR + PICADD 512311116Sdimdef : InstRW<[R52WriteLd], 513341825Sdim (instregex "t?LDRLIT_ga_abs", "t?LDRLIT_ga_pcrel$")>; 514311116Sdim// LDRLIT_ga_pcrel_ldr expands to LDR + PICLDR 515311116Sdimdef : InstRW<[R52WriteLd], (instregex "LDRLIT_ga_pcrel_ldr")>; 516311116Sdim 517311116Sdim 518311116Sdim 519311116Sdim//===----------------------------------------------------------------------===// 520311116Sdim// VFP, Floating Point Support 521311116Sdimdef : InstRW<[R52WriteFPALU_F5, R52Read_F1, R52Read_F1], (instregex "VABD(fd|hd)")>; 522311116Sdimdef : InstRW<[R52Write2FPALU_F5, R52Read_F1, R52Read_F1], (instregex "VABD(fq|hq)")>; 523311116Sdim 524311116Sdimdef : InstRW<[R52WriteFPALU_F5, R52Read_F1], (instregex "VABS(D|S|H)")>; 525311116Sdimdef : InstRW<[R52WriteFPALU_F5, R52Read_F1], (instregex "VABS(fd|hd)")>; 526311116Sdimdef : InstRW<[R52Write2FPALU_F5, R52Read_F1], (instregex "VABS(fq|hq)")>; 527311116Sdim 528311116Sdimdef : InstRW<[R52WriteFPALU_F3, R52Read_F1, R52Read_F1], (instregex "(VACGE|VACGT)(fd|hd)")>; 529311116Sdimdef : InstRW<[R52Write2FPALU_F3, R52Read_F1, R52Read_F1], (instregex "(VACGE|VACGT)(fq|hq)")>; 530311116Sdim 531341825Sdimdef : InstRW<[R52WriteFPALU_F5, R52Read_F1, R52Read_F1], (instregex "(VADD|VSUB)(D|S|H|fd|hd)$")>; 532311116Sdimdef : InstRW<[R52Write2FPALU_F5, R52Read_F1, R52Read_F1], (instregex "(VADD|VSUB)(fq|hq)")>; 533311116Sdim 534311116Sdimdef : InstRW<[R52WriteFPLd_F4, R52Read_ISS, R52Read_F1], (instregex "VLDR")>; 535311116Sdimdef : InstRW<[R52WriteFPST_F4, R52Read_ISS, R52Read_F1], (instregex "VSTR")>; 536311116Sdim 537311116Sdim 538311116Sdim//===----------------------------------------------------------------------===// 539311116Sdim// Neon Support 540311116Sdim 541311116Sdim// vector multiple load stores 542311116Sdimforeach NumAddr = 1-16 in { 543311116Sdim def R52LMAddrPred#NumAddr : 544311116Sdim SchedPredicate<"MI->getNumOperands() == "#NumAddr>; 545311116Sdim} 546311116Sdimforeach Lat = 1-32 in { 547311116Sdim def R52WriteLM#Lat#Cy : SchedWriteRes<[]> { 548311116Sdim let Latency = Lat; 549311116Sdim } 550311116Sdim} 551311116Sdimforeach Num = 1-32 in { // reserve LdSt resource, no dual-issue 552311116Sdim def R52ReserveLd#Num#Cy : SchedWriteRes<[R52UnitLd]> { 553311116Sdim let Latency = 0; 554311116Sdim let NumMicroOps = Num; 555311116Sdim let ResourceCycles = [Num]; 556311116Sdim } 557311116Sdim} 558311116Sdimdef R52WriteVLDM : SchedWriteVariant<[ 559311116Sdim // 1 D reg 560311116Sdim SchedVar<R52LMAddrPred1, [R52WriteLM5Cy, 561311116Sdim R52ReserveLd5Cy]>, 562311116Sdim SchedVar<R52LMAddrPred2, [R52WriteLM5Cy, 563311116Sdim R52ReserveLd5Cy]>, 564311116Sdim 565311116Sdim // 2 D reg 566311116Sdim SchedVar<R52LMAddrPred3, [R52WriteLM5Cy, R52WriteLM6Cy, 567311116Sdim R52ReserveLd6Cy]>, 568311116Sdim SchedVar<R52LMAddrPred4, [R52WriteLM5Cy, R52WriteLM6Cy, 569311116Sdim R52ReserveLd6Cy]>, 570311116Sdim 571311116Sdim // 3 D reg 572311116Sdim SchedVar<R52LMAddrPred5, [R52WriteLM5Cy, R52WriteLM6Cy, 573311116Sdim R52WriteLM7Cy, 574311116Sdim R52ReserveLd4Cy]>, 575311116Sdim SchedVar<R52LMAddrPred6, [R52WriteLM5Cy, R52WriteLM6Cy, 576311116Sdim R52WriteLM7Cy, 577311116Sdim R52ReserveLd7Cy]>, 578311116Sdim 579311116Sdim // 4 D reg 580311116Sdim SchedVar<R52LMAddrPred7, [R52WriteLM5Cy, R52WriteLM6Cy, 581311116Sdim R52WriteLM7Cy, R52WriteLM8Cy, 582311116Sdim R52ReserveLd8Cy]>, 583311116Sdim SchedVar<R52LMAddrPred8, [R52WriteLM5Cy, R52WriteLM6Cy, 584311116Sdim R52WriteLM7Cy, R52WriteLM8Cy, 585311116Sdim R52ReserveLd8Cy]>, 586311116Sdim 587311116Sdim // 5 D reg 588311116Sdim SchedVar<R52LMAddrPred9, [R52WriteLM5Cy, R52WriteLM6Cy, 589311116Sdim R52WriteLM7Cy, R52WriteLM8Cy, 590311116Sdim R52WriteLM9Cy, 591311116Sdim R52ReserveLd9Cy]>, 592311116Sdim SchedVar<R52LMAddrPred10, [R52WriteLM5Cy, R52WriteLM6Cy, 593311116Sdim R52WriteLM7Cy, R52WriteLM8Cy, 594311116Sdim R52WriteLM9Cy, 595311116Sdim R52ReserveLd9Cy]>, 596311116Sdim 597311116Sdim // 6 D reg 598311116Sdim SchedVar<R52LMAddrPred11, [R52WriteLM5Cy, R52WriteLM6Cy, 599311116Sdim R52WriteLM7Cy, R52WriteLM8Cy, 600311116Sdim R52WriteLM9Cy, R52WriteLM10Cy, 601311116Sdim R52ReserveLd10Cy]>, 602311116Sdim SchedVar<R52LMAddrPred12, [R52WriteLM5Cy, R52WriteLM6Cy, 603311116Sdim R52WriteLM7Cy, R52WriteLM8Cy, 604311116Sdim R52WriteLM9Cy, R52WriteLM10Cy, 605311116Sdim R52ReserveLd10Cy]>, 606311116Sdim 607311116Sdim // 7 D reg 608311116Sdim SchedVar<R52LMAddrPred13, [R52WriteLM5Cy, R52WriteLM6Cy, 609311116Sdim R52WriteLM7Cy, R52WriteLM8Cy, 610311116Sdim R52WriteLM9Cy, R52WriteLM10Cy, 611311116Sdim R52WriteLM11Cy, 612311116Sdim R52ReserveLd11Cy]>, 613311116Sdim SchedVar<R52LMAddrPred14, [R52WriteLM5Cy, R52WriteLM6Cy, 614311116Sdim R52WriteLM7Cy, R52WriteLM8Cy, 615311116Sdim R52WriteLM9Cy, R52WriteLM10Cy, 616311116Sdim R52WriteLM11Cy, 617311116Sdim R52ReserveLd11Cy]>, 618311116Sdim 619311116Sdim // 8 D reg 620311116Sdim SchedVar<R52LMAddrPred14, [R52WriteLM5Cy, R52WriteLM6Cy, 621311116Sdim R52WriteLM7Cy, R52WriteLM8Cy, 622311116Sdim R52WriteLM9Cy, R52WriteLM10Cy, 623311116Sdim R52WriteLM11Cy, R52WriteLM12Cy, 624311116Sdim R52ReserveLd12Cy]>, 625311116Sdim SchedVar<R52LMAddrPred15, [R52WriteLM5Cy, R52WriteLM6Cy, 626311116Sdim R52WriteLM7Cy, R52WriteLM8Cy, 627311116Sdim R52WriteLM9Cy, R52WriteLM10Cy, 628311116Sdim R52WriteLM11Cy, R52WriteLM12Cy, 629311116Sdim R52ReserveLd12Cy]>, 630311116Sdim // unknown number of reg. 631311116Sdim SchedVar<NoSchedPred, [R52WriteLM5Cy, R52WriteLM6Cy, 632311116Sdim R52WriteLM7Cy, R52WriteLM8Cy, 633311116Sdim R52WriteLM9Cy, R52WriteLM10Cy, 634311116Sdim R52WriteLM11Cy, R52WriteLM12Cy, 635311116Sdim R52ReserveLd5Cy]> 636311116Sdim]> { let Variadic=1;} 637311116Sdim 638311116Sdim// variable stores. Cannot dual-issue 639311116Sdimdef R52WriteSTM5 : SchedWriteRes<[R52UnitLd]> { 640311116Sdim let Latency = 5; 641311116Sdim let NumMicroOps = 2; 642311116Sdim let ResourceCycles = [1]; 643311116Sdim} 644311116Sdimdef R52WriteSTM6 : SchedWriteRes<[R52UnitLd]> { 645311116Sdim let Latency = 6; 646311116Sdim let NumMicroOps = 4; 647311116Sdim let ResourceCycles = [2]; 648311116Sdim} 649311116Sdimdef R52WriteSTM7 : SchedWriteRes<[R52UnitLd]> { 650311116Sdim let Latency = 7; 651311116Sdim let NumMicroOps = 6; 652311116Sdim let ResourceCycles = [3]; 653311116Sdim} 654311116Sdimdef R52WriteSTM8 : SchedWriteRes<[R52UnitLd]> { 655311116Sdim let Latency = 8; 656311116Sdim let NumMicroOps = 8; 657311116Sdim let ResourceCycles = [4]; 658311116Sdim} 659311116Sdimdef R52WriteSTM9 : SchedWriteRes<[R52UnitLd]> { 660311116Sdim let Latency = 9; 661311116Sdim let NumMicroOps = 10; 662311116Sdim let ResourceCycles = [5]; 663311116Sdim} 664311116Sdimdef R52WriteSTM10 : SchedWriteRes<[R52UnitLd]> { 665311116Sdim let Latency = 10; 666311116Sdim let NumMicroOps = 12; 667311116Sdim let ResourceCycles = [6]; 668311116Sdim} 669311116Sdimdef R52WriteSTM11 : SchedWriteRes<[R52UnitLd]> { 670311116Sdim let Latency = 11; 671311116Sdim let NumMicroOps = 14; 672311116Sdim let ResourceCycles = [7]; 673311116Sdim} 674311116Sdimdef R52WriteSTM12 : SchedWriteRes<[R52UnitLd]> { 675311116Sdim let Latency = 12; 676311116Sdim let NumMicroOps = 16; 677311116Sdim let ResourceCycles = [8]; 678311116Sdim} 679311116Sdimdef R52WriteSTM13 : SchedWriteRes<[R52UnitLd]> { 680311116Sdim let Latency = 13; 681311116Sdim let NumMicroOps = 18; 682311116Sdim let ResourceCycles = [9]; 683311116Sdim} 684311116Sdimdef R52WriteSTM14 : SchedWriteRes<[R52UnitLd]> { 685311116Sdim let Latency = 14; 686311116Sdim let NumMicroOps = 20; 687311116Sdim let ResourceCycles = [10]; 688311116Sdim} 689311116Sdimdef R52WriteSTM15 : SchedWriteRes<[R52UnitLd]> { 690311116Sdim let Latency = 15; 691311116Sdim let NumMicroOps = 22; 692311116Sdim let ResourceCycles = [11]; 693311116Sdim} 694311116Sdim 695311116Sdimdef R52WriteSTM : SchedWriteVariant<[ 696311116Sdim SchedVar<R52LMAddrPred1, [R52WriteSTM5]>, 697311116Sdim SchedVar<R52LMAddrPred2, [R52WriteSTM5]>, 698311116Sdim SchedVar<R52LMAddrPred3, [R52WriteSTM6]>, 699311116Sdim SchedVar<R52LMAddrPred4, [R52WriteSTM6]>, 700311116Sdim SchedVar<R52LMAddrPred5, [R52WriteSTM7]>, 701311116Sdim SchedVar<R52LMAddrPred6, [R52WriteSTM7]>, 702311116Sdim SchedVar<R52LMAddrPred7, [R52WriteSTM8]>, 703311116Sdim SchedVar<R52LMAddrPred8, [R52WriteSTM8]>, 704311116Sdim SchedVar<R52LMAddrPred9, [R52WriteSTM9]>, 705311116Sdim SchedVar<R52LMAddrPred10, [R52WriteSTM9]>, 706311116Sdim SchedVar<R52LMAddrPred11, [R52WriteSTM10]>, 707311116Sdim SchedVar<R52LMAddrPred12, [R52WriteSTM10]>, 708311116Sdim SchedVar<R52LMAddrPred13, [R52WriteSTM11]>, 709311116Sdim SchedVar<R52LMAddrPred14, [R52WriteSTM11]>, 710311116Sdim SchedVar<R52LMAddrPred15, [R52WriteSTM12]>, 711311116Sdim SchedVar<R52LMAddrPred16, [R52WriteSTM12]>, 712311116Sdim // unknown number of registers, just use resources for two 713311116Sdim SchedVar<NoSchedPred, [R52WriteSTM6]> 714311116Sdim]>; 715311116Sdim 716311116Sdim// Vector Load/Stores. Can issue only in slot-0. Can dual-issue with 717311116Sdim// another instruction in slot-1, but only in the last issue. 718321369Sdimdef : WriteRes<WriteVLD1, [R52UnitLd]> { let Latency = 5;} 719321369Sdimdef : WriteRes<WriteVLD2, [R52UnitLd]> { 720311116Sdim let Latency = 6; 721311116Sdim let NumMicroOps = 3; 722311116Sdim let ResourceCycles = [2]; 723321369Sdim let SingleIssue = 1; 724311116Sdim} 725321369Sdimdef : WriteRes<WriteVLD3, [R52UnitLd]> { 726311116Sdim let Latency = 7; 727311116Sdim let NumMicroOps = 5; 728311116Sdim let ResourceCycles = [3]; 729321369Sdim let SingleIssue = 1; 730311116Sdim} 731321369Sdimdef : WriteRes<WriteVLD4, [R52UnitLd]> { 732311116Sdim let Latency = 8; 733311116Sdim let NumMicroOps = 7; 734311116Sdim let ResourceCycles = [4]; 735321369Sdim let SingleIssue = 1; 736311116Sdim} 737311116Sdimdef R52WriteVST1Mem : SchedWriteRes<[R52UnitLd]> { 738311116Sdim let Latency = 5; 739311116Sdim let NumMicroOps = 1; 740311116Sdim let ResourceCycles = [1]; 741311116Sdim} 742311116Sdimdef R52WriteVST2Mem : SchedWriteRes<[R52UnitLd]> { 743311116Sdim let Latency = 6; 744311116Sdim let NumMicroOps = 3; 745311116Sdim let ResourceCycles = [2]; 746311116Sdim} 747311116Sdimdef R52WriteVST3Mem : SchedWriteRes<[R52UnitLd]> { 748311116Sdim let Latency = 7; 749311116Sdim let NumMicroOps = 5; 750311116Sdim let ResourceCycles = [3]; 751311116Sdim} 752311116Sdimdef R52WriteVST4Mem : SchedWriteRes<[R52UnitLd]> { 753311116Sdim let Latency = 8; 754311116Sdim let NumMicroOps = 7; 755311116Sdim let ResourceCycles = [4]; 756311116Sdim} 757311116Sdimdef R52WriteVST5Mem : SchedWriteRes<[R52UnitLd]> { 758311116Sdim let Latency = 9; 759311116Sdim let NumMicroOps = 9; 760311116Sdim let ResourceCycles = [5]; 761311116Sdim} 762311116Sdim 763311116Sdim 764311116Sdimdef : InstRW<[R52WriteFPALU_F5, R52Read_F1, R52Read_F1, R52Read_F1], (instregex "VABA(u|s)(v8i8|v4i16|v2i32)")>; 765311116Sdimdef : InstRW<[R52Write2FPALU_F5, R52Read_F1, R52Read_F1, R52Read_F1], (instregex "VABA(u|s)(v16i8|v8i16|v4i32)")>; 766311116Sdimdef : InstRW<[R52Write2FPALU_F5, R52Read_F1, R52Read_F1, R52Read_F1], (instregex "VABAL(u|s)(v8i16|v4i32|v2i64)")>; 767311116Sdim 768311116Sdimdef : InstRW<[R52WriteFPALU_F4, R52Read_F1, R52Read_F1], (instregex "VABD(u|s)(v8i8|v4i16|v2i32)")>; 769311116Sdimdef : InstRW<[R52Write2FPALU_F4, R52Read_F1, R52Read_F1], (instregex "VABD(u|s)(v16i8|v8i16|v4i32)")>; 770311116Sdimdef : InstRW<[R52Write2FPALU_F4, R52Read_F1, R52Read_F1], (instregex "VABDL(u|s)(v16i8|v8i16|v4i32)")>; 771311116Sdim 772311116Sdimdef : InstRW<[R52Write2FPALU_F4, R52Read_F1], (instregex "VABS(v16i8|v8i16|v4i32)")>; 773311116Sdim 774311116Sdimdef : InstRW<[R52WriteFPALU_F4, R52Read_F2, R52Read_F2], 775311116Sdim (instregex "(VADD|VSUB)(v8i8|v4i16|v2i32|v1i64)")>; 776311116Sdimdef : InstRW<[R52Write2FPALU_F4, R52Read_F2, R52Read_F2], 777311116Sdim (instregex "(VADD|VSUB)(v16i8|v8i16|v4i32|v2i64)")>; 778311116Sdimdef : InstRW<[R52Write2FPALU_F5, R52Read_F2, R52Read_F2], 779311116Sdim (instregex "(VADDHN|VRADDHN|VSUBHN|VRSUBHN)(v8i8|v4i16|v2i32)")>; 780311116Sdim 781311116Sdimdef : InstRW<[R52Write2FPALU_F4, R52Read_F1, R52Read_F1], 782311116Sdim (instregex "VADDL", "VADDW", "VSUBL", "VSUBW")>; 783311116Sdim 784311116Sdimdef : InstRW<[R52WriteFPALU_F3, R52Read_F2, R52Read_F2], (instregex "(VAND|VBIC|VEOR)d")>; 785311116Sdimdef : InstRW<[R52Write2FPALU_F3, R52Read_F2, R52Read_F2], (instregex "(VAND|VBIC|VEOR)q")>; 786311116Sdim 787311116Sdimdef : InstRW<[R52WriteFPALU_F3, R52Read_F2], (instregex "VBICi(v4i16|v2i32)")>; 788311116Sdimdef : InstRW<[R52Write2FPALU_F3, R52Read_F2], (instregex "VBICi(v8i16|v4i32)")>; 789311116Sdim 790311116Sdimdef : InstRW<[R52WriteFPALU_F3, R52Read_F1, R52Read_F2, R52Read_F2], (instregex "(VBIF|VBIT|VBSL)d")>; 791311116Sdimdef : InstRW<[R52Write2FPALU_F3, R52Read_F1, R52Read_F2, R52Read_F2], (instregex "(VBIF|VBIT|VBSL)q")>; 792311116Sdim 793311116Sdimdef : InstRW<[R52WriteFPALU_F3, R52Read_F1, R52Read_F1], 794311116Sdim (instregex "(VCEQ|VCGE|VCGT|VCLE|VCLT|VCLZ|VCMP|VCMPE|VCNT)")>; 795311116Sdimdef : InstRW<[R52WriteFPALU_F5, R52Read_F1, R52Read_F1], 796311116Sdim (instregex "VCVT", "VSITO", "VUITO", "VTO")>; 797311116Sdim 798311116Sdimdef : InstRW<[R52WriteFPALU_F3, R52Read_ISS], (instregex "VDUP(8|16|32)d")>; 799311116Sdimdef : InstRW<[R52Write2FPALU_F3, R52Read_ISS], (instregex "VDUP(8|16|32)q")>; 800311116Sdimdef : InstRW<[R52WriteFPALU_F3, R52Read_F1], (instregex "VDUPLN(8|16|32)d")>; 801311116Sdimdef : InstRW<[R52Write2FPALU_F3, R52Read_F1], (instregex "VDUPLN(8|16|32)q")>; 802311116Sdim 803311116Sdimdef : InstRW<[R52WriteFPALU_F3, R52Read_F1, R52Read_F1], (instregex "VEXTd(8|16|32)", "VSEL")>; 804311116Sdimdef : InstRW<[R52Write2FPALU_F3, R52Read_F1, R52Read_F1], (instregex "VEXTq(8|16|32|64)")>; 805311116Sdim 806311116Sdimdef : InstRW<[R52WriteFPMAC_F5, R52Read_F1, R52Read_F1, R52Read_F1], (instregex "(VFMA|VFMS)(f|h)d")>; 807311116Sdimdef : InstRW<[R52Write2FPMAC_F5, R52Read_F1, R52Read_F1, R52Read_F1], (instregex "(VFMA|VFMS)(f|h)q")>; 808311116Sdim 809311116Sdimdef : InstRW<[R52WriteFPALU_F4, R52Read_F2, R52Read_F2], (instregex "(VHADD|VHSUB)(u|s)(v8i8|v4i16|v2i32)")>; 810311116Sdimdef : InstRW<[R52Write2FPALU_F4, R52Read_F2, R52Read_F2], (instregex "(VHADD|VHSUB)(u|s)(v16i8|v8i16|v4i32)")>; 811311116Sdim 812311116Sdimdef : InstRW<[R52WriteVLDM], (instregex "VLDM[SD](IA|DB)$")>; 813311116Sdimdef : InstRW<[R52WriteFPALU_F4, R52Read_F1, R52Read_F1], (instregex "VMAX", "VMIN", "VPMAX", "VPMIN")>; 814321369Sdimdef : InstRW<[R52WriteFPALU_F3, R52Read_F1, R52Read_F1], (instregex "VORR", "VORN", "VREV")>; 815311116Sdimdef : InstRW<[R52WriteNoRSRC_WRI], (instregex "VMRS")>; 816311116Sdimdef : InstRW<[R52WriteFPALU_F5, R52Read_F1], (instregex "VNEG")>; 817311116Sdimdef : InstRW<[R52WriteFPALU_F4, R52Read_F1, R52Read_F1], (instregex "VPADDi")>; 818311116Sdimdef : InstRW<[R52Write2FPALU_F4, R52Read_F1, R52Read_F1], (instregex "VPADAL", "VPADDL")>; 819311116Sdimdef : InstRW<[R52WriteFPALU_F5, R52Read_F1], (instregex "VQABS(v8i8|v4i16|v2i32|v1i64)")>; 820311116Sdimdef : InstRW<[R52Write2FPALU_F5, R52Read_F1], (instregex "VQABS(v16i8|v8i16|v4i32|v2i64)")>; 821311116Sdimdef : InstRW<[R52WriteFPALU_F5, R52Read_F2, R52Read_F2], 822311116Sdim (instregex "(VQADD|VQSUB)(u|s)(v8i8|v4i16|v2i32|v1i64)")>; 823311116Sdimdef : InstRW<[R52Write2FPALU_F5, R52Read_F2, R52Read_F2], 824311116Sdim (instregex "(VQADD|VQSUB)(u|s)(v16i8|v8i16|v4i32|v2i64)")>; 825311116Sdimdef : InstRW<[R52Write2FPMAC_F5, R52Read_F1, R52Read_F1, R52Read_F1], (instregex "VQDMLAL", "VQDMLSL")>; 826311116Sdimdef : InstRW<[R52WriteFPMUL_F5, R52Read_F1, R52Read_F1, R52Read_F1], (instregex "VQDMUL","VQRDMUL")>; 827311116Sdimdef : InstRW<[R52WriteFPALU_F5, R52Read_F1, R52Read_F1], 828311116Sdim (instregex "VQMOVN", "VQNEG", "VQSHL", "VQSHRN")>; 829311116Sdimdef : InstRW<[R52WriteFPALU_F4, R52Read_F1, R52Read_F1], (instregex "VRSHL", "VRSHR", "VRSHRN", "VTB")>; 830311116Sdimdef : InstRW<[R52WriteFPALU_F3, R52Read_F1, R52Read_F1], (instregex "VSWP", "VTRN", "VUZP", "VZIP")>; 831311116Sdim 832311116Sdim//--- 833311116Sdim// VSTx. Vector Stores 834311116Sdim//--- 835311116Sdim// 1-element structure store 836311116Sdimdef : InstRW<[R52WriteVST1Mem, R52Read_ISS, R52Read_F2], (instregex "VST1d(8|16|32|64)$")>; 837311116Sdimdef : InstRW<[R52WriteVST2Mem, R52Read_ISS, R52Read_F2], (instregex "VST1q(8|16|32|64)$")>; 838311116Sdimdef : InstRW<[R52WriteVST3Mem, R52Read_ISS, R52Read_F2], (instregex "VST1d(8|16|32|64)T$")>; 839311116Sdimdef : InstRW<[R52WriteVST4Mem, R52Read_ISS, R52Read_F2], (instregex "VST1d(8|16|32|64)Q$")>; 840311116Sdimdef : InstRW<[R52WriteVST3Mem, R52Read_ISS, R52Read_F2], (instregex "VST1d64TPseudo$")>; 841311116Sdimdef : InstRW<[R52WriteVST4Mem, R52Read_ISS, R52Read_F2], (instregex "VST1d64QPseudo$")>; 842311116Sdim 843311116Sdimdef : InstRW<[R52WriteVST1Mem, R52Read_ISS, R52Read_F2], (instregex "VST1LNd(8|16|32)$")>; 844311116Sdimdef : InstRW<[R52WriteVST1Mem, R52Read_ISS, R52Read_F2], (instregex "VST1LNdAsm_(8|16|32)$")>; 845311116Sdimdef : InstRW<[R52WriteVST1Mem, R52Read_ISS, R52Read_F2], (instregex "VST1LNq(8|16|32)Pseudo$")>; 846311116Sdim 847311116Sdimdef : InstRW<[R52WriteVST1Mem, R52WriteAdr, R52Read_ISS, R52Read_F2], (instregex "VST1d(8|16|32|64)wb")>; 848311116Sdimdef : InstRW<[R52WriteVST2Mem, R52WriteAdr, R52Read_ISS, R52Read_F2], (instregex "VST1q(8|16|32|64)wb")>; 849311116Sdimdef : InstRW<[R52WriteVST3Mem, R52WriteAdr, R52Read_ISS, R52Read_F2], (instregex "VST1d(8|16|32|64)Twb")>; 850311116Sdimdef : InstRW<[R52WriteVST4Mem, R52WriteAdr, R52Read_ISS, R52Read_F2], (instregex "VST1d(8|16|32|64)Qwb")>; 851311116Sdimdef : InstRW<[R52WriteVST3Mem, R52WriteAdr, R52Read_ISS, R52Read_F2], (instregex "VST1d64TPseudoWB")>; 852311116Sdimdef : InstRW<[R52WriteVST4Mem, R52WriteAdr, R52Read_ISS, R52Read_F2], (instregex "VST1d64QPseudoWB")>; 853311116Sdim 854311116Sdimdef : InstRW<[R52WriteVST1Mem, R52WriteAdr, R52Read_ISS, R52Read_F2], (instregex "VST1LNd(8|16|32)_UPD")>; 855311116Sdimdef : InstRW<[R52WriteVST1Mem, R52WriteAdr, R52Read_ISS, R52Read_F2], (instregex "VST1LNdWB_(fixed|register)_Asm_(8|16|32)")>; 856311116Sdimdef : InstRW<[R52WriteVST1Mem, R52WriteAdr, R52Read_ISS, R52Read_F2], (instregex "VST1LNq(8|16|32)Pseudo_UPD")>; 857311116Sdim 858311116Sdim// 2-element structure store 859311116Sdimdef : InstRW<[R52WriteVST2Mem, R52Read_ISS, R52Read_F2], (instregex "VST2(d|b)(8|16|32)$")>; 860311116Sdimdef : InstRW<[R52WriteVST4Mem, R52Read_ISS, R52Read_F2], (instregex "VST2q(8|16|32)$")>; 861311116Sdimdef : InstRW<[R52WriteVST4Mem, R52Read_ISS, R52Read_F2], (instregex "VST2q(8|16|32)Pseudo$")>; 862311116Sdim 863311116Sdimdef : InstRW<[R52WriteVST1Mem, R52Read_ISS, R52Read_F2], (instregex "VST2LNd(8|16|32)$")>; 864311116Sdimdef : InstRW<[R52WriteVST1Mem, R52Read_ISS, R52Read_F2], (instregex "VST2LNdAsm_(8|16|32)$")>; 865311116Sdimdef : InstRW<[R52WriteVST1Mem, R52Read_ISS, R52Read_F2], (instregex "VST2LNd(8|16|32)Pseudo$")>; 866311116Sdimdef : InstRW<[R52WriteVST1Mem, R52Read_ISS, R52Read_F2], (instregex "VST2LNq(16|32)$")>; 867311116Sdimdef : InstRW<[R52WriteVST1Mem, R52Read_ISS, R52Read_F2], (instregex "VST2LNqAsm_(16|32)$")>; 868311116Sdimdef : InstRW<[R52WriteVST1Mem, R52Read_ISS, R52Read_F2], (instregex "VST2LNq(16|32)Pseudo$")>; 869311116Sdim 870311116Sdimdef : InstRW<[R52WriteVST2Mem, R52WriteAdr, R52Read_ISS, R52Read_F2], (instregex "VST2(d|b)(8|16|32)wb")>; 871311116Sdimdef : InstRW<[R52WriteVST4Mem, R52WriteAdr, R52Read_ISS, R52Read_F2], (instregex "VST2q(8|16|32)wb")>; 872311116Sdimdef : InstRW<[R52WriteVST4Mem, R52WriteAdr, R52Read_ISS, R52Read_F2], (instregex "VST2q(8|16|32)PseudoWB")>; 873311116Sdim 874311116Sdimdef : InstRW<[R52WriteVST1Mem, R52WriteAdr, R52Read_ISS, R52Read_F2], (instregex "VST2LNd(8|16|32)_UPD")>; 875311116Sdimdef : InstRW<[R52WriteVST1Mem, R52WriteAdr, R52Read_ISS, R52Read_F2], (instregex "VST2LNdWB_(fixed|register)_Asm_(8|16|32)")>; 876311116Sdimdef : InstRW<[R52WriteVST1Mem, R52WriteAdr, R52Read_ISS, R52Read_F2], (instregex "VST2LNd(8|16|32)Pseudo_UPD")>; 877311116Sdimdef : InstRW<[R52WriteVST1Mem, R52WriteAdr, R52Read_ISS, R52Read_F2], (instregex "VST2LNq(16|32)_UPD")>; 878311116Sdimdef : InstRW<[R52WriteVST1Mem, R52WriteAdr, R52Read_ISS, R52Read_F2], (instregex "VST2LNqWB_(fixed|register)_Asm_(16|32)")>; 879311116Sdimdef : InstRW<[R52WriteVST1Mem, R52WriteAdr, R52Read_ISS, R52Read_F2], (instregex "VST2LNq(16|32)Pseudo_UPD")>; 880311116Sdim 881311116Sdim// 3-element structure store 882311116Sdimdef : InstRW<[R52WriteVST4Mem, R52Read_ISS, R52Read_F2], (instregex "VST3(d|q)(8|16|32)$")>; 883311116Sdimdef : InstRW<[R52WriteVST4Mem, R52Read_ISS, R52Read_F2], (instregex "VST3(d|q)Asm_(8|16|32)$")>; 884311116Sdimdef : InstRW<[R52WriteVST4Mem, R52Read_ISS, R52Read_F2], (instregex "VST3d(8|16|32)(oddP|P)seudo$")>; 885311116Sdim 886311116Sdimdef : InstRW<[R52WriteVST2Mem, R52Read_ISS, R52Read_F2], (instregex "VST3LNd(8|16|32)$")>; 887311116Sdimdef : InstRW<[R52WriteVST2Mem, R52Read_ISS, R52Read_F2], (instregex "VST3LNdAsm_(8|16|32)$")>; 888311116Sdimdef : InstRW<[R52WriteVST2Mem, R52Read_ISS, R52Read_F2], (instregex "VST3LNd(8|16|32)Pseudo$")>; 889311116Sdimdef : InstRW<[R52WriteVST2Mem, R52Read_ISS, R52Read_F2], (instregex "VST3LNq(16|32)$")>; 890311116Sdimdef : InstRW<[R52WriteVST2Mem, R52Read_ISS, R52Read_F2], (instregex "VST3LNqAsm_(16|32)$")>; 891311116Sdimdef : InstRW<[R52WriteVST2Mem, R52Read_ISS, R52Read_F2], (instregex "VST3LNq(16|32)Pseudo$")>; 892311116Sdim 893311116Sdimdef : InstRW<[R52WriteVST4Mem, R52WriteAdr, R52Read_ISS, R52Read_F2], (instregex "VST3(d|q)(8|16|32)_UPD$")>; 894311116Sdimdef : InstRW<[R52WriteVST4Mem, R52WriteAdr, R52Read_ISS, R52Read_F2], (instregex "VST3(d|q)WB_(fixed|register)_Asm_(8|16|32)$")>; 895311116Sdimdef : InstRW<[R52WriteVST4Mem, R52WriteAdr, R52Read_ISS, R52Read_F2], (instregex "VST3(d|q)(8|16|32)(oddP|P)seudo_UPD$")>; 896311116Sdim 897311116Sdimdef : InstRW<[R52WriteVST2Mem, R52WriteAdr, R52Read_ISS, R52Read_F2], (instregex "VST3LNd(8|16|32)_UPD$")>; 898311116Sdimdef : InstRW<[R52WriteVST2Mem, R52WriteAdr, R52Read_ISS, R52Read_F2], (instregex "VST3LNdWB_(fixed|register)_Asm_(8|16|32)")>; 899311116Sdimdef : InstRW<[R52WriteVST2Mem, R52WriteAdr, R52Read_ISS, R52Read_F2], (instregex "VST3LNd(8|16|32)Pseudo_UPD$")>; 900311116Sdimdef : InstRW<[R52WriteVST2Mem, R52WriteAdr, R52Read_ISS, R52Read_F2], (instregex "VST3LNq(16|32)_UPD$")>; 901311116Sdimdef : InstRW<[R52WriteVST2Mem, R52WriteAdr, R52Read_ISS, R52Read_F2], (instregex "VST3LNqWB_(fixed|register)_Asm_(16|32)$")>; 902311116Sdimdef : InstRW<[R52WriteVST2Mem, R52WriteAdr, R52Read_ISS, R52Read_F2], (instregex "VST3LNq(16|32)Pseudo_UPD$")>; 903311116Sdim 904311116Sdim// 4-element structure store 905311116Sdimdef : InstRW<[R52WriteVST5Mem, R52Read_ISS, R52Read_F2], (instregex "VST4(d|q)(8|16|32)$")>; 906311116Sdimdef : InstRW<[R52WriteVST5Mem, R52Read_ISS, R52Read_F2], (instregex "VST4(d|q)Asm_(8|16|32)$")>; 907311116Sdimdef : InstRW<[R52WriteVST5Mem, R52Read_ISS, R52Read_F2], (instregex "VST4d(8|16|32)Pseudo$")>; 908311116Sdim 909311116Sdimdef : InstRW<[R52WriteVST2Mem, R52Read_ISS, R52Read_F2], (instregex "VST4LNd(8|16|32)$")>; 910311116Sdimdef : InstRW<[R52WriteVST2Mem, R52Read_ISS, R52Read_F2], (instregex "VST4LNdAsm_(8|16|32)$")>; 911311116Sdimdef : InstRW<[R52WriteVST2Mem, R52Read_ISS, R52Read_F2], (instregex "VST4LNd(8|16|32)Pseudo$")>; 912311116Sdimdef : InstRW<[R52WriteVST2Mem, R52Read_ISS, R52Read_F2], (instregex "VST4LNq(16|32)$")>; 913311116Sdimdef : InstRW<[R52WriteVST2Mem, R52Read_ISS, R52Read_F2], (instregex "VST4LNqAsm_(16|32)$")>; 914311116Sdimdef : InstRW<[R52WriteVST2Mem, R52Read_ISS, R52Read_F2], (instregex "VST4LNq(16|32)Pseudo$")>; 915311116Sdim 916311116Sdimdef : InstRW<[R52WriteVST5Mem, R52WriteAdr, R52Read_ISS, R52Read_F2], (instregex "VST4(d|q)(8|16|32)_UPD")>; 917311116Sdimdef : InstRW<[R52WriteVST5Mem, R52WriteAdr, R52Read_ISS, R52Read_F2], (instregex "VST4(d|q)WB_(fixed|register)_Asm_(8|16|32)")>; 918311116Sdimdef : InstRW<[R52WriteVST5Mem, R52WriteAdr, R52Read_ISS, R52Read_F2], (instregex "VST4(d|q)(8|16|32)(oddP|P)seudo_UPD")>; 919311116Sdim 920311116Sdimdef : InstRW<[R52WriteVST2Mem, R52WriteAdr, R52Read_ISS, R52Read_F2], (instregex "VST4LNd(8|16|32)_UPD")>; 921311116Sdimdef : InstRW<[R52WriteVST2Mem, R52WriteAdr, R52Read_ISS, R52Read_F2], (instregex "VST4LNdWB_(fixed|register)_Asm_(8|16|32)")>; 922311116Sdimdef : InstRW<[R52WriteVST2Mem, R52WriteAdr, R52Read_ISS, R52Read_F2], (instregex "VST4LNd(8|16|32)Pseudo_UPD")>; 923311116Sdimdef : InstRW<[R52WriteVST2Mem, R52WriteAdr, R52Read_ISS, R52Read_F2], (instregex "VST4LNq(16|32)_UPD")>; 924311116Sdimdef : InstRW<[R52WriteVST2Mem, R52WriteAdr, R52Read_ISS, R52Read_F2], (instregex "VST4LNqWB_(fixed|register)_Asm_(16|32)")>; 925311116Sdimdef : InstRW<[R52WriteVST2Mem, R52WriteAdr, R52Read_ISS, R52Read_F2], (instregex "VST4LNq(16|32)Pseudo_UPD")>; 926311116Sdim 927311116Sdim} // R52 SchedModel 928