ARMLegalizerInfo.cpp revision 341825 
1//===- ARMLegalizerInfo.cpp --------------------------------------*- C++ -*-==//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9/// \file
10/// This file implements the targeting of the Machinelegalizer class for ARM.
11/// \todo This should be generated by TableGen.
12//===----------------------------------------------------------------------===//
13
14#include "ARMLegalizerInfo.h"
15#include "ARMCallLowering.h"
16#include "ARMSubtarget.h"
17#include "llvm/CodeGen/GlobalISel/LegalizerHelper.h"
18#include "llvm/CodeGen/LowLevelType.h"
19#include "llvm/CodeGen/MachineRegisterInfo.h"
20#include "llvm/CodeGen/TargetOpcodes.h"
21#include "llvm/CodeGen/ValueTypes.h"
22#include "llvm/IR/DerivedTypes.h"
23#include "llvm/IR/Type.h"
24
25using namespace llvm;
26using namespace LegalizeActions;
27
28/// FIXME: The following static functions are SizeChangeStrategy functions
29/// that are meant to temporarily mimic the behaviour of the old legalization
30/// based on doubling/halving non-legal types as closely as possible. This is
31/// not entirly possible as only legalizing the types that are exactly a power
32/// of 2 times the size of the legal types would require specifying all those
33/// sizes explicitly.
34/// In practice, not specifying those isn't a problem, and the below functions
35/// should disappear quickly as we add support for legalizing non-power-of-2
36/// sized types further.
37static void
38addAndInterleaveWithUnsupported(LegalizerInfo::SizeAndActionsVec &result,
39                                const LegalizerInfo::SizeAndActionsVec &v) {
40  for (unsigned i = 0; i < v.size(); ++i) {
41    result.push_back(v[i]);
42    if (i + 1 < v[i].first && i + 1 < v.size() &&
43        v[i + 1].first != v[i].first + 1)
44      result.push_back({v[i].first + 1, Unsupported});
45  }
46}
47
48static LegalizerInfo::SizeAndActionsVec
49widen_8_16(const LegalizerInfo::SizeAndActionsVec &v) {
50  assert(v.size() >= 1);
51  assert(v[0].first > 17);
52  LegalizerInfo::SizeAndActionsVec result = {{1, Unsupported},
53                                             {8, WidenScalar},
54                                             {9, Unsupported},
55                                             {16, WidenScalar},
56                                             {17, Unsupported}};
57  addAndInterleaveWithUnsupported(result, v);
58  auto Largest = result.back().first;
59  result.push_back({Largest + 1, Unsupported});
60  return result;
61}
62
63static bool AEABI(const ARMSubtarget &ST) {
64  return ST.isTargetAEABI() || ST.isTargetGNUAEABI() || ST.isTargetMuslAEABI();
65}
66
67ARMLegalizerInfo::ARMLegalizerInfo(const ARMSubtarget &ST) {
68  using namespace TargetOpcode;
69
70  const LLT p0 = LLT::pointer(0, 32);
71
72  const LLT s1 = LLT::scalar(1);
73  const LLT s8 = LLT::scalar(8);
74  const LLT s16 = LLT::scalar(16);
75  const LLT s32 = LLT::scalar(32);
76  const LLT s64 = LLT::scalar(64);
77
78  getActionDefinitionsBuilder(G_GLOBAL_VALUE).legalFor({p0});
79  getActionDefinitionsBuilder(G_FRAME_INDEX).legalFor({p0});
80
81  getActionDefinitionsBuilder({G_ADD, G_SUB, G_MUL, G_AND, G_OR, G_XOR})
82      .legalFor({s32})
83      .minScalar(0, s32);
84
85  if (ST.hasDivideInARMMode())
86    getActionDefinitionsBuilder({G_SDIV, G_UDIV})
87        .legalFor({s32})
88        .clampScalar(0, s32, s32);
89  else
90    getActionDefinitionsBuilder({G_SDIV, G_UDIV})
91        .libcallFor({s32})
92        .clampScalar(0, s32, s32);
93
94  for (unsigned Op : {G_SREM, G_UREM}) {
95    setLegalizeScalarToDifferentSizeStrategy(Op, 0, widen_8_16);
96    if (ST.hasDivideInARMMode())
97      setAction({Op, s32}, Lower);
98    else if (AEABI(ST))
99      setAction({Op, s32}, Custom);
100    else
101      setAction({Op, s32}, Libcall);
102  }
103
104  getActionDefinitionsBuilder({G_SEXT, G_ZEXT, G_ANYEXT})
105      .legalForCartesianProduct({s32}, {s1, s8, s16});
106
107  getActionDefinitionsBuilder(G_INTTOPTR).legalFor({{p0, s32}});
108  getActionDefinitionsBuilder(G_PTRTOINT).legalFor({{s32, p0}});
109
110  getActionDefinitionsBuilder({G_ASHR, G_LSHR, G_SHL}).legalFor({s32});
111
112  getActionDefinitionsBuilder(G_GEP).legalFor({{p0, s32}});
113
114  getActionDefinitionsBuilder(G_SELECT).legalForCartesianProduct({s32, p0},
115                                                                 {s1});
116
117  getActionDefinitionsBuilder(G_BRCOND).legalFor({s1});
118
119  getActionDefinitionsBuilder(G_CONSTANT)
120      .legalFor({s32, p0})
121      .clampScalar(0, s32, s32);
122
123  getActionDefinitionsBuilder(G_ICMP)
124      .legalForCartesianProduct({s1}, {s32, p0})
125      .minScalar(1, s32);
126
127  // We're keeping these builders around because we'll want to add support for
128  // floating point to them.
129  auto &LoadStoreBuilder =
130      getActionDefinitionsBuilder({G_LOAD, G_STORE})
131          .legalForCartesianProduct({s1, s8, s16, s32, p0}, {p0});
132
133  auto &PhiBuilder =
134      getActionDefinitionsBuilder(G_PHI).legalFor({s32, p0}).minScalar(0, s32);
135
136  if (!ST.useSoftFloat() && ST.hasVFP2()) {
137    getActionDefinitionsBuilder(
138        {G_FADD, G_FSUB, G_FMUL, G_FDIV, G_FCONSTANT, G_FNEG})
139        .legalFor({s32, s64});
140
141    LoadStoreBuilder.legalFor({{s64, p0}});
142    PhiBuilder.legalFor({s64});
143
144    getActionDefinitionsBuilder(G_FCMP).legalForCartesianProduct({s1},
145                                                                 {s32, s64});
146
147    getActionDefinitionsBuilder(G_MERGE_VALUES).legalFor({{s64, s32}});
148    getActionDefinitionsBuilder(G_UNMERGE_VALUES).legalFor({{s32, s64}});
149
150    getActionDefinitionsBuilder(G_FPEXT).legalFor({{s64, s32}});
151    getActionDefinitionsBuilder(G_FPTRUNC).legalFor({{s32, s64}});
152
153    getActionDefinitionsBuilder({G_FPTOSI, G_FPTOUI})
154        .legalForCartesianProduct({s32}, {s32, s64});
155    getActionDefinitionsBuilder({G_SITOFP, G_UITOFP})
156        .legalForCartesianProduct({s32, s64}, {s32});
157  } else {
158    getActionDefinitionsBuilder({G_FADD, G_FSUB, G_FMUL, G_FDIV})
159        .libcallFor({s32, s64});
160
161    LoadStoreBuilder.maxScalar(0, s32);
162
163    for (auto Ty : {s32, s64})
164      setAction({G_FNEG, Ty}, Lower);
165
166    getActionDefinitionsBuilder(G_FCONSTANT).customFor({s32, s64});
167
168    getActionDefinitionsBuilder(G_FCMP).customForCartesianProduct({s1},
169                                                                  {s32, s64});
170
171    if (AEABI(ST))
172      setFCmpLibcallsAEABI();
173    else
174      setFCmpLibcallsGNU();
175
176    getActionDefinitionsBuilder(G_FPEXT).libcallFor({{s64, s32}});
177    getActionDefinitionsBuilder(G_FPTRUNC).libcallFor({{s32, s64}});
178
179    getActionDefinitionsBuilder({G_FPTOSI, G_FPTOUI})
180        .libcallForCartesianProduct({s32}, {s32, s64});
181    getActionDefinitionsBuilder({G_SITOFP, G_UITOFP})
182        .libcallForCartesianProduct({s32, s64}, {s32});
183  }
184
185  if (!ST.useSoftFloat() && ST.hasVFP4())
186    getActionDefinitionsBuilder(G_FMA).legalFor({s32, s64});
187  else
188    getActionDefinitionsBuilder(G_FMA).libcallFor({s32, s64});
189
190  getActionDefinitionsBuilder({G_FREM, G_FPOW}).libcallFor({s32, s64});
191
192  computeTables();
193  verify(*ST.getInstrInfo());
194}
195
196void ARMLegalizerInfo::setFCmpLibcallsAEABI() {
197  // FCMP_TRUE and FCMP_FALSE don't need libcalls, they should be
198  // default-initialized.
199  FCmp32Libcalls.resize(CmpInst::LAST_FCMP_PREDICATE + 1);
200  FCmp32Libcalls[CmpInst::FCMP_OEQ] = {
201      {RTLIB::OEQ_F32, CmpInst::BAD_ICMP_PREDICATE}};
202  FCmp32Libcalls[CmpInst::FCMP_OGE] = {
203      {RTLIB::OGE_F32, CmpInst::BAD_ICMP_PREDICATE}};
204  FCmp32Libcalls[CmpInst::FCMP_OGT] = {
205      {RTLIB::OGT_F32, CmpInst::BAD_ICMP_PREDICATE}};
206  FCmp32Libcalls[CmpInst::FCMP_OLE] = {
207      {RTLIB::OLE_F32, CmpInst::BAD_ICMP_PREDICATE}};
208  FCmp32Libcalls[CmpInst::FCMP_OLT] = {
209      {RTLIB::OLT_F32, CmpInst::BAD_ICMP_PREDICATE}};
210  FCmp32Libcalls[CmpInst::FCMP_ORD] = {{RTLIB::O_F32, CmpInst::ICMP_EQ}};
211  FCmp32Libcalls[CmpInst::FCMP_UGE] = {{RTLIB::OLT_F32, CmpInst::ICMP_EQ}};
212  FCmp32Libcalls[CmpInst::FCMP_UGT] = {{RTLIB::OLE_F32, CmpInst::ICMP_EQ}};
213  FCmp32Libcalls[CmpInst::FCMP_ULE] = {{RTLIB::OGT_F32, CmpInst::ICMP_EQ}};
214  FCmp32Libcalls[CmpInst::FCMP_ULT] = {{RTLIB::OGE_F32, CmpInst::ICMP_EQ}};
215  FCmp32Libcalls[CmpInst::FCMP_UNE] = {{RTLIB::UNE_F32, CmpInst::ICMP_EQ}};
216  FCmp32Libcalls[CmpInst::FCMP_UNO] = {
217      {RTLIB::UO_F32, CmpInst::BAD_ICMP_PREDICATE}};
218  FCmp32Libcalls[CmpInst::FCMP_ONE] = {
219      {RTLIB::OGT_F32, CmpInst::BAD_ICMP_PREDICATE},
220      {RTLIB::OLT_F32, CmpInst::BAD_ICMP_PREDICATE}};
221  FCmp32Libcalls[CmpInst::FCMP_UEQ] = {
222      {RTLIB::OEQ_F32, CmpInst::BAD_ICMP_PREDICATE},
223      {RTLIB::UO_F32, CmpInst::BAD_ICMP_PREDICATE}};
224
225  FCmp64Libcalls.resize(CmpInst::LAST_FCMP_PREDICATE + 1);
226  FCmp64Libcalls[CmpInst::FCMP_OEQ] = {
227      {RTLIB::OEQ_F64, CmpInst::BAD_ICMP_PREDICATE}};
228  FCmp64Libcalls[CmpInst::FCMP_OGE] = {
229      {RTLIB::OGE_F64, CmpInst::BAD_ICMP_PREDICATE}};
230  FCmp64Libcalls[CmpInst::FCMP_OGT] = {
231      {RTLIB::OGT_F64, CmpInst::BAD_ICMP_PREDICATE}};
232  FCmp64Libcalls[CmpInst::FCMP_OLE] = {
233      {RTLIB::OLE_F64, CmpInst::BAD_ICMP_PREDICATE}};
234  FCmp64Libcalls[CmpInst::FCMP_OLT] = {
235      {RTLIB::OLT_F64, CmpInst::BAD_ICMP_PREDICATE}};
236  FCmp64Libcalls[CmpInst::FCMP_ORD] = {{RTLIB::O_F64, CmpInst::ICMP_EQ}};
237  FCmp64Libcalls[CmpInst::FCMP_UGE] = {{RTLIB::OLT_F64, CmpInst::ICMP_EQ}};
238  FCmp64Libcalls[CmpInst::FCMP_UGT] = {{RTLIB::OLE_F64, CmpInst::ICMP_EQ}};
239  FCmp64Libcalls[CmpInst::FCMP_ULE] = {{RTLIB::OGT_F64, CmpInst::ICMP_EQ}};
240  FCmp64Libcalls[CmpInst::FCMP_ULT] = {{RTLIB::OGE_F64, CmpInst::ICMP_EQ}};
241  FCmp64Libcalls[CmpInst::FCMP_UNE] = {{RTLIB::UNE_F64, CmpInst::ICMP_EQ}};
242  FCmp64Libcalls[CmpInst::FCMP_UNO] = {
243      {RTLIB::UO_F64, CmpInst::BAD_ICMP_PREDICATE}};
244  FCmp64Libcalls[CmpInst::FCMP_ONE] = {
245      {RTLIB::OGT_F64, CmpInst::BAD_ICMP_PREDICATE},
246      {RTLIB::OLT_F64, CmpInst::BAD_ICMP_PREDICATE}};
247  FCmp64Libcalls[CmpInst::FCMP_UEQ] = {
248      {RTLIB::OEQ_F64, CmpInst::BAD_ICMP_PREDICATE},
249      {RTLIB::UO_F64, CmpInst::BAD_ICMP_PREDICATE}};
250}
251
252void ARMLegalizerInfo::setFCmpLibcallsGNU() {
253  // FCMP_TRUE and FCMP_FALSE don't need libcalls, they should be
254  // default-initialized.
255  FCmp32Libcalls.resize(CmpInst::LAST_FCMP_PREDICATE + 1);
256  FCmp32Libcalls[CmpInst::FCMP_OEQ] = {{RTLIB::OEQ_F32, CmpInst::ICMP_EQ}};
257  FCmp32Libcalls[CmpInst::FCMP_OGE] = {{RTLIB::OGE_F32, CmpInst::ICMP_SGE}};
258  FCmp32Libcalls[CmpInst::FCMP_OGT] = {{RTLIB::OGT_F32, CmpInst::ICMP_SGT}};
259  FCmp32Libcalls[CmpInst::FCMP_OLE] = {{RTLIB::OLE_F32, CmpInst::ICMP_SLE}};
260  FCmp32Libcalls[CmpInst::FCMP_OLT] = {{RTLIB::OLT_F32, CmpInst::ICMP_SLT}};
261  FCmp32Libcalls[CmpInst::FCMP_ORD] = {{RTLIB::O_F32, CmpInst::ICMP_EQ}};
262  FCmp32Libcalls[CmpInst::FCMP_UGE] = {{RTLIB::OLT_F32, CmpInst::ICMP_SGE}};
263  FCmp32Libcalls[CmpInst::FCMP_UGT] = {{RTLIB::OLE_F32, CmpInst::ICMP_SGT}};
264  FCmp32Libcalls[CmpInst::FCMP_ULE] = {{RTLIB::OGT_F32, CmpInst::ICMP_SLE}};
265  FCmp32Libcalls[CmpInst::FCMP_ULT] = {{RTLIB::OGE_F32, CmpInst::ICMP_SLT}};
266  FCmp32Libcalls[CmpInst::FCMP_UNE] = {{RTLIB::UNE_F32, CmpInst::ICMP_NE}};
267  FCmp32Libcalls[CmpInst::FCMP_UNO] = {{RTLIB::UO_F32, CmpInst::ICMP_NE}};
268  FCmp32Libcalls[CmpInst::FCMP_ONE] = {{RTLIB::OGT_F32, CmpInst::ICMP_SGT},
269                                       {RTLIB::OLT_F32, CmpInst::ICMP_SLT}};
270  FCmp32Libcalls[CmpInst::FCMP_UEQ] = {{RTLIB::OEQ_F32, CmpInst::ICMP_EQ},
271                                       {RTLIB::UO_F32, CmpInst::ICMP_NE}};
272
273  FCmp64Libcalls.resize(CmpInst::LAST_FCMP_PREDICATE + 1);
274  FCmp64Libcalls[CmpInst::FCMP_OEQ] = {{RTLIB::OEQ_F64, CmpInst::ICMP_EQ}};
275  FCmp64Libcalls[CmpInst::FCMP_OGE] = {{RTLIB::OGE_F64, CmpInst::ICMP_SGE}};
276  FCmp64Libcalls[CmpInst::FCMP_OGT] = {{RTLIB::OGT_F64, CmpInst::ICMP_SGT}};
277  FCmp64Libcalls[CmpInst::FCMP_OLE] = {{RTLIB::OLE_F64, CmpInst::ICMP_SLE}};
278  FCmp64Libcalls[CmpInst::FCMP_OLT] = {{RTLIB::OLT_F64, CmpInst::ICMP_SLT}};
279  FCmp64Libcalls[CmpInst::FCMP_ORD] = {{RTLIB::O_F64, CmpInst::ICMP_EQ}};
280  FCmp64Libcalls[CmpInst::FCMP_UGE] = {{RTLIB::OLT_F64, CmpInst::ICMP_SGE}};
281  FCmp64Libcalls[CmpInst::FCMP_UGT] = {{RTLIB::OLE_F64, CmpInst::ICMP_SGT}};
282  FCmp64Libcalls[CmpInst::FCMP_ULE] = {{RTLIB::OGT_F64, CmpInst::ICMP_SLE}};
283  FCmp64Libcalls[CmpInst::FCMP_ULT] = {{RTLIB::OGE_F64, CmpInst::ICMP_SLT}};
284  FCmp64Libcalls[CmpInst::FCMP_UNE] = {{RTLIB::UNE_F64, CmpInst::ICMP_NE}};
285  FCmp64Libcalls[CmpInst::FCMP_UNO] = {{RTLIB::UO_F64, CmpInst::ICMP_NE}};
286  FCmp64Libcalls[CmpInst::FCMP_ONE] = {{RTLIB::OGT_F64, CmpInst::ICMP_SGT},
287                                       {RTLIB::OLT_F64, CmpInst::ICMP_SLT}};
288  FCmp64Libcalls[CmpInst::FCMP_UEQ] = {{RTLIB::OEQ_F64, CmpInst::ICMP_EQ},
289                                       {RTLIB::UO_F64, CmpInst::ICMP_NE}};
290}
291
292ARMLegalizerInfo::FCmpLibcallsList
293ARMLegalizerInfo::getFCmpLibcalls(CmpInst::Predicate Predicate,
294                                  unsigned Size) const {
295  assert(CmpInst::isFPPredicate(Predicate) && "Unsupported FCmp predicate");
296  if (Size == 32)
297    return FCmp32Libcalls[Predicate];
298  if (Size == 64)
299    return FCmp64Libcalls[Predicate];
300  llvm_unreachable("Unsupported size for FCmp predicate");
301}
302
303bool ARMLegalizerInfo::legalizeCustom(MachineInstr &MI,
304                                      MachineRegisterInfo &MRI,
305                                      MachineIRBuilder &MIRBuilder) const {
306  using namespace TargetOpcode;
307
308  MIRBuilder.setInstr(MI);
309  LLVMContext &Ctx = MIRBuilder.getMF().getFunction().getContext();
310
311  switch (MI.getOpcode()) {
312  default:
313    return false;
314  case G_SREM:
315  case G_UREM: {
316    unsigned OriginalResult = MI.getOperand(0).getReg();
317    auto Size = MRI.getType(OriginalResult).getSizeInBits();
318    if (Size != 32)
319      return false;
320
321    auto Libcall =
322        MI.getOpcode() == G_SREM ? RTLIB::SDIVREM_I32 : RTLIB::UDIVREM_I32;
323
324    // Our divmod libcalls return a struct containing the quotient and the
325    // remainder. We need to create a virtual register for it.
326    Type *ArgTy = Type::getInt32Ty(Ctx);
327    StructType *RetTy = StructType::get(Ctx, {ArgTy, ArgTy}, /* Packed */ true);
328    auto RetVal = MRI.createGenericVirtualRegister(
329        getLLTForType(*RetTy, MIRBuilder.getMF().getDataLayout()));
330
331    auto Status = createLibcall(MIRBuilder, Libcall, {RetVal, RetTy},
332                                {{MI.getOperand(1).getReg(), ArgTy},
333                                 {MI.getOperand(2).getReg(), ArgTy}});
334    if (Status != LegalizerHelper::Legalized)
335      return false;
336
337    // The remainder is the second result of divmod. Split the return value into
338    // a new, unused register for the quotient and the destination of the
339    // original instruction for the remainder.
340    MIRBuilder.buildUnmerge(
341        {MRI.createGenericVirtualRegister(LLT::scalar(32)), OriginalResult},
342        RetVal);
343    break;
344  }
345  case G_FCMP: {
346    assert(MRI.getType(MI.getOperand(2).getReg()) ==
347               MRI.getType(MI.getOperand(3).getReg()) &&
348           "Mismatched operands for G_FCMP");
349    auto OpSize = MRI.getType(MI.getOperand(2).getReg()).getSizeInBits();
350
351    auto OriginalResult = MI.getOperand(0).getReg();
352    auto Predicate =
353        static_cast<CmpInst::Predicate>(MI.getOperand(1).getPredicate());
354    auto Libcalls = getFCmpLibcalls(Predicate, OpSize);
355
356    if (Libcalls.empty()) {
357      assert((Predicate == CmpInst::FCMP_TRUE ||
358              Predicate == CmpInst::FCMP_FALSE) &&
359             "Predicate needs libcalls, but none specified");
360      MIRBuilder.buildConstant(OriginalResult,
361                               Predicate == CmpInst::FCMP_TRUE ? 1 : 0);
362      MI.eraseFromParent();
363      return true;
364    }
365
366    assert((OpSize == 32 || OpSize == 64) && "Unsupported operand size");
367    auto *ArgTy = OpSize == 32 ? Type::getFloatTy(Ctx) : Type::getDoubleTy(Ctx);
368    auto *RetTy = Type::getInt32Ty(Ctx);
369
370    SmallVector<unsigned, 2> Results;
371    for (auto Libcall : Libcalls) {
372      auto LibcallResult = MRI.createGenericVirtualRegister(LLT::scalar(32));
373      auto Status =
374          createLibcall(MIRBuilder, Libcall.LibcallID, {LibcallResult, RetTy},
375                        {{MI.getOperand(2).getReg(), ArgTy},
376                         {MI.getOperand(3).getReg(), ArgTy}});
377
378      if (Status != LegalizerHelper::Legalized)
379        return false;
380
381      auto ProcessedResult =
382          Libcalls.size() == 1
383              ? OriginalResult
384              : MRI.createGenericVirtualRegister(MRI.getType(OriginalResult));
385
386      // We have a result, but we need to transform it into a proper 1-bit 0 or
387      // 1, taking into account the different peculiarities of the values
388      // returned by the comparison functions.
389      CmpInst::Predicate ResultPred = Libcall.Predicate;
390      if (ResultPred == CmpInst::BAD_ICMP_PREDICATE) {
391        // We have a nice 0 or 1, and we just need to truncate it back to 1 bit
392        // to keep the types consistent.
393        MIRBuilder.buildTrunc(ProcessedResult, LibcallResult);
394      } else {
395        // We need to compare against 0.
396        assert(CmpInst::isIntPredicate(ResultPred) && "Unsupported predicate");
397        auto Zero = MRI.createGenericVirtualRegister(LLT::scalar(32));
398        MIRBuilder.buildConstant(Zero, 0);
399        MIRBuilder.buildICmp(ResultPred, ProcessedResult, LibcallResult, Zero);
400      }
401      Results.push_back(ProcessedResult);
402    }
403
404    if (Results.size() != 1) {
405      assert(Results.size() == 2 && "Unexpected number of results");
406      MIRBuilder.buildOr(OriginalResult, Results[0], Results[1]);
407    }
408    break;
409  }
410  case G_FCONSTANT: {
411    // Convert to integer constants, while preserving the binary representation.
412    auto AsInteger =
413        MI.getOperand(1).getFPImm()->getValueAPF().bitcastToAPInt();
414    MIRBuilder.buildConstant(MI.getOperand(0).getReg(),
415                             *ConstantInt::get(Ctx, AsInteger));
416    break;
417  }
418  }
419
420  MI.eraseFromParent();
421  return true;
422}
423