ARMISelDAGToDAG.cpp revision 208599
1//===-- ARMISelDAGToDAG.cpp - A dag to dag inst selector for ARM ----------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines an instruction selector for the ARM target. 11// 12//===----------------------------------------------------------------------===// 13 14#include "ARM.h" 15#include "ARMAddressingModes.h" 16#include "ARMTargetMachine.h" 17#include "llvm/CallingConv.h" 18#include "llvm/Constants.h" 19#include "llvm/DerivedTypes.h" 20#include "llvm/Function.h" 21#include "llvm/Intrinsics.h" 22#include "llvm/LLVMContext.h" 23#include "llvm/CodeGen/MachineFrameInfo.h" 24#include "llvm/CodeGen/MachineFunction.h" 25#include "llvm/CodeGen/MachineInstrBuilder.h" 26#include "llvm/CodeGen/SelectionDAG.h" 27#include "llvm/CodeGen/SelectionDAGISel.h" 28#include "llvm/Target/TargetLowering.h" 29#include "llvm/Target/TargetOptions.h" 30#include "llvm/Support/CommandLine.h" 31#include "llvm/Support/Compiler.h" 32#include "llvm/Support/Debug.h" 33#include "llvm/Support/ErrorHandling.h" 34#include "llvm/Support/raw_ostream.h" 35 36using namespace llvm; 37 38static cl::opt<bool> 39UseRegSeq("neon-reg-sequence", cl::Hidden, 40 cl::desc("Use reg_sequence to model ld / st of multiple neon regs"), 41 cl::init(true)); 42 43//===--------------------------------------------------------------------===// 44/// ARMDAGToDAGISel - ARM specific code to select ARM machine 45/// instructions for SelectionDAG operations. 46/// 47namespace { 48class ARMDAGToDAGISel : public SelectionDAGISel { 49 ARMBaseTargetMachine &TM; 50 51 /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can 52 /// make the right decision when generating code for different targets. 53 const ARMSubtarget *Subtarget; 54 55public: 56 explicit ARMDAGToDAGISel(ARMBaseTargetMachine &tm, 57 CodeGenOpt::Level OptLevel) 58 : SelectionDAGISel(tm, OptLevel), TM(tm), 59 Subtarget(&TM.getSubtarget<ARMSubtarget>()) { 60 } 61 62 virtual const char *getPassName() const { 63 return "ARM Instruction Selection"; 64 } 65 66 /// getI32Imm - Return a target constant of type i32 with the specified 67 /// value. 68 inline SDValue getI32Imm(unsigned Imm) { 69 return CurDAG->getTargetConstant(Imm, MVT::i32); 70 } 71 72 SDNode *Select(SDNode *N); 73 74 bool SelectShifterOperandReg(SDNode *Op, SDValue N, SDValue &A, 75 SDValue &B, SDValue &C); 76 bool SelectAddrMode2(SDNode *Op, SDValue N, SDValue &Base, 77 SDValue &Offset, SDValue &Opc); 78 bool SelectAddrMode2Offset(SDNode *Op, SDValue N, 79 SDValue &Offset, SDValue &Opc); 80 bool SelectAddrMode3(SDNode *Op, SDValue N, SDValue &Base, 81 SDValue &Offset, SDValue &Opc); 82 bool SelectAddrMode3Offset(SDNode *Op, SDValue N, 83 SDValue &Offset, SDValue &Opc); 84 bool SelectAddrMode4(SDNode *Op, SDValue N, SDValue &Addr, 85 SDValue &Mode); 86 bool SelectAddrMode5(SDNode *Op, SDValue N, SDValue &Base, 87 SDValue &Offset); 88 bool SelectAddrMode6(SDNode *Op, SDValue N, SDValue &Addr, SDValue &Align); 89 90 bool SelectAddrModePC(SDNode *Op, SDValue N, SDValue &Offset, 91 SDValue &Label); 92 93 bool SelectThumbAddrModeRR(SDNode *Op, SDValue N, SDValue &Base, 94 SDValue &Offset); 95 bool SelectThumbAddrModeRI5(SDNode *Op, SDValue N, unsigned Scale, 96 SDValue &Base, SDValue &OffImm, 97 SDValue &Offset); 98 bool SelectThumbAddrModeS1(SDNode *Op, SDValue N, SDValue &Base, 99 SDValue &OffImm, SDValue &Offset); 100 bool SelectThumbAddrModeS2(SDNode *Op, SDValue N, SDValue &Base, 101 SDValue &OffImm, SDValue &Offset); 102 bool SelectThumbAddrModeS4(SDNode *Op, SDValue N, SDValue &Base, 103 SDValue &OffImm, SDValue &Offset); 104 bool SelectThumbAddrModeSP(SDNode *Op, SDValue N, SDValue &Base, 105 SDValue &OffImm); 106 107 bool SelectT2ShifterOperandReg(SDNode *Op, SDValue N, 108 SDValue &BaseReg, SDValue &Opc); 109 bool SelectT2AddrModeImm12(SDNode *Op, SDValue N, SDValue &Base, 110 SDValue &OffImm); 111 bool SelectT2AddrModeImm8(SDNode *Op, SDValue N, SDValue &Base, 112 SDValue &OffImm); 113 bool SelectT2AddrModeImm8Offset(SDNode *Op, SDValue N, 114 SDValue &OffImm); 115 bool SelectT2AddrModeImm8s4(SDNode *Op, SDValue N, SDValue &Base, 116 SDValue &OffImm); 117 bool SelectT2AddrModeSoReg(SDNode *Op, SDValue N, SDValue &Base, 118 SDValue &OffReg, SDValue &ShImm); 119 120 // Include the pieces autogenerated from the target description. 121#include "ARMGenDAGISel.inc" 122 123private: 124 /// SelectARMIndexedLoad - Indexed (pre/post inc/dec) load matching code for 125 /// ARM. 126 SDNode *SelectARMIndexedLoad(SDNode *N); 127 SDNode *SelectT2IndexedLoad(SDNode *N); 128 129 /// SelectVLD - Select NEON load intrinsics. NumVecs should be 130 /// 1, 2, 3 or 4. The opcode arrays specify the instructions used for 131 /// loads of D registers and even subregs and odd subregs of Q registers. 132 /// For NumVecs <= 2, QOpcodes1 is not used. 133 SDNode *SelectVLD(SDNode *N, unsigned NumVecs, unsigned *DOpcodes, 134 unsigned *QOpcodes0, unsigned *QOpcodes1); 135 136 /// SelectVST - Select NEON store intrinsics. NumVecs should 137 /// be 1, 2, 3 or 4. The opcode arrays specify the instructions used for 138 /// stores of D registers and even subregs and odd subregs of Q registers. 139 /// For NumVecs <= 2, QOpcodes1 is not used. 140 SDNode *SelectVST(SDNode *N, unsigned NumVecs, unsigned *DOpcodes, 141 unsigned *QOpcodes0, unsigned *QOpcodes1); 142 143 /// SelectVLDSTLane - Select NEON load/store lane intrinsics. NumVecs should 144 /// be 2, 3 or 4. The opcode arrays specify the instructions used for 145 /// load/store of D registers and even subregs and odd subregs of Q registers. 146 SDNode *SelectVLDSTLane(SDNode *N, bool IsLoad, unsigned NumVecs, 147 unsigned *DOpcodes, unsigned *QOpcodes0, 148 unsigned *QOpcodes1); 149 150 /// SelectV6T2BitfieldExtractOp - Select SBFX/UBFX instructions for ARM. 151 SDNode *SelectV6T2BitfieldExtractOp(SDNode *N, bool isSigned); 152 153 /// SelectCMOVOp - Select CMOV instructions for ARM. 154 SDNode *SelectCMOVOp(SDNode *N); 155 SDNode *SelectT2CMOVShiftOp(SDNode *N, SDValue FalseVal, SDValue TrueVal, 156 ARMCC::CondCodes CCVal, SDValue CCR, 157 SDValue InFlag); 158 SDNode *SelectARMCMOVShiftOp(SDNode *N, SDValue FalseVal, SDValue TrueVal, 159 ARMCC::CondCodes CCVal, SDValue CCR, 160 SDValue InFlag); 161 SDNode *SelectT2CMOVSoImmOp(SDNode *N, SDValue FalseVal, SDValue TrueVal, 162 ARMCC::CondCodes CCVal, SDValue CCR, 163 SDValue InFlag); 164 SDNode *SelectARMCMOVSoImmOp(SDNode *N, SDValue FalseVal, SDValue TrueVal, 165 ARMCC::CondCodes CCVal, SDValue CCR, 166 SDValue InFlag); 167 168 SDNode *SelectConcatVector(SDNode *N); 169 170 /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for 171 /// inline asm expressions. 172 virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op, 173 char ConstraintCode, 174 std::vector<SDValue> &OutOps); 175 176 /// PairDRegs - Form a quad register from a pair of D registers. 177 /// 178 SDNode *PairDRegs(EVT VT, SDValue V0, SDValue V1); 179 180 /// PairDRegs - Form a quad register pair from a pair of Q registers. 181 /// 182 SDNode *PairQRegs(EVT VT, SDValue V0, SDValue V1); 183 184 /// QuadDRegs - Form a quad register pair from a quad of D registers. 185 /// 186 SDNode *QuadDRegs(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3); 187 188 /// QuadQRegs - Form 4 consecutive Q registers. 189 /// 190 SDNode *QuadQRegs(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3); 191 192 /// OctoDRegs - Form 8 consecutive D registers. 193 /// 194 SDNode *OctoDRegs(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3, 195 SDValue V4, SDValue V5, SDValue V6, SDValue V7); 196}; 197} 198 199/// isInt32Immediate - This method tests to see if the node is a 32-bit constant 200/// operand. If so Imm will receive the 32-bit value. 201static bool isInt32Immediate(SDNode *N, unsigned &Imm) { 202 if (N->getOpcode() == ISD::Constant && N->getValueType(0) == MVT::i32) { 203 Imm = cast<ConstantSDNode>(N)->getZExtValue(); 204 return true; 205 } 206 return false; 207} 208 209// isInt32Immediate - This method tests to see if a constant operand. 210// If so Imm will receive the 32 bit value. 211static bool isInt32Immediate(SDValue N, unsigned &Imm) { 212 return isInt32Immediate(N.getNode(), Imm); 213} 214 215// isOpcWithIntImmediate - This method tests to see if the node is a specific 216// opcode and that it has a immediate integer right operand. 217// If so Imm will receive the 32 bit value. 218static bool isOpcWithIntImmediate(SDNode *N, unsigned Opc, unsigned& Imm) { 219 return N->getOpcode() == Opc && 220 isInt32Immediate(N->getOperand(1).getNode(), Imm); 221} 222 223 224bool ARMDAGToDAGISel::SelectShifterOperandReg(SDNode *Op, 225 SDValue N, 226 SDValue &BaseReg, 227 SDValue &ShReg, 228 SDValue &Opc) { 229 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N); 230 231 // Don't match base register only case. That is matched to a separate 232 // lower complexity pattern with explicit register operand. 233 if (ShOpcVal == ARM_AM::no_shift) return false; 234 235 BaseReg = N.getOperand(0); 236 unsigned ShImmVal = 0; 237 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) { 238 ShReg = CurDAG->getRegister(0, MVT::i32); 239 ShImmVal = RHS->getZExtValue() & 31; 240 } else { 241 ShReg = N.getOperand(1); 242 } 243 Opc = CurDAG->getTargetConstant(ARM_AM::getSORegOpc(ShOpcVal, ShImmVal), 244 MVT::i32); 245 return true; 246} 247 248bool ARMDAGToDAGISel::SelectAddrMode2(SDNode *Op, SDValue N, 249 SDValue &Base, SDValue &Offset, 250 SDValue &Opc) { 251 if (N.getOpcode() == ISD::MUL) { 252 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) { 253 // X * [3,5,9] -> X + X * [2,4,8] etc. 254 int RHSC = (int)RHS->getZExtValue(); 255 if (RHSC & 1) { 256 RHSC = RHSC & ~1; 257 ARM_AM::AddrOpc AddSub = ARM_AM::add; 258 if (RHSC < 0) { 259 AddSub = ARM_AM::sub; 260 RHSC = - RHSC; 261 } 262 if (isPowerOf2_32(RHSC)) { 263 unsigned ShAmt = Log2_32(RHSC); 264 Base = Offset = N.getOperand(0); 265 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt, 266 ARM_AM::lsl), 267 MVT::i32); 268 return true; 269 } 270 } 271 } 272 } 273 274 if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB) { 275 Base = N; 276 if (N.getOpcode() == ISD::FrameIndex) { 277 int FI = cast<FrameIndexSDNode>(N)->getIndex(); 278 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy()); 279 } else if (N.getOpcode() == ARMISD::Wrapper && 280 !(Subtarget->useMovt() && 281 N.getOperand(0).getOpcode() == ISD::TargetGlobalAddress)) { 282 Base = N.getOperand(0); 283 } 284 Offset = CurDAG->getRegister(0, MVT::i32); 285 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(ARM_AM::add, 0, 286 ARM_AM::no_shift), 287 MVT::i32); 288 return true; 289 } 290 291 // Match simple R +/- imm12 operands. 292 if (N.getOpcode() == ISD::ADD) 293 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) { 294 int RHSC = (int)RHS->getZExtValue(); 295 if ((RHSC >= 0 && RHSC < 0x1000) || 296 (RHSC < 0 && RHSC > -0x1000)) { // 12 bits. 297 Base = N.getOperand(0); 298 if (Base.getOpcode() == ISD::FrameIndex) { 299 int FI = cast<FrameIndexSDNode>(Base)->getIndex(); 300 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy()); 301 } 302 Offset = CurDAG->getRegister(0, MVT::i32); 303 304 ARM_AM::AddrOpc AddSub = ARM_AM::add; 305 if (RHSC < 0) { 306 AddSub = ARM_AM::sub; 307 RHSC = - RHSC; 308 } 309 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, RHSC, 310 ARM_AM::no_shift), 311 MVT::i32); 312 return true; 313 } 314 } 315 316 // Otherwise this is R +/- [possibly shifted] R. 317 ARM_AM::AddrOpc AddSub = N.getOpcode() == ISD::ADD ? ARM_AM::add:ARM_AM::sub; 318 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOperand(1)); 319 unsigned ShAmt = 0; 320 321 Base = N.getOperand(0); 322 Offset = N.getOperand(1); 323 324 if (ShOpcVal != ARM_AM::no_shift) { 325 // Check to see if the RHS of the shift is a constant, if not, we can't fold 326 // it. 327 if (ConstantSDNode *Sh = 328 dyn_cast<ConstantSDNode>(N.getOperand(1).getOperand(1))) { 329 ShAmt = Sh->getZExtValue(); 330 Offset = N.getOperand(1).getOperand(0); 331 } else { 332 ShOpcVal = ARM_AM::no_shift; 333 } 334 } 335 336 // Try matching (R shl C) + (R). 337 if (N.getOpcode() == ISD::ADD && ShOpcVal == ARM_AM::no_shift) { 338 ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOperand(0)); 339 if (ShOpcVal != ARM_AM::no_shift) { 340 // Check to see if the RHS of the shift is a constant, if not, we can't 341 // fold it. 342 if (ConstantSDNode *Sh = 343 dyn_cast<ConstantSDNode>(N.getOperand(0).getOperand(1))) { 344 ShAmt = Sh->getZExtValue(); 345 Offset = N.getOperand(0).getOperand(0); 346 Base = N.getOperand(1); 347 } else { 348 ShOpcVal = ARM_AM::no_shift; 349 } 350 } 351 } 352 353 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt, ShOpcVal), 354 MVT::i32); 355 return true; 356} 357 358bool ARMDAGToDAGISel::SelectAddrMode2Offset(SDNode *Op, SDValue N, 359 SDValue &Offset, SDValue &Opc) { 360 unsigned Opcode = Op->getOpcode(); 361 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD) 362 ? cast<LoadSDNode>(Op)->getAddressingMode() 363 : cast<StoreSDNode>(Op)->getAddressingMode(); 364 ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC) 365 ? ARM_AM::add : ARM_AM::sub; 366 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N)) { 367 int Val = (int)C->getZExtValue(); 368 if (Val >= 0 && Val < 0x1000) { // 12 bits. 369 Offset = CurDAG->getRegister(0, MVT::i32); 370 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, Val, 371 ARM_AM::no_shift), 372 MVT::i32); 373 return true; 374 } 375 } 376 377 Offset = N; 378 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N); 379 unsigned ShAmt = 0; 380 if (ShOpcVal != ARM_AM::no_shift) { 381 // Check to see if the RHS of the shift is a constant, if not, we can't fold 382 // it. 383 if (ConstantSDNode *Sh = dyn_cast<ConstantSDNode>(N.getOperand(1))) { 384 ShAmt = Sh->getZExtValue(); 385 Offset = N.getOperand(0); 386 } else { 387 ShOpcVal = ARM_AM::no_shift; 388 } 389 } 390 391 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt, ShOpcVal), 392 MVT::i32); 393 return true; 394} 395 396 397bool ARMDAGToDAGISel::SelectAddrMode3(SDNode *Op, SDValue N, 398 SDValue &Base, SDValue &Offset, 399 SDValue &Opc) { 400 if (N.getOpcode() == ISD::SUB) { 401 // X - C is canonicalize to X + -C, no need to handle it here. 402 Base = N.getOperand(0); 403 Offset = N.getOperand(1); 404 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::sub, 0),MVT::i32); 405 return true; 406 } 407 408 if (N.getOpcode() != ISD::ADD) { 409 Base = N; 410 if (N.getOpcode() == ISD::FrameIndex) { 411 int FI = cast<FrameIndexSDNode>(N)->getIndex(); 412 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy()); 413 } 414 Offset = CurDAG->getRegister(0, MVT::i32); 415 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::add, 0),MVT::i32); 416 return true; 417 } 418 419 // If the RHS is +/- imm8, fold into addr mode. 420 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) { 421 int RHSC = (int)RHS->getZExtValue(); 422 if ((RHSC >= 0 && RHSC < 256) || 423 (RHSC < 0 && RHSC > -256)) { // note -256 itself isn't allowed. 424 Base = N.getOperand(0); 425 if (Base.getOpcode() == ISD::FrameIndex) { 426 int FI = cast<FrameIndexSDNode>(Base)->getIndex(); 427 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy()); 428 } 429 Offset = CurDAG->getRegister(0, MVT::i32); 430 431 ARM_AM::AddrOpc AddSub = ARM_AM::add; 432 if (RHSC < 0) { 433 AddSub = ARM_AM::sub; 434 RHSC = - RHSC; 435 } 436 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(AddSub, RHSC),MVT::i32); 437 return true; 438 } 439 } 440 441 Base = N.getOperand(0); 442 Offset = N.getOperand(1); 443 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::add, 0), MVT::i32); 444 return true; 445} 446 447bool ARMDAGToDAGISel::SelectAddrMode3Offset(SDNode *Op, SDValue N, 448 SDValue &Offset, SDValue &Opc) { 449 unsigned Opcode = Op->getOpcode(); 450 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD) 451 ? cast<LoadSDNode>(Op)->getAddressingMode() 452 : cast<StoreSDNode>(Op)->getAddressingMode(); 453 ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC) 454 ? ARM_AM::add : ARM_AM::sub; 455 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N)) { 456 int Val = (int)C->getZExtValue(); 457 if (Val >= 0 && Val < 256) { 458 Offset = CurDAG->getRegister(0, MVT::i32); 459 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(AddSub, Val), MVT::i32); 460 return true; 461 } 462 } 463 464 Offset = N; 465 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(AddSub, 0), MVT::i32); 466 return true; 467} 468 469bool ARMDAGToDAGISel::SelectAddrMode4(SDNode *Op, SDValue N, 470 SDValue &Addr, SDValue &Mode) { 471 Addr = N; 472 Mode = CurDAG->getTargetConstant(0, MVT::i32); 473 return true; 474} 475 476bool ARMDAGToDAGISel::SelectAddrMode5(SDNode *Op, SDValue N, 477 SDValue &Base, SDValue &Offset) { 478 if (N.getOpcode() != ISD::ADD) { 479 Base = N; 480 if (N.getOpcode() == ISD::FrameIndex) { 481 int FI = cast<FrameIndexSDNode>(N)->getIndex(); 482 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy()); 483 } else if (N.getOpcode() == ARMISD::Wrapper && 484 !(Subtarget->useMovt() && 485 N.getOperand(0).getOpcode() == ISD::TargetGlobalAddress)) { 486 Base = N.getOperand(0); 487 } 488 Offset = CurDAG->getTargetConstant(ARM_AM::getAM5Opc(ARM_AM::add, 0), 489 MVT::i32); 490 return true; 491 } 492 493 // If the RHS is +/- imm8, fold into addr mode. 494 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) { 495 int RHSC = (int)RHS->getZExtValue(); 496 if ((RHSC & 3) == 0) { // The constant is implicitly multiplied by 4. 497 RHSC >>= 2; 498 if ((RHSC >= 0 && RHSC < 256) || 499 (RHSC < 0 && RHSC > -256)) { // note -256 itself isn't allowed. 500 Base = N.getOperand(0); 501 if (Base.getOpcode() == ISD::FrameIndex) { 502 int FI = cast<FrameIndexSDNode>(Base)->getIndex(); 503 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy()); 504 } 505 506 ARM_AM::AddrOpc AddSub = ARM_AM::add; 507 if (RHSC < 0) { 508 AddSub = ARM_AM::sub; 509 RHSC = - RHSC; 510 } 511 Offset = CurDAG->getTargetConstant(ARM_AM::getAM5Opc(AddSub, RHSC), 512 MVT::i32); 513 return true; 514 } 515 } 516 } 517 518 Base = N; 519 Offset = CurDAG->getTargetConstant(ARM_AM::getAM5Opc(ARM_AM::add, 0), 520 MVT::i32); 521 return true; 522} 523 524bool ARMDAGToDAGISel::SelectAddrMode6(SDNode *Op, SDValue N, 525 SDValue &Addr, SDValue &Align) { 526 Addr = N; 527 // Default to no alignment. 528 Align = CurDAG->getTargetConstant(0, MVT::i32); 529 return true; 530} 531 532bool ARMDAGToDAGISel::SelectAddrModePC(SDNode *Op, SDValue N, 533 SDValue &Offset, SDValue &Label) { 534 if (N.getOpcode() == ARMISD::PIC_ADD && N.hasOneUse()) { 535 Offset = N.getOperand(0); 536 SDValue N1 = N.getOperand(1); 537 Label = CurDAG->getTargetConstant(cast<ConstantSDNode>(N1)->getZExtValue(), 538 MVT::i32); 539 return true; 540 } 541 return false; 542} 543 544bool ARMDAGToDAGISel::SelectThumbAddrModeRR(SDNode *Op, SDValue N, 545 SDValue &Base, SDValue &Offset){ 546 // FIXME dl should come from the parent load or store, not the address 547 DebugLoc dl = Op->getDebugLoc(); 548 if (N.getOpcode() != ISD::ADD) { 549 ConstantSDNode *NC = dyn_cast<ConstantSDNode>(N); 550 if (!NC || NC->getZExtValue() != 0) 551 return false; 552 553 Base = Offset = N; 554 return true; 555 } 556 557 Base = N.getOperand(0); 558 Offset = N.getOperand(1); 559 return true; 560} 561 562bool 563ARMDAGToDAGISel::SelectThumbAddrModeRI5(SDNode *Op, SDValue N, 564 unsigned Scale, SDValue &Base, 565 SDValue &OffImm, SDValue &Offset) { 566 if (Scale == 4) { 567 SDValue TmpBase, TmpOffImm; 568 if (SelectThumbAddrModeSP(Op, N, TmpBase, TmpOffImm)) 569 return false; // We want to select tLDRspi / tSTRspi instead. 570 if (N.getOpcode() == ARMISD::Wrapper && 571 N.getOperand(0).getOpcode() == ISD::TargetConstantPool) 572 return false; // We want to select tLDRpci instead. 573 } 574 575 if (N.getOpcode() != ISD::ADD) { 576 if (N.getOpcode() == ARMISD::Wrapper && 577 !(Subtarget->useMovt() && 578 N.getOperand(0).getOpcode() == ISD::TargetGlobalAddress)) { 579 Base = N.getOperand(0); 580 } else 581 Base = N; 582 583 Offset = CurDAG->getRegister(0, MVT::i32); 584 OffImm = CurDAG->getTargetConstant(0, MVT::i32); 585 return true; 586 } 587 588 // Thumb does not have [sp, r] address mode. 589 RegisterSDNode *LHSR = dyn_cast<RegisterSDNode>(N.getOperand(0)); 590 RegisterSDNode *RHSR = dyn_cast<RegisterSDNode>(N.getOperand(1)); 591 if ((LHSR && LHSR->getReg() == ARM::SP) || 592 (RHSR && RHSR->getReg() == ARM::SP)) { 593 Base = N; 594 Offset = CurDAG->getRegister(0, MVT::i32); 595 OffImm = CurDAG->getTargetConstant(0, MVT::i32); 596 return true; 597 } 598 599 // If the RHS is + imm5 * scale, fold into addr mode. 600 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) { 601 int RHSC = (int)RHS->getZExtValue(); 602 if ((RHSC & (Scale-1)) == 0) { // The constant is implicitly multiplied. 603 RHSC /= Scale; 604 if (RHSC >= 0 && RHSC < 32) { 605 Base = N.getOperand(0); 606 Offset = CurDAG->getRegister(0, MVT::i32); 607 OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32); 608 return true; 609 } 610 } 611 } 612 613 Base = N.getOperand(0); 614 Offset = N.getOperand(1); 615 OffImm = CurDAG->getTargetConstant(0, MVT::i32); 616 return true; 617} 618 619bool ARMDAGToDAGISel::SelectThumbAddrModeS1(SDNode *Op, SDValue N, 620 SDValue &Base, SDValue &OffImm, 621 SDValue &Offset) { 622 return SelectThumbAddrModeRI5(Op, N, 1, Base, OffImm, Offset); 623} 624 625bool ARMDAGToDAGISel::SelectThumbAddrModeS2(SDNode *Op, SDValue N, 626 SDValue &Base, SDValue &OffImm, 627 SDValue &Offset) { 628 return SelectThumbAddrModeRI5(Op, N, 2, Base, OffImm, Offset); 629} 630 631bool ARMDAGToDAGISel::SelectThumbAddrModeS4(SDNode *Op, SDValue N, 632 SDValue &Base, SDValue &OffImm, 633 SDValue &Offset) { 634 return SelectThumbAddrModeRI5(Op, N, 4, Base, OffImm, Offset); 635} 636 637bool ARMDAGToDAGISel::SelectThumbAddrModeSP(SDNode *Op, SDValue N, 638 SDValue &Base, SDValue &OffImm) { 639 if (N.getOpcode() == ISD::FrameIndex) { 640 int FI = cast<FrameIndexSDNode>(N)->getIndex(); 641 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy()); 642 OffImm = CurDAG->getTargetConstant(0, MVT::i32); 643 return true; 644 } 645 646 if (N.getOpcode() != ISD::ADD) 647 return false; 648 649 RegisterSDNode *LHSR = dyn_cast<RegisterSDNode>(N.getOperand(0)); 650 if (N.getOperand(0).getOpcode() == ISD::FrameIndex || 651 (LHSR && LHSR->getReg() == ARM::SP)) { 652 // If the RHS is + imm8 * scale, fold into addr mode. 653 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) { 654 int RHSC = (int)RHS->getZExtValue(); 655 if ((RHSC & 3) == 0) { // The constant is implicitly multiplied. 656 RHSC >>= 2; 657 if (RHSC >= 0 && RHSC < 256) { 658 Base = N.getOperand(0); 659 if (Base.getOpcode() == ISD::FrameIndex) { 660 int FI = cast<FrameIndexSDNode>(Base)->getIndex(); 661 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy()); 662 } 663 OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32); 664 return true; 665 } 666 } 667 } 668 } 669 670 return false; 671} 672 673bool ARMDAGToDAGISel::SelectT2ShifterOperandReg(SDNode *Op, SDValue N, 674 SDValue &BaseReg, 675 SDValue &Opc) { 676 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N); 677 678 // Don't match base register only case. That is matched to a separate 679 // lower complexity pattern with explicit register operand. 680 if (ShOpcVal == ARM_AM::no_shift) return false; 681 682 BaseReg = N.getOperand(0); 683 unsigned ShImmVal = 0; 684 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) { 685 ShImmVal = RHS->getZExtValue() & 31; 686 Opc = getI32Imm(ARM_AM::getSORegOpc(ShOpcVal, ShImmVal)); 687 return true; 688 } 689 690 return false; 691} 692 693bool ARMDAGToDAGISel::SelectT2AddrModeImm12(SDNode *Op, SDValue N, 694 SDValue &Base, SDValue &OffImm) { 695 // Match simple R + imm12 operands. 696 697 // Base only. 698 if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB) { 699 if (N.getOpcode() == ISD::FrameIndex) { 700 // Match frame index... 701 int FI = cast<FrameIndexSDNode>(N)->getIndex(); 702 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy()); 703 OffImm = CurDAG->getTargetConstant(0, MVT::i32); 704 return true; 705 } else if (N.getOpcode() == ARMISD::Wrapper && 706 !(Subtarget->useMovt() && 707 N.getOperand(0).getOpcode() == ISD::TargetGlobalAddress)) { 708 Base = N.getOperand(0); 709 if (Base.getOpcode() == ISD::TargetConstantPool) 710 return false; // We want to select t2LDRpci instead. 711 } else 712 Base = N; 713 OffImm = CurDAG->getTargetConstant(0, MVT::i32); 714 return true; 715 } 716 717 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) { 718 if (SelectT2AddrModeImm8(Op, N, Base, OffImm)) 719 // Let t2LDRi8 handle (R - imm8). 720 return false; 721 722 int RHSC = (int)RHS->getZExtValue(); 723 if (N.getOpcode() == ISD::SUB) 724 RHSC = -RHSC; 725 726 if (RHSC >= 0 && RHSC < 0x1000) { // 12 bits (unsigned) 727 Base = N.getOperand(0); 728 if (Base.getOpcode() == ISD::FrameIndex) { 729 int FI = cast<FrameIndexSDNode>(Base)->getIndex(); 730 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy()); 731 } 732 OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32); 733 return true; 734 } 735 } 736 737 // Base only. 738 Base = N; 739 OffImm = CurDAG->getTargetConstant(0, MVT::i32); 740 return true; 741} 742 743bool ARMDAGToDAGISel::SelectT2AddrModeImm8(SDNode *Op, SDValue N, 744 SDValue &Base, SDValue &OffImm) { 745 // Match simple R - imm8 operands. 746 if (N.getOpcode() == ISD::ADD || N.getOpcode() == ISD::SUB) { 747 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) { 748 int RHSC = (int)RHS->getSExtValue(); 749 if (N.getOpcode() == ISD::SUB) 750 RHSC = -RHSC; 751 752 if ((RHSC >= -255) && (RHSC < 0)) { // 8 bits (always negative) 753 Base = N.getOperand(0); 754 if (Base.getOpcode() == ISD::FrameIndex) { 755 int FI = cast<FrameIndexSDNode>(Base)->getIndex(); 756 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy()); 757 } 758 OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32); 759 return true; 760 } 761 } 762 } 763 764 return false; 765} 766 767bool ARMDAGToDAGISel::SelectT2AddrModeImm8Offset(SDNode *Op, SDValue N, 768 SDValue &OffImm){ 769 unsigned Opcode = Op->getOpcode(); 770 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD) 771 ? cast<LoadSDNode>(Op)->getAddressingMode() 772 : cast<StoreSDNode>(Op)->getAddressingMode(); 773 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N)) { 774 int RHSC = (int)RHS->getZExtValue(); 775 if (RHSC >= 0 && RHSC < 0x100) { // 8 bits. 776 OffImm = ((AM == ISD::PRE_INC) || (AM == ISD::POST_INC)) 777 ? CurDAG->getTargetConstant(RHSC, MVT::i32) 778 : CurDAG->getTargetConstant(-RHSC, MVT::i32); 779 return true; 780 } 781 } 782 783 return false; 784} 785 786bool ARMDAGToDAGISel::SelectT2AddrModeImm8s4(SDNode *Op, SDValue N, 787 SDValue &Base, SDValue &OffImm) { 788 if (N.getOpcode() == ISD::ADD) { 789 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) { 790 int RHSC = (int)RHS->getZExtValue(); 791 if (((RHSC & 0x3) == 0) && 792 ((RHSC >= 0 && RHSC < 0x400) || (RHSC < 0 && RHSC > -0x400))) { // 8 bits. 793 Base = N.getOperand(0); 794 OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32); 795 return true; 796 } 797 } 798 } else if (N.getOpcode() == ISD::SUB) { 799 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) { 800 int RHSC = (int)RHS->getZExtValue(); 801 if (((RHSC & 0x3) == 0) && (RHSC >= 0 && RHSC < 0x400)) { // 8 bits. 802 Base = N.getOperand(0); 803 OffImm = CurDAG->getTargetConstant(-RHSC, MVT::i32); 804 return true; 805 } 806 } 807 } 808 809 return false; 810} 811 812bool ARMDAGToDAGISel::SelectT2AddrModeSoReg(SDNode *Op, SDValue N, 813 SDValue &Base, 814 SDValue &OffReg, SDValue &ShImm) { 815 // (R - imm8) should be handled by t2LDRi8. The rest are handled by t2LDRi12. 816 if (N.getOpcode() != ISD::ADD) 817 return false; 818 819 // Leave (R + imm12) for t2LDRi12, (R - imm8) for t2LDRi8. 820 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) { 821 int RHSC = (int)RHS->getZExtValue(); 822 if (RHSC >= 0 && RHSC < 0x1000) // 12 bits (unsigned) 823 return false; 824 else if (RHSC < 0 && RHSC >= -255) // 8 bits 825 return false; 826 } 827 828 // Look for (R + R) or (R + (R << [1,2,3])). 829 unsigned ShAmt = 0; 830 Base = N.getOperand(0); 831 OffReg = N.getOperand(1); 832 833 // Swap if it is ((R << c) + R). 834 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(OffReg); 835 if (ShOpcVal != ARM_AM::lsl) { 836 ShOpcVal = ARM_AM::getShiftOpcForNode(Base); 837 if (ShOpcVal == ARM_AM::lsl) 838 std::swap(Base, OffReg); 839 } 840 841 if (ShOpcVal == ARM_AM::lsl) { 842 // Check to see if the RHS of the shift is a constant, if not, we can't fold 843 // it. 844 if (ConstantSDNode *Sh = dyn_cast<ConstantSDNode>(OffReg.getOperand(1))) { 845 ShAmt = Sh->getZExtValue(); 846 if (ShAmt >= 4) { 847 ShAmt = 0; 848 ShOpcVal = ARM_AM::no_shift; 849 } else 850 OffReg = OffReg.getOperand(0); 851 } else { 852 ShOpcVal = ARM_AM::no_shift; 853 } 854 } 855 856 ShImm = CurDAG->getTargetConstant(ShAmt, MVT::i32); 857 858 return true; 859} 860 861//===--------------------------------------------------------------------===// 862 863/// getAL - Returns a ARMCC::AL immediate node. 864static inline SDValue getAL(SelectionDAG *CurDAG) { 865 return CurDAG->getTargetConstant((uint64_t)ARMCC::AL, MVT::i32); 866} 867 868SDNode *ARMDAGToDAGISel::SelectARMIndexedLoad(SDNode *N) { 869 LoadSDNode *LD = cast<LoadSDNode>(N); 870 ISD::MemIndexedMode AM = LD->getAddressingMode(); 871 if (AM == ISD::UNINDEXED) 872 return NULL; 873 874 EVT LoadedVT = LD->getMemoryVT(); 875 SDValue Offset, AMOpc; 876 bool isPre = (AM == ISD::PRE_INC) || (AM == ISD::PRE_DEC); 877 unsigned Opcode = 0; 878 bool Match = false; 879 if (LoadedVT == MVT::i32 && 880 SelectAddrMode2Offset(N, LD->getOffset(), Offset, AMOpc)) { 881 Opcode = isPre ? ARM::LDR_PRE : ARM::LDR_POST; 882 Match = true; 883 } else if (LoadedVT == MVT::i16 && 884 SelectAddrMode3Offset(N, LD->getOffset(), Offset, AMOpc)) { 885 Match = true; 886 Opcode = (LD->getExtensionType() == ISD::SEXTLOAD) 887 ? (isPre ? ARM::LDRSH_PRE : ARM::LDRSH_POST) 888 : (isPre ? ARM::LDRH_PRE : ARM::LDRH_POST); 889 } else if (LoadedVT == MVT::i8 || LoadedVT == MVT::i1) { 890 if (LD->getExtensionType() == ISD::SEXTLOAD) { 891 if (SelectAddrMode3Offset(N, LD->getOffset(), Offset, AMOpc)) { 892 Match = true; 893 Opcode = isPre ? ARM::LDRSB_PRE : ARM::LDRSB_POST; 894 } 895 } else { 896 if (SelectAddrMode2Offset(N, LD->getOffset(), Offset, AMOpc)) { 897 Match = true; 898 Opcode = isPre ? ARM::LDRB_PRE : ARM::LDRB_POST; 899 } 900 } 901 } 902 903 if (Match) { 904 SDValue Chain = LD->getChain(); 905 SDValue Base = LD->getBasePtr(); 906 SDValue Ops[]= { Base, Offset, AMOpc, getAL(CurDAG), 907 CurDAG->getRegister(0, MVT::i32), Chain }; 908 return CurDAG->getMachineNode(Opcode, N->getDebugLoc(), MVT::i32, MVT::i32, 909 MVT::Other, Ops, 6); 910 } 911 912 return NULL; 913} 914 915SDNode *ARMDAGToDAGISel::SelectT2IndexedLoad(SDNode *N) { 916 LoadSDNode *LD = cast<LoadSDNode>(N); 917 ISD::MemIndexedMode AM = LD->getAddressingMode(); 918 if (AM == ISD::UNINDEXED) 919 return NULL; 920 921 EVT LoadedVT = LD->getMemoryVT(); 922 bool isSExtLd = LD->getExtensionType() == ISD::SEXTLOAD; 923 SDValue Offset; 924 bool isPre = (AM == ISD::PRE_INC) || (AM == ISD::PRE_DEC); 925 unsigned Opcode = 0; 926 bool Match = false; 927 if (SelectT2AddrModeImm8Offset(N, LD->getOffset(), Offset)) { 928 switch (LoadedVT.getSimpleVT().SimpleTy) { 929 case MVT::i32: 930 Opcode = isPre ? ARM::t2LDR_PRE : ARM::t2LDR_POST; 931 break; 932 case MVT::i16: 933 if (isSExtLd) 934 Opcode = isPre ? ARM::t2LDRSH_PRE : ARM::t2LDRSH_POST; 935 else 936 Opcode = isPre ? ARM::t2LDRH_PRE : ARM::t2LDRH_POST; 937 break; 938 case MVT::i8: 939 case MVT::i1: 940 if (isSExtLd) 941 Opcode = isPre ? ARM::t2LDRSB_PRE : ARM::t2LDRSB_POST; 942 else 943 Opcode = isPre ? ARM::t2LDRB_PRE : ARM::t2LDRB_POST; 944 break; 945 default: 946 return NULL; 947 } 948 Match = true; 949 } 950 951 if (Match) { 952 SDValue Chain = LD->getChain(); 953 SDValue Base = LD->getBasePtr(); 954 SDValue Ops[]= { Base, Offset, getAL(CurDAG), 955 CurDAG->getRegister(0, MVT::i32), Chain }; 956 return CurDAG->getMachineNode(Opcode, N->getDebugLoc(), MVT::i32, MVT::i32, 957 MVT::Other, Ops, 5); 958 } 959 960 return NULL; 961} 962 963/// PairDRegs - Form a quad register from a pair of D registers. 964/// 965SDNode *ARMDAGToDAGISel::PairDRegs(EVT VT, SDValue V0, SDValue V1) { 966 DebugLoc dl = V0.getNode()->getDebugLoc(); 967 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::dsub_0, MVT::i32); 968 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::dsub_1, MVT::i32); 969 if (llvm::ModelWithRegSequence()) { 970 const SDValue Ops[] = { V0, SubReg0, V1, SubReg1 }; 971 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 4); 972 } 973 SDValue Undef = 974 SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, dl, VT), 0); 975 SDNode *Pair = CurDAG->getMachineNode(TargetOpcode::INSERT_SUBREG, dl, 976 VT, Undef, V0, SubReg0); 977 return CurDAG->getMachineNode(TargetOpcode::INSERT_SUBREG, dl, 978 VT, SDValue(Pair, 0), V1, SubReg1); 979} 980 981/// PairQRegs - Form 4 consecutive D registers from a pair of Q registers. 982/// 983SDNode *ARMDAGToDAGISel::PairQRegs(EVT VT, SDValue V0, SDValue V1) { 984 DebugLoc dl = V0.getNode()->getDebugLoc(); 985 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::qsub_0, MVT::i32); 986 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::qsub_1, MVT::i32); 987 const SDValue Ops[] = { V0, SubReg0, V1, SubReg1 }; 988 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 4); 989} 990 991/// QuadDRegs - Form 4 consecutive D registers. 992/// 993SDNode *ARMDAGToDAGISel::QuadDRegs(EVT VT, SDValue V0, SDValue V1, 994 SDValue V2, SDValue V3) { 995 DebugLoc dl = V0.getNode()->getDebugLoc(); 996 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::dsub_0, MVT::i32); 997 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::dsub_1, MVT::i32); 998 SDValue SubReg2 = CurDAG->getTargetConstant(ARM::dsub_2, MVT::i32); 999 SDValue SubReg3 = CurDAG->getTargetConstant(ARM::dsub_3, MVT::i32); 1000 const SDValue Ops[] = { V0, SubReg0, V1, SubReg1, V2, SubReg2, V3, SubReg3 }; 1001 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 8); 1002} 1003 1004/// QuadQRegs - Form 4 consecutive Q registers. 1005/// 1006SDNode *ARMDAGToDAGISel::QuadQRegs(EVT VT, SDValue V0, SDValue V1, 1007 SDValue V2, SDValue V3) { 1008 DebugLoc dl = V0.getNode()->getDebugLoc(); 1009 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::qsub_0, MVT::i32); 1010 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::qsub_1, MVT::i32); 1011 SDValue SubReg2 = CurDAG->getTargetConstant(ARM::qsub_2, MVT::i32); 1012 SDValue SubReg3 = CurDAG->getTargetConstant(ARM::qsub_3, MVT::i32); 1013 const SDValue Ops[] = { V0, SubReg0, V1, SubReg1, V2, SubReg2, V3, SubReg3 }; 1014 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 8); 1015} 1016 1017/// OctoDRegs - Form 8 consecutive D registers. 1018/// 1019SDNode *ARMDAGToDAGISel::OctoDRegs(EVT VT, SDValue V0, SDValue V1, 1020 SDValue V2, SDValue V3, 1021 SDValue V4, SDValue V5, 1022 SDValue V6, SDValue V7) { 1023 DebugLoc dl = V0.getNode()->getDebugLoc(); 1024 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::dsub_0, MVT::i32); 1025 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::dsub_1, MVT::i32); 1026 SDValue SubReg2 = CurDAG->getTargetConstant(ARM::dsub_2, MVT::i32); 1027 SDValue SubReg3 = CurDAG->getTargetConstant(ARM::dsub_3, MVT::i32); 1028 SDValue SubReg4 = CurDAG->getTargetConstant(ARM::dsub_4, MVT::i32); 1029 SDValue SubReg5 = CurDAG->getTargetConstant(ARM::dsub_5, MVT::i32); 1030 SDValue SubReg6 = CurDAG->getTargetConstant(ARM::dsub_6, MVT::i32); 1031 SDValue SubReg7 = CurDAG->getTargetConstant(ARM::dsub_7, MVT::i32); 1032 const SDValue Ops[] ={ V0, SubReg0, V1, SubReg1, V2, SubReg2, V3, SubReg3, 1033 V4, SubReg4, V5, SubReg5, V6, SubReg6, V7, SubReg7 }; 1034 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 16); 1035} 1036 1037/// GetNEONSubregVT - Given a type for a 128-bit NEON vector, return the type 1038/// for a 64-bit subregister of the vector. 1039static EVT GetNEONSubregVT(EVT VT) { 1040 switch (VT.getSimpleVT().SimpleTy) { 1041 default: llvm_unreachable("unhandled NEON type"); 1042 case MVT::v16i8: return MVT::v8i8; 1043 case MVT::v8i16: return MVT::v4i16; 1044 case MVT::v4f32: return MVT::v2f32; 1045 case MVT::v4i32: return MVT::v2i32; 1046 case MVT::v2i64: return MVT::v1i64; 1047 } 1048} 1049 1050SDNode *ARMDAGToDAGISel::SelectVLD(SDNode *N, unsigned NumVecs, 1051 unsigned *DOpcodes, unsigned *QOpcodes0, 1052 unsigned *QOpcodes1) { 1053 assert(NumVecs >= 1 && NumVecs <= 4 && "VLD NumVecs out-of-range"); 1054 DebugLoc dl = N->getDebugLoc(); 1055 1056 SDValue MemAddr, Align; 1057 if (!SelectAddrMode6(N, N->getOperand(2), MemAddr, Align)) 1058 return NULL; 1059 1060 SDValue Chain = N->getOperand(0); 1061 EVT VT = N->getValueType(0); 1062 bool is64BitVector = VT.is64BitVector(); 1063 1064 unsigned OpcodeIndex; 1065 switch (VT.getSimpleVT().SimpleTy) { 1066 default: llvm_unreachable("unhandled vld type"); 1067 // Double-register operations: 1068 case MVT::v8i8: OpcodeIndex = 0; break; 1069 case MVT::v4i16: OpcodeIndex = 1; break; 1070 case MVT::v2f32: 1071 case MVT::v2i32: OpcodeIndex = 2; break; 1072 case MVT::v1i64: OpcodeIndex = 3; break; 1073 // Quad-register operations: 1074 case MVT::v16i8: OpcodeIndex = 0; break; 1075 case MVT::v8i16: OpcodeIndex = 1; break; 1076 case MVT::v4f32: 1077 case MVT::v4i32: OpcodeIndex = 2; break; 1078 case MVT::v2i64: OpcodeIndex = 3; 1079 assert(NumVecs == 1 && "v2i64 type only supported for VLD1"); 1080 break; 1081 } 1082 1083 SDValue Pred = getAL(CurDAG); 1084 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); 1085 if (is64BitVector) { 1086 unsigned Opc = DOpcodes[OpcodeIndex]; 1087 const SDValue Ops[] = { MemAddr, Align, Pred, Reg0, Chain }; 1088 std::vector<EVT> ResTys(NumVecs, VT); 1089 ResTys.push_back(MVT::Other); 1090 SDNode *VLd = CurDAG->getMachineNode(Opc, dl, ResTys, Ops, 5); 1091 if (!llvm::ModelWithRegSequence() || NumVecs < 2) 1092 return VLd; 1093 1094 SDValue RegSeq; 1095 SDValue V0 = SDValue(VLd, 0); 1096 SDValue V1 = SDValue(VLd, 1); 1097 1098 // Form a REG_SEQUENCE to force register allocation. 1099 if (NumVecs == 2) 1100 RegSeq = SDValue(PairDRegs(MVT::v2i64, V0, V1), 0); 1101 else { 1102 SDValue V2 = SDValue(VLd, 2); 1103 // If it's a vld3, form a quad D-register but discard the last part. 1104 SDValue V3 = (NumVecs == 3) 1105 ? SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF,dl,VT), 0) 1106 : SDValue(VLd, 3); 1107 RegSeq = SDValue(QuadDRegs(MVT::v4i64, V0, V1, V2, V3), 0); 1108 } 1109 1110 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering"); 1111 for (unsigned Vec = 0; Vec < NumVecs; ++Vec) { 1112 SDValue D = CurDAG->getTargetExtractSubreg(ARM::dsub_0+Vec, 1113 dl, VT, RegSeq); 1114 ReplaceUses(SDValue(N, Vec), D); 1115 } 1116 ReplaceUses(SDValue(N, NumVecs), SDValue(VLd, NumVecs)); 1117 return NULL; 1118 } 1119 1120 EVT RegVT = GetNEONSubregVT(VT); 1121 if (NumVecs <= 2) { 1122 // Quad registers are directly supported for VLD1 and VLD2, 1123 // loading pairs of D regs. 1124 unsigned Opc = QOpcodes0[OpcodeIndex]; 1125 const SDValue Ops[] = { MemAddr, Align, Pred, Reg0, Chain }; 1126 std::vector<EVT> ResTys(2 * NumVecs, RegVT); 1127 ResTys.push_back(MVT::Other); 1128 SDNode *VLd = CurDAG->getMachineNode(Opc, dl, ResTys, Ops, 5); 1129 Chain = SDValue(VLd, 2 * NumVecs); 1130 1131 // Combine the even and odd subregs to produce the result. 1132 if (llvm::ModelWithRegSequence()) { 1133 if (NumVecs == 1) { 1134 SDNode *Q = PairDRegs(VT, SDValue(VLd, 0), SDValue(VLd, 1)); 1135 ReplaceUses(SDValue(N, 0), SDValue(Q, 0)); 1136 } else { 1137 SDValue QQ = SDValue(QuadDRegs(MVT::v4i64, 1138 SDValue(VLd, 0), SDValue(VLd, 1), 1139 SDValue(VLd, 2), SDValue(VLd, 3)), 0); 1140 SDValue Q0 = CurDAG->getTargetExtractSubreg(ARM::qsub_0, dl, VT, QQ); 1141 SDValue Q1 = CurDAG->getTargetExtractSubreg(ARM::qsub_1, dl, VT, QQ); 1142 ReplaceUses(SDValue(N, 0), Q0); 1143 ReplaceUses(SDValue(N, 1), Q1); 1144 } 1145 } else { 1146 for (unsigned Vec = 0; Vec < NumVecs; ++Vec) { 1147 SDNode *Q = PairDRegs(VT, SDValue(VLd, 2*Vec), SDValue(VLd, 2*Vec+1)); 1148 ReplaceUses(SDValue(N, Vec), SDValue(Q, 0)); 1149 } 1150 } 1151 } else { 1152 // Otherwise, quad registers are loaded with two separate instructions, 1153 // where one loads the even registers and the other loads the odd registers. 1154 1155 std::vector<EVT> ResTys(NumVecs, RegVT); 1156 ResTys.push_back(MemAddr.getValueType()); 1157 ResTys.push_back(MVT::Other); 1158 1159 // Load the even subregs. 1160 unsigned Opc = QOpcodes0[OpcodeIndex]; 1161 const SDValue OpsA[] = { MemAddr, Align, Reg0, Pred, Reg0, Chain }; 1162 SDNode *VLdA = CurDAG->getMachineNode(Opc, dl, ResTys, OpsA, 6); 1163 Chain = SDValue(VLdA, NumVecs+1); 1164 1165 // Load the odd subregs. 1166 Opc = QOpcodes1[OpcodeIndex]; 1167 const SDValue OpsB[] = { SDValue(VLdA, NumVecs), 1168 Align, Reg0, Pred, Reg0, Chain }; 1169 SDNode *VLdB = CurDAG->getMachineNode(Opc, dl, ResTys, OpsB, 6); 1170 Chain = SDValue(VLdB, NumVecs+1); 1171 1172 if (llvm::ModelWithRegSequence()) { 1173 SDValue V0 = SDValue(VLdA, 0); 1174 SDValue V1 = SDValue(VLdB, 0); 1175 SDValue V2 = SDValue(VLdA, 1); 1176 SDValue V3 = SDValue(VLdB, 1); 1177 SDValue V4 = SDValue(VLdA, 2); 1178 SDValue V5 = SDValue(VLdB, 2); 1179 SDValue V6 = (NumVecs == 3) 1180 ? SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF,dl,RegVT), 1181 0) 1182 : SDValue(VLdA, 3); 1183 SDValue V7 = (NumVecs == 3) 1184 ? SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF,dl,RegVT), 1185 0) 1186 : SDValue(VLdB, 3); 1187 SDValue RegSeq = SDValue(OctoDRegs(MVT::v8i64, V0, V1, V2, V3, 1188 V4, V5, V6, V7), 0); 1189 1190 // Extract out the 3 / 4 Q registers. 1191 assert(ARM::qsub_3 == ARM::qsub_0+3 && "Unexpected subreg numbering"); 1192 for (unsigned Vec = 0; Vec < NumVecs; ++Vec) { 1193 SDValue Q = CurDAG->getTargetExtractSubreg(ARM::qsub_0+Vec, 1194 dl, VT, RegSeq); 1195 ReplaceUses(SDValue(N, Vec), Q); 1196 } 1197 } else { 1198 // Combine the even and odd subregs to produce the result. 1199 for (unsigned Vec = 0; Vec < NumVecs; ++Vec) { 1200 SDNode *Q = PairDRegs(VT, SDValue(VLdA, Vec), SDValue(VLdB, Vec)); 1201 ReplaceUses(SDValue(N, Vec), SDValue(Q, 0)); 1202 } 1203 } 1204 } 1205 ReplaceUses(SDValue(N, NumVecs), Chain); 1206 return NULL; 1207} 1208 1209SDNode *ARMDAGToDAGISel::SelectVST(SDNode *N, unsigned NumVecs, 1210 unsigned *DOpcodes, unsigned *QOpcodes0, 1211 unsigned *QOpcodes1) { 1212 assert(NumVecs >=1 && NumVecs <= 4 && "VST NumVecs out-of-range"); 1213 DebugLoc dl = N->getDebugLoc(); 1214 1215 SDValue MemAddr, Align; 1216 if (!SelectAddrMode6(N, N->getOperand(2), MemAddr, Align)) 1217 return NULL; 1218 1219 SDValue Chain = N->getOperand(0); 1220 EVT VT = N->getOperand(3).getValueType(); 1221 bool is64BitVector = VT.is64BitVector(); 1222 1223 unsigned OpcodeIndex; 1224 switch (VT.getSimpleVT().SimpleTy) { 1225 default: llvm_unreachable("unhandled vst type"); 1226 // Double-register operations: 1227 case MVT::v8i8: OpcodeIndex = 0; break; 1228 case MVT::v4i16: OpcodeIndex = 1; break; 1229 case MVT::v2f32: 1230 case MVT::v2i32: OpcodeIndex = 2; break; 1231 case MVT::v1i64: OpcodeIndex = 3; break; 1232 // Quad-register operations: 1233 case MVT::v16i8: OpcodeIndex = 0; break; 1234 case MVT::v8i16: OpcodeIndex = 1; break; 1235 case MVT::v4f32: 1236 case MVT::v4i32: OpcodeIndex = 2; break; 1237 case MVT::v2i64: OpcodeIndex = 3; 1238 assert(NumVecs == 1 && "v2i64 type only supported for VST1"); 1239 break; 1240 } 1241 1242 SDValue Pred = getAL(CurDAG); 1243 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); 1244 1245 SmallVector<SDValue, 10> Ops; 1246 Ops.push_back(MemAddr); 1247 Ops.push_back(Align); 1248 1249 if (is64BitVector) { 1250 if (llvm::ModelWithRegSequence() && NumVecs >= 2) { 1251 SDValue RegSeq; 1252 SDValue V0 = N->getOperand(0+3); 1253 SDValue V1 = N->getOperand(1+3); 1254 1255 // Form a REG_SEQUENCE to force register allocation. 1256 if (NumVecs == 2) 1257 RegSeq = SDValue(PairDRegs(MVT::v2i64, V0, V1), 0); 1258 else { 1259 SDValue V2 = N->getOperand(2+3); 1260 // If it's a vld3, form a quad D-register and leave the last part as 1261 // an undef. 1262 SDValue V3 = (NumVecs == 3) 1263 ? SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF,dl,VT), 0) 1264 : N->getOperand(3+3); 1265 RegSeq = SDValue(QuadDRegs(MVT::v4i64, V0, V1, V2, V3), 0); 1266 } 1267 1268 // Now extract the D registers back out. 1269 Ops.push_back(CurDAG->getTargetExtractSubreg(ARM::dsub_0, dl, VT, 1270 RegSeq)); 1271 Ops.push_back(CurDAG->getTargetExtractSubreg(ARM::dsub_1, dl, VT, 1272 RegSeq)); 1273 if (NumVecs > 2) 1274 Ops.push_back(CurDAG->getTargetExtractSubreg(ARM::dsub_2, dl, VT, 1275 RegSeq)); 1276 if (NumVecs > 3) 1277 Ops.push_back(CurDAG->getTargetExtractSubreg(ARM::dsub_3, dl, VT, 1278 RegSeq)); 1279 } else { 1280 for (unsigned Vec = 0; Vec < NumVecs; ++Vec) 1281 Ops.push_back(N->getOperand(Vec+3)); 1282 } 1283 Ops.push_back(Pred); 1284 Ops.push_back(Reg0); // predicate register 1285 Ops.push_back(Chain); 1286 unsigned Opc = DOpcodes[OpcodeIndex]; 1287 return CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops.data(), NumVecs+5); 1288 } 1289 1290 EVT RegVT = GetNEONSubregVT(VT); 1291 if (NumVecs <= 2) { 1292 // Quad registers are directly supported for VST1 and VST2, 1293 // storing pairs of D regs. 1294 unsigned Opc = QOpcodes0[OpcodeIndex]; 1295 if (llvm::ModelWithRegSequence() && NumVecs == 2) { 1296 // First extract the pair of Q registers. 1297 SDValue Q0 = N->getOperand(3); 1298 SDValue Q1 = N->getOperand(4); 1299 1300 // Form a QQ register. 1301 SDValue QQ = SDValue(PairQRegs(MVT::v4i64, Q0, Q1), 0); 1302 1303 // Now extract the D registers back out. 1304 Ops.push_back(CurDAG->getTargetExtractSubreg(ARM::dsub_0, dl, RegVT, 1305 QQ)); 1306 Ops.push_back(CurDAG->getTargetExtractSubreg(ARM::dsub_1, dl, RegVT, 1307 QQ)); 1308 Ops.push_back(CurDAG->getTargetExtractSubreg(ARM::dsub_2, dl, RegVT, 1309 QQ)); 1310 Ops.push_back(CurDAG->getTargetExtractSubreg(ARM::dsub_3, dl, RegVT, 1311 QQ)); 1312 Ops.push_back(Pred); 1313 Ops.push_back(Reg0); // predicate register 1314 Ops.push_back(Chain); 1315 return CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops.data(), 5 + 4); 1316 } else { 1317 for (unsigned Vec = 0; Vec < NumVecs; ++Vec) { 1318 Ops.push_back(CurDAG->getTargetExtractSubreg(ARM::dsub_0, dl, RegVT, 1319 N->getOperand(Vec+3))); 1320 Ops.push_back(CurDAG->getTargetExtractSubreg(ARM::dsub_1, dl, RegVT, 1321 N->getOperand(Vec+3))); 1322 } 1323 Ops.push_back(Pred); 1324 Ops.push_back(Reg0); // predicate register 1325 Ops.push_back(Chain); 1326 return CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops.data(), 1327 5 + 2 * NumVecs); 1328 } 1329 } 1330 1331 // Otherwise, quad registers are stored with two separate instructions, 1332 // where one stores the even registers and the other stores the odd registers. 1333 if (llvm::ModelWithRegSequence()) { 1334 // Form the QQQQ REG_SEQUENCE. 1335 SDValue V[8]; 1336 for (unsigned Vec = 0, i = 0; Vec < NumVecs; ++Vec, i+=2) { 1337 V[i] = CurDAG->getTargetExtractSubreg(ARM::dsub_0, dl, RegVT, 1338 N->getOperand(Vec+3)); 1339 V[i+1] = CurDAG->getTargetExtractSubreg(ARM::dsub_1, dl, RegVT, 1340 N->getOperand(Vec+3)); 1341 } 1342 if (NumVecs == 3) 1343 V[6] = V[7] = SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, 1344 dl, RegVT), 0); 1345 1346 SDValue RegSeq = SDValue(OctoDRegs(MVT::v8i64, V[0], V[1], V[2], V[3], 1347 V[4], V[5], V[6], V[7]), 0); 1348 1349 // Store the even D registers. 1350 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering"); 1351 Ops.push_back(Reg0); // post-access address offset 1352 for (unsigned Vec = 0; Vec < NumVecs; ++Vec) 1353 Ops.push_back(CurDAG->getTargetExtractSubreg(ARM::dsub_0+Vec*2, dl, 1354 RegVT, RegSeq)); 1355 Ops.push_back(Pred); 1356 Ops.push_back(Reg0); // predicate register 1357 Ops.push_back(Chain); 1358 unsigned Opc = QOpcodes0[OpcodeIndex]; 1359 SDNode *VStA = CurDAG->getMachineNode(Opc, dl, MemAddr.getValueType(), 1360 MVT::Other, Ops.data(), NumVecs+6); 1361 Chain = SDValue(VStA, 1); 1362 1363 // Store the odd D registers. 1364 Ops[0] = SDValue(VStA, 0); // MemAddr 1365 for (unsigned Vec = 0; Vec < NumVecs; ++Vec) 1366 Ops[Vec+3] = CurDAG->getTargetExtractSubreg(ARM::dsub_1+Vec*2, dl, 1367 RegVT, RegSeq); 1368 Ops[NumVecs+5] = Chain; 1369 Opc = QOpcodes1[OpcodeIndex]; 1370 SDNode *VStB = CurDAG->getMachineNode(Opc, dl, MemAddr.getValueType(), 1371 MVT::Other, Ops.data(), NumVecs+6); 1372 Chain = SDValue(VStB, 1); 1373 ReplaceUses(SDValue(N, 0), Chain); 1374 return NULL; 1375 } else { 1376 Ops.push_back(Reg0); // post-access address offset 1377 1378 // Store the even subregs. 1379 for (unsigned Vec = 0; Vec < NumVecs; ++Vec) 1380 Ops.push_back(CurDAG->getTargetExtractSubreg(ARM::dsub_0, dl, RegVT, 1381 N->getOperand(Vec+3))); 1382 Ops.push_back(Pred); 1383 Ops.push_back(Reg0); // predicate register 1384 Ops.push_back(Chain); 1385 unsigned Opc = QOpcodes0[OpcodeIndex]; 1386 SDNode *VStA = CurDAG->getMachineNode(Opc, dl, MemAddr.getValueType(), 1387 MVT::Other, Ops.data(), NumVecs+6); 1388 Chain = SDValue(VStA, 1); 1389 1390 // Store the odd subregs. 1391 Ops[0] = SDValue(VStA, 0); // MemAddr 1392 for (unsigned Vec = 0; Vec < NumVecs; ++Vec) 1393 Ops[Vec+3] = CurDAG->getTargetExtractSubreg(ARM::dsub_1, dl, RegVT, 1394 N->getOperand(Vec+3)); 1395 Ops[NumVecs+5] = Chain; 1396 Opc = QOpcodes1[OpcodeIndex]; 1397 SDNode *VStB = CurDAG->getMachineNode(Opc, dl, MemAddr.getValueType(), 1398 MVT::Other, Ops.data(), NumVecs+6); 1399 Chain = SDValue(VStB, 1); 1400 ReplaceUses(SDValue(N, 0), Chain); 1401 return NULL; 1402 } 1403} 1404 1405SDNode *ARMDAGToDAGISel::SelectVLDSTLane(SDNode *N, bool IsLoad, 1406 unsigned NumVecs, unsigned *DOpcodes, 1407 unsigned *QOpcodes0, 1408 unsigned *QOpcodes1) { 1409 assert(NumVecs >=2 && NumVecs <= 4 && "VLDSTLane NumVecs out-of-range"); 1410 DebugLoc dl = N->getDebugLoc(); 1411 1412 SDValue MemAddr, Align; 1413 if (!SelectAddrMode6(N, N->getOperand(2), MemAddr, Align)) 1414 return NULL; 1415 1416 SDValue Chain = N->getOperand(0); 1417 unsigned Lane = 1418 cast<ConstantSDNode>(N->getOperand(NumVecs+3))->getZExtValue(); 1419 EVT VT = IsLoad ? N->getValueType(0) : N->getOperand(3).getValueType(); 1420 bool is64BitVector = VT.is64BitVector(); 1421 1422 // Quad registers are handled by load/store of subregs. Find the subreg info. 1423 unsigned NumElts = 0; 1424 int SubregIdx = 0; 1425 bool Even = false; 1426 EVT RegVT = VT; 1427 if (!is64BitVector) { 1428 RegVT = GetNEONSubregVT(VT); 1429 NumElts = RegVT.getVectorNumElements(); 1430 SubregIdx = (Lane < NumElts) ? ARM::dsub_0 : ARM::dsub_1; 1431 Even = Lane < NumElts; 1432 } 1433 1434 unsigned OpcodeIndex; 1435 switch (VT.getSimpleVT().SimpleTy) { 1436 default: llvm_unreachable("unhandled vld/vst lane type"); 1437 // Double-register operations: 1438 case MVT::v8i8: OpcodeIndex = 0; break; 1439 case MVT::v4i16: OpcodeIndex = 1; break; 1440 case MVT::v2f32: 1441 case MVT::v2i32: OpcodeIndex = 2; break; 1442 // Quad-register operations: 1443 case MVT::v8i16: OpcodeIndex = 0; break; 1444 case MVT::v4f32: 1445 case MVT::v4i32: OpcodeIndex = 1; break; 1446 } 1447 1448 SDValue Pred = getAL(CurDAG); 1449 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); 1450 1451 SmallVector<SDValue, 10> Ops; 1452 Ops.push_back(MemAddr); 1453 Ops.push_back(Align); 1454 1455 unsigned Opc = 0; 1456 if (is64BitVector) { 1457 Opc = DOpcodes[OpcodeIndex]; 1458 if (llvm::ModelWithRegSequence()) { 1459 SDValue RegSeq; 1460 SDValue V0 = N->getOperand(0+3); 1461 SDValue V1 = N->getOperand(1+3); 1462 if (NumVecs == 2) { 1463 RegSeq = SDValue(PairDRegs(MVT::v2i64, V0, V1), 0); 1464 } else { 1465 SDValue V2 = N->getOperand(2+3); 1466 SDValue V3 = (NumVecs == 3) 1467 ? SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF,dl,VT), 0) 1468 : N->getOperand(3+3); 1469 RegSeq = SDValue(QuadDRegs(MVT::v4i64, V0, V1, V2, V3), 0); 1470 } 1471 1472 // Now extract the D registers back out. 1473 Ops.push_back(CurDAG->getTargetExtractSubreg(ARM::dsub_0, dl, VT, 1474 RegSeq)); 1475 Ops.push_back(CurDAG->getTargetExtractSubreg(ARM::dsub_1, dl, VT, 1476 RegSeq)); 1477 if (NumVecs > 2) 1478 Ops.push_back(CurDAG->getTargetExtractSubreg(ARM::dsub_2, dl, VT, 1479 RegSeq)); 1480 if (NumVecs > 3) 1481 Ops.push_back(CurDAG->getTargetExtractSubreg(ARM::dsub_3, dl, VT, 1482 RegSeq)); 1483 } else { 1484 for (unsigned Vec = 0; Vec < NumVecs; ++Vec) 1485 Ops.push_back(N->getOperand(Vec+3)); 1486 } 1487 } else { 1488 // Check if this is loading the even or odd subreg of a Q register. 1489 if (Lane < NumElts) { 1490 Opc = QOpcodes0[OpcodeIndex]; 1491 } else { 1492 Lane -= NumElts; 1493 Opc = QOpcodes1[OpcodeIndex]; 1494 } 1495 1496 if (llvm::ModelWithRegSequence()) { 1497 SDValue RegSeq; 1498 SDValue V0 = N->getOperand(0+3); 1499 SDValue V1 = N->getOperand(1+3); 1500 if (NumVecs == 2) { 1501 RegSeq = SDValue(PairQRegs(MVT::v4i64, V0, V1), 0); 1502 } else { 1503 SDValue V2 = N->getOperand(2+3); 1504 SDValue V3 = (NumVecs == 3) 1505 ? SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF,dl,VT), 0) 1506 : N->getOperand(3+3); 1507 RegSeq = SDValue(QuadQRegs(MVT::v8i64, V0, V1, V2, V3), 0); 1508 } 1509 1510 // Extract the subregs of the input vector. 1511 unsigned SubIdx = Even ? ARM::dsub_0 : ARM::dsub_1; 1512 for (unsigned Vec = 0; Vec < NumVecs; ++Vec) 1513 Ops.push_back(CurDAG->getTargetExtractSubreg(SubIdx+Vec*2, dl, RegVT, 1514 RegSeq)); 1515 } else { 1516 // Extract the subregs of the input vector. 1517 for (unsigned Vec = 0; Vec < NumVecs; ++Vec) 1518 Ops.push_back(CurDAG->getTargetExtractSubreg(SubregIdx, dl, RegVT, 1519 N->getOperand(Vec+3))); 1520 } 1521 } 1522 Ops.push_back(getI32Imm(Lane)); 1523 Ops.push_back(Pred); 1524 Ops.push_back(Reg0); 1525 Ops.push_back(Chain); 1526 1527 if (!IsLoad) 1528 return CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops.data(), NumVecs+6); 1529 1530 std::vector<EVT> ResTys(NumVecs, RegVT); 1531 ResTys.push_back(MVT::Other); 1532 SDNode *VLdLn = CurDAG->getMachineNode(Opc, dl, ResTys, Ops.data(),NumVecs+6); 1533 1534 if (llvm::ModelWithRegSequence()) { 1535 // Form a REG_SEQUENCE to force register allocation. 1536 SDValue RegSeq; 1537 if (is64BitVector) { 1538 SDValue V0 = SDValue(VLdLn, 0); 1539 SDValue V1 = SDValue(VLdLn, 1); 1540 if (NumVecs == 2) { 1541 RegSeq = SDValue(PairDRegs(MVT::v2i64, V0, V1), 0); 1542 } else { 1543 SDValue V2 = SDValue(VLdLn, 2); 1544 // If it's a vld3, form a quad D-register but discard the last part. 1545 SDValue V3 = (NumVecs == 3) 1546 ? SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF,dl,VT), 0) 1547 : SDValue(VLdLn, 3); 1548 RegSeq = SDValue(QuadDRegs(MVT::v4i64, V0, V1, V2, V3), 0); 1549 } 1550 } else { 1551 // For 128-bit vectors, take the 64-bit results of the load and insert them 1552 // as subregs into the result. 1553 SDValue V[8]; 1554 for (unsigned Vec = 0, i = 0; Vec < NumVecs; ++Vec, i+=2) { 1555 if (Even) { 1556 V[i] = SDValue(VLdLn, Vec); 1557 V[i+1] = SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, 1558 dl, RegVT), 0); 1559 } else { 1560 V[i] = SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, 1561 dl, RegVT), 0); 1562 V[i+1] = SDValue(VLdLn, Vec); 1563 } 1564 } 1565 if (NumVecs == 3) 1566 V[6] = V[7] = SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, 1567 dl, RegVT), 0); 1568 1569 if (NumVecs == 2) 1570 RegSeq = SDValue(QuadDRegs(MVT::v4i64, V[0], V[1], V[2], V[3]), 0); 1571 else 1572 RegSeq = SDValue(OctoDRegs(MVT::v8i64, V[0], V[1], V[2], V[3], 1573 V[4], V[5], V[6], V[7]), 0); 1574 } 1575 1576 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering"); 1577 assert(ARM::qsub_3 == ARM::qsub_0+3 && "Unexpected subreg numbering"); 1578 unsigned SubIdx = is64BitVector ? ARM::dsub_0 : ARM::qsub_0; 1579 for (unsigned Vec = 0; Vec < NumVecs; ++Vec) 1580 ReplaceUses(SDValue(N, Vec), 1581 CurDAG->getTargetExtractSubreg(SubIdx+Vec, dl, VT, RegSeq)); 1582 ReplaceUses(SDValue(N, NumVecs), SDValue(VLdLn, NumVecs)); 1583 return NULL; 1584 } 1585 1586 // For a 64-bit vector load to D registers, nothing more needs to be done. 1587 if (is64BitVector) 1588 return VLdLn; 1589 1590 // For 128-bit vectors, take the 64-bit results of the load and insert them 1591 // as subregs into the result. 1592 for (unsigned Vec = 0; Vec < NumVecs; ++Vec) { 1593 SDValue QuadVec = CurDAG->getTargetInsertSubreg(SubregIdx, dl, VT, 1594 N->getOperand(Vec+3), 1595 SDValue(VLdLn, Vec)); 1596 ReplaceUses(SDValue(N, Vec), QuadVec); 1597 } 1598 1599 Chain = SDValue(VLdLn, NumVecs); 1600 ReplaceUses(SDValue(N, NumVecs), Chain); 1601 return NULL; 1602} 1603 1604SDNode *ARMDAGToDAGISel::SelectV6T2BitfieldExtractOp(SDNode *N, 1605 bool isSigned) { 1606 if (!Subtarget->hasV6T2Ops()) 1607 return NULL; 1608 1609 unsigned Opc = isSigned ? (Subtarget->isThumb() ? ARM::t2SBFX : ARM::SBFX) 1610 : (Subtarget->isThumb() ? ARM::t2UBFX : ARM::UBFX); 1611 1612 1613 // For unsigned extracts, check for a shift right and mask 1614 unsigned And_imm = 0; 1615 if (N->getOpcode() == ISD::AND) { 1616 if (isOpcWithIntImmediate(N, ISD::AND, And_imm)) { 1617 1618 // The immediate is a mask of the low bits iff imm & (imm+1) == 0 1619 if (And_imm & (And_imm + 1)) 1620 return NULL; 1621 1622 unsigned Srl_imm = 0; 1623 if (isOpcWithIntImmediate(N->getOperand(0).getNode(), ISD::SRL, 1624 Srl_imm)) { 1625 assert(Srl_imm > 0 && Srl_imm < 32 && "bad amount in shift node!"); 1626 1627 unsigned Width = CountTrailingOnes_32(And_imm); 1628 unsigned LSB = Srl_imm; 1629 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); 1630 SDValue Ops[] = { N->getOperand(0).getOperand(0), 1631 CurDAG->getTargetConstant(LSB, MVT::i32), 1632 CurDAG->getTargetConstant(Width, MVT::i32), 1633 getAL(CurDAG), Reg0 }; 1634 return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops, 5); 1635 } 1636 } 1637 return NULL; 1638 } 1639 1640 // Otherwise, we're looking for a shift of a shift 1641 unsigned Shl_imm = 0; 1642 if (isOpcWithIntImmediate(N->getOperand(0).getNode(), ISD::SHL, Shl_imm)) { 1643 assert(Shl_imm > 0 && Shl_imm < 32 && "bad amount in shift node!"); 1644 unsigned Srl_imm = 0; 1645 if (isInt32Immediate(N->getOperand(1), Srl_imm)) { 1646 assert(Srl_imm > 0 && Srl_imm < 32 && "bad amount in shift node!"); 1647 unsigned Width = 32 - Srl_imm; 1648 int LSB = Srl_imm - Shl_imm; 1649 if (LSB < 0) 1650 return NULL; 1651 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); 1652 SDValue Ops[] = { N->getOperand(0).getOperand(0), 1653 CurDAG->getTargetConstant(LSB, MVT::i32), 1654 CurDAG->getTargetConstant(Width, MVT::i32), 1655 getAL(CurDAG), Reg0 }; 1656 return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops, 5); 1657 } 1658 } 1659 return NULL; 1660} 1661 1662SDNode *ARMDAGToDAGISel:: 1663SelectT2CMOVShiftOp(SDNode *N, SDValue FalseVal, SDValue TrueVal, 1664 ARMCC::CondCodes CCVal, SDValue CCR, SDValue InFlag) { 1665 SDValue CPTmp0; 1666 SDValue CPTmp1; 1667 if (SelectT2ShifterOperandReg(N, TrueVal, CPTmp0, CPTmp1)) { 1668 unsigned SOVal = cast<ConstantSDNode>(CPTmp1)->getZExtValue(); 1669 unsigned SOShOp = ARM_AM::getSORegShOp(SOVal); 1670 unsigned Opc = 0; 1671 switch (SOShOp) { 1672 case ARM_AM::lsl: Opc = ARM::t2MOVCClsl; break; 1673 case ARM_AM::lsr: Opc = ARM::t2MOVCClsr; break; 1674 case ARM_AM::asr: Opc = ARM::t2MOVCCasr; break; 1675 case ARM_AM::ror: Opc = ARM::t2MOVCCror; break; 1676 default: 1677 llvm_unreachable("Unknown so_reg opcode!"); 1678 break; 1679 } 1680 SDValue SOShImm = 1681 CurDAG->getTargetConstant(ARM_AM::getSORegOffset(SOVal), MVT::i32); 1682 SDValue CC = CurDAG->getTargetConstant(CCVal, MVT::i32); 1683 SDValue Ops[] = { FalseVal, CPTmp0, SOShImm, CC, CCR, InFlag }; 1684 return CurDAG->SelectNodeTo(N, Opc, MVT::i32,Ops, 6); 1685 } 1686 return 0; 1687} 1688 1689SDNode *ARMDAGToDAGISel:: 1690SelectARMCMOVShiftOp(SDNode *N, SDValue FalseVal, SDValue TrueVal, 1691 ARMCC::CondCodes CCVal, SDValue CCR, SDValue InFlag) { 1692 SDValue CPTmp0; 1693 SDValue CPTmp1; 1694 SDValue CPTmp2; 1695 if (SelectShifterOperandReg(N, TrueVal, CPTmp0, CPTmp1, CPTmp2)) { 1696 SDValue CC = CurDAG->getTargetConstant(CCVal, MVT::i32); 1697 SDValue Ops[] = { FalseVal, CPTmp0, CPTmp1, CPTmp2, CC, CCR, InFlag }; 1698 return CurDAG->SelectNodeTo(N, ARM::MOVCCs, MVT::i32, Ops, 7); 1699 } 1700 return 0; 1701} 1702 1703SDNode *ARMDAGToDAGISel:: 1704SelectT2CMOVSoImmOp(SDNode *N, SDValue FalseVal, SDValue TrueVal, 1705 ARMCC::CondCodes CCVal, SDValue CCR, SDValue InFlag) { 1706 ConstantSDNode *T = dyn_cast<ConstantSDNode>(TrueVal); 1707 if (!T) 1708 return 0; 1709 1710 if (Predicate_t2_so_imm(TrueVal.getNode())) { 1711 SDValue True = CurDAG->getTargetConstant(T->getZExtValue(), MVT::i32); 1712 SDValue CC = CurDAG->getTargetConstant(CCVal, MVT::i32); 1713 SDValue Ops[] = { FalseVal, True, CC, CCR, InFlag }; 1714 return CurDAG->SelectNodeTo(N, 1715 ARM::t2MOVCCi, MVT::i32, Ops, 5); 1716 } 1717 return 0; 1718} 1719 1720SDNode *ARMDAGToDAGISel:: 1721SelectARMCMOVSoImmOp(SDNode *N, SDValue FalseVal, SDValue TrueVal, 1722 ARMCC::CondCodes CCVal, SDValue CCR, SDValue InFlag) { 1723 ConstantSDNode *T = dyn_cast<ConstantSDNode>(TrueVal); 1724 if (!T) 1725 return 0; 1726 1727 if (Predicate_so_imm(TrueVal.getNode())) { 1728 SDValue True = CurDAG->getTargetConstant(T->getZExtValue(), MVT::i32); 1729 SDValue CC = CurDAG->getTargetConstant(CCVal, MVT::i32); 1730 SDValue Ops[] = { FalseVal, True, CC, CCR, InFlag }; 1731 return CurDAG->SelectNodeTo(N, 1732 ARM::MOVCCi, MVT::i32, Ops, 5); 1733 } 1734 return 0; 1735} 1736 1737SDNode *ARMDAGToDAGISel::SelectCMOVOp(SDNode *N) { 1738 EVT VT = N->getValueType(0); 1739 SDValue FalseVal = N->getOperand(0); 1740 SDValue TrueVal = N->getOperand(1); 1741 SDValue CC = N->getOperand(2); 1742 SDValue CCR = N->getOperand(3); 1743 SDValue InFlag = N->getOperand(4); 1744 assert(CC.getOpcode() == ISD::Constant); 1745 assert(CCR.getOpcode() == ISD::Register); 1746 ARMCC::CondCodes CCVal = 1747 (ARMCC::CondCodes)cast<ConstantSDNode>(CC)->getZExtValue(); 1748 1749 if (!Subtarget->isThumb1Only() && VT == MVT::i32) { 1750 // Pattern: (ARMcmov:i32 GPR:i32:$false, so_reg:i32:$true, (imm:i32):$cc) 1751 // Emits: (MOVCCs:i32 GPR:i32:$false, so_reg:i32:$true, (imm:i32):$cc) 1752 // Pattern complexity = 18 cost = 1 size = 0 1753 SDValue CPTmp0; 1754 SDValue CPTmp1; 1755 SDValue CPTmp2; 1756 if (Subtarget->isThumb()) { 1757 SDNode *Res = SelectT2CMOVShiftOp(N, FalseVal, TrueVal, 1758 CCVal, CCR, InFlag); 1759 if (!Res) 1760 Res = SelectT2CMOVShiftOp(N, TrueVal, FalseVal, 1761 ARMCC::getOppositeCondition(CCVal), CCR, InFlag); 1762 if (Res) 1763 return Res; 1764 } else { 1765 SDNode *Res = SelectARMCMOVShiftOp(N, FalseVal, TrueVal, 1766 CCVal, CCR, InFlag); 1767 if (!Res) 1768 Res = SelectARMCMOVShiftOp(N, TrueVal, FalseVal, 1769 ARMCC::getOppositeCondition(CCVal), CCR, InFlag); 1770 if (Res) 1771 return Res; 1772 } 1773 1774 // Pattern: (ARMcmov:i32 GPR:i32:$false, 1775 // (imm:i32)<<P:Predicate_so_imm>>:$true, 1776 // (imm:i32):$cc) 1777 // Emits: (MOVCCi:i32 GPR:i32:$false, 1778 // (so_imm:i32 (imm:i32):$true), (imm:i32):$cc) 1779 // Pattern complexity = 10 cost = 1 size = 0 1780 if (Subtarget->isThumb()) { 1781 SDNode *Res = SelectT2CMOVSoImmOp(N, FalseVal, TrueVal, 1782 CCVal, CCR, InFlag); 1783 if (!Res) 1784 Res = SelectT2CMOVSoImmOp(N, TrueVal, FalseVal, 1785 ARMCC::getOppositeCondition(CCVal), CCR, InFlag); 1786 if (Res) 1787 return Res; 1788 } else { 1789 SDNode *Res = SelectARMCMOVSoImmOp(N, FalseVal, TrueVal, 1790 CCVal, CCR, InFlag); 1791 if (!Res) 1792 Res = SelectARMCMOVSoImmOp(N, TrueVal, FalseVal, 1793 ARMCC::getOppositeCondition(CCVal), CCR, InFlag); 1794 if (Res) 1795 return Res; 1796 } 1797 } 1798 1799 // Pattern: (ARMcmov:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc) 1800 // Emits: (MOVCCr:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc) 1801 // Pattern complexity = 6 cost = 1 size = 0 1802 // 1803 // Pattern: (ARMcmov:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc) 1804 // Emits: (tMOVCCr:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc) 1805 // Pattern complexity = 6 cost = 11 size = 0 1806 // 1807 // Also FCPYScc and FCPYDcc. 1808 SDValue Tmp2 = CurDAG->getTargetConstant(CCVal, MVT::i32); 1809 SDValue Ops[] = { FalseVal, TrueVal, Tmp2, CCR, InFlag }; 1810 unsigned Opc = 0; 1811 switch (VT.getSimpleVT().SimpleTy) { 1812 default: assert(false && "Illegal conditional move type!"); 1813 break; 1814 case MVT::i32: 1815 Opc = Subtarget->isThumb() 1816 ? (Subtarget->hasThumb2() ? ARM::t2MOVCCr : ARM::tMOVCCr_pseudo) 1817 : ARM::MOVCCr; 1818 break; 1819 case MVT::f32: 1820 Opc = ARM::VMOVScc; 1821 break; 1822 case MVT::f64: 1823 Opc = ARM::VMOVDcc; 1824 break; 1825 } 1826 return CurDAG->SelectNodeTo(N, Opc, VT, Ops, 5); 1827} 1828 1829SDNode *ARMDAGToDAGISel::SelectConcatVector(SDNode *N) { 1830 // The only time a CONCAT_VECTORS operation can have legal types is when 1831 // two 64-bit vectors are concatenated to a 128-bit vector. 1832 EVT VT = N->getValueType(0); 1833 if (!VT.is128BitVector() || N->getNumOperands() != 2) 1834 llvm_unreachable("unexpected CONCAT_VECTORS"); 1835 DebugLoc dl = N->getDebugLoc(); 1836 SDValue V0 = N->getOperand(0); 1837 SDValue V1 = N->getOperand(1); 1838 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::dsub_0, MVT::i32); 1839 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::dsub_1, MVT::i32); 1840 const SDValue Ops[] = { V0, SubReg0, V1, SubReg1 }; 1841 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 4); 1842} 1843 1844SDNode *ARMDAGToDAGISel::Select(SDNode *N) { 1845 DebugLoc dl = N->getDebugLoc(); 1846 1847 if (N->isMachineOpcode()) 1848 return NULL; // Already selected. 1849 1850 switch (N->getOpcode()) { 1851 default: break; 1852 case ISD::Constant: { 1853 unsigned Val = cast<ConstantSDNode>(N)->getZExtValue(); 1854 bool UseCP = true; 1855 if (Subtarget->hasThumb2()) 1856 // Thumb2-aware targets have the MOVT instruction, so all immediates can 1857 // be done with MOV + MOVT, at worst. 1858 UseCP = 0; 1859 else { 1860 if (Subtarget->isThumb()) { 1861 UseCP = (Val > 255 && // MOV 1862 ~Val > 255 && // MOV + MVN 1863 !ARM_AM::isThumbImmShiftedVal(Val)); // MOV + LSL 1864 } else 1865 UseCP = (ARM_AM::getSOImmVal(Val) == -1 && // MOV 1866 ARM_AM::getSOImmVal(~Val) == -1 && // MVN 1867 !ARM_AM::isSOImmTwoPartVal(Val)); // two instrs. 1868 } 1869 1870 if (UseCP) { 1871 SDValue CPIdx = 1872 CurDAG->getTargetConstantPool(ConstantInt::get( 1873 Type::getInt32Ty(*CurDAG->getContext()), Val), 1874 TLI.getPointerTy()); 1875 1876 SDNode *ResNode; 1877 if (Subtarget->isThumb1Only()) { 1878 SDValue Pred = getAL(CurDAG); 1879 SDValue PredReg = CurDAG->getRegister(0, MVT::i32); 1880 SDValue Ops[] = { CPIdx, Pred, PredReg, CurDAG->getEntryNode() }; 1881 ResNode = CurDAG->getMachineNode(ARM::tLDRcp, dl, MVT::i32, MVT::Other, 1882 Ops, 4); 1883 } else { 1884 SDValue Ops[] = { 1885 CPIdx, 1886 CurDAG->getRegister(0, MVT::i32), 1887 CurDAG->getTargetConstant(0, MVT::i32), 1888 getAL(CurDAG), 1889 CurDAG->getRegister(0, MVT::i32), 1890 CurDAG->getEntryNode() 1891 }; 1892 ResNode=CurDAG->getMachineNode(ARM::LDRcp, dl, MVT::i32, MVT::Other, 1893 Ops, 6); 1894 } 1895 ReplaceUses(SDValue(N, 0), SDValue(ResNode, 0)); 1896 return NULL; 1897 } 1898 1899 // Other cases are autogenerated. 1900 break; 1901 } 1902 case ISD::FrameIndex: { 1903 // Selects to ADDri FI, 0 which in turn will become ADDri SP, imm. 1904 int FI = cast<FrameIndexSDNode>(N)->getIndex(); 1905 SDValue TFI = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy()); 1906 if (Subtarget->isThumb1Only()) { 1907 return CurDAG->SelectNodeTo(N, ARM::tADDrSPi, MVT::i32, TFI, 1908 CurDAG->getTargetConstant(0, MVT::i32)); 1909 } else { 1910 unsigned Opc = ((Subtarget->isThumb() && Subtarget->hasThumb2()) ? 1911 ARM::t2ADDri : ARM::ADDri); 1912 SDValue Ops[] = { TFI, CurDAG->getTargetConstant(0, MVT::i32), 1913 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32), 1914 CurDAG->getRegister(0, MVT::i32) }; 1915 return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops, 5); 1916 } 1917 } 1918 case ISD::SRL: 1919 if (SDNode *I = SelectV6T2BitfieldExtractOp(N, false)) 1920 return I; 1921 break; 1922 case ISD::SRA: 1923 if (SDNode *I = SelectV6T2BitfieldExtractOp(N, true)) 1924 return I; 1925 break; 1926 case ISD::MUL: 1927 if (Subtarget->isThumb1Only()) 1928 break; 1929 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1))) { 1930 unsigned RHSV = C->getZExtValue(); 1931 if (!RHSV) break; 1932 if (isPowerOf2_32(RHSV-1)) { // 2^n+1? 1933 unsigned ShImm = Log2_32(RHSV-1); 1934 if (ShImm >= 32) 1935 break; 1936 SDValue V = N->getOperand(0); 1937 ShImm = ARM_AM::getSORegOpc(ARM_AM::lsl, ShImm); 1938 SDValue ShImmOp = CurDAG->getTargetConstant(ShImm, MVT::i32); 1939 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); 1940 if (Subtarget->isThumb()) { 1941 SDValue Ops[] = { V, V, ShImmOp, getAL(CurDAG), Reg0, Reg0 }; 1942 return CurDAG->SelectNodeTo(N, ARM::t2ADDrs, MVT::i32, Ops, 6); 1943 } else { 1944 SDValue Ops[] = { V, V, Reg0, ShImmOp, getAL(CurDAG), Reg0, Reg0 }; 1945 return CurDAG->SelectNodeTo(N, ARM::ADDrs, MVT::i32, Ops, 7); 1946 } 1947 } 1948 if (isPowerOf2_32(RHSV+1)) { // 2^n-1? 1949 unsigned ShImm = Log2_32(RHSV+1); 1950 if (ShImm >= 32) 1951 break; 1952 SDValue V = N->getOperand(0); 1953 ShImm = ARM_AM::getSORegOpc(ARM_AM::lsl, ShImm); 1954 SDValue ShImmOp = CurDAG->getTargetConstant(ShImm, MVT::i32); 1955 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); 1956 if (Subtarget->isThumb()) { 1957 SDValue Ops[] = { V, V, ShImmOp, getAL(CurDAG), Reg0 }; 1958 return CurDAG->SelectNodeTo(N, ARM::t2RSBrs, MVT::i32, Ops, 5); 1959 } else { 1960 SDValue Ops[] = { V, V, Reg0, ShImmOp, getAL(CurDAG), Reg0, Reg0 }; 1961 return CurDAG->SelectNodeTo(N, ARM::RSBrs, MVT::i32, Ops, 7); 1962 } 1963 } 1964 } 1965 break; 1966 case ISD::AND: { 1967 // Check for unsigned bitfield extract 1968 if (SDNode *I = SelectV6T2BitfieldExtractOp(N, false)) 1969 return I; 1970 1971 // (and (or x, c2), c1) and top 16-bits of c1 and c2 match, lower 16-bits 1972 // of c1 are 0xffff, and lower 16-bit of c2 are 0. That is, the top 16-bits 1973 // are entirely contributed by c2 and lower 16-bits are entirely contributed 1974 // by x. That's equal to (or (and x, 0xffff), (and c1, 0xffff0000)). 1975 // Select it to: "movt x, ((c1 & 0xffff) >> 16) 1976 EVT VT = N->getValueType(0); 1977 if (VT != MVT::i32) 1978 break; 1979 unsigned Opc = (Subtarget->isThumb() && Subtarget->hasThumb2()) 1980 ? ARM::t2MOVTi16 1981 : (Subtarget->hasV6T2Ops() ? ARM::MOVTi16 : 0); 1982 if (!Opc) 1983 break; 1984 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1); 1985 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1986 if (!N1C) 1987 break; 1988 if (N0.getOpcode() == ISD::OR && N0.getNode()->hasOneUse()) { 1989 SDValue N2 = N0.getOperand(1); 1990 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2); 1991 if (!N2C) 1992 break; 1993 unsigned N1CVal = N1C->getZExtValue(); 1994 unsigned N2CVal = N2C->getZExtValue(); 1995 if ((N1CVal & 0xffff0000U) == (N2CVal & 0xffff0000U) && 1996 (N1CVal & 0xffffU) == 0xffffU && 1997 (N2CVal & 0xffffU) == 0x0U) { 1998 SDValue Imm16 = CurDAG->getTargetConstant((N2CVal & 0xFFFF0000U) >> 16, 1999 MVT::i32); 2000 SDValue Ops[] = { N0.getOperand(0), Imm16, 2001 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32) }; 2002 return CurDAG->getMachineNode(Opc, dl, VT, Ops, 4); 2003 } 2004 } 2005 break; 2006 } 2007 case ARMISD::VMOVRRD: 2008 return CurDAG->getMachineNode(ARM::VMOVRRD, dl, MVT::i32, MVT::i32, 2009 N->getOperand(0), getAL(CurDAG), 2010 CurDAG->getRegister(0, MVT::i32)); 2011 case ISD::UMUL_LOHI: { 2012 if (Subtarget->isThumb1Only()) 2013 break; 2014 if (Subtarget->isThumb()) { 2015 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), 2016 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32), 2017 CurDAG->getRegister(0, MVT::i32) }; 2018 return CurDAG->getMachineNode(ARM::t2UMULL, dl, MVT::i32, MVT::i32, Ops,4); 2019 } else { 2020 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), 2021 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32), 2022 CurDAG->getRegister(0, MVT::i32) }; 2023 return CurDAG->getMachineNode(ARM::UMULL, dl, MVT::i32, MVT::i32, Ops, 5); 2024 } 2025 } 2026 case ISD::SMUL_LOHI: { 2027 if (Subtarget->isThumb1Only()) 2028 break; 2029 if (Subtarget->isThumb()) { 2030 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), 2031 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32) }; 2032 return CurDAG->getMachineNode(ARM::t2SMULL, dl, MVT::i32, MVT::i32, Ops,4); 2033 } else { 2034 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), 2035 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32), 2036 CurDAG->getRegister(0, MVT::i32) }; 2037 return CurDAG->getMachineNode(ARM::SMULL, dl, MVT::i32, MVT::i32, Ops, 5); 2038 } 2039 } 2040 case ISD::LOAD: { 2041 SDNode *ResNode = 0; 2042 if (Subtarget->isThumb() && Subtarget->hasThumb2()) 2043 ResNode = SelectT2IndexedLoad(N); 2044 else 2045 ResNode = SelectARMIndexedLoad(N); 2046 if (ResNode) 2047 return ResNode; 2048 2049 // VLDMQ must be custom-selected for "v2f64 load" to set the AM5Opc value. 2050 if (Subtarget->hasVFP2() && 2051 N->getValueType(0).getSimpleVT().SimpleTy == MVT::v2f64) { 2052 SDValue Chain = N->getOperand(0); 2053 SDValue AM5Opc = 2054 CurDAG->getTargetConstant(ARM_AM::getAM5Opc(ARM_AM::ia, 4), MVT::i32); 2055 SDValue Pred = getAL(CurDAG); 2056 SDValue PredReg = CurDAG->getRegister(0, MVT::i32); 2057 SDValue Ops[] = { N->getOperand(1), AM5Opc, Pred, PredReg, Chain }; 2058 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1); 2059 MemOp[0] = cast<MemSDNode>(N)->getMemOperand(); 2060 SDNode *Ret = CurDAG->getMachineNode(ARM::VLDMQ, dl, 2061 MVT::v2f64, MVT::Other, Ops, 5); 2062 cast<MachineSDNode>(Ret)->setMemRefs(MemOp, MemOp + 1); 2063 return Ret; 2064 } 2065 // Other cases are autogenerated. 2066 break; 2067 } 2068 case ISD::STORE: { 2069 // VSTMQ must be custom-selected for "v2f64 store" to set the AM5Opc value. 2070 if (Subtarget->hasVFP2() && 2071 N->getOperand(1).getValueType().getSimpleVT().SimpleTy == MVT::v2f64) { 2072 SDValue Chain = N->getOperand(0); 2073 SDValue AM5Opc = 2074 CurDAG->getTargetConstant(ARM_AM::getAM5Opc(ARM_AM::ia, 4), MVT::i32); 2075 SDValue Pred = getAL(CurDAG); 2076 SDValue PredReg = CurDAG->getRegister(0, MVT::i32); 2077 SDValue Ops[] = { N->getOperand(1), N->getOperand(2), 2078 AM5Opc, Pred, PredReg, Chain }; 2079 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1); 2080 MemOp[0] = cast<MemSDNode>(N)->getMemOperand(); 2081 SDNode *Ret = CurDAG->getMachineNode(ARM::VSTMQ, dl, MVT::Other, Ops, 6); 2082 cast<MachineSDNode>(Ret)->setMemRefs(MemOp, MemOp + 1); 2083 return Ret; 2084 } 2085 // Other cases are autogenerated. 2086 break; 2087 } 2088 case ARMISD::BRCOND: { 2089 // Pattern: (ARMbrcond:void (bb:Other):$dst, (imm:i32):$cc) 2090 // Emits: (Bcc:void (bb:Other):$dst, (imm:i32):$cc) 2091 // Pattern complexity = 6 cost = 1 size = 0 2092 2093 // Pattern: (ARMbrcond:void (bb:Other):$dst, (imm:i32):$cc) 2094 // Emits: (tBcc:void (bb:Other):$dst, (imm:i32):$cc) 2095 // Pattern complexity = 6 cost = 1 size = 0 2096 2097 // Pattern: (ARMbrcond:void (bb:Other):$dst, (imm:i32):$cc) 2098 // Emits: (t2Bcc:void (bb:Other):$dst, (imm:i32):$cc) 2099 // Pattern complexity = 6 cost = 1 size = 0 2100 2101 unsigned Opc = Subtarget->isThumb() ? 2102 ((Subtarget->hasThumb2()) ? ARM::t2Bcc : ARM::tBcc) : ARM::Bcc; 2103 SDValue Chain = N->getOperand(0); 2104 SDValue N1 = N->getOperand(1); 2105 SDValue N2 = N->getOperand(2); 2106 SDValue N3 = N->getOperand(3); 2107 SDValue InFlag = N->getOperand(4); 2108 assert(N1.getOpcode() == ISD::BasicBlock); 2109 assert(N2.getOpcode() == ISD::Constant); 2110 assert(N3.getOpcode() == ISD::Register); 2111 2112 SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned) 2113 cast<ConstantSDNode>(N2)->getZExtValue()), 2114 MVT::i32); 2115 SDValue Ops[] = { N1, Tmp2, N3, Chain, InFlag }; 2116 SDNode *ResNode = CurDAG->getMachineNode(Opc, dl, MVT::Other, 2117 MVT::Flag, Ops, 5); 2118 Chain = SDValue(ResNode, 0); 2119 if (N->getNumValues() == 2) { 2120 InFlag = SDValue(ResNode, 1); 2121 ReplaceUses(SDValue(N, 1), InFlag); 2122 } 2123 ReplaceUses(SDValue(N, 0), 2124 SDValue(Chain.getNode(), Chain.getResNo())); 2125 return NULL; 2126 } 2127 case ARMISD::CMOV: 2128 return SelectCMOVOp(N); 2129 case ARMISD::CNEG: { 2130 EVT VT = N->getValueType(0); 2131 SDValue N0 = N->getOperand(0); 2132 SDValue N1 = N->getOperand(1); 2133 SDValue N2 = N->getOperand(2); 2134 SDValue N3 = N->getOperand(3); 2135 SDValue InFlag = N->getOperand(4); 2136 assert(N2.getOpcode() == ISD::Constant); 2137 assert(N3.getOpcode() == ISD::Register); 2138 2139 SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned) 2140 cast<ConstantSDNode>(N2)->getZExtValue()), 2141 MVT::i32); 2142 SDValue Ops[] = { N0, N1, Tmp2, N3, InFlag }; 2143 unsigned Opc = 0; 2144 switch (VT.getSimpleVT().SimpleTy) { 2145 default: assert(false && "Illegal conditional move type!"); 2146 break; 2147 case MVT::f32: 2148 Opc = ARM::VNEGScc; 2149 break; 2150 case MVT::f64: 2151 Opc = ARM::VNEGDcc; 2152 break; 2153 } 2154 return CurDAG->SelectNodeTo(N, Opc, VT, Ops, 5); 2155 } 2156 2157 case ARMISD::VZIP: { 2158 unsigned Opc = 0; 2159 EVT VT = N->getValueType(0); 2160 switch (VT.getSimpleVT().SimpleTy) { 2161 default: return NULL; 2162 case MVT::v8i8: Opc = ARM::VZIPd8; break; 2163 case MVT::v4i16: Opc = ARM::VZIPd16; break; 2164 case MVT::v2f32: 2165 case MVT::v2i32: Opc = ARM::VZIPd32; break; 2166 case MVT::v16i8: Opc = ARM::VZIPq8; break; 2167 case MVT::v8i16: Opc = ARM::VZIPq16; break; 2168 case MVT::v4f32: 2169 case MVT::v4i32: Opc = ARM::VZIPq32; break; 2170 } 2171 SDValue Pred = getAL(CurDAG); 2172 SDValue PredReg = CurDAG->getRegister(0, MVT::i32); 2173 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), Pred, PredReg }; 2174 return CurDAG->getMachineNode(Opc, dl, VT, VT, Ops, 4); 2175 } 2176 case ARMISD::VUZP: { 2177 unsigned Opc = 0; 2178 EVT VT = N->getValueType(0); 2179 switch (VT.getSimpleVT().SimpleTy) { 2180 default: return NULL; 2181 case MVT::v8i8: Opc = ARM::VUZPd8; break; 2182 case MVT::v4i16: Opc = ARM::VUZPd16; break; 2183 case MVT::v2f32: 2184 case MVT::v2i32: Opc = ARM::VUZPd32; break; 2185 case MVT::v16i8: Opc = ARM::VUZPq8; break; 2186 case MVT::v8i16: Opc = ARM::VUZPq16; break; 2187 case MVT::v4f32: 2188 case MVT::v4i32: Opc = ARM::VUZPq32; break; 2189 } 2190 SDValue Pred = getAL(CurDAG); 2191 SDValue PredReg = CurDAG->getRegister(0, MVT::i32); 2192 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), Pred, PredReg }; 2193 return CurDAG->getMachineNode(Opc, dl, VT, VT, Ops, 4); 2194 } 2195 case ARMISD::VTRN: { 2196 unsigned Opc = 0; 2197 EVT VT = N->getValueType(0); 2198 switch (VT.getSimpleVT().SimpleTy) { 2199 default: return NULL; 2200 case MVT::v8i8: Opc = ARM::VTRNd8; break; 2201 case MVT::v4i16: Opc = ARM::VTRNd16; break; 2202 case MVT::v2f32: 2203 case MVT::v2i32: Opc = ARM::VTRNd32; break; 2204 case MVT::v16i8: Opc = ARM::VTRNq8; break; 2205 case MVT::v8i16: Opc = ARM::VTRNq16; break; 2206 case MVT::v4f32: 2207 case MVT::v4i32: Opc = ARM::VTRNq32; break; 2208 } 2209 SDValue Pred = getAL(CurDAG); 2210 SDValue PredReg = CurDAG->getRegister(0, MVT::i32); 2211 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), Pred, PredReg }; 2212 return CurDAG->getMachineNode(Opc, dl, VT, VT, Ops, 4); 2213 } 2214 2215 case ISD::INTRINSIC_VOID: 2216 case ISD::INTRINSIC_W_CHAIN: { 2217 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue(); 2218 switch (IntNo) { 2219 default: 2220 break; 2221 2222 case Intrinsic::arm_neon_vld1: { 2223 unsigned DOpcodes[] = { ARM::VLD1d8, ARM::VLD1d16, 2224 ARM::VLD1d32, ARM::VLD1d64 }; 2225 unsigned QOpcodes[] = { ARM::VLD1q8, ARM::VLD1q16, 2226 ARM::VLD1q32, ARM::VLD1q64 }; 2227 return SelectVLD(N, 1, DOpcodes, QOpcodes, 0); 2228 } 2229 2230 case Intrinsic::arm_neon_vld2: { 2231 unsigned DOpcodes[] = { ARM::VLD2d8, ARM::VLD2d16, 2232 ARM::VLD2d32, ARM::VLD1q64 }; 2233 unsigned QOpcodes[] = { ARM::VLD2q8, ARM::VLD2q16, ARM::VLD2q32 }; 2234 return SelectVLD(N, 2, DOpcodes, QOpcodes, 0); 2235 } 2236 2237 case Intrinsic::arm_neon_vld3: { 2238 unsigned DOpcodes[] = { ARM::VLD3d8, ARM::VLD3d16, 2239 ARM::VLD3d32, ARM::VLD1d64T }; 2240 unsigned QOpcodes0[] = { ARM::VLD3q8_UPD, 2241 ARM::VLD3q16_UPD, 2242 ARM::VLD3q32_UPD }; 2243 unsigned QOpcodes1[] = { ARM::VLD3q8odd_UPD, 2244 ARM::VLD3q16odd_UPD, 2245 ARM::VLD3q32odd_UPD }; 2246 return SelectVLD(N, 3, DOpcodes, QOpcodes0, QOpcodes1); 2247 } 2248 2249 case Intrinsic::arm_neon_vld4: { 2250 unsigned DOpcodes[] = { ARM::VLD4d8, ARM::VLD4d16, 2251 ARM::VLD4d32, ARM::VLD1d64Q }; 2252 unsigned QOpcodes0[] = { ARM::VLD4q8_UPD, 2253 ARM::VLD4q16_UPD, 2254 ARM::VLD4q32_UPD }; 2255 unsigned QOpcodes1[] = { ARM::VLD4q8odd_UPD, 2256 ARM::VLD4q16odd_UPD, 2257 ARM::VLD4q32odd_UPD }; 2258 return SelectVLD(N, 4, DOpcodes, QOpcodes0, QOpcodes1); 2259 } 2260 2261 case Intrinsic::arm_neon_vld2lane: { 2262 unsigned DOpcodes[] = { ARM::VLD2LNd8, ARM::VLD2LNd16, ARM::VLD2LNd32 }; 2263 unsigned QOpcodes0[] = { ARM::VLD2LNq16, ARM::VLD2LNq32 }; 2264 unsigned QOpcodes1[] = { ARM::VLD2LNq16odd, ARM::VLD2LNq32odd }; 2265 return SelectVLDSTLane(N, true, 2, DOpcodes, QOpcodes0, QOpcodes1); 2266 } 2267 2268 case Intrinsic::arm_neon_vld3lane: { 2269 unsigned DOpcodes[] = { ARM::VLD3LNd8, ARM::VLD3LNd16, ARM::VLD3LNd32 }; 2270 unsigned QOpcodes0[] = { ARM::VLD3LNq16, ARM::VLD3LNq32 }; 2271 unsigned QOpcodes1[] = { ARM::VLD3LNq16odd, ARM::VLD3LNq32odd }; 2272 return SelectVLDSTLane(N, true, 3, DOpcodes, QOpcodes0, QOpcodes1); 2273 } 2274 2275 case Intrinsic::arm_neon_vld4lane: { 2276 unsigned DOpcodes[] = { ARM::VLD4LNd8, ARM::VLD4LNd16, ARM::VLD4LNd32 }; 2277 unsigned QOpcodes0[] = { ARM::VLD4LNq16, ARM::VLD4LNq32 }; 2278 unsigned QOpcodes1[] = { ARM::VLD4LNq16odd, ARM::VLD4LNq32odd }; 2279 return SelectVLDSTLane(N, true, 4, DOpcodes, QOpcodes0, QOpcodes1); 2280 } 2281 2282 case Intrinsic::arm_neon_vst1: { 2283 unsigned DOpcodes[] = { ARM::VST1d8, ARM::VST1d16, 2284 ARM::VST1d32, ARM::VST1d64 }; 2285 unsigned QOpcodes[] = { ARM::VST1q8, ARM::VST1q16, 2286 ARM::VST1q32, ARM::VST1q64 }; 2287 return SelectVST(N, 1, DOpcodes, QOpcodes, 0); 2288 } 2289 2290 case Intrinsic::arm_neon_vst2: { 2291 unsigned DOpcodes[] = { ARM::VST2d8, ARM::VST2d16, 2292 ARM::VST2d32, ARM::VST1q64 }; 2293 unsigned QOpcodes[] = { ARM::VST2q8, ARM::VST2q16, ARM::VST2q32 }; 2294 return SelectVST(N, 2, DOpcodes, QOpcodes, 0); 2295 } 2296 2297 case Intrinsic::arm_neon_vst3: { 2298 unsigned DOpcodes[] = { ARM::VST3d8, ARM::VST3d16, 2299 ARM::VST3d32, ARM::VST1d64T }; 2300 unsigned QOpcodes0[] = { ARM::VST3q8_UPD, 2301 ARM::VST3q16_UPD, 2302 ARM::VST3q32_UPD }; 2303 unsigned QOpcodes1[] = { ARM::VST3q8odd_UPD, 2304 ARM::VST3q16odd_UPD, 2305 ARM::VST3q32odd_UPD }; 2306 return SelectVST(N, 3, DOpcodes, QOpcodes0, QOpcodes1); 2307 } 2308 2309 case Intrinsic::arm_neon_vst4: { 2310 unsigned DOpcodes[] = { ARM::VST4d8, ARM::VST4d16, 2311 ARM::VST4d32, ARM::VST1d64Q }; 2312 unsigned QOpcodes0[] = { ARM::VST4q8_UPD, 2313 ARM::VST4q16_UPD, 2314 ARM::VST4q32_UPD }; 2315 unsigned QOpcodes1[] = { ARM::VST4q8odd_UPD, 2316 ARM::VST4q16odd_UPD, 2317 ARM::VST4q32odd_UPD }; 2318 return SelectVST(N, 4, DOpcodes, QOpcodes0, QOpcodes1); 2319 } 2320 2321 case Intrinsic::arm_neon_vst2lane: { 2322 unsigned DOpcodes[] = { ARM::VST2LNd8, ARM::VST2LNd16, ARM::VST2LNd32 }; 2323 unsigned QOpcodes0[] = { ARM::VST2LNq16, ARM::VST2LNq32 }; 2324 unsigned QOpcodes1[] = { ARM::VST2LNq16odd, ARM::VST2LNq32odd }; 2325 return SelectVLDSTLane(N, false, 2, DOpcodes, QOpcodes0, QOpcodes1); 2326 } 2327 2328 case Intrinsic::arm_neon_vst3lane: { 2329 unsigned DOpcodes[] = { ARM::VST3LNd8, ARM::VST3LNd16, ARM::VST3LNd32 }; 2330 unsigned QOpcodes0[] = { ARM::VST3LNq16, ARM::VST3LNq32 }; 2331 unsigned QOpcodes1[] = { ARM::VST3LNq16odd, ARM::VST3LNq32odd }; 2332 return SelectVLDSTLane(N, false, 3, DOpcodes, QOpcodes0, QOpcodes1); 2333 } 2334 2335 case Intrinsic::arm_neon_vst4lane: { 2336 unsigned DOpcodes[] = { ARM::VST4LNd8, ARM::VST4LNd16, ARM::VST4LNd32 }; 2337 unsigned QOpcodes0[] = { ARM::VST4LNq16, ARM::VST4LNq32 }; 2338 unsigned QOpcodes1[] = { ARM::VST4LNq16odd, ARM::VST4LNq32odd }; 2339 return SelectVLDSTLane(N, false, 4, DOpcodes, QOpcodes0, QOpcodes1); 2340 } 2341 } 2342 break; 2343 } 2344 2345 case ISD::CONCAT_VECTORS: 2346 return SelectConcatVector(N); 2347 } 2348 2349 return SelectCode(N); 2350} 2351 2352bool ARMDAGToDAGISel:: 2353SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode, 2354 std::vector<SDValue> &OutOps) { 2355 assert(ConstraintCode == 'm' && "unexpected asm memory constraint"); 2356 // Require the address to be in a register. That is safe for all ARM 2357 // variants and it is hard to do anything much smarter without knowing 2358 // how the operand is used. 2359 OutOps.push_back(Op); 2360 return false; 2361} 2362 2363/// createARMISelDag - This pass converts a legalized DAG into a 2364/// ARM-specific DAG, ready for instruction scheduling. 2365/// 2366FunctionPass *llvm::createARMISelDag(ARMBaseTargetMachine &TM, 2367 CodeGenOpt::Level OptLevel) { 2368 return new ARMDAGToDAGISel(TM, OptLevel); 2369} 2370 2371/// ModelWithRegSequence - Return true if isel should use REG_SEQUENCE to model 2372/// operations involving sub-registers. 2373bool llvm::ModelWithRegSequence() { 2374 return UseRegSeq; 2375} 2376