SIISelLowering.h revision 327952
1284677Sdim//===-- SIISelLowering.h - SI DAG Lowering Interface ------------*- C++ -*-===// 2284677Sdim// 3284677Sdim// The LLVM Compiler Infrastructure 4284677Sdim// 5284677Sdim// This file is distributed under the University of Illinois Open Source 6284677Sdim// License. See LICENSE.TXT for details. 7284677Sdim// 8284677Sdim//===----------------------------------------------------------------------===// 9284677Sdim// 10284677Sdim/// \file 11284677Sdim/// \brief SI DAG Lowering interface definition 12284677Sdim// 13284677Sdim//===----------------------------------------------------------------------===// 14284677Sdim 15309124Sdim#ifndef LLVM_LIB_TARGET_AMDGPU_SIISELLOWERING_H 16309124Sdim#define LLVM_LIB_TARGET_AMDGPU_SIISELLOWERING_H 17284677Sdim 18284677Sdim#include "AMDGPUISelLowering.h" 19327952Sdim#include "AMDGPUArgumentUsageInfo.h" 20284677Sdim#include "SIInstrInfo.h" 21284677Sdim 22284677Sdimnamespace llvm { 23284677Sdim 24309124Sdimclass SITargetLowering final : public AMDGPUTargetLowering { 25321369Sdim SDValue lowerKernArgParameterPtr(SelectionDAG &DAG, const SDLoc &SL, 26321369Sdim SDValue Chain, uint64_t Offset) const; 27327952Sdim SDValue getImplicitArgPtr(SelectionDAG &DAG, const SDLoc &SL) const; 28321369Sdim SDValue lowerKernargMemParameter(SelectionDAG &DAG, EVT VT, EVT MemVT, 29321369Sdim const SDLoc &SL, SDValue Chain, 30321369Sdim uint64_t Offset, bool Signed, 31321369Sdim const ISD::InputArg *Arg = nullptr) const; 32321369Sdim 33321369Sdim SDValue lowerStackParameter(SelectionDAG &DAG, CCValAssign &VA, 34321369Sdim const SDLoc &SL, SDValue Chain, 35321369Sdim const ISD::InputArg &Arg) const; 36327952Sdim SDValue getPreloadedValue(SelectionDAG &DAG, 37327952Sdim const SIMachineFunctionInfo &MFI, 38327952Sdim EVT VT, 39327952Sdim AMDGPUFunctionArgInfo::PreloadedValue) const; 40321369Sdim 41284677Sdim SDValue LowerGlobalAddress(AMDGPUMachineFunction *MFI, SDValue Op, 42284677Sdim SelectionDAG &DAG) const override; 43296417Sdim SDValue lowerImplicitZextParam(SelectionDAG &DAG, SDValue Op, 44296417Sdim MVT VT, unsigned Offset) const; 45296417Sdim 46284677Sdim SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const; 47309124Sdim SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) const; 48284677Sdim SDValue LowerINTRINSIC_VOID(SDValue Op, SelectionDAG &DAG) const; 49284677Sdim SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const; 50284677Sdim SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const; 51309124Sdim SDValue lowerFastUnsafeFDIV(SDValue Op, SelectionDAG &DAG) const; 52309124Sdim SDValue lowerFDIV_FAST(SDValue Op, SelectionDAG &DAG) const; 53314564Sdim SDValue LowerFDIV16(SDValue Op, SelectionDAG &DAG) const; 54284677Sdim SDValue LowerFDIV32(SDValue Op, SelectionDAG &DAG) const; 55284677Sdim SDValue LowerFDIV64(SDValue Op, SelectionDAG &DAG) const; 56284677Sdim SDValue LowerFDIV(SDValue Op, SelectionDAG &DAG) const; 57284677Sdim SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG, bool Signed) const; 58284677Sdim SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const; 59284677Sdim SDValue LowerTrig(SDValue Op, SelectionDAG &DAG) const; 60309124Sdim SDValue LowerATOMIC_CMP_SWAP(SDValue Op, SelectionDAG &DAG) const; 61284677Sdim SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const; 62284677Sdim 63314564Sdim /// \brief Converts \p Op, which must be of floating point type, to the 64314564Sdim /// floating point type \p VT, by either extending or truncating it. 65314564Sdim SDValue getFPExtOrFPTrunc(SelectionDAG &DAG, 66314564Sdim SDValue Op, 67314564Sdim const SDLoc &DL, 68314564Sdim EVT VT) const; 69314564Sdim 70321369Sdim SDValue convertArgType( 71321369Sdim SelectionDAG &DAG, EVT VT, EVT MemVT, const SDLoc &SL, SDValue Val, 72321369Sdim bool Signed, const ISD::InputArg *Arg = nullptr) const; 73321369Sdim 74314564Sdim /// \brief Custom lowering for ISD::FP_ROUND for MVT::f16. 75314564Sdim SDValue lowerFP_ROUND(SDValue Op, SelectionDAG &DAG) const; 76314564Sdim 77321369Sdim SDValue getSegmentAperture(unsigned AS, const SDLoc &DL, 78321369Sdim SelectionDAG &DAG) const; 79321369Sdim 80309124Sdim SDValue lowerADDRSPACECAST(SDValue Op, SelectionDAG &DAG) const; 81321369Sdim SDValue lowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const; 82321369Sdim SDValue lowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const; 83309124Sdim SDValue lowerTRAP(SDValue Op, SelectionDAG &DAG) const; 84309124Sdim 85327952Sdim SDNode *adjustWritemask(MachineSDNode *&N, SelectionDAG &DAG) const; 86284677Sdim 87284677Sdim SDValue performUCharToFloatCombine(SDNode *N, 88284677Sdim DAGCombinerInfo &DCI) const; 89284677Sdim SDValue performSHLPtrCombine(SDNode *N, 90284677Sdim unsigned AS, 91327952Sdim EVT MemVT, 92284677Sdim DAGCombinerInfo &DCI) const; 93314564Sdim 94314564Sdim SDValue performMemSDNodeCombine(MemSDNode *N, DAGCombinerInfo &DCI) const; 95314564Sdim 96314564Sdim SDValue splitBinaryBitConstantOp(DAGCombinerInfo &DCI, const SDLoc &SL, 97314564Sdim unsigned Opc, SDValue LHS, 98314564Sdim const ConstantSDNode *CRHS) const; 99314564Sdim 100284677Sdim SDValue performAndCombine(SDNode *N, DAGCombinerInfo &DCI) const; 101284677Sdim SDValue performOrCombine(SDNode *N, DAGCombinerInfo &DCI) const; 102314564Sdim SDValue performXorCombine(SDNode *N, DAGCombinerInfo &DCI) const; 103321369Sdim SDValue performZeroExtendCombine(SDNode *N, DAGCombinerInfo &DCI) const; 104284677Sdim SDValue performClassCombine(SDNode *N, DAGCombinerInfo &DCI) const; 105309124Sdim SDValue performFCanonicalizeCombine(SDNode *N, DAGCombinerInfo &DCI) const; 106284677Sdim 107321369Sdim SDValue performFPMed3ImmCombine(SelectionDAG &DAG, const SDLoc &SL, 108321369Sdim SDValue Op0, SDValue Op1) const; 109321369Sdim SDValue performIntMed3ImmCombine(SelectionDAG &DAG, const SDLoc &SL, 110321369Sdim SDValue Op0, SDValue Op1, bool Signed) const; 111309124Sdim SDValue performMinMaxCombine(SDNode *N, DAGCombinerInfo &DCI) const; 112321369Sdim SDValue performFMed3Combine(SDNode *N, DAGCombinerInfo &DCI) const; 113321369Sdim SDValue performCvtPkRTZCombine(SDNode *N, DAGCombinerInfo &DCI) const; 114321369Sdim SDValue performExtractVectorEltCombine(SDNode *N, DAGCombinerInfo &DCI) const; 115327952Sdim SDValue performBuildVectorCombine(SDNode *N, DAGCombinerInfo &DCI) const; 116309124Sdim 117314564Sdim unsigned getFusedOpcode(const SelectionDAG &DAG, 118314564Sdim const SDNode *N0, const SDNode *N1) const; 119321369Sdim SDValue performAddCombine(SDNode *N, DAGCombinerInfo &DCI) const; 120321369Sdim SDValue performAddCarrySubCarryCombine(SDNode *N, DAGCombinerInfo &DCI) const; 121321369Sdim SDValue performSubCombine(SDNode *N, DAGCombinerInfo &DCI) const; 122314564Sdim SDValue performFAddCombine(SDNode *N, DAGCombinerInfo &DCI) const; 123314564Sdim SDValue performFSubCombine(SDNode *N, DAGCombinerInfo &DCI) const; 124284677Sdim SDValue performSetCCCombine(SDNode *N, DAGCombinerInfo &DCI) const; 125314564Sdim SDValue performCvtF32UByteNCombine(SDNode *N, DAGCombinerInfo &DCI) const; 126284677Sdim 127287521Sdim bool isLegalFlatAddressingMode(const AddrMode &AM) const; 128327952Sdim bool isLegalGlobalAddressingMode(const AddrMode &AM) const; 129296417Sdim bool isLegalMUBUFAddressingMode(const AddrMode &AM) const; 130309124Sdim 131321369Sdim unsigned isCFIntrinsic(const SDNode *Intr) const; 132309124Sdim 133309124Sdim void createDebuggerPrologueStackObjects(MachineFunction &MF) const; 134314564Sdim 135314564Sdim /// \returns True if fixup needs to be emitted for given global value \p GV, 136314564Sdim /// false otherwise. 137314564Sdim bool shouldEmitFixup(const GlobalValue *GV) const; 138314564Sdim 139314564Sdim /// \returns True if GOT relocation needs to be emitted for given global value 140314564Sdim /// \p GV, false otherwise. 141314564Sdim bool shouldEmitGOTReloc(const GlobalValue *GV) const; 142314564Sdim 143314564Sdim /// \returns True if PC-relative relocation needs to be emitted for given 144314564Sdim /// global value \p GV, false otherwise. 145314564Sdim bool shouldEmitPCReloc(const GlobalValue *GV) const; 146314564Sdim 147284677Sdimpublic: 148309124Sdim SITargetLowering(const TargetMachine &tm, const SISubtarget &STI); 149284677Sdim 150309124Sdim const SISubtarget *getSubtarget() const; 151309124Sdim 152327952Sdim bool isShuffleMaskLegal(ArrayRef<int> /*Mask*/, EVT /*VT*/) const override; 153321369Sdim 154309124Sdim bool getTgtMemIntrinsic(IntrinsicInfo &, const CallInst &, 155327952Sdim MachineFunction &MF, 156309124Sdim unsigned IntrinsicID) const override; 157309124Sdim 158321369Sdim bool getAddrModeArguments(IntrinsicInst * /*I*/, 159321369Sdim SmallVectorImpl<Value*> &/*Ops*/, 160321369Sdim Type *&/*AccessTy*/) const override; 161284677Sdim 162286684Sdim bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, 163327952Sdim unsigned AS, 164327952Sdim Instruction *I = nullptr) const override; 165284677Sdim 166321369Sdim bool canMergeStoresTo(unsigned AS, EVT MemVT, 167321369Sdim const SelectionDAG &DAG) const override; 168321369Sdim 169284677Sdim bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AS, 170284677Sdim unsigned Align, 171284677Sdim bool *IsFast) const override; 172284677Sdim 173284677Sdim EVT getOptimalMemOpType(uint64_t Size, unsigned DstAlign, 174284677Sdim unsigned SrcAlign, bool IsMemset, 175284677Sdim bool ZeroMemset, 176284677Sdim bool MemcpyStrSrc, 177284677Sdim MachineFunction &MF) const override; 178284677Sdim 179296417Sdim bool isMemOpUniform(const SDNode *N) const; 180314564Sdim bool isMemOpHasNoClobberedMemOperand(const SDNode *N) const; 181296417Sdim bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override; 182314564Sdim bool isCheapAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override; 183296417Sdim 184284677Sdim TargetLoweringBase::LegalizeTypeAction 185284677Sdim getPreferredVectorAction(EVT VT) const override; 186284677Sdim 187284677Sdim bool shouldConvertConstantLoadToIntImm(const APInt &Imm, 188284677Sdim Type *Ty) const override; 189284677Sdim 190309124Sdim bool isTypeDesirableForOp(unsigned Op, EVT VT) const override; 191309124Sdim 192309124Sdim bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override; 193309124Sdim 194327952Sdim bool supportSplitCSR(MachineFunction *MF) const override; 195327952Sdim void initializeSplitCSR(MachineBasicBlock *Entry) const override; 196327952Sdim void insertCopiesSplitCSR( 197327952Sdim MachineBasicBlock *Entry, 198327952Sdim const SmallVectorImpl<MachineBasicBlock *> &Exits) const override; 199327952Sdim 200284677Sdim SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, 201284677Sdim bool isVarArg, 202284677Sdim const SmallVectorImpl<ISD::InputArg> &Ins, 203309124Sdim const SDLoc &DL, SelectionDAG &DAG, 204284677Sdim SmallVectorImpl<SDValue> &InVals) const override; 205284677Sdim 206321369Sdim bool CanLowerReturn(CallingConv::ID CallConv, 207321369Sdim MachineFunction &MF, bool isVarArg, 208296417Sdim const SmallVectorImpl<ISD::OutputArg> &Outs, 209321369Sdim LLVMContext &Context) const override; 210321369Sdim 211321369Sdim SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, 212321369Sdim const SmallVectorImpl<ISD::OutputArg> &Outs, 213309124Sdim const SmallVectorImpl<SDValue> &OutVals, const SDLoc &DL, 214309124Sdim SelectionDAG &DAG) const override; 215296417Sdim 216327952Sdim void passSpecialInputs( 217327952Sdim CallLoweringInfo &CLI, 218327952Sdim const SIMachineFunctionInfo &Info, 219327952Sdim SmallVectorImpl<std::pair<unsigned, SDValue>> &RegsToPass, 220327952Sdim SmallVectorImpl<SDValue> &MemOpChains, 221327952Sdim SDValue Chain, 222327952Sdim SDValue StackPtr) const; 223327952Sdim 224327952Sdim SDValue LowerCallResult(SDValue Chain, SDValue InFlag, 225327952Sdim CallingConv::ID CallConv, bool isVarArg, 226327952Sdim const SmallVectorImpl<ISD::InputArg> &Ins, 227327952Sdim const SDLoc &DL, SelectionDAG &DAG, 228327952Sdim SmallVectorImpl<SDValue> &InVals, bool isThisReturn, 229327952Sdim SDValue ThisVal) const; 230327952Sdim 231327952Sdim bool mayBeEmittedAsTailCall(const CallInst *) const override; 232327952Sdim 233327952Sdim bool isEligibleForTailCallOptimization( 234327952Sdim SDValue Callee, CallingConv::ID CalleeCC, bool isVarArg, 235327952Sdim const SmallVectorImpl<ISD::OutputArg> &Outs, 236327952Sdim const SmallVectorImpl<SDValue> &OutVals, 237327952Sdim const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG &DAG) const; 238327952Sdim 239327952Sdim SDValue LowerCall(CallLoweringInfo &CLI, 240327952Sdim SmallVectorImpl<SDValue> &InVals) const override; 241327952Sdim 242309124Sdim unsigned getRegisterByName(const char* RegName, EVT VT, 243309124Sdim SelectionDAG &DAG) const override; 244309124Sdim 245309124Sdim MachineBasicBlock *splitKillBlock(MachineInstr &MI, 246309124Sdim MachineBasicBlock *BB) const; 247309124Sdim 248309124Sdim MachineBasicBlock * 249309124Sdim EmitInstrWithCustomInserter(MachineInstr &MI, 250309124Sdim MachineBasicBlock *BB) const override; 251327952Sdim 252327952Sdim bool hasBitPreservingFPLogic(EVT VT) const override; 253284677Sdim bool enableAggressiveFMAFusion(EVT VT) const override; 254286684Sdim EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, 255286684Sdim EVT VT) const override; 256286684Sdim MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override; 257284677Sdim bool isFMAFasterThanFMulAndFAdd(EVT VT) const override; 258284677Sdim SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override; 259321369Sdim void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue> &Results, 260321369Sdim SelectionDAG &DAG) const override; 261321369Sdim 262284677Sdim SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override; 263284677Sdim SDNode *PostISelFolding(MachineSDNode *N, SelectionDAG &DAG) const override; 264309124Sdim void AdjustInstrPostInstrSelection(MachineInstr &MI, 265284677Sdim SDNode *Node) const override; 266284677Sdim 267321369Sdim SDNode *legalizeTargetIndependentNode(SDNode *Node, SelectionDAG &DAG) const; 268284677Sdim 269309124Sdim MachineSDNode *wrapAddr64Rsrc(SelectionDAG &DAG, const SDLoc &DL, 270309124Sdim SDValue Ptr) const; 271309124Sdim MachineSDNode *buildRSRC(SelectionDAG &DAG, const SDLoc &DL, SDValue Ptr, 272309124Sdim uint32_t RsrcDword1, uint64_t RsrcDword2And3) const; 273286684Sdim std::pair<unsigned, const TargetRegisterClass *> 274286684Sdim getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, 275286684Sdim StringRef Constraint, MVT VT) const override; 276296417Sdim ConstraintType getConstraintType(StringRef Constraint) const override; 277309124Sdim SDValue copyToM0(SelectionDAG &DAG, SDValue Chain, const SDLoc &DL, 278309124Sdim SDValue V) const; 279321369Sdim 280321369Sdim void finalizeLowering(MachineFunction &MF) const override; 281327952Sdim 282327952Sdim void computeKnownBitsForFrameIndex(const SDValue Op, 283327952Sdim KnownBits &Known, 284327952Sdim const APInt &DemandedElts, 285327952Sdim const SelectionDAG &DAG, 286327952Sdim unsigned Depth = 0) const override; 287284677Sdim}; 288284677Sdim 289284677Sdim} // End namespace llvm 290284677Sdim 291284677Sdim#endif 292