AArch64TargetMachine.cpp revision 360784 
1//===-- AArch64TargetMachine.cpp - Define TargetMachine for AArch64 -------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9//
10//===----------------------------------------------------------------------===//
11
12#include "AArch64TargetMachine.h"
13#include "AArch64.h"
14#include "AArch64MacroFusion.h"
15#include "AArch64Subtarget.h"
16#include "AArch64TargetObjectFile.h"
17#include "AArch64TargetTransformInfo.h"
18#include "MCTargetDesc/AArch64MCTargetDesc.h"
19#include "TargetInfo/AArch64TargetInfo.h"
20#include "llvm/ADT/STLExtras.h"
21#include "llvm/ADT/Triple.h"
22#include "llvm/Analysis/TargetTransformInfo.h"
23#include "llvm/CodeGen/CSEConfigBase.h"
24#include "llvm/CodeGen/GlobalISel/IRTranslator.h"
25#include "llvm/CodeGen/GlobalISel/InstructionSelect.h"
26#include "llvm/CodeGen/GlobalISel/Legalizer.h"
27#include "llvm/CodeGen/GlobalISel/Localizer.h"
28#include "llvm/CodeGen/GlobalISel/RegBankSelect.h"
29#include "llvm/CodeGen/MachineScheduler.h"
30#include "llvm/CodeGen/Passes.h"
31#include "llvm/CodeGen/TargetPassConfig.h"
32#include "llvm/IR/Attributes.h"
33#include "llvm/IR/Function.h"
34#include "llvm/InitializePasses.h"
35#include "llvm/MC/MCAsmInfo.h"
36#include "llvm/MC/MCTargetOptions.h"
37#include "llvm/Pass.h"
38#include "llvm/Support/CodeGen.h"
39#include "llvm/Support/CommandLine.h"
40#include "llvm/Support/TargetRegistry.h"
41#include "llvm/Target/TargetLoweringObjectFile.h"
42#include "llvm/Target/TargetOptions.h"
43#include "llvm/Transforms/CFGuard.h"
44#include "llvm/Transforms/Scalar.h"
45#include <memory>
46#include <string>
47
48using namespace llvm;
49
50static cl::opt<bool> EnableCCMP("aarch64-enable-ccmp",
51                                cl::desc("Enable the CCMP formation pass"),
52                                cl::init(true), cl::Hidden);
53
54static cl::opt<bool>
55    EnableCondBrTuning("aarch64-enable-cond-br-tune",
56                       cl::desc("Enable the conditional branch tuning pass"),
57                       cl::init(true), cl::Hidden);
58
59static cl::opt<bool> EnableMCR("aarch64-enable-mcr",
60                               cl::desc("Enable the machine combiner pass"),
61                               cl::init(true), cl::Hidden);
62
63static cl::opt<bool> EnableStPairSuppress("aarch64-enable-stp-suppress",
64                                          cl::desc("Suppress STP for AArch64"),
65                                          cl::init(true), cl::Hidden);
66
67static cl::opt<bool> EnableAdvSIMDScalar(
68    "aarch64-enable-simd-scalar",
69    cl::desc("Enable use of AdvSIMD scalar integer instructions"),
70    cl::init(false), cl::Hidden);
71
72static cl::opt<bool>
73    EnablePromoteConstant("aarch64-enable-promote-const",
74                          cl::desc("Enable the promote constant pass"),
75                          cl::init(true), cl::Hidden);
76
77static cl::opt<bool> EnableCollectLOH(
78    "aarch64-enable-collect-loh",
79    cl::desc("Enable the pass that emits the linker optimization hints (LOH)"),
80    cl::init(true), cl::Hidden);
81
82static cl::opt<bool>
83    EnableDeadRegisterElimination("aarch64-enable-dead-defs", cl::Hidden,
84                                  cl::desc("Enable the pass that removes dead"
85                                           " definitons and replaces stores to"
86                                           " them with stores to the zero"
87                                           " register"),
88                                  cl::init(true));
89
90static cl::opt<bool> EnableRedundantCopyElimination(
91    "aarch64-enable-copyelim",
92    cl::desc("Enable the redundant copy elimination pass"), cl::init(true),
93    cl::Hidden);
94
95static cl::opt<bool> EnableLoadStoreOpt("aarch64-enable-ldst-opt",
96                                        cl::desc("Enable the load/store pair"
97                                                 " optimization pass"),
98                                        cl::init(true), cl::Hidden);
99
100static cl::opt<bool> EnableAtomicTidy(
101    "aarch64-enable-atomic-cfg-tidy", cl::Hidden,
102    cl::desc("Run SimplifyCFG after expanding atomic operations"
103             " to make use of cmpxchg flow-based information"),
104    cl::init(true));
105
106static cl::opt<bool>
107EnableEarlyIfConversion("aarch64-enable-early-ifcvt", cl::Hidden,
108                        cl::desc("Run early if-conversion"),
109                        cl::init(true));
110
111static cl::opt<bool>
112    EnableCondOpt("aarch64-enable-condopt",
113                  cl::desc("Enable the condition optimizer pass"),
114                  cl::init(true), cl::Hidden);
115
116static cl::opt<bool>
117EnableA53Fix835769("aarch64-fix-cortex-a53-835769", cl::Hidden,
118                cl::desc("Work around Cortex-A53 erratum 835769"),
119                cl::init(false));
120
121static cl::opt<bool>
122    EnableGEPOpt("aarch64-enable-gep-opt", cl::Hidden,
123                 cl::desc("Enable optimizations on complex GEPs"),
124                 cl::init(false));
125
126static cl::opt<bool>
127    BranchRelaxation("aarch64-enable-branch-relax", cl::Hidden, cl::init(true),
128                     cl::desc("Relax out of range conditional branches"));
129
130static cl::opt<bool> EnableCompressJumpTables(
131    "aarch64-enable-compress-jump-tables", cl::Hidden, cl::init(true),
132    cl::desc("Use smallest entry possible for jump tables"));
133
134// FIXME: Unify control over GlobalMerge.
135static cl::opt<cl::boolOrDefault>
136    EnableGlobalMerge("aarch64-enable-global-merge", cl::Hidden,
137                      cl::desc("Enable the global merge pass"));
138
139static cl::opt<bool>
140    EnableLoopDataPrefetch("aarch64-enable-loop-data-prefetch", cl::Hidden,
141                           cl::desc("Enable the loop data prefetch pass"),
142                           cl::init(true));
143
144static cl::opt<int> EnableGlobalISelAtO(
145    "aarch64-enable-global-isel-at-O", cl::Hidden,
146    cl::desc("Enable GlobalISel at or below an opt level (-1 to disable)"),
147    cl::init(0));
148
149static cl::opt<bool> EnableFalkorHWPFFix("aarch64-enable-falkor-hwpf-fix",
150                                         cl::init(true), cl::Hidden);
151
152static cl::opt<bool>
153    EnableBranchTargets("aarch64-enable-branch-targets", cl::Hidden,
154                        cl::desc("Enable the AAcrh64 branch target pass"),
155                        cl::init(true));
156
157extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAArch64Target() {
158  // Register the target.
159  RegisterTargetMachine<AArch64leTargetMachine> X(getTheAArch64leTarget());
160  RegisterTargetMachine<AArch64beTargetMachine> Y(getTheAArch64beTarget());
161  RegisterTargetMachine<AArch64leTargetMachine> Z(getTheARM64Target());
162  RegisterTargetMachine<AArch64leTargetMachine> W(getTheARM64_32Target());
163  RegisterTargetMachine<AArch64leTargetMachine> V(getTheAArch64_32Target());
164  auto PR = PassRegistry::getPassRegistry();
165  initializeGlobalISel(*PR);
166  initializeAArch64A53Fix835769Pass(*PR);
167  initializeAArch64A57FPLoadBalancingPass(*PR);
168  initializeAArch64AdvSIMDScalarPass(*PR);
169  initializeAArch64BranchTargetsPass(*PR);
170  initializeAArch64CollectLOHPass(*PR);
171  initializeAArch64CompressJumpTablesPass(*PR);
172  initializeAArch64ConditionalComparesPass(*PR);
173  initializeAArch64ConditionOptimizerPass(*PR);
174  initializeAArch64DeadRegisterDefinitionsPass(*PR);
175  initializeAArch64ExpandPseudoPass(*PR);
176  initializeAArch64LoadStoreOptPass(*PR);
177  initializeAArch64SIMDInstrOptPass(*PR);
178  initializeAArch64PreLegalizerCombinerPass(*PR);
179  initializeAArch64PromoteConstantPass(*PR);
180  initializeAArch64RedundantCopyEliminationPass(*PR);
181  initializeAArch64StorePairSuppressPass(*PR);
182  initializeFalkorHWPFFixPass(*PR);
183  initializeFalkorMarkStridedAccessesLegacyPass(*PR);
184  initializeLDTLSCleanupPass(*PR);
185  initializeAArch64SpeculationHardeningPass(*PR);
186  initializeAArch64StackTaggingPass(*PR);
187  initializeAArch64StackTaggingPreRAPass(*PR);
188}
189
190//===----------------------------------------------------------------------===//
191// AArch64 Lowering public interface.
192//===----------------------------------------------------------------------===//
193static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
194  if (TT.isOSBinFormatMachO())
195    return std::make_unique<AArch64_MachoTargetObjectFile>();
196  if (TT.isOSBinFormatCOFF())
197    return std::make_unique<AArch64_COFFTargetObjectFile>();
198
199  return std::make_unique<AArch64_ELFTargetObjectFile>();
200}
201
202// Helper function to build a DataLayout string
203static std::string computeDataLayout(const Triple &TT,
204                                     const MCTargetOptions &Options,
205                                     bool LittleEndian) {
206  if (Options.getABIName() == "ilp32")
207    return "e-m:e-p:32:32-i8:8-i16:16-i64:64-S128";
208  if (TT.isOSBinFormatMachO()) {
209    if (TT.getArch() == Triple::aarch64_32)
210      return "e-m:o-p:32:32-i64:64-i128:128-n32:64-S128";
211    return "e-m:o-i64:64-i128:128-n32:64-S128";
212  }
213  if (TT.isOSBinFormatCOFF())
214    return "e-m:w-p:64:64-i32:32-i64:64-i128:128-n32:64-S128";
215  if (LittleEndian)
216    return "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128";
217  return "E-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128";
218}
219
220static Reloc::Model getEffectiveRelocModel(const Triple &TT,
221                                           Optional<Reloc::Model> RM) {
222  // AArch64 Darwin and Windows are always PIC.
223  if (TT.isOSDarwin() || TT.isOSWindows())
224    return Reloc::PIC_;
225  // On ELF platforms the default static relocation model has a smart enough
226  // linker to cope with referencing external symbols defined in a shared
227  // library. Hence DynamicNoPIC doesn't need to be promoted to PIC.
228  if (!RM.hasValue() || *RM == Reloc::DynamicNoPIC)
229    return Reloc::Static;
230  return *RM;
231}
232
233static CodeModel::Model
234getEffectiveAArch64CodeModel(const Triple &TT, Optional<CodeModel::Model> CM,
235                             bool JIT) {
236  if (CM) {
237    if (*CM != CodeModel::Small && *CM != CodeModel::Tiny &&
238        *CM != CodeModel::Large) {
239      if (!TT.isOSFuchsia())
240        report_fatal_error(
241            "Only small, tiny and large code models are allowed on AArch64");
242      else if (*CM != CodeModel::Kernel)
243        report_fatal_error("Only small, tiny, kernel, and large code models "
244                           "are allowed on AArch64");
245    } else if (*CM == CodeModel::Tiny && !TT.isOSBinFormatELF())
246      report_fatal_error("tiny code model is only supported on ELF");
247    return *CM;
248  }
249  // The default MCJIT memory managers make no guarantees about where they can
250  // find an executable page; JITed code needs to be able to refer to globals
251  // no matter how far away they are.
252  // We should set the CodeModel::Small for Windows ARM64 in JIT mode,
253  // since with large code model LLVM generating 4 MOV instructions, and
254  // Windows doesn't support relocating these long branch (4 MOVs).
255  if (JIT && !TT.isOSWindows())
256    return CodeModel::Large;
257  return CodeModel::Small;
258}
259
260/// Create an AArch64 architecture model.
261///
262AArch64TargetMachine::AArch64TargetMachine(const Target &T, const Triple &TT,
263                                           StringRef CPU, StringRef FS,
264                                           const TargetOptions &Options,
265                                           Optional<Reloc::Model> RM,
266                                           Optional<CodeModel::Model> CM,
267                                           CodeGenOpt::Level OL, bool JIT,
268                                           bool LittleEndian)
269    : LLVMTargetMachine(T,
270                        computeDataLayout(TT, Options.MCOptions, LittleEndian),
271                        TT, CPU, FS, Options, getEffectiveRelocModel(TT, RM),
272                        getEffectiveAArch64CodeModel(TT, CM, JIT), OL),
273      TLOF(createTLOF(getTargetTriple())), isLittle(LittleEndian) {
274  initAsmInfo();
275
276  if (TT.isOSBinFormatMachO()) {
277    this->Options.TrapUnreachable = true;
278    this->Options.NoTrapAfterNoreturn = true;
279  }
280
281  if (getMCAsmInfo()->usesWindowsCFI()) {
282    // Unwinding can get confused if the last instruction in an
283    // exception-handling region (function, funclet, try block, etc.)
284    // is a call.
285    //
286    // FIXME: We could elide the trap if the next instruction would be in
287    // the same region anyway.
288    this->Options.TrapUnreachable = true;
289  }
290
291  if (this->Options.TLSSize == 0) // default
292    this->Options.TLSSize = 24;
293  if ((getCodeModel() == CodeModel::Small ||
294       getCodeModel() == CodeModel::Kernel) &&
295      this->Options.TLSSize > 32)
296    // for the small (and kernel) code model, the maximum TLS size is 4GiB
297    this->Options.TLSSize = 32;
298  else if (getCodeModel() == CodeModel::Tiny && this->Options.TLSSize > 24)
299    // for the tiny code model, the maximum TLS size is 1MiB (< 16MiB)
300    this->Options.TLSSize = 24;
301
302  // Enable GlobalISel at or below EnableGlobalISelAt0, unless this is
303  // MachO/CodeModel::Large, which GlobalISel does not support.
304  if (getOptLevel() <= EnableGlobalISelAtO &&
305      TT.getArch() != Triple::aarch64_32 &&
306      !(getCodeModel() == CodeModel::Large && TT.isOSBinFormatMachO())) {
307    setGlobalISel(true);
308    setGlobalISelAbort(GlobalISelAbortMode::Disable);
309  }
310
311  // AArch64 supports the MachineOutliner.
312  setMachineOutliner(true);
313
314  // AArch64 supports default outlining behaviour.
315  setSupportsDefaultOutlining(true);
316}
317
318AArch64TargetMachine::~AArch64TargetMachine() = default;
319
320const AArch64Subtarget *
321AArch64TargetMachine::getSubtargetImpl(const Function &F) const {
322  Attribute CPUAttr = F.getFnAttribute("target-cpu");
323  Attribute FSAttr = F.getFnAttribute("target-features");
324
325  std::string CPU = !CPUAttr.hasAttribute(Attribute::None)
326                        ? CPUAttr.getValueAsString().str()
327                        : TargetCPU;
328  std::string FS = !FSAttr.hasAttribute(Attribute::None)
329                       ? FSAttr.getValueAsString().str()
330                       : TargetFS;
331
332  auto &I = SubtargetMap[CPU + FS];
333  if (!I) {
334    // This needs to be done before we create a new subtarget since any
335    // creation will depend on the TM and the code generation flags on the
336    // function that reside in TargetOptions.
337    resetTargetOptions(F);
338    I = std::make_unique<AArch64Subtarget>(TargetTriple, CPU, FS, *this,
339                                            isLittle);
340  }
341  return I.get();
342}
343
344void AArch64leTargetMachine::anchor() { }
345
346AArch64leTargetMachine::AArch64leTargetMachine(
347    const Target &T, const Triple &TT, StringRef CPU, StringRef FS,
348    const TargetOptions &Options, Optional<Reloc::Model> RM,
349    Optional<CodeModel::Model> CM, CodeGenOpt::Level OL, bool JIT)
350    : AArch64TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, JIT, true) {}
351
352void AArch64beTargetMachine::anchor() { }
353
354AArch64beTargetMachine::AArch64beTargetMachine(
355    const Target &T, const Triple &TT, StringRef CPU, StringRef FS,
356    const TargetOptions &Options, Optional<Reloc::Model> RM,
357    Optional<CodeModel::Model> CM, CodeGenOpt::Level OL, bool JIT)
358    : AArch64TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, JIT, false) {}
359
360namespace {
361
362/// AArch64 Code Generator Pass Configuration Options.
363class AArch64PassConfig : public TargetPassConfig {
364public:
365  AArch64PassConfig(AArch64TargetMachine &TM, PassManagerBase &PM)
366      : TargetPassConfig(TM, PM) {
367    if (TM.getOptLevel() != CodeGenOpt::None)
368      substitutePass(&PostRASchedulerID, &PostMachineSchedulerID);
369  }
370
371  AArch64TargetMachine &getAArch64TargetMachine() const {
372    return getTM<AArch64TargetMachine>();
373  }
374
375  ScheduleDAGInstrs *
376  createMachineScheduler(MachineSchedContext *C) const override {
377    const AArch64Subtarget &ST = C->MF->getSubtarget<AArch64Subtarget>();
378    ScheduleDAGMILive *DAG = createGenericSchedLive(C);
379    DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
380    DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
381    if (ST.hasFusion())
382      DAG->addMutation(createAArch64MacroFusionDAGMutation());
383    return DAG;
384  }
385
386  ScheduleDAGInstrs *
387  createPostMachineScheduler(MachineSchedContext *C) const override {
388    const AArch64Subtarget &ST = C->MF->getSubtarget<AArch64Subtarget>();
389    if (ST.hasFusion()) {
390      // Run the Macro Fusion after RA again since literals are expanded from
391      // pseudos then (v. addPreSched2()).
392      ScheduleDAGMI *DAG = createGenericSchedPostRA(C);
393      DAG->addMutation(createAArch64MacroFusionDAGMutation());
394      return DAG;
395    }
396
397    return nullptr;
398  }
399
400  void addIRPasses()  override;
401  bool addPreISel() override;
402  bool addInstSelector() override;
403  bool addIRTranslator() override;
404  void addPreLegalizeMachineIR() override;
405  bool addLegalizeMachineIR() override;
406  bool addRegBankSelect() override;
407  void addPreGlobalInstructionSelect() override;
408  bool addGlobalInstructionSelect() override;
409  bool addILPOpts() override;
410  void addPreRegAlloc() override;
411  void addPostRegAlloc() override;
412  void addPreSched2() override;
413  void addPreEmitPass() override;
414
415  std::unique_ptr<CSEConfigBase> getCSEConfig() const override;
416};
417
418} // end anonymous namespace
419
420TargetTransformInfo
421AArch64TargetMachine::getTargetTransformInfo(const Function &F) {
422  return TargetTransformInfo(AArch64TTIImpl(this, F));
423}
424
425TargetPassConfig *AArch64TargetMachine::createPassConfig(PassManagerBase &PM) {
426  return new AArch64PassConfig(*this, PM);
427}
428
429std::unique_ptr<CSEConfigBase> AArch64PassConfig::getCSEConfig() const {
430  return getStandardCSEConfigForOpt(TM->getOptLevel());
431}
432
433void AArch64PassConfig::addIRPasses() {
434  // Always expand atomic operations, we don't deal with atomicrmw or cmpxchg
435  // ourselves.
436  addPass(createAtomicExpandPass());
437
438  // Cmpxchg instructions are often used with a subsequent comparison to
439  // determine whether it succeeded. We can exploit existing control-flow in
440  // ldrex/strex loops to simplify this, but it needs tidying up.
441  if (TM->getOptLevel() != CodeGenOpt::None && EnableAtomicTidy)
442    addPass(createCFGSimplificationPass(1, true, true, false, true));
443
444  // Run LoopDataPrefetch
445  //
446  // Run this before LSR to remove the multiplies involved in computing the
447  // pointer values N iterations ahead.
448  if (TM->getOptLevel() != CodeGenOpt::None) {
449    if (EnableLoopDataPrefetch)
450      addPass(createLoopDataPrefetchPass());
451    if (EnableFalkorHWPFFix)
452      addPass(createFalkorMarkStridedAccessesPass());
453  }
454
455  TargetPassConfig::addIRPasses();
456
457  // Match interleaved memory accesses to ldN/stN intrinsics.
458  if (TM->getOptLevel() != CodeGenOpt::None) {
459    addPass(createInterleavedLoadCombinePass());
460    addPass(createInterleavedAccessPass());
461  }
462
463  if (TM->getOptLevel() == CodeGenOpt::Aggressive && EnableGEPOpt) {
464    // Call SeparateConstOffsetFromGEP pass to extract constants within indices
465    // and lower a GEP with multiple indices to either arithmetic operations or
466    // multiple GEPs with single index.
467    addPass(createSeparateConstOffsetFromGEPPass(true));
468    // Call EarlyCSE pass to find and remove subexpressions in the lowered
469    // result.
470    addPass(createEarlyCSEPass());
471    // Do loop invariant code motion in case part of the lowered result is
472    // invariant.
473    addPass(createLICMPass());
474  }
475
476  addPass(createAArch64StackTaggingPass(/* MergeInit = */ TM->getOptLevel() !=
477                                        CodeGenOpt::None));
478
479  // Add Control Flow Guard checks.
480  if (TM->getTargetTriple().isOSWindows())
481    addPass(createCFGuardCheckPass());
482}
483
484// Pass Pipeline Configuration
485bool AArch64PassConfig::addPreISel() {
486  // Run promote constant before global merge, so that the promoted constants
487  // get a chance to be merged
488  if (TM->getOptLevel() != CodeGenOpt::None && EnablePromoteConstant)
489    addPass(createAArch64PromoteConstantPass());
490  // FIXME: On AArch64, this depends on the type.
491  // Basically, the addressable offsets are up to 4095 * Ty.getSizeInBytes().
492  // and the offset has to be a multiple of the related size in bytes.
493  if ((TM->getOptLevel() != CodeGenOpt::None &&
494       EnableGlobalMerge == cl::BOU_UNSET) ||
495      EnableGlobalMerge == cl::BOU_TRUE) {
496    bool OnlyOptimizeForSize = (TM->getOptLevel() < CodeGenOpt::Aggressive) &&
497                               (EnableGlobalMerge == cl::BOU_UNSET);
498
499    // Merging of extern globals is enabled by default on non-Mach-O as we
500    // expect it to be generally either beneficial or harmless. On Mach-O it
501    // is disabled as we emit the .subsections_via_symbols directive which
502    // means that merging extern globals is not safe.
503    bool MergeExternalByDefault = !TM->getTargetTriple().isOSBinFormatMachO();
504
505    // FIXME: extern global merging is only enabled when we optimise for size
506    // because there are some regressions with it also enabled for performance.
507    if (!OnlyOptimizeForSize)
508      MergeExternalByDefault = false;
509
510    addPass(createGlobalMergePass(TM, 4095, OnlyOptimizeForSize,
511                                  MergeExternalByDefault));
512  }
513
514  return false;
515}
516
517bool AArch64PassConfig::addInstSelector() {
518  addPass(createAArch64ISelDag(getAArch64TargetMachine(), getOptLevel()));
519
520  // For ELF, cleanup any local-dynamic TLS accesses (i.e. combine as many
521  // references to _TLS_MODULE_BASE_ as possible.
522  if (TM->getTargetTriple().isOSBinFormatELF() &&
523      getOptLevel() != CodeGenOpt::None)
524    addPass(createAArch64CleanupLocalDynamicTLSPass());
525
526  return false;
527}
528
529bool AArch64PassConfig::addIRTranslator() {
530  addPass(new IRTranslator());
531  return false;
532}
533
534void AArch64PassConfig::addPreLegalizeMachineIR() {
535  bool IsOptNone = getOptLevel() == CodeGenOpt::None;
536  addPass(createAArch64PreLegalizeCombiner(IsOptNone));
537}
538
539bool AArch64PassConfig::addLegalizeMachineIR() {
540  addPass(new Legalizer());
541  return false;
542}
543
544bool AArch64PassConfig::addRegBankSelect() {
545  addPass(new RegBankSelect());
546  return false;
547}
548
549void AArch64PassConfig::addPreGlobalInstructionSelect() {
550  addPass(new Localizer());
551}
552
553bool AArch64PassConfig::addGlobalInstructionSelect() {
554  addPass(new InstructionSelect());
555  return false;
556}
557
558bool AArch64PassConfig::addILPOpts() {
559  if (EnableCondOpt)
560    addPass(createAArch64ConditionOptimizerPass());
561  if (EnableCCMP)
562    addPass(createAArch64ConditionalCompares());
563  if (EnableMCR)
564    addPass(&MachineCombinerID);
565  if (EnableCondBrTuning)
566    addPass(createAArch64CondBrTuning());
567  if (EnableEarlyIfConversion)
568    addPass(&EarlyIfConverterID);
569  if (EnableStPairSuppress)
570    addPass(createAArch64StorePairSuppressPass());
571  addPass(createAArch64SIMDInstrOptPass());
572  if (TM->getOptLevel() != CodeGenOpt::None)
573    addPass(createAArch64StackTaggingPreRAPass());
574  return true;
575}
576
577void AArch64PassConfig::addPreRegAlloc() {
578  // Change dead register definitions to refer to the zero register.
579  if (TM->getOptLevel() != CodeGenOpt::None && EnableDeadRegisterElimination)
580    addPass(createAArch64DeadRegisterDefinitions());
581
582  // Use AdvSIMD scalar instructions whenever profitable.
583  if (TM->getOptLevel() != CodeGenOpt::None && EnableAdvSIMDScalar) {
584    addPass(createAArch64AdvSIMDScalar());
585    // The AdvSIMD pass may produce copies that can be rewritten to
586    // be register coalescer friendly.
587    addPass(&PeepholeOptimizerID);
588  }
589}
590
591void AArch64PassConfig::addPostRegAlloc() {
592  // Remove redundant copy instructions.
593  if (TM->getOptLevel() != CodeGenOpt::None && EnableRedundantCopyElimination)
594    addPass(createAArch64RedundantCopyEliminationPass());
595
596  if (TM->getOptLevel() != CodeGenOpt::None && usingDefaultRegAlloc())
597    // Improve performance for some FP/SIMD code for A57.
598    addPass(createAArch64A57FPLoadBalancing());
599}
600
601void AArch64PassConfig::addPreSched2() {
602  // Expand some pseudo instructions to allow proper scheduling.
603  addPass(createAArch64ExpandPseudoPass());
604  // Use load/store pair instructions when possible.
605  if (TM->getOptLevel() != CodeGenOpt::None) {
606    if (EnableLoadStoreOpt)
607      addPass(createAArch64LoadStoreOptimizationPass());
608  }
609
610  // The AArch64SpeculationHardeningPass destroys dominator tree and natural
611  // loop info, which is needed for the FalkorHWPFFixPass and also later on.
612  // Therefore, run the AArch64SpeculationHardeningPass before the
613  // FalkorHWPFFixPass to avoid recomputing dominator tree and natural loop
614  // info.
615  addPass(createAArch64SpeculationHardeningPass());
616
617  if (TM->getOptLevel() != CodeGenOpt::None) {
618    if (EnableFalkorHWPFFix)
619      addPass(createFalkorHWPFFixPass());
620  }
621}
622
623void AArch64PassConfig::addPreEmitPass() {
624  // Machine Block Placement might have created new opportunities when run
625  // at O3, where the Tail Duplication Threshold is set to 4 instructions.
626  // Run the load/store optimizer once more.
627  if (TM->getOptLevel() >= CodeGenOpt::Aggressive && EnableLoadStoreOpt)
628    addPass(createAArch64LoadStoreOptimizationPass());
629
630  if (EnableA53Fix835769)
631    addPass(createAArch64A53Fix835769());
632
633  if (EnableBranchTargets)
634    addPass(createAArch64BranchTargetsPass());
635
636  // Relax conditional branch instructions if they're otherwise out of
637  // range of their destination.
638  if (BranchRelaxation)
639    addPass(&BranchRelaxationPassID);
640
641  // Identify valid longjmp targets for Windows Control Flow Guard.
642  if (TM->getTargetTriple().isOSWindows())
643    addPass(createCFGuardLongjmpPass());
644
645  if (TM->getOptLevel() != CodeGenOpt::None && EnableCompressJumpTables)
646    addPass(createAArch64CompressJumpTablesPass());
647
648  if (TM->getOptLevel() != CodeGenOpt::None && EnableCollectLOH &&
649      TM->getTargetTriple().isOSBinFormatMachO())
650    addPass(createAArch64CollectLOHPass());
651}
652