AArch64SchedExynosM5.td revision 363496
1//=- AArch64SchedExynosM5.td - Samsung Exynos M5 Sched Defs --*- tablegen -*-=// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file defines the machine model for the Samsung Exynos M5 to support 10// instruction scheduling and other instruction cost heuristics. 11// 12//===----------------------------------------------------------------------===// 13 14//===----------------------------------------------------------------------===// 15// The Exynos-M5 is an advanced superscalar microprocessor with a 6-wide 16// in-order stage for decode and dispatch and a wider issue stage. 17// The execution units and loads and stores are out-of-order. 18 19def ExynosM5Model : SchedMachineModel { 20 let IssueWidth = 6; // Up to 6 uops per cycle. 21 let MicroOpBufferSize = 228; // ROB size. 22 let LoopMicroOpBufferSize = 60; // Based on the instruction queue size. 23 let LoadLatency = 4; // Optimistic load cases. 24 let MispredictPenalty = 15; // Minimum branch misprediction penalty. 25 let CompleteModel = 1; // Use the default model otherwise. 26 27 list<Predicate> UnsupportedFeatures = !listconcat(SVEUnsupported.F, 28 PAUnsupported.F); 29} 30 31//===----------------------------------------------------------------------===// 32// Define each kind of processor resource and number available on the Exynos-M5. 33 34let SchedModel = ExynosM5Model in { 35 36def M5UnitA : ProcResource<2>; // Simple integer 37def M5UnitC : ProcResource<2>; // Simple and complex integer 38let Super = M5UnitC, BufferSize = 1 in 39def M5UnitD : ProcResource<1>; // Integer division (inside C0, serialized) 40def M5UnitE : ProcResource<2>; // Simple 32-bit integer 41let Super = M5UnitC in 42def M5UnitF : ProcResource<2>; // CRC (inside C) 43def M5UnitB : ProcResource<1>; // Branch 44def M5UnitL0 : ProcResource<1>; // Load 45def M5UnitS0 : ProcResource<1>; // Store 46def M5PipeLS : ProcResource<1>; // Load/Store 47let Super = M5PipeLS in { 48 def M5UnitL1 : ProcResource<1>; 49 def M5UnitS1 : ProcResource<1>; 50} 51def M5PipeF0 : ProcResource<1>; // FP #0 52let Super = M5PipeF0 in { 53 def M5UnitFMAC0 : ProcResource<1>; // FP multiplication 54 def M5UnitFADD0 : ProcResource<1>; // Simple FP 55 def M5UnitNALU0 : ProcResource<1>; // Simple vector 56 def M5UnitNDOT0 : ProcResource<1>; // Dot product vector 57 def M5UnitNHAD : ProcResource<1>; // Horizontal vector 58 def M5UnitNMSC : ProcResource<1>; // FP and vector miscellanea 59 def M5UnitNMUL0 : ProcResource<1>; // Vector multiplication 60 def M5UnitNSHT0 : ProcResource<1>; // Vector shifting 61 def M5UnitNSHF0 : ProcResource<1>; // Vector shuffling 62 def M5UnitNCRY0 : ProcResource<1>; // Cryptographic 63} 64def M5PipeF1 : ProcResource<1>; // FP #1 65let Super = M5PipeF1 in { 66 def M5UnitFMAC1 : ProcResource<1>; // FP multiplication 67 def M5UnitFADD1 : ProcResource<1>; // Simple FP 68 def M5UnitFCVT0 : ProcResource<1>; // FP conversion 69 def M5UnitFDIV0 : ProcResource<2>; // FP division (serialized) 70 def M5UnitFSQR0 : ProcResource<2>; // FP square root (serialized) 71 def M5UnitFST0 : ProcResource<1>; // FP store 72 def M5UnitNALU1 : ProcResource<1>; // Simple vector 73 def M5UnitNDOT1 : ProcResource<1>; // Dot product vector 74 def M5UnitNSHT1 : ProcResource<1>; // Vector shifting 75 def M5UnitNSHF1 : ProcResource<1>; // Vector shuffling 76} 77def M5PipeF2 : ProcResource<1>; // FP #2 78let Super = M5PipeF2 in { 79 def M5UnitFMAC2 : ProcResource<1>; // FP multiplication 80 def M5UnitFADD2 : ProcResource<1>; // Simple FP 81 def M5UnitFCVT1 : ProcResource<1>; // FP conversion 82 def M5UnitFDIV1 : ProcResource<2>; // FP division (serialized) 83 def M5UnitFSQR1 : ProcResource<2>; // FP square root (serialized) 84 def M5UnitFST1 : ProcResource<1>; // FP store 85 def M5UnitNALU2 : ProcResource<1>; // Simple vector 86 def M5UnitNDOT2 : ProcResource<1>; // Dot product vector 87 def M5UnitNMUL1 : ProcResource<1>; // Vector multiplication 88 def M5UnitNSHT2 : ProcResource<1>; // Vector shifting 89 def M5UnitNCRY1 : ProcResource<1>; // Cryptographic 90} 91 92def M5UnitAX : ProcResGroup<[M5UnitA, 93 M5UnitC]>; 94def M5UnitAW : ProcResGroup<[M5UnitA, 95 M5UnitC, 96 M5UnitE]>; 97def M5UnitL : ProcResGroup<[M5UnitL0, 98 M5UnitL1]>; 99def M5UnitS : ProcResGroup<[M5UnitS0, 100 M5UnitS1]>; 101def M5UnitFMAC : ProcResGroup<[M5UnitFMAC0, 102 M5UnitFMAC1, 103 M5UnitFMAC2]>; 104def M5UnitFADD : ProcResGroup<[M5UnitFADD0, 105 M5UnitFADD1, 106 M5UnitFADD2]>; 107def M5UnitFCVT : ProcResGroup<[M5UnitFCVT0, 108 M5UnitFCVT1]>; 109def M5UnitFDIV : ProcResGroup<[M5UnitFDIV0, 110 M5UnitFDIV1]>; 111def M5UnitFSQR : ProcResGroup<[M5UnitFSQR0, 112 M5UnitFSQR1]>; 113def M5UnitFST : ProcResGroup<[M5UnitFST0, 114 M5UnitFST1]>; 115def M5UnitNALU : ProcResGroup<[M5UnitNALU0, 116 M5UnitNALU1, 117 M5UnitNALU2]>; 118def M5UnitNDOT : ProcResGroup<[M5UnitNDOT0, 119 M5UnitNDOT1, 120 M5UnitNDOT2]>; 121def M5UnitNMUL : ProcResGroup<[M5UnitNMUL0, 122 M5UnitNMUL1]>; 123def M5UnitNSHT : ProcResGroup<[M5UnitNSHT0, 124 M5UnitNSHT1, 125 M5UnitNSHT2]>; 126def M5UnitNSHF : ProcResGroup<[M5UnitNSHF0, 127 M5UnitNSHF1]>; 128def M5UnitNCRY : ProcResGroup<[M5UnitNCRY0, 129 M5UnitNCRY1]>; 130 131//===----------------------------------------------------------------------===// 132// Resources details. 133 134def M5WriteZ0 : SchedWriteRes<[]> { let Latency = 0; } 135def M5WriteZ1 : SchedWriteRes<[]> { let Latency = 1; 136 let NumMicroOps = 0; } 137def M5WriteZ4 : SchedWriteRes<[]> { let Latency = 4; 138 let NumMicroOps = 0; } 139 140def M5WriteA1W : SchedWriteRes<[M5UnitAW]> { let Latency = 1; } 141def M5WriteA1X : SchedWriteRes<[M5UnitAX]> { let Latency = 1; } 142def M5WriteAAW : SchedWriteRes<[M5UnitAW]> { let Latency = 2; 143 let ResourceCycles = [2]; } 144def M5WriteAAX : SchedWriteRes<[M5UnitAX]> { let Latency = 2; 145 let ResourceCycles = [2]; } 146def M5WriteAB : SchedWriteRes<[M5UnitAX, 147 M5UnitC, 148 M5UnitE]> { let Latency = 2; 149 let NumMicroOps = 2; } 150def M5WriteAC : SchedWriteRes<[M5UnitAX, 151 M5UnitAX, 152 M5UnitC]> { let Latency = 3; 153 let NumMicroOps = 3; } 154def M5WriteAD : SchedWriteRes<[M5UnitAW, 155 M5UnitC]> { let Latency = 2; 156 let NumMicroOps = 2; } 157def M5WriteAFW : SchedWriteRes<[M5UnitAW]> { let Latency = 2; 158 let NumMicroOps = 2; } 159def M5WriteAFX : SchedWriteRes<[M5UnitAX]> { let Latency = 2; 160 let NumMicroOps = 2; } 161def M5WriteAUW : SchedWriteVariant<[SchedVar<IsCopyIdiomPred, [M5WriteZ0]>, 162 SchedVar<ExynosArithPred, [M5WriteA1W]>, 163 SchedVar<ExynosLogicExPred, [M5WriteA1W]>, 164 SchedVar<NoSchedPred, [M5WriteAAW]>]>; 165def M5WriteAUX : SchedWriteVariant<[SchedVar<IsCopyIdiomPred, [M5WriteZ0]>, 166 SchedVar<ExynosArithPred, [M5WriteA1X]>, 167 SchedVar<ExynosLogicExPred, [M5WriteA1X]>, 168 SchedVar<NoSchedPred, [M5WriteAAX]>]>; 169def M5WriteAVW : SchedWriteVariant<[SchedVar<ExynosResetPred, [M5WriteZ0]>, 170 SchedVar<ExynosArithPred, [M5WriteA1W]>, 171 SchedVar<ExynosLogicExPred, [M5WriteA1W]>, 172 SchedVar<NoSchedPred, [M5WriteAAW]>]>; 173def M5WriteAVX : SchedWriteVariant<[SchedVar<ExynosResetPred, [M5WriteZ0]>, 174 SchedVar<ExynosArithPred, [M5WriteA1X]>, 175 SchedVar<ExynosLogicExPred, [M5WriteA1X]>, 176 SchedVar<NoSchedPred, [M5WriteAAX]>]>; 177def M5WriteAXW : SchedWriteVariant<[SchedVar<ExynosArithPred, [M5WriteA1W]>, 178 SchedVar<ExynosLogicExPred, [M5WriteA1W]>, 179 SchedVar<NoSchedPred, [M5WriteAAW]>]>; 180def M5WriteAXX : SchedWriteVariant<[SchedVar<ExynosArithPred, [M5WriteA1X]>, 181 SchedVar<ExynosLogicExPred, [M5WriteA1X]>, 182 SchedVar<NoSchedPred, [M5WriteAAX]>]>; 183def M5WriteAYW : SchedWriteVariant<[SchedVar<ExynosRotateRightImmPred, [M5WriteA1W]>, 184 SchedVar<NoSchedPred, [M5WriteAFW]>]>; 185def M5WriteAYX : SchedWriteVariant<[SchedVar<ExynosRotateRightImmPred, [M5WriteA1X]>, 186 SchedVar<NoSchedPred, [M5WriteAFX]>]>; 187 188def M5WriteB1 : SchedWriteRes<[M5UnitB]> { let Latency = 1; } 189def M5WriteBX : SchedWriteVariant<[SchedVar<ExynosBranchLinkLRPred, [M5WriteAC]>, 190 SchedVar<NoSchedPred, [M5WriteAB]>]>; 191 192def M5WriteC1 : SchedWriteRes<[M5UnitC]> { let Latency = 1; } 193def M5WriteC2 : SchedWriteRes<[M5UnitC]> { let Latency = 2; } 194def M5WriteCA : SchedWriteRes<[M5UnitC]> { let Latency = 3; 195 let ResourceCycles = [2]; } 196 197def M5WriteD10 : SchedWriteRes<[M5UnitD]> { let Latency = 10; 198 let ResourceCycles = [10]; } 199def M5WriteD16 : SchedWriteRes<[M5UnitD]> { let Latency = 16; 200 let ResourceCycles = [16]; } 201 202def M5WriteF2 : SchedWriteRes<[M5UnitF]> { let Latency = 2; } 203 204def M5WriteL4 : SchedWriteRes<[M5UnitL]> { let Latency = 4; } 205def M5WriteL5 : SchedWriteRes<[M5UnitL]> { let Latency = 5; } 206def M5WriteL6 : SchedWriteRes<[M5UnitL]> { let Latency = 6; } 207def M5WriteLA : SchedWriteRes<[M5UnitL, 208 M5UnitL]> { let Latency = 6; 209 let NumMicroOps = 1; } 210def M5WriteLB : SchedWriteRes<[M5UnitAX, 211 M5UnitL]> { let Latency = 6; 212 let NumMicroOps = 2; } 213def M5WriteLC : SchedWriteRes<[M5UnitAX, 214 M5UnitL, 215 M5UnitL]> { let Latency = 6; 216 let NumMicroOps = 2; } 217def M5WriteLD : SchedWriteRes<[M5UnitAX, 218 M5UnitL]> { let Latency = 4; 219 let NumMicroOps = 2; } 220def M5WriteLE : SchedWriteRes<[M5UnitAX, 221 M5UnitL]> { let Latency = 7; 222 let NumMicroOps = 2; } 223def M5WriteLFW : SchedWriteRes<[M5UnitAW, 224 M5UnitAW, 225 M5UnitAW, 226 M5UnitAW, 227 M5UnitL]> { let Latency = 15; 228 let NumMicroOps = 6; 229 let ResourceCycles = [1, 1, 1, 1, 15]; } 230def M5WriteLFX : SchedWriteRes<[M5UnitAX, 231 M5UnitAX, 232 M5UnitAX, 233 M5UnitAX, 234 M5UnitL]> { let Latency = 15; 235 let NumMicroOps = 6; 236 let ResourceCycles = [1, 1, 1, 1, 15]; } 237def M5WriteLGW : SchedWriteRes<[M5UnitAW, 238 M5UnitL]> { let Latency = 13; 239 let NumMicroOps = 1; 240 let ResourceCycles = [1, 13]; } 241def M5WriteLGX : SchedWriteRes<[M5UnitAX, 242 M5UnitL]> { let Latency = 13; 243 let NumMicroOps = 1; 244 let ResourceCycles = [1, 13]; } 245def M5WriteLH : SchedWriteRes<[]> { let Latency = 6; 246 let NumMicroOps = 0; } 247def M5WriteLX : SchedWriteVariant<[SchedVar<ExynosScaledIdxPred, [M5WriteL5]>, 248 SchedVar<NoSchedPred, [M5WriteL4]>]>; 249def M5WriteLY : SchedWriteVariant<[SchedVar<ExynosScaledIdxPred, [M5WriteLE]>, 250 SchedVar<NoSchedPred, [M5WriteL6]>]>; 251 252def M5WriteS1 : SchedWriteRes<[M5UnitS]> { let Latency = 1; } 253def M5WriteSA : SchedWriteRes<[M5UnitS0]> { let Latency = 4; } 254def M5WriteSB : SchedWriteRes<[M5UnitAX, 255 M5UnitS]> { let Latency = 2; 256 let NumMicroOps = 1; } 257def M5WriteSX : SchedWriteVariant<[SchedVar<ExynosScaledIdxPred, [M5WriteSB]>, 258 SchedVar<NoSchedPred, [M5WriteS1]>]>; 259 260def M5ReadAdrBase : SchedReadVariant<[SchedVar< 261 MCSchedPredicate< 262 CheckAny< 263 [ScaledIdxFn, 264 ExynosScaledIdxFn]>>, [ReadDefault]>, 265 SchedVar<NoSchedPred, [ReadDefault]>]>; 266 267def M5WriteNEONB : SchedWriteRes<[M5UnitNALU, 268 M5UnitS0]> { let Latency = 5; 269 let NumMicroOps = 2; } 270def M5WriteNEONH : SchedWriteRes<[M5UnitNALU, 271 M5UnitS0]> { let Latency = 2; 272 let NumMicroOps = 2; } 273def M5WriteNEONI : SchedWriteRes<[M5UnitS0, 274 M5UnitNSHF]> { let Latency = 6; 275 let NumMicroOps = 2; } 276def M5WriteNEONK : SchedWriteRes<[M5UnitNSHF, 277 M5UnitFCVT0, 278 M5UnitS0]> { let Latency = 5; 279 let NumMicroOps = 2; } 280def M5WriteNEONN : SchedWriteRes<[M5UnitNMSC, 281 M5UnitNMSC]> { let Latency = 5; 282 let NumMicroOps = 2; 283 let ResourceCycles = [7, 7]; } 284def M5WriteNEONO : SchedWriteRes<[M5UnitNMSC, 285 M5UnitNMSC, 286 M5UnitNMSC]> { let Latency = 8; 287 let NumMicroOps = 3; 288 let ResourceCycles = [10, 10, 10]; } 289def M5WriteNEONP : SchedWriteRes<[M5UnitNSHF, 290 M5UnitS0, 291 M5UnitFCVT]> { let Latency = 7; 292 let NumMicroOps = 2; } 293def M5WriteNEONQ : SchedWriteRes<[M5UnitNMSC, 294 M5UnitC]> { let Latency = 3; 295 let NumMicroOps = 1; } 296def M5WriteNEONU : SchedWriteRes<[M5UnitFSQR, 297 M5UnitFSQR]> { let Latency = 7; 298 let ResourceCycles = [4, 4]; } 299def M5WriteNEONV : SchedWriteRes<[M5UnitFDIV, 300 M5UnitFDIV]> { let Latency = 7; 301 let ResourceCycles = [6, 6]; } 302def M5WriteNEONW : SchedWriteRes<[M5UnitFDIV, 303 M5UnitFDIV]> { let Latency = 12; 304 let ResourceCycles = [9, 9]; } 305def M5WriteNEONX : SchedWriteRes<[M5UnitFSQR, 306 M5UnitFSQR]> { let Latency = 8; 307 let ResourceCycles = [5, 5]; } 308def M5WriteNEONY : SchedWriteRes<[M5UnitFSQR, 309 M5UnitFSQR]> { let Latency = 12; 310 let ResourceCycles = [9, 9]; } 311def M5WriteNEONZ : SchedWriteVariant<[SchedVar<ExynosQFormPred, [M5WriteNEONO]>, 312 SchedVar<NoSchedPred, [M5WriteNEONN]>]>; 313 314def M5WriteFADD2 : SchedWriteRes<[M5UnitFADD]> { let Latency = 2; } 315 316def M5WriteFCVT2 : SchedWriteRes<[M5UnitFCVT]> { let Latency = 2; } 317def M5WriteFCVT2A : SchedWriteRes<[M5UnitFCVT0]> { let Latency = 2; } 318def M5WriteFCVT3 : SchedWriteRes<[M5UnitFCVT]> { let Latency = 3; } 319def M5WriteFCVT3A : SchedWriteRes<[M5UnitFCVT0]> { let Latency = 3; } 320def M5WriteFCVTA : SchedWriteRes<[M5UnitFCVT0, 321 M5UnitS0]> { let Latency = 3; 322 let NumMicroOps = 1; } 323def M5WriteFCVTB : SchedWriteRes<[M5UnitFCVT, 324 M5UnitS0]> { let Latency = 4; 325 let NumMicroOps = 1; } 326def M5WriteFCVTC : SchedWriteRes<[M5UnitFCVT, 327 M5UnitS0]> { let Latency = 6; 328 let NumMicroOps = 1; } 329 330def M5WriteFDIV5 : SchedWriteRes<[M5UnitFDIV]> { let Latency = 5; 331 let ResourceCycles = [2]; } 332def M5WriteFDIV7 : SchedWriteRes<[M5UnitFDIV]> { let Latency = 7; 333 let ResourceCycles = [4]; } 334def M5WriteFDIV12 : SchedWriteRes<[M5UnitFDIV]> { let Latency = 12; 335 let ResourceCycles = [9]; } 336 337def M5WriteFMAC3 : SchedWriteRes<[M5UnitFMAC]> { let Latency = 3; } 338def M5WriteFMAC4 : SchedWriteRes<[M5UnitFMAC]> { let Latency = 4; } 339def M5WriteFMAC5 : SchedWriteRes<[M5UnitFMAC]> { let Latency = 5; } 340 341def M5WriteFSQR5 : SchedWriteRes<[M5UnitFSQR]> { let Latency = 5; 342 let ResourceCycles = [2]; } 343def M5WriteFSQR7 : SchedWriteRes<[M5UnitFSQR]> { let Latency = 7; 344 let ResourceCycles = [4]; } 345def M5WriteFSQR8 : SchedWriteRes<[M5UnitFSQR]> { let Latency = 8; 346 let ResourceCycles = [5]; } 347def M5WriteFSQR12 : SchedWriteRes<[M5UnitFSQR]> { let Latency = 12; 348 let ResourceCycles = [9]; } 349 350def M5WriteNALU1 : SchedWriteRes<[M5UnitNALU]> { let Latency = 1; } 351def M5WriteNALU2 : SchedWriteRes<[M5UnitNALU]> { let Latency = 2; } 352 353def M5WriteNDOT2 : SchedWriteRes<[M5UnitNDOT]> { let Latency = 2; } 354 355def M5WriteNCRY2 : SchedWriteRes<[M5UnitNCRY]> { let Latency = 2; } 356def M5WriteNCRY1A : SchedWriteRes<[M5UnitNCRY0]> { let Latency = 1; } 357def M5WriteNCRY2A : SchedWriteRes<[M5UnitNCRY0]> { let Latency = 2; } 358def M5WriteNCRY3A : SchedWriteRes<[M5UnitNCRY0]> { let Latency = 3; } 359def M5WriteNCRY5A : SchedWriteRes<[M5UnitNCRY]> { let Latency = 5; } 360 361def M5WriteNHAD1 : SchedWriteRes<[M5UnitNHAD]> { let Latency = 1; } 362def M5WriteNHAD3 : SchedWriteRes<[M5UnitNHAD]> { let Latency = 3; } 363 364def M5WriteNMSC1 : SchedWriteRes<[M5UnitNMSC]> { let Latency = 1; } 365def M5WriteNMSC2 : SchedWriteRes<[M5UnitNMSC]> { let Latency = 2; } 366 367def M5WriteNMUL3 : SchedWriteRes<[M5UnitNMUL]> { let Latency = 3; } 368 369def M5WriteNSHF1 : SchedWriteRes<[M5UnitNSHF]> { let Latency = 1; } 370def M5WriteNSHF2 : SchedWriteRes<[M5UnitNSHF]> { let Latency = 2; } 371def M5WriteNSHFA : SchedWriteRes<[M5UnitNSHF]> { let Latency = 2; } 372def M5WriteNSHFB : SchedWriteRes<[M5UnitNSHF]> { let Latency = 4; 373 let NumMicroOps = 2; } 374def M5WriteNSHFC : SchedWriteRes<[M5UnitNSHF]> { let Latency = 6; 375 let NumMicroOps = 3; } 376def M5WriteNSHFD : SchedWriteRes<[M5UnitNSHF]> { let Latency = 8; 377 let NumMicroOps = 4; } 378 379def M5WriteNSHT2 : SchedWriteRes<[M5UnitNSHT]> { let Latency = 2; } 380def M5WriteNSHT4A : SchedWriteRes<[M5UnitNSHT1]> { let Latency = 4; } 381 382def M5WriteVLDA : SchedWriteRes<[M5UnitL, 383 M5UnitL]> { let Latency = 6; 384 let NumMicroOps = 2; } 385def M5WriteVLDB : SchedWriteRes<[M5UnitL, 386 M5UnitL, 387 M5UnitL]> { let Latency = 7; 388 let NumMicroOps = 3; } 389def M5WriteVLDC : SchedWriteRes<[M5UnitL, 390 M5UnitL, 391 M5UnitL, 392 M5UnitL]> { let Latency = 7; 393 let NumMicroOps = 4; } 394def M5WriteVLDD : SchedWriteRes<[M5UnitL, 395 M5UnitNSHF]> { let Latency = 7; 396 let NumMicroOps = 2; 397 let ResourceCycles = [2, 1]; } 398def M5WriteVLDF : SchedWriteRes<[M5UnitL, 399 M5UnitL]> { let Latency = 11; 400 let NumMicroOps = 2; 401 let ResourceCycles = [6, 5]; } 402def M5WriteVLDG : SchedWriteRes<[M5UnitL, 403 M5UnitNSHF, 404 M5UnitNSHF]> { let Latency = 7; 405 let NumMicroOps = 3; 406 let ResourceCycles = [2, 1, 1]; } 407def M5WriteVLDI : SchedWriteRes<[M5UnitL, 408 M5UnitL, 409 M5UnitL]> { let Latency = 13; 410 let NumMicroOps = 3; } 411def M5WriteVLDJ : SchedWriteRes<[M5UnitL, 412 M5UnitNSHF, 413 M5UnitNSHF, 414 M5UnitNSHF]> { let Latency = 8; 415 let NumMicroOps = 4; } 416def M5WriteVLDK : SchedWriteRes<[M5UnitL, 417 M5UnitNSHF, 418 M5UnitNSHF, 419 M5UnitNSHF, 420 M5UnitNSHF]> { let Latency = 8; 421 let NumMicroOps = 5; } 422def M5WriteVLDL : SchedWriteRes<[M5UnitL, 423 M5UnitNSHF, 424 M5UnitNSHF, 425 M5UnitL, 426 M5UnitNSHF]> { let Latency = 8; 427 let NumMicroOps = 5; } 428def M5WriteVLDM : SchedWriteRes<[M5UnitL, 429 M5UnitNSHF, 430 M5UnitNSHF, 431 M5UnitL, 432 M5UnitNSHF, 433 M5UnitNSHF]> { let Latency = 8; 434 let NumMicroOps = 6; } 435def M5WriteVLDN : SchedWriteRes<[M5UnitL, 436 M5UnitL, 437 M5UnitL, 438 M5UnitL]> { let Latency = 15; 439 let NumMicroOps = 4; 440 let ResourceCycles = [2, 2, 2, 2]; } 441 442def M5WriteVST1 : SchedWriteRes<[M5UnitS, 443 M5UnitFST]> { let Latency = 1; 444 let NumMicroOps = 1; } 445def M5WriteVSTA : SchedWriteRes<[M5UnitS, 446 M5UnitFST, 447 M5UnitS, 448 M5UnitFST]> { let Latency = 2; 449 let NumMicroOps = 2; } 450def M5WriteVSTB : SchedWriteRes<[M5UnitS, 451 M5UnitFST, 452 M5UnitS, 453 M5UnitFST, 454 M5UnitS, 455 M5UnitFST]> { let Latency = 3; 456 let NumMicroOps = 3; } 457def M5WriteVSTC : SchedWriteRes<[M5UnitS, 458 M5UnitFST, 459 M5UnitS, 460 M5UnitFST, 461 M5UnitS, 462 M5UnitFST, 463 M5UnitS, 464 M5UnitFST]> { let Latency = 4; 465 let NumMicroOps = 4; } 466def M5WriteVSTD : SchedWriteRes<[M5UnitS, 467 M5UnitFST]> { let Latency = 2; } 468def M5WriteVSTE : SchedWriteRes<[M5UnitS, 469 M5UnitFST, 470 M5UnitS, 471 M5UnitFST]> { let Latency = 2; 472 let NumMicroOps = 1; } 473def M5WriteVSTF : SchedWriteRes<[M5UnitNSHF, 474 M5UnitNSHF, 475 M5UnitS, 476 M5UnitFST]> { let Latency = 4; 477 let NumMicroOps = 3; } 478def M5WriteVSTG : SchedWriteRes<[M5UnitNSHF, 479 M5UnitNSHF, 480 M5UnitNSHF, 481 M5UnitS, 482 M5UnitFST, 483 M5UnitS, 484 M5UnitFST]> { let Latency = 4; 485 let NumMicroOps = 5; } 486def M5WriteVSTH : SchedWriteRes<[M5UnitS0, 487 M5UnitFST]> { let Latency = 1; 488 let NumMicroOps = 1; } 489def M5WriteVSTI : SchedWriteRes<[M5UnitNSHF, 490 M5UnitNSHF, 491 M5UnitNSHF, 492 M5UnitNSHF, 493 M5UnitS, 494 M5UnitFST, 495 M5UnitS, 496 M5UnitFST, 497 M5UnitS, 498 M5UnitFST, 499 M5UnitS, 500 M5UnitFST]> { let Latency = 8; 501 let NumMicroOps = 5; 502 let ResourceCycles = [1, 1, 1, 1, 2, 1, 2, 1, 2, 1, 2, 1]; } 503def M5WriteVSTJ : SchedWriteRes<[M5UnitA, 504 M5UnitS0, 505 M5UnitFST]> { let Latency = 1; 506 let NumMicroOps = 1; } 507def M5WriteVSTK : SchedWriteRes<[M5UnitAX, 508 M5UnitS, 509 M5UnitFST]> { let Latency = 3; 510 let NumMicroOps = 2; } 511def M5WriteVSTL : SchedWriteRes<[M5UnitNSHF, 512 M5UnitNSHF, 513 M5UnitS, 514 M5UnitFST, 515 M5UnitS, 516 M5UnitFST]> { let Latency = 4; 517 let NumMicroOps = 4; 518 let ResourceCycles = [1, 1, 2, 1, 2, 1]; } 519def M5WriteVSTY : SchedWriteVariant<[SchedVar<ExynosScaledIdxPred, [M5WriteVSTK]>, 520 SchedVar<NoSchedPred, [WriteVST]>]>; 521 522// Special cases. 523def M5WriteCOPY : SchedWriteVariant<[SchedVar<ExynosFPPred, [M5WriteNALU2]>, 524 SchedVar<NoSchedPred, [M5WriteZ0]>]>; 525def M5WriteMOVI : SchedWriteVariant<[SchedVar<IsZeroFPIdiomPred, [M5WriteZ0]>, 526 SchedVar<NoSchedPred, [M5WriteNALU1]>]>; 527 528// Fast forwarding. 529def M5ReadFM1 : SchedReadAdvance<+1, [M5WriteF2]>; 530def M5ReadAESM2 : SchedReadAdvance<+2, [M5WriteNCRY2]>; 531def M5ReadFMACM1 : SchedReadAdvance<+1, [M5WriteFMAC4, 532 M5WriteFMAC5]>; 533def M5ReadNMULM1 : SchedReadAdvance<+1, [M5WriteNMUL3]>; 534 535//===----------------------------------------------------------------------===// 536// Coarse scheduling model. 537 538// Branch instructions. 539def : SchedAlias<WriteBr, M5WriteZ0>; 540def : SchedAlias<WriteBrReg, M5WriteC1>; 541 542// Arithmetic and logical integer instructions. 543def : SchedAlias<WriteI, M5WriteA1W>; 544def : SchedAlias<WriteIEReg, M5WriteA1W>; // FIXME: M5WriteAX crashes TableGen. 545def : SchedAlias<WriteISReg, M5WriteA1W>; // FIXME: M5WriteAX crashes TableGen. 546def : SchedAlias<WriteIS, M5WriteA1W>; 547 548// Move instructions. 549def : SchedAlias<WriteImm, M5WriteA1W>; 550 551// Divide and multiply instructions. 552def : SchedAlias<WriteID32, M5WriteD10>; 553def : SchedAlias<WriteID64, M5WriteD16>; 554def : SchedAlias<WriteIM32, M5WriteC2>; 555def : SchedAlias<WriteIM64, M5WriteCA>; 556 557// Miscellaneous instructions. 558def : SchedAlias<WriteExtr, M5WriteAYW>; 559 560// Addressing modes. 561def : SchedAlias<WriteAdr, M5WriteZ1>; 562def : SchedAlias<ReadAdrBase, M5ReadAdrBase>; 563 564// Load instructions. 565def : SchedAlias<WriteLD, M5WriteL4>; 566def : SchedAlias<WriteLDHi, M5WriteZ4>; 567def : SchedAlias<WriteLDIdx, M5WriteLX>; 568 569// Store instructions. 570def : SchedAlias<WriteST, M5WriteS1>; 571def : SchedAlias<WriteSTP, M5WriteS1>; 572def : SchedAlias<WriteSTX, M5WriteS1>; 573def : SchedAlias<WriteSTIdx, M5WriteSX>; 574 575// Atomic load and store instructions. 576def : SchedAlias<WriteAtomic, M5WriteLGW>; 577 578// FP data instructions. 579def : SchedAlias<WriteF, M5WriteFADD2>; 580def : SchedAlias<WriteFCmp, M5WriteNMSC2>; 581def : SchedAlias<WriteFDiv, M5WriteFDIV12>; 582def : SchedAlias<WriteFMul, M5WriteFMAC3>; 583 584// FP miscellaneous instructions. 585def : SchedAlias<WriteFCvt, M5WriteFCVT2>; 586def : SchedAlias<WriteFImm, M5WriteNALU1>; 587def : SchedAlias<WriteFCopy, M5WriteNALU2>; 588 589// FP load instructions. 590def : SchedAlias<WriteVLD, M5WriteL6>; 591 592// FP store instructions. 593def : SchedAlias<WriteVST, M5WriteVST1>; 594 595// ASIMD FP instructions. 596def : SchedAlias<WriteV, M5WriteNALU1>; 597 598// Other miscellaneous instructions. 599def : WriteRes<WriteBarrier, []> { let Latency = 1; } 600def : WriteRes<WriteHint, []> { let Latency = 1; } 601def : WriteRes<WriteSys, []> { let Latency = 1; } 602 603//===----------------------------------------------------------------------===// 604// Generic fast forwarding. 605 606// TODO: Add FP register forwarding rules. 607 608def : ReadAdvance<ReadI, 0>; 609def : ReadAdvance<ReadISReg, 0>; 610def : ReadAdvance<ReadIEReg, 0>; 611def : ReadAdvance<ReadIM, 0>; 612// TODO: The forwarding for 32 bits actually saves 2 cycles. 613def : ReadAdvance<ReadIMA, 3, [WriteIM32, WriteIM64]>; 614def : ReadAdvance<ReadID, 0>; 615def : ReadAdvance<ReadExtrHi, 0>; 616def : ReadAdvance<ReadAdrBase, 0>; 617def : ReadAdvance<ReadVLD, 0>; 618 619//===----------------------------------------------------------------------===// 620// Finer scheduling model. 621 622// Branch instructions 623def : InstRW<[M5WriteB1], (instrs Bcc)>; 624def : InstRW<[M5WriteAFX], (instrs BL)>; 625def : InstRW<[M5WriteBX], (instrs BLR)>; 626def : InstRW<[M5WriteC1], (instregex "^CBN?Z[WX]")>; 627def : InstRW<[M5WriteAD], (instregex "^TBN?ZW")>; 628def : InstRW<[M5WriteAB], (instregex "^TBN?ZX")>; 629 630// Arithmetic and logical integer instructions. 631def : InstRW<[M5WriteA1W], (instregex "^(ADC|SBC)S?Wr$")>; 632def : InstRW<[M5WriteA1X], (instregex "^(ADC|SBC)S?Xr$")>; 633def : InstRW<[M5WriteAXW], (instregex "^(ADD|AND|BIC|EON|EOR|ORN|SUB)Wrs$")>; 634def : InstRW<[M5WriteAXX], (instregex "^(ADD|AND|BIC|EON|EOR|ORN|SUB)Xrs$")>; 635def : InstRW<[M5WriteAUW], (instrs ORRWrs)>; 636def : InstRW<[M5WriteAUX], (instrs ORRXrs)>; 637def : InstRW<[M5WriteAXW], (instregex "^(ADD|AND|BIC|SUB)SWrs$")>; 638def : InstRW<[M5WriteAXX], (instregex "^(ADD|AND|BIC|SUB)SXrs$")>; 639def : InstRW<[M5WriteAXW], (instregex "^(ADD|SUB)S?Wrx(64)?$")>; 640def : InstRW<[M5WriteAXX], (instregex "^(ADD|SUB)S?Xrx(64)?$")>; 641def : InstRW<[M5WriteAVW], (instrs ADDWri, ORRWri)>; 642def : InstRW<[M5WriteAVX], (instrs ADDXri, ORRXri)>; 643def : InstRW<[M5WriteA1W], (instregex "^CCM[NP]W[ir]$")>; 644def : InstRW<[M5WriteA1X], (instregex "^CCM[NP]X[ir]$")>; 645def : InstRW<[M5WriteA1W], (instrs CSELWr, CSINCWr, CSINVWr, CSNEGWr)>; 646def : InstRW<[M5WriteA1X], (instrs CSELXr, CSINCXr, CSINVXr, CSNEGXr)>; 647 648// Move instructions. 649def : InstRW<[M5WriteCOPY], (instrs COPY)>; 650def : InstRW<[M5WriteZ0], (instrs ADR, ADRP)>; 651def : InstRW<[M5WriteZ0], (instregex "^MOV[NZ][WX]i$")>; 652 653// Shift instructions. 654def : InstRW<[M5WriteA1W], (instrs ASRVWr, LSLVWr, LSRVWr, RORVWr)>; 655def : InstRW<[M5WriteA1X], (instrs ASRVXr, LSLVXr, LSRVXr, RORVXr)>; 656 657// Miscellaneous instructions. 658def : InstRW<[M5WriteAYW], (instrs EXTRWrri)>; 659def : InstRW<[M5WriteAYX], (instrs EXTRXrri)>; 660def : InstRW<[M5WriteA1W], (instrs BFMWri, SBFMWri, UBFMWri)>; 661def : InstRW<[M5WriteA1X], (instrs BFMXri, SBFMXri, UBFMXri)>; 662def : InstRW<[M5WriteA1W], (instrs CLSWr, CLZWr)>; 663def : InstRW<[M5WriteA1X], (instrs CLSXr, CLZXr)>; 664def : InstRW<[M5WriteA1W], (instrs RBITWr, REVWr, REV16Wr)>; 665def : InstRW<[M5WriteA1X], (instrs RBITXr, REVXr, REV16Xr, REV32Xr)>; 666 667// Load instructions. 668def : InstRW<[M5WriteLD, 669 WriteLDHi, 670 WriteAdr], (instregex "^LDP(SW|W|X)(post|pre)")>; 671def : InstRW<[M5WriteL5, 672 ReadAdrBase], (instregex "^LDR(BB|SBW|SBX|HH|SHW|SHX|SW|W|X)roW")>; 673def : InstRW<[WriteLDIdx, 674 ReadAdrBase], (instregex "^LDR(BB|SBW|SBX|HH|SHW|SHX|SW|W|X)roX")>; 675def : InstRW<[M5WriteL5, 676 ReadAdrBase], (instrs PRFMroW)>; 677def : InstRW<[WriteLDIdx, 678 ReadAdrBase], (instrs PRFMroX)>; 679 680// Store instructions. 681def : InstRW<[M5WriteSB, 682 ReadAdrBase], (instregex "^STR(BB|HH|W|X)roW")>; 683def : InstRW<[WriteST, 684 ReadAdrBase], (instregex "^STR(BB|HH|W|X)roX")>; 685 686// Atomic load and store instructions. 687def : InstRW<[M5WriteLGW], (instregex "^CAS(A|AL|L)?[BHW]$")>; 688def : InstRW<[M5WriteLGX], (instregex "^CAS(A|AL|L)?X$")>; 689def : InstRW<[M5WriteLFW], (instregex "^CASP(A|AL|L)?W$")>; 690def : InstRW<[M5WriteLFX], (instregex "^CASP(A|AL|L)?X$")>; 691def : InstRW<[M5WriteLGW], (instregex "^LD(ADD|CLR|EOR|SET|[SU]MAX|[SU]MIN)(A|AL|L)?[BHW]$")>; 692def : InstRW<[M5WriteLGX], (instregex "^LD(ADD|CLR|EOR|SET|[SU]MAX|[SU]MIN)(A|AL|L)?X$")>; 693def : InstRW<[M5WriteLGW], (instregex "^SWP(A|AL|L)?[BHW]$")>; 694def : InstRW<[M5WriteLGX], (instregex "^SWP(A|AL|L)?X$")>; 695 696// FP data instructions. 697def : InstRW<[M5WriteNSHF1], (instrs FABSHr, FABSSr,FABSDr)>; 698def : InstRW<[M5WriteFADD2], (instregex "^F(ADD|SUB)[HSD]rr")>; 699def : InstRW<[M5WriteFADD2], (instregex "^FADDPv.i(16|32|64)")>; 700def : InstRW<[M5WriteNEONQ], (instregex "^FCCMPE?[HSD]rr")>; 701def : InstRW<[M5WriteNMSC2], (instregex "^FCMPE?[HSD]r[ir]")>; 702def : InstRW<[M5WriteNMSC1], (instregex "^F(AC|CM)(EQ|GE|GT|LE|LT)(16|32|64|v1)")>; 703def : InstRW<[M5WriteFDIV5], (instrs FDIVHrr)>; 704def : InstRW<[M5WriteFDIV7], (instrs FDIVSrr)>; 705def : InstRW<[M5WriteFDIV12], (instrs FDIVDrr)>; 706def : InstRW<[M5WriteNMSC1], (instregex "^F(MAX|MIN)(NM)?[HSD]rr")>; 707def : InstRW<[M5WriteFMAC3], (instregex "^FN?MUL[HSD]rr")>; 708def : InstRW<[M5WriteFMAC3], (instrs FMULX16, FMULX32, FMULX64)>; 709def : InstRW<[M5WriteFMAC4, 710 M5ReadFMACM1], (instregex "^FN?M(ADD|SUB)[HSD]rrr")>; 711def : InstRW<[M5WriteNALU2], (instrs FNEGHr, FNEGSr, FNEGDr)>; 712def : InstRW<[M5WriteFCVT3A], (instregex "^FRINT.+r")>; 713def : InstRW<[M5WriteNEONH], (instregex "^FCSEL[HSD]rrr")>; 714def : InstRW<[M5WriteFSQR5], (instrs FSQRTHr)>; 715def : InstRW<[M5WriteFSQR8], (instrs FSQRTSr)>; 716def : InstRW<[M5WriteFSQR12], (instrs FSQRTDr)>; 717 718// FP miscellaneous instructions. 719def : InstRW<[M5WriteFCVT2], (instregex "^FCVT[HSD][HSD]r")>; 720def : InstRW<[M5WriteFCVTC], (instregex "^[SU]CVTF[SU][XW][HSD]ri")>; 721def : InstRW<[M5WriteFCVTB], (instregex "^FCVT[AMNPZ][SU][SU][XW][HSD]r")>; 722def : InstRW<[M5WriteNALU1], (instregex "^FMOV[HSD]i")>; 723def : InstRW<[M5WriteNALU2], (instregex "^FMOV[HSD]r")>; 724def : InstRW<[M5WriteSA], (instregex "^FMOV[WX][HSD]r")>; 725def : InstRW<[M5WriteFCVTA], (instregex "^FMOV[HSD][WX]r")>; 726def : InstRW<[M5WriteNEONI], (instregex "^FMOVXDHighr")>; 727def : InstRW<[M5WriteNEONK], (instregex "^FMOVDXHighr")>; 728def : InstRW<[M5WriteFCVT3], (instregex "^F(RECP|RSQRT)Ev1(f16|i32|i64)")>; 729def : InstRW<[M5WriteNMSC1], (instregex "^FRECPXv1")>; 730def : InstRW<[M5WriteFMAC4], (instregex "^F(RECP|RSQRT)S(16|32|64)")>; 731 732// FP load instructions. 733def : InstRW<[WriteVLD], (instregex "^LDR[SDQ]l")>; 734def : InstRW<[WriteVLD], (instregex "^LDUR[BHSDQ]i")>; 735def : InstRW<[WriteVLD, 736 WriteAdr], (instregex "^LDR[BHSDQ](post|pre)")>; 737def : InstRW<[WriteVLD], (instregex "^LDR[BHSDQ]ui")>; 738def : InstRW<[M5WriteLE, 739 ReadAdrBase], (instregex "^LDR[BHSDQ]roW")>; 740def : InstRW<[WriteVLD, 741 ReadAdrBase], (instregex "^LDR[BHSD]roX")>; 742def : InstRW<[M5WriteLY, 743 ReadAdrBase], (instrs LDRQroX)>; 744def : InstRW<[WriteVLD, 745 M5WriteLH], (instregex "^LDN?P[SD]i")>; 746def : InstRW<[M5WriteLA, 747 M5WriteLH], (instregex "^LDN?PQi")>; 748def : InstRW<[M5WriteLB, 749 M5WriteLH, 750 WriteAdr], (instregex "^LDP[SD](post|pre)")>; 751def : InstRW<[M5WriteLC, 752 M5WriteLH, 753 WriteAdr], (instregex "^LDPQ(post|pre)")>; 754 755// FP store instructions. 756def : InstRW<[WriteVST], (instregex "^STUR[BHSDQ]i")>; 757def : InstRW<[WriteVST, 758 WriteAdr], (instregex "^STR[BHSDQ](post|pre)")>; 759def : InstRW<[WriteVST], (instregex "^STR[BHSDQ]ui")>; 760def : InstRW<[WriteVST, 761 ReadAdrBase], (instregex "^STR[BHSD]ro[WX]")>; 762def : InstRW<[M5WriteVSTK, 763 ReadAdrBase], (instregex "^STRQroW")>; 764def : InstRW<[M5WriteVSTY, 765 ReadAdrBase], (instregex "^STRQroX")>; 766def : InstRW<[WriteVST], (instregex "^STN?P[SD]i")>; 767def : InstRW<[M5WriteVSTH], (instregex "^STN?PQi")>; 768def : InstRW<[WriteVST, 769 WriteAdr], (instregex "^STP[SD](post|pre)")>; 770def : InstRW<[M5WriteVSTJ, 771 WriteAdr], (instregex "^STPQ(post|pre)")>; 772 773// ASIMD instructions. 774def : InstRW<[M5WriteNHAD1], (instregex "^[SU]ABDL?v")>; 775def : InstRW<[M5WriteNHAD3], (instregex "^[SU]ABAL?v")>; 776def : InstRW<[M5WriteNMSC1], (instregex "^ABSv")>; 777def : InstRW<[M5WriteNALU2], (instregex "^(ADD|NEG|SUB)v")>; 778def : InstRW<[M5WriteNHAD3], (instregex "^[SU]?ADDL?Pv")>; 779def : InstRW<[M5WriteNHAD3], (instregex "^[SU]H(ADD|SUB)v")>; 780def : InstRW<[M5WriteNHAD3], (instregex "^[SU](ADD|SUB)[LW]v")>; 781def : InstRW<[M5WriteNHAD3], (instregex "^R?(ADD|SUB)HN2?v")>; 782def : InstRW<[M5WriteNHAD3], (instregex "^[SU]Q(ADD|SUB)v")>; 783def : InstRW<[M5WriteNHAD3], (instregex "^(SU|US)QADDv")>; 784def : InstRW<[M5WriteNHAD3], (instregex "^[SU]RHADDv")>; 785def : InstRW<[M5WriteNMSC1], (instregex "^SQ(ABS|NEG)v")>; 786def : InstRW<[M5WriteNHAD3], (instregex "^[SU]?ADDL?Vv")>; 787def : InstRW<[M5WriteNMSC1], (instregex "^CM(EQ|GE|GT|HI|HS|LE|LT)v")>; 788def : InstRW<[M5WriteNALU2], (instregex "^CMTSTv")>; 789def : InstRW<[M5WriteNALU2], (instregex "^(AND|BIC|EOR|NOT|ORN|ORR)v")>; 790def : InstRW<[M5WriteNMSC1], (instregex "^[SU](MIN|MAX)v")>; 791def : InstRW<[M5WriteNMSC2], (instregex "^[SU](MIN|MAX)Pv")>; 792def : InstRW<[M5WriteNHAD3], (instregex "^[SU](MIN|MAX)Vv")>; 793def : InstRW<[M5WriteNMUL3], (instregex "^(SQR?D)?MULH?v")>; 794def : InstRW<[M5WriteNMUL3, 795 M5ReadNMULM1], (instregex "^ML[AS]v")>; 796def : InstRW<[M5WriteNMUL3, 797 M5ReadNMULM1], (instregex "^SQRDML[AS]H")>; 798def : InstRW<[M5WriteNMUL3], (instregex "^(S|U|SQD)ML[AS]L(v1(i32|i64)|v2i32|v4i16|v8i8)")>; 799def : InstRW<[M5WriteNMUL3, 800 M5ReadNMULM1], (instregex "^(S|U|SQD)ML[AS]L(v4i32|v8i16|v16i8)")>; 801def : InstRW<[M5WriteNMUL3, 802 M5ReadNMULM1], (instregex "^(S|U|SQD)MULL(v1(i32|i64)|v2i32|v4i16|v8i8)")>; 803def : InstRW<[M5WriteNMUL3, 804 M5ReadNMULM1], (instregex "^(S|U|SQD)MULL(v4i32|v8i16|v16i8)")>; 805def : InstRW<[M5WriteNDOT2], (instregex "^[SU]DOT(lane)?v")>; 806def : InstRW<[M5WriteNHAD3], (instregex "^[SU]ADALPv")>; 807def : InstRW<[M5WriteNSHT4A], (instregex "^[SU]R?SRA[dv]")>; 808def : InstRW<[M5WriteNSHT2], (instregex "^SHL[dv]")>; 809def : InstRW<[M5WriteNSHT2], (instregex "^S[LR]I[dv]")>; 810def : InstRW<[M5WriteNSHT2], (instregex "^[SU]SH[LR][dv]")>; 811def : InstRW<[M5WriteNSHT2], (instregex "^[SU]?SHLLv")>; 812def : InstRW<[M5WriteNSHT4A], (instregex "^[SU]?Q?R?SHRU?N[bhsv]")>; 813def : InstRW<[M5WriteNSHT4A], (instregex "^[SU]RSH[LR][dv]")>; 814def : InstRW<[M5WriteNSHT4A], (instregex "^[SU]QR?SHLU?[bhsdv]")>; 815 816// ASIMD FP instructions. 817def : InstRW<[M5WriteNSHF2], (instregex "^FABSv.f(16|32|64)")>; 818def : InstRW<[M5WriteFADD2], (instregex "^F(ABD|ADD|SUB)v.f(16|32|64)")>; 819def : InstRW<[M5WriteFADD2], (instregex "^FADDPv.f(16|32|64)")>; 820def : InstRW<[M5WriteNMSC1], (instregex "^F(AC|CM)(EQ|GE|GT|LE|LT)v[^1]")>; 821def : InstRW<[M5WriteFCVT2], (instregex "^FCVT(L|N|XN)v")>; 822def : InstRW<[M5WriteFCVT2A], (instregex "^FCVT[AMNPZ][SU]v")>; 823def : InstRW<[M5WriteFCVT2], (instregex "^[SU]CVTFv.[fi](16|32|64)")>; 824def : InstRW<[M5WriteFDIV7], (instrs FDIVv4f16)>; 825def : InstRW<[M5WriteNEONV], (instrs FDIVv8f16)>; 826def : InstRW<[M5WriteFDIV7], (instrs FDIVv2f32)>; 827def : InstRW<[M5WriteNEONV], (instrs FDIVv4f32)>; 828def : InstRW<[M5WriteNEONW], (instrs FDIVv2f64)>; 829def : InstRW<[M5WriteNMSC1], (instregex "^F(MAX|MIN)(NM)?v")>; 830def : InstRW<[M5WriteNMSC2], (instregex "^F(MAX|MIN)(NM)?Pv")>; 831def : InstRW<[M5WriteNEONZ], (instregex "^F(MAX|MIN)(NM)?Vv")>; 832def : InstRW<[M5WriteFMAC3], (instregex "^FMULX?v.[fi](16|32|64)")>; 833def : InstRW<[M5WriteFMAC4, 834 M5ReadFMACM1], (instregex "^FML[AS]v.[fi](16|32|64)")>; 835def : InstRW<[M5WriteNALU2], (instregex "^FNEGv.f(16|32|64)")>; 836def : InstRW<[M5WriteFCVT3A], (instregex "^FRINT[AIMNPXZ]v")>; 837def : InstRW<[M5WriteFSQR7], (instrs FSQRTv4f16)>; 838def : InstRW<[M5WriteNEONU], (instrs FSQRTv8f16)>; 839def : InstRW<[M5WriteFSQR8], (instrs FSQRTv2f32)>; 840def : InstRW<[M5WriteNEONX], (instrs FSQRTv4f32)>; 841def : InstRW<[M5WriteNEONY], (instrs FSQRTv2f64)>; 842 843// ASIMD miscellaneous instructions. 844def : InstRW<[M5WriteNALU2], (instregex "^RBITv")>; 845def : InstRW<[M5WriteNALU2], (instregex "^(BIF|BIT|BSL)v")>; 846def : InstRW<[M5WriteNALU2], (instregex "^CL[STZ]v")>; 847def : InstRW<[M5WriteNEONB], (instregex "^DUPv.+gpr")>; 848def : InstRW<[M5WriteNSHF2], (instregex "^CPY")>; 849def : InstRW<[M5WriteNSHF2], (instregex "^DUPv.+lane")>; 850def : InstRW<[M5WriteNSHF2], (instregex "^EXTv")>; 851def : InstRW<[M5WriteNSHT4A], (instregex "^XTNv")>; 852def : InstRW<[M5WriteNSHT4A], (instregex "^[SU]?QXTU?Nv")>; 853def : InstRW<[M5WriteNEONB], (instregex "^INSv.+gpr")>; 854def : InstRW<[M5WriteNSHF2], (instregex "^INSv.+lane")>; 855def : InstRW<[M5WriteMOVI], (instregex "^(MOV|MVN)I")>; 856def : InstRW<[M5WriteNALU1], (instregex "^FMOVv.f(16|32|64)")>; 857def : InstRW<[M5WriteFCVT3], (instregex "^F(RECP|RSQRT)Ev[248]f(16|32|64)")>; 858def : InstRW<[M5WriteFCVT3], (instregex "^U(RECP|RSQRT)Ev[24]i32")>; 859def : InstRW<[M5WriteFMAC4], (instregex "^F(RECP|RSQRT)Sv.f(16|32|64)")>; 860def : InstRW<[M5WriteNSHF2], (instregex "^REV(16|32|64)v")>; 861def : InstRW<[M5WriteNSHFA], (instregex "^TB[LX]v(8|16)i8One")>; 862def : InstRW<[M5WriteNSHFB], (instregex "^TB[LX]v(8|16)i8Two")>; 863def : InstRW<[M5WriteNSHFC], (instregex "^TB[LX]v(8|16)i8Three")>; 864def : InstRW<[M5WriteNSHFD], (instregex "^TB[LX]v(8|16)i8Four")>; 865def : InstRW<[M5WriteNEONP], (instregex "^[SU]MOVv")>; 866def : InstRW<[M5WriteNSHF2], (instregex "^(TRN|UZP|ZIP)[12]v")>; 867 868// ASIMD load instructions. 869def : InstRW<[WriteVLD], (instregex "LD1Onev(8b|16b|4h|8h|2s|4s|1d|2d)$")>; 870def : InstRW<[WriteVLD, 871 M5WriteA1X, 872 WriteAdr], (instregex "LD1Onev(8b|16b|4h|8h|2s|4s|1d|2d)_POST$")>; 873def : InstRW<[M5WriteVLDA], (instregex "LD1Twov(8b|16b|4h|8h|2s|4s|1d|2d)$")>; 874def : InstRW<[M5WriteVLDA, 875 M5WriteA1X, 876 WriteAdr], (instregex "LD1Twov(8b|16b|4h|8h|2s|4s|1d|2d)_POST$")>; 877def : InstRW<[M5WriteVLDB], (instregex "LD1Threev(8b|16b|4h|8h|2s|4s|1d|2d)$")>; 878def : InstRW<[M5WriteVLDB, 879 M5WriteA1X, 880 WriteAdr], (instregex "LD1Threev(8b|16b|4h|8h|2s|4s|1d|2d)_POST$")>; 881def : InstRW<[M5WriteVLDC], (instregex "LD1Fourv(8b|16b|4h|8h|2s|4s|1d|2d)$")>; 882def : InstRW<[M5WriteVLDC, 883 M5WriteA1X, 884 WriteAdr], (instregex "LD1Fourv(8b|16b|4h|8h|2s|4s|1d|2d)_POST$")>; 885def : InstRW<[M5WriteVLDD], (instregex "LD1i(8|16|32|64)$")>; 886def : InstRW<[M5WriteVLDD, 887 M5WriteA1X, 888 WriteAdr], (instregex "LD1i(8|16|32|64)_POST$")>; 889def : InstRW<[WriteVLD], (instregex "LD1Rv(8b|16b|4h|8h|2s|4s|1d|2d)$")>; 890def : InstRW<[WriteVLD, 891 M5WriteA1X, 892 WriteAdr], (instregex "LD1Rv(8b|16b|4h|8h|2s|4s|1d|2d)_POST$")>; 893def : InstRW<[M5WriteVLDF], (instregex "LD2Twov(8b|16b|4h|8h|2s|4s|2d)$")>; 894def : InstRW<[M5WriteVLDF, 895 M5WriteA1X, 896 WriteAdr], (instregex "LD2Twov(8b|16b|4h|8h|2s|4s|2d)_POST$")>; 897def : InstRW<[M5WriteVLDG], (instregex "LD2i(8|16|32|64)$")>; 898def : InstRW<[M5WriteVLDG, 899 M5WriteA1X, 900 WriteAdr], (instregex "LD2i(8|16|32|64)_POST$")>; 901def : InstRW<[M5WriteVLDA], (instregex "LD2Rv(8b|16b|4h|8h|2s|4s|1d|2d)$")>; 902def : InstRW<[M5WriteVLDA, 903 M5WriteA1X, 904 WriteAdr], (instregex "LD2Rv(8b|16b|4h|8h|2s|4s|1d|2d)_POST$")>; 905def : InstRW<[M5WriteVLDI], (instregex "LD3Threev(8b|16b|4h|8h|2s|4s|2d)$")>; 906def : InstRW<[M5WriteVLDI, 907 M5WriteA1X, 908 WriteAdr], (instregex "LD3Threev(8b|16b|4h|8h|2s|4s|2d)_POST$")>; 909def : InstRW<[M5WriteVLDJ], (instregex "LD3i(8|16|32)$")>; 910def : InstRW<[M5WriteVLDJ, 911 M5WriteA1X, 912 WriteAdr], (instregex "LD3i(8|16|32)_POST$")>; 913def : InstRW<[M5WriteVLDL], (instregex "LD3i64$")>; 914def : InstRW<[M5WriteVLDL, 915 M5WriteA1X, 916 WriteAdr], (instregex "LD3i64_POST$")>; 917def : InstRW<[M5WriteVLDB], (instregex "LD3Rv(8b|16b|4h|8h|2s|4s|1d|2d)$")>; 918def : InstRW<[M5WriteVLDB, 919 M5WriteA1X], (instregex "LD3Rv(8b|16b|4h|8h|2s|4s|1d|2d)_POST$")>; 920def : InstRW<[M5WriteVLDN], (instregex "LD4Fourv(8b|16b|4h|8h|2s|4s|2d)$")>; 921def : InstRW<[M5WriteVLDN, 922 M5WriteA1X, 923 WriteAdr], (instregex "LD4Fourv(8b|16b|4h|8h|2s|4s|2d)_POST$")>; 924def : InstRW<[M5WriteVLDK], (instregex "LD4i(8|16|32)$")>; 925def : InstRW<[M5WriteVLDK, 926 M5WriteA1X, 927 WriteAdr], (instregex "LD4i(8|16|32)_POST$")>; 928def : InstRW<[M5WriteVLDM], (instregex "LD4i64$")>; 929def : InstRW<[M5WriteVLDM, 930 M5WriteA1X, 931 WriteAdr], (instregex "LD4i64_POST$")>; 932def : InstRW<[M5WriteVLDC], (instregex "LD4Rv(8b|16b|4h|8h|2s|4s|1d|2d)$")>; 933def : InstRW<[M5WriteVLDC, 934 M5WriteA1X, 935 WriteAdr], (instregex "LD4Rv(8b|16b|4h|8h|2s|4s|1d|2d)_POST$")>; 936 937// ASIMD store instructions. 938def : InstRW<[WriteVST], (instregex "ST1Onev(8b|16b|4h|8h|2s|4s|1d|2d)$")>; 939def : InstRW<[WriteVST, 940 M5WriteA1X, 941 WriteAdr], (instregex "ST1Onev(8b|16b|4h|8h|2s|4s|1d|2d)_POST$")>; 942def : InstRW<[M5WriteVSTA], (instregex "ST1Twov(8b|16b|4h|8h|2s|4s|1d|2d)$")>; 943def : InstRW<[M5WriteVSTA, 944 M5WriteA1X, 945 WriteAdr], (instregex "ST1Twov(8b|16b|4h|8h|2s|4s|1d|2d)_POST$")>; 946 947def : InstRW<[M5WriteVSTB], (instregex "ST1Threev(8b|16b|4h|8h|2s|4s|1d|2d)$")>; 948def : InstRW<[M5WriteVSTB, 949 M5WriteA1X, 950 WriteAdr], (instregex "ST1Threev(8b|16b|4h|8h|2s|4s|1d|2d)_POST$")>; 951def : InstRW<[M5WriteVSTC], (instregex "ST1Fourv(8b|16b|4h|8h|2s|4s|1d|2d)$")>; 952def : InstRW<[M5WriteVSTC, 953 M5WriteA1X, 954 WriteAdr], (instregex "ST1Fourv(8b|16b|4h|8h|2s|4s|1d|2d)_POST$")>; 955def : InstRW<[WriteVST], (instregex "ST1i(8|16|32|64)$")>; 956def : InstRW<[WriteVST, 957 M5WriteA1X, 958 WriteAdr], (instregex "ST1i(8|16|32|64)_POST$")>; 959def : InstRW<[M5WriteVSTD], (instregex "ST2Twov(8b|4h|2s)$")>; 960def : InstRW<[M5WriteVSTD, 961 M5WriteA1X, 962 WriteAdr], (instregex "ST2Twov(8b|4h|2s)_POST$")>; 963def : InstRW<[M5WriteVSTE], (instregex "ST2Twov(16b|8h|4s|2d)$")>; 964def : InstRW<[M5WriteVSTE, 965 M5WriteA1X, 966 WriteAdr], (instregex "ST2Twov(16b|8h|4s|2d)_POST$")>; 967def : InstRW<[M5WriteVSTD], (instregex "ST2i(8|16|32|64)$")>; 968def : InstRW<[M5WriteVSTD, 969 M5WriteA1X, 970 WriteAdr], (instregex "ST2i(8|16|32|64)_POST$")>; 971def : InstRW<[M5WriteVSTF], (instregex "ST3Threev(8b|4h|2s)$")>; 972def : InstRW<[M5WriteVSTF, 973 M5WriteA1X, 974 WriteAdr], (instregex "ST3Threev(8b|4h|2s)_POST$")>; 975def : InstRW<[M5WriteVSTG], (instregex "ST3Threev(16b|8h|4s|2d)$")>; 976def : InstRW<[M5WriteVSTG, 977 M5WriteA1X, 978 WriteAdr], (instregex "ST3Threev(16b|8h|4s|2d)_POST$")>; 979def : InstRW<[M5WriteVSTA], (instregex "ST3i(8|16|32|64)$")>; 980def : InstRW<[M5WriteVSTA, 981 M5WriteA1X, 982 WriteAdr], (instregex "ST3i(8|16|32|64)_POST$")>; 983def : InstRW<[M5WriteVSTL], (instregex "ST4Fourv(8b|4h|2s)$")>; 984def : InstRW<[M5WriteVSTL, 985 M5WriteA1X, 986 WriteAdr], (instregex "ST4Fourv(8b|4h|2s)_POST$")>; 987def : InstRW<[M5WriteVSTI], (instregex "ST4Fourv(16b|8h|4s|2d)$")>; 988def : InstRW<[M5WriteVSTI, 989 M5WriteA1X, 990 WriteAdr], (instregex "ST4Fourv(16b|8h|4s|2d)_POST$")>; 991def : InstRW<[M5WriteVSTA], (instregex "ST4i(8|16|32|64)$")>; 992def : InstRW<[M5WriteVSTA, 993 M5WriteA1X, 994 WriteAdr], (instregex "ST4i(8|16|32|64)_POST$")>; 995 996// Cryptography instructions. 997def : InstRW<[M5WriteNCRY2], (instregex "^AES[DE]")>; 998def : InstRW<[M5WriteNCRY2, 999 M5ReadAESM2], (instregex "^AESI?MC")>; 1000def : InstRW<[M5WriteNCRY2A], (instregex "^PMULv")>; 1001def : InstRW<[M5WriteNCRY1A], (instregex "^PMULLv(1|8)i")>; 1002def : InstRW<[M5WriteNCRY3A], (instregex "^PMULLv(2|16)i")>; 1003def : InstRW<[M5WriteNCRY2A], (instregex "^SHA1(H|SU[01])")>; 1004def : InstRW<[M5WriteNCRY5A], (instregex "^SHA1[CMP]")>; 1005def : InstRW<[M5WriteNCRY2A], (instrs SHA256SU0rr)>; 1006def : InstRW<[M5WriteNCRY5A], (instrs SHA256SU1rrr)>; 1007def : InstRW<[M5WriteNCRY5A], (instregex "^SHA256H2?")>; 1008 1009// CRC instructions. 1010def : InstRW<[M5WriteF2, 1011 M5ReadFM1], (instregex "^CRC32C?[BHWX]")>; 1012 1013} // SchedModel = ExynosM5Model 1014