AArch64SchedExynosM5.td revision 360784
1//=- AArch64SchedExynosM5.td - Samsung Exynos M5 Sched Defs --*- tablegen -*-=// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file defines the machine model for the Samsung Exynos M5 to support 10// instruction scheduling and other instruction cost heuristics. 11// 12//===----------------------------------------------------------------------===// 13 14//===----------------------------------------------------------------------===// 15// The Exynos-M5 is an advanced superscalar microprocessor with a 6-wide 16// in-order stage for decode and dispatch and a wider issue stage. 17// The execution units and loads and stores are out-of-order. 18 19def ExynosM5Model : SchedMachineModel { 20 let IssueWidth = 6; // Up to 6 uops per cycle. 21 let MicroOpBufferSize = 228; // ROB size. 22 let LoopMicroOpBufferSize = 60; // Based on the instruction queue size. 23 let LoadLatency = 4; // Optimistic load cases. 24 let MispredictPenalty = 15; // Minimum branch misprediction penalty. 25 let CompleteModel = 1; // Use the default model otherwise. 26 27 list<Predicate> UnsupportedFeatures = SVEUnsupported.F; 28} 29 30//===----------------------------------------------------------------------===// 31// Define each kind of processor resource and number available on the Exynos-M5. 32 33let SchedModel = ExynosM5Model in { 34 35def M5UnitA : ProcResource<2>; // Simple integer 36def M5UnitC : ProcResource<2>; // Simple and complex integer 37let Super = M5UnitC, BufferSize = 1 in 38def M5UnitD : ProcResource<1>; // Integer division (inside C0, serialized) 39def M5UnitE : ProcResource<2>; // Simple 32-bit integer 40let Super = M5UnitC in 41def M5UnitF : ProcResource<2>; // CRC (inside C) 42def M5UnitB : ProcResource<1>; // Branch 43def M5UnitL0 : ProcResource<1>; // Load 44def M5UnitS0 : ProcResource<1>; // Store 45def M5PipeLS : ProcResource<1>; // Load/Store 46let Super = M5PipeLS in { 47 def M5UnitL1 : ProcResource<1>; 48 def M5UnitS1 : ProcResource<1>; 49} 50def M5PipeF0 : ProcResource<1>; // FP #0 51let Super = M5PipeF0 in { 52 def M5UnitFMAC0 : ProcResource<1>; // FP multiplication 53 def M5UnitFADD0 : ProcResource<1>; // Simple FP 54 def M5UnitNALU0 : ProcResource<1>; // Simple vector 55 def M5UnitNDOT0 : ProcResource<1>; // Dot product vector 56 def M5UnitNHAD : ProcResource<1>; // Horizontal vector 57 def M5UnitNMSC : ProcResource<1>; // FP and vector miscellanea 58 def M5UnitNMUL0 : ProcResource<1>; // Vector multiplication 59 def M5UnitNSHT0 : ProcResource<1>; // Vector shifting 60 def M5UnitNSHF0 : ProcResource<1>; // Vector shuffling 61 def M5UnitNCRY0 : ProcResource<1>; // Cryptographic 62} 63def M5PipeF1 : ProcResource<1>; // FP #1 64let Super = M5PipeF1 in { 65 def M5UnitFMAC1 : ProcResource<1>; // FP multiplication 66 def M5UnitFADD1 : ProcResource<1>; // Simple FP 67 def M5UnitFCVT0 : ProcResource<1>; // FP conversion 68 def M5UnitFDIV0 : ProcResource<2>; // FP division (serialized) 69 def M5UnitFSQR0 : ProcResource<2>; // FP square root (serialized) 70 def M5UnitFST0 : ProcResource<1>; // FP store 71 def M5UnitNALU1 : ProcResource<1>; // Simple vector 72 def M5UnitNDOT1 : ProcResource<1>; // Dot product vector 73 def M5UnitNSHT1 : ProcResource<1>; // Vector shifting 74 def M5UnitNSHF1 : ProcResource<1>; // Vector shuffling 75} 76def M5PipeF2 : ProcResource<1>; // FP #2 77let Super = M5PipeF2 in { 78 def M5UnitFMAC2 : ProcResource<1>; // FP multiplication 79 def M5UnitFADD2 : ProcResource<1>; // Simple FP 80 def M5UnitFCVT1 : ProcResource<1>; // FP conversion 81 def M5UnitFDIV1 : ProcResource<2>; // FP division (serialized) 82 def M5UnitFSQR1 : ProcResource<2>; // FP square root (serialized) 83 def M5UnitFST1 : ProcResource<1>; // FP store 84 def M5UnitNALU2 : ProcResource<1>; // Simple vector 85 def M5UnitNDOT2 : ProcResource<1>; // Dot product vector 86 def M5UnitNMUL1 : ProcResource<1>; // Vector multiplication 87 def M5UnitNSHT2 : ProcResource<1>; // Vector shifting 88 def M5UnitNCRY1 : ProcResource<1>; // Cryptographic 89} 90 91def M5UnitAX : ProcResGroup<[M5UnitA, 92 M5UnitC]>; 93def M5UnitAW : ProcResGroup<[M5UnitA, 94 M5UnitC, 95 M5UnitE]>; 96def M5UnitL : ProcResGroup<[M5UnitL0, 97 M5UnitL1]>; 98def M5UnitS : ProcResGroup<[M5UnitS0, 99 M5UnitS1]>; 100def M5UnitFMAC : ProcResGroup<[M5UnitFMAC0, 101 M5UnitFMAC1, 102 M5UnitFMAC2]>; 103def M5UnitFADD : ProcResGroup<[M5UnitFADD0, 104 M5UnitFADD1, 105 M5UnitFADD2]>; 106def M5UnitFCVT : ProcResGroup<[M5UnitFCVT0, 107 M5UnitFCVT1]>; 108def M5UnitFDIV : ProcResGroup<[M5UnitFDIV0, 109 M5UnitFDIV1]>; 110def M5UnitFSQR : ProcResGroup<[M5UnitFSQR0, 111 M5UnitFSQR1]>; 112def M5UnitFST : ProcResGroup<[M5UnitFST0, 113 M5UnitFST1]>; 114def M5UnitNALU : ProcResGroup<[M5UnitNALU0, 115 M5UnitNALU1, 116 M5UnitNALU2]>; 117def M5UnitNDOT : ProcResGroup<[M5UnitNDOT0, 118 M5UnitNDOT1, 119 M5UnitNDOT2]>; 120def M5UnitNMUL : ProcResGroup<[M5UnitNMUL0, 121 M5UnitNMUL1]>; 122def M5UnitNSHT : ProcResGroup<[M5UnitNSHT0, 123 M5UnitNSHT1, 124 M5UnitNSHT2]>; 125def M5UnitNSHF : ProcResGroup<[M5UnitNSHF0, 126 M5UnitNSHF1]>; 127def M5UnitNCRY : ProcResGroup<[M5UnitNCRY0, 128 M5UnitNCRY1]>; 129 130//===----------------------------------------------------------------------===// 131// Resources details. 132 133def M5WriteZ0 : SchedWriteRes<[]> { let Latency = 0; } 134def M5WriteZ1 : SchedWriteRes<[]> { let Latency = 1; 135 let NumMicroOps = 0; } 136def M5WriteZ4 : SchedWriteRes<[]> { let Latency = 4; 137 let NumMicroOps = 0; } 138 139def M5WriteA1W : SchedWriteRes<[M5UnitAW]> { let Latency = 1; } 140def M5WriteA1X : SchedWriteRes<[M5UnitAX]> { let Latency = 1; } 141def M5WriteAAW : SchedWriteRes<[M5UnitAW]> { let Latency = 2; 142 let ResourceCycles = [2]; } 143def M5WriteAAX : SchedWriteRes<[M5UnitAX]> { let Latency = 2; 144 let ResourceCycles = [2]; } 145def M5WriteAB : SchedWriteRes<[M5UnitAX, 146 M5UnitC, 147 M5UnitE]> { let Latency = 2; 148 let NumMicroOps = 2; } 149def M5WriteAC : SchedWriteRes<[M5UnitAX, 150 M5UnitAX, 151 M5UnitC]> { let Latency = 3; 152 let NumMicroOps = 3; } 153def M5WriteAD : SchedWriteRes<[M5UnitAW, 154 M5UnitC]> { let Latency = 2; 155 let NumMicroOps = 2; } 156def M5WriteAFW : SchedWriteRes<[M5UnitAW]> { let Latency = 2; 157 let NumMicroOps = 2; } 158def M5WriteAFX : SchedWriteRes<[M5UnitAX]> { let Latency = 2; 159 let NumMicroOps = 2; } 160def M5WriteAUW : SchedWriteVariant<[SchedVar<IsCopyIdiomPred, [M5WriteZ0]>, 161 SchedVar<ExynosArithPred, [M5WriteA1W]>, 162 SchedVar<ExynosLogicExPred, [M5WriteA1W]>, 163 SchedVar<NoSchedPred, [M5WriteAAW]>]>; 164def M5WriteAUX : SchedWriteVariant<[SchedVar<IsCopyIdiomPred, [M5WriteZ0]>, 165 SchedVar<ExynosArithPred, [M5WriteA1X]>, 166 SchedVar<ExynosLogicExPred, [M5WriteA1X]>, 167 SchedVar<NoSchedPred, [M5WriteAAX]>]>; 168def M5WriteAVW : SchedWriteVariant<[SchedVar<ExynosResetPred, [M5WriteZ0]>, 169 SchedVar<ExynosArithPred, [M5WriteA1W]>, 170 SchedVar<ExynosLogicExPred, [M5WriteA1W]>, 171 SchedVar<NoSchedPred, [M5WriteAAW]>]>; 172def M5WriteAVX : SchedWriteVariant<[SchedVar<ExynosResetPred, [M5WriteZ0]>, 173 SchedVar<ExynosArithPred, [M5WriteA1X]>, 174 SchedVar<ExynosLogicExPred, [M5WriteA1X]>, 175 SchedVar<NoSchedPred, [M5WriteAAX]>]>; 176def M5WriteAXW : SchedWriteVariant<[SchedVar<ExynosArithPred, [M5WriteA1W]>, 177 SchedVar<ExynosLogicExPred, [M5WriteA1W]>, 178 SchedVar<NoSchedPred, [M5WriteAAW]>]>; 179def M5WriteAXX : SchedWriteVariant<[SchedVar<ExynosArithPred, [M5WriteA1X]>, 180 SchedVar<ExynosLogicExPred, [M5WriteA1X]>, 181 SchedVar<NoSchedPred, [M5WriteAAX]>]>; 182def M5WriteAYW : SchedWriteVariant<[SchedVar<ExynosRotateRightImmPred, [M5WriteA1W]>, 183 SchedVar<NoSchedPred, [M5WriteAFW]>]>; 184def M5WriteAYX : SchedWriteVariant<[SchedVar<ExynosRotateRightImmPred, [M5WriteA1X]>, 185 SchedVar<NoSchedPred, [M5WriteAFX]>]>; 186 187def M5WriteB1 : SchedWriteRes<[M5UnitB]> { let Latency = 1; } 188def M5WriteBX : SchedWriteVariant<[SchedVar<ExynosBranchLinkLRPred, [M5WriteAC]>, 189 SchedVar<NoSchedPred, [M5WriteAB]>]>; 190 191def M5WriteC1 : SchedWriteRes<[M5UnitC]> { let Latency = 1; } 192def M5WriteC2 : SchedWriteRes<[M5UnitC]> { let Latency = 2; } 193def M5WriteCA : SchedWriteRes<[M5UnitC]> { let Latency = 3; 194 let ResourceCycles = [2]; } 195 196def M5WriteD10 : SchedWriteRes<[M5UnitD]> { let Latency = 10; 197 let ResourceCycles = [10]; } 198def M5WriteD16 : SchedWriteRes<[M5UnitD]> { let Latency = 16; 199 let ResourceCycles = [16]; } 200 201def M5WriteF2 : SchedWriteRes<[M5UnitF]> { let Latency = 2; } 202 203def M5WriteL4 : SchedWriteRes<[M5UnitL]> { let Latency = 4; } 204def M5WriteL5 : SchedWriteRes<[M5UnitL]> { let Latency = 5; } 205def M5WriteL6 : SchedWriteRes<[M5UnitL]> { let Latency = 6; } 206def M5WriteLA : SchedWriteRes<[M5UnitL, 207 M5UnitL]> { let Latency = 6; 208 let NumMicroOps = 1; } 209def M5WriteLB : SchedWriteRes<[M5UnitAX, 210 M5UnitL]> { let Latency = 6; 211 let NumMicroOps = 2; } 212def M5WriteLC : SchedWriteRes<[M5UnitAX, 213 M5UnitL, 214 M5UnitL]> { let Latency = 6; 215 let NumMicroOps = 2; } 216def M5WriteLD : SchedWriteRes<[M5UnitAX, 217 M5UnitL]> { let Latency = 4; 218 let NumMicroOps = 2; } 219def M5WriteLE : SchedWriteRes<[M5UnitAX, 220 M5UnitL]> { let Latency = 7; 221 let NumMicroOps = 2; } 222def M5WriteLFW : SchedWriteRes<[M5UnitAW, 223 M5UnitAW, 224 M5UnitAW, 225 M5UnitAW, 226 M5UnitL]> { let Latency = 15; 227 let NumMicroOps = 6; 228 let ResourceCycles = [1, 1, 1, 1, 15]; } 229def M5WriteLFX : SchedWriteRes<[M5UnitAX, 230 M5UnitAX, 231 M5UnitAX, 232 M5UnitAX, 233 M5UnitL]> { let Latency = 15; 234 let NumMicroOps = 6; 235 let ResourceCycles = [1, 1, 1, 1, 15]; } 236def M5WriteLGW : SchedWriteRes<[M5UnitAW, 237 M5UnitL]> { let Latency = 13; 238 let NumMicroOps = 1; 239 let ResourceCycles = [1, 13]; } 240def M5WriteLGX : SchedWriteRes<[M5UnitAX, 241 M5UnitL]> { let Latency = 13; 242 let NumMicroOps = 1; 243 let ResourceCycles = [1, 13]; } 244def M5WriteLH : SchedWriteRes<[]> { let Latency = 6; 245 let NumMicroOps = 0; } 246def M5WriteLX : SchedWriteVariant<[SchedVar<ExynosScaledIdxPred, [M5WriteL5]>, 247 SchedVar<NoSchedPred, [M5WriteL4]>]>; 248def M5WriteLY : SchedWriteVariant<[SchedVar<ExynosScaledIdxPred, [M5WriteLE]>, 249 SchedVar<NoSchedPred, [M5WriteL6]>]>; 250 251def M5WriteS1 : SchedWriteRes<[M5UnitS]> { let Latency = 1; } 252def M5WriteSA : SchedWriteRes<[M5UnitS0]> { let Latency = 4; } 253def M5WriteSB : SchedWriteRes<[M5UnitAX, 254 M5UnitS]> { let Latency = 2; 255 let NumMicroOps = 1; } 256def M5WriteSX : SchedWriteVariant<[SchedVar<ExynosScaledIdxPred, [M5WriteSB]>, 257 SchedVar<NoSchedPred, [M5WriteS1]>]>; 258 259def M5ReadAdrBase : SchedReadVariant<[SchedVar< 260 MCSchedPredicate< 261 CheckAny< 262 [ScaledIdxFn, 263 ExynosScaledIdxFn]>>, [ReadDefault]>, 264 SchedVar<NoSchedPred, [ReadDefault]>]>; 265 266def M5WriteNEONB : SchedWriteRes<[M5UnitNALU, 267 M5UnitS0]> { let Latency = 5; 268 let NumMicroOps = 2; } 269def M5WriteNEONH : SchedWriteRes<[M5UnitNALU, 270 M5UnitS0]> { let Latency = 2; 271 let NumMicroOps = 2; } 272def M5WriteNEONI : SchedWriteRes<[M5UnitS0, 273 M5UnitNSHF]> { let Latency = 6; 274 let NumMicroOps = 2; } 275def M5WriteNEONK : SchedWriteRes<[M5UnitNSHF, 276 M5UnitFCVT0, 277 M5UnitS0]> { let Latency = 5; 278 let NumMicroOps = 2; } 279def M5WriteNEONN : SchedWriteRes<[M5UnitNMSC, 280 M5UnitNMSC]> { let Latency = 5; 281 let NumMicroOps = 2; 282 let ResourceCycles = [7, 7]; } 283def M5WriteNEONO : SchedWriteRes<[M5UnitNMSC, 284 M5UnitNMSC, 285 M5UnitNMSC]> { let Latency = 8; 286 let NumMicroOps = 3; 287 let ResourceCycles = [10, 10, 10]; } 288def M5WriteNEONP : SchedWriteRes<[M5UnitNSHF, 289 M5UnitS0, 290 M5UnitFCVT]> { let Latency = 7; 291 let NumMicroOps = 2; } 292def M5WriteNEONQ : SchedWriteRes<[M5UnitNMSC, 293 M5UnitC]> { let Latency = 3; 294 let NumMicroOps = 1; } 295def M5WriteNEONU : SchedWriteRes<[M5UnitFSQR, 296 M5UnitFSQR]> { let Latency = 7; 297 let ResourceCycles = [4, 4]; } 298def M5WriteNEONV : SchedWriteRes<[M5UnitFDIV, 299 M5UnitFDIV]> { let Latency = 7; 300 let ResourceCycles = [6, 6]; } 301def M5WriteNEONW : SchedWriteRes<[M5UnitFDIV, 302 M5UnitFDIV]> { let Latency = 12; 303 let ResourceCycles = [9, 9]; } 304def M5WriteNEONX : SchedWriteRes<[M5UnitFSQR, 305 M5UnitFSQR]> { let Latency = 8; 306 let ResourceCycles = [5, 5]; } 307def M5WriteNEONY : SchedWriteRes<[M5UnitFSQR, 308 M5UnitFSQR]> { let Latency = 12; 309 let ResourceCycles = [9, 9]; } 310def M5WriteNEONZ : SchedWriteVariant<[SchedVar<ExynosQFormPred, [M5WriteNEONO]>, 311 SchedVar<NoSchedPred, [M5WriteNEONN]>]>; 312 313def M5WriteFADD2 : SchedWriteRes<[M5UnitFADD]> { let Latency = 2; } 314 315def M5WriteFCVT2 : SchedWriteRes<[M5UnitFCVT]> { let Latency = 2; } 316def M5WriteFCVT2A : SchedWriteRes<[M5UnitFCVT0]> { let Latency = 2; } 317def M5WriteFCVT3 : SchedWriteRes<[M5UnitFCVT]> { let Latency = 3; } 318def M5WriteFCVT3A : SchedWriteRes<[M5UnitFCVT0]> { let Latency = 3; } 319def M5WriteFCVTA : SchedWriteRes<[M5UnitFCVT0, 320 M5UnitS0]> { let Latency = 3; 321 let NumMicroOps = 1; } 322def M5WriteFCVTB : SchedWriteRes<[M5UnitFCVT, 323 M5UnitS0]> { let Latency = 4; 324 let NumMicroOps = 1; } 325def M5WriteFCVTC : SchedWriteRes<[M5UnitFCVT, 326 M5UnitS0]> { let Latency = 6; 327 let NumMicroOps = 1; } 328 329def M5WriteFDIV5 : SchedWriteRes<[M5UnitFDIV]> { let Latency = 5; 330 let ResourceCycles = [2]; } 331def M5WriteFDIV7 : SchedWriteRes<[M5UnitFDIV]> { let Latency = 7; 332 let ResourceCycles = [4]; } 333def M5WriteFDIV12 : SchedWriteRes<[M5UnitFDIV]> { let Latency = 12; 334 let ResourceCycles = [9]; } 335 336def M5WriteFMAC3 : SchedWriteRes<[M5UnitFMAC]> { let Latency = 3; } 337def M5WriteFMAC4 : SchedWriteRes<[M5UnitFMAC]> { let Latency = 4; } 338def M5WriteFMAC5 : SchedWriteRes<[M5UnitFMAC]> { let Latency = 5; } 339 340def M5WriteFSQR5 : SchedWriteRes<[M5UnitFSQR]> { let Latency = 5; 341 let ResourceCycles = [2]; } 342def M5WriteFSQR7 : SchedWriteRes<[M5UnitFSQR]> { let Latency = 7; 343 let ResourceCycles = [4]; } 344def M5WriteFSQR8 : SchedWriteRes<[M5UnitFSQR]> { let Latency = 8; 345 let ResourceCycles = [5]; } 346def M5WriteFSQR12 : SchedWriteRes<[M5UnitFSQR]> { let Latency = 12; 347 let ResourceCycles = [9]; } 348 349def M5WriteNALU1 : SchedWriteRes<[M5UnitNALU]> { let Latency = 1; } 350def M5WriteNALU2 : SchedWriteRes<[M5UnitNALU]> { let Latency = 2; } 351 352def M5WriteNDOT2 : SchedWriteRes<[M5UnitNDOT]> { let Latency = 2; } 353 354def M5WriteNCRY2 : SchedWriteRes<[M5UnitNCRY]> { let Latency = 2; } 355def M5WriteNCRY1A : SchedWriteRes<[M5UnitNCRY0]> { let Latency = 1; } 356def M5WriteNCRY2A : SchedWriteRes<[M5UnitNCRY0]> { let Latency = 2; } 357def M5WriteNCRY3A : SchedWriteRes<[M5UnitNCRY0]> { let Latency = 3; } 358def M5WriteNCRY5A : SchedWriteRes<[M5UnitNCRY]> { let Latency = 5; } 359 360def M5WriteNHAD1 : SchedWriteRes<[M5UnitNHAD]> { let Latency = 1; } 361def M5WriteNHAD3 : SchedWriteRes<[M5UnitNHAD]> { let Latency = 3; } 362 363def M5WriteNMSC1 : SchedWriteRes<[M5UnitNMSC]> { let Latency = 1; } 364def M5WriteNMSC2 : SchedWriteRes<[M5UnitNMSC]> { let Latency = 2; } 365 366def M5WriteNMUL3 : SchedWriteRes<[M5UnitNMUL]> { let Latency = 3; } 367 368def M5WriteNSHF1 : SchedWriteRes<[M5UnitNSHF]> { let Latency = 1; } 369def M5WriteNSHF2 : SchedWriteRes<[M5UnitNSHF]> { let Latency = 2; } 370def M5WriteNSHFA : SchedWriteRes<[M5UnitNSHF]> { let Latency = 2; } 371def M5WriteNSHFB : SchedWriteRes<[M5UnitNSHF]> { let Latency = 4; 372 let NumMicroOps = 2; } 373def M5WriteNSHFC : SchedWriteRes<[M5UnitNSHF]> { let Latency = 6; 374 let NumMicroOps = 3; } 375def M5WriteNSHFD : SchedWriteRes<[M5UnitNSHF]> { let Latency = 8; 376 let NumMicroOps = 4; } 377 378def M5WriteNSHT2 : SchedWriteRes<[M5UnitNSHT]> { let Latency = 2; } 379def M5WriteNSHT4A : SchedWriteRes<[M5UnitNSHT1]> { let Latency = 4; } 380 381def M5WriteVLDA : SchedWriteRes<[M5UnitL, 382 M5UnitL]> { let Latency = 6; 383 let NumMicroOps = 2; } 384def M5WriteVLDB : SchedWriteRes<[M5UnitL, 385 M5UnitL, 386 M5UnitL]> { let Latency = 7; 387 let NumMicroOps = 3; } 388def M5WriteVLDC : SchedWriteRes<[M5UnitL, 389 M5UnitL, 390 M5UnitL, 391 M5UnitL]> { let Latency = 7; 392 let NumMicroOps = 4; } 393def M5WriteVLDD : SchedWriteRes<[M5UnitL, 394 M5UnitNSHF]> { let Latency = 7; 395 let NumMicroOps = 2; 396 let ResourceCycles = [2, 1]; } 397def M5WriteVLDF : SchedWriteRes<[M5UnitL, 398 M5UnitL]> { let Latency = 11; 399 let NumMicroOps = 2; 400 let ResourceCycles = [6, 5]; } 401def M5WriteVLDG : SchedWriteRes<[M5UnitL, 402 M5UnitNSHF, 403 M5UnitNSHF]> { let Latency = 7; 404 let NumMicroOps = 3; 405 let ResourceCycles = [2, 1, 1]; } 406def M5WriteVLDI : SchedWriteRes<[M5UnitL, 407 M5UnitL, 408 M5UnitL]> { let Latency = 13; 409 let NumMicroOps = 3; } 410def M5WriteVLDJ : SchedWriteRes<[M5UnitL, 411 M5UnitNSHF, 412 M5UnitNSHF, 413 M5UnitNSHF]> { let Latency = 8; 414 let NumMicroOps = 4; } 415def M5WriteVLDK : SchedWriteRes<[M5UnitL, 416 M5UnitNSHF, 417 M5UnitNSHF, 418 M5UnitNSHF, 419 M5UnitNSHF]> { let Latency = 8; 420 let NumMicroOps = 5; } 421def M5WriteVLDL : SchedWriteRes<[M5UnitL, 422 M5UnitNSHF, 423 M5UnitNSHF, 424 M5UnitL, 425 M5UnitNSHF]> { let Latency = 8; 426 let NumMicroOps = 5; } 427def M5WriteVLDM : SchedWriteRes<[M5UnitL, 428 M5UnitNSHF, 429 M5UnitNSHF, 430 M5UnitL, 431 M5UnitNSHF, 432 M5UnitNSHF]> { let Latency = 8; 433 let NumMicroOps = 6; } 434def M5WriteVLDN : SchedWriteRes<[M5UnitL, 435 M5UnitL, 436 M5UnitL, 437 M5UnitL]> { let Latency = 15; 438 let NumMicroOps = 4; 439 let ResourceCycles = [2, 2, 2, 2]; } 440 441def M5WriteVST1 : SchedWriteRes<[M5UnitS, 442 M5UnitFST]> { let Latency = 1; 443 let NumMicroOps = 1; } 444def M5WriteVSTA : SchedWriteRes<[M5UnitS, 445 M5UnitFST, 446 M5UnitS, 447 M5UnitFST]> { let Latency = 2; 448 let NumMicroOps = 2; } 449def M5WriteVSTB : SchedWriteRes<[M5UnitS, 450 M5UnitFST, 451 M5UnitS, 452 M5UnitFST, 453 M5UnitS, 454 M5UnitFST]> { let Latency = 3; 455 let NumMicroOps = 3; } 456def M5WriteVSTC : SchedWriteRes<[M5UnitS, 457 M5UnitFST, 458 M5UnitS, 459 M5UnitFST, 460 M5UnitS, 461 M5UnitFST, 462 M5UnitS, 463 M5UnitFST]> { let Latency = 4; 464 let NumMicroOps = 4; } 465def M5WriteVSTD : SchedWriteRes<[M5UnitS, 466 M5UnitFST]> { let Latency = 2; } 467def M5WriteVSTE : SchedWriteRes<[M5UnitS, 468 M5UnitFST, 469 M5UnitS, 470 M5UnitFST]> { let Latency = 2; 471 let NumMicroOps = 1; } 472def M5WriteVSTF : SchedWriteRes<[M5UnitNSHF, 473 M5UnitNSHF, 474 M5UnitS, 475 M5UnitFST]> { let Latency = 4; 476 let NumMicroOps = 3; } 477def M5WriteVSTG : SchedWriteRes<[M5UnitNSHF, 478 M5UnitNSHF, 479 M5UnitNSHF, 480 M5UnitS, 481 M5UnitFST, 482 M5UnitS, 483 M5UnitFST]> { let Latency = 4; 484 let NumMicroOps = 5; } 485def M5WriteVSTH : SchedWriteRes<[M5UnitS0, 486 M5UnitFST]> { let Latency = 1; 487 let NumMicroOps = 1; } 488def M5WriteVSTI : SchedWriteRes<[M5UnitNSHF, 489 M5UnitNSHF, 490 M5UnitNSHF, 491 M5UnitNSHF, 492 M5UnitS, 493 M5UnitFST, 494 M5UnitS, 495 M5UnitFST, 496 M5UnitS, 497 M5UnitFST, 498 M5UnitS, 499 M5UnitFST]> { let Latency = 8; 500 let NumMicroOps = 5; 501 let ResourceCycles = [1, 1, 1, 1, 2, 1, 2, 1, 2, 1, 2, 1]; } 502def M5WriteVSTJ : SchedWriteRes<[M5UnitA, 503 M5UnitS0, 504 M5UnitFST]> { let Latency = 1; 505 let NumMicroOps = 1; } 506def M5WriteVSTK : SchedWriteRes<[M5UnitAX, 507 M5UnitS, 508 M5UnitFST]> { let Latency = 3; 509 let NumMicroOps = 2; } 510def M5WriteVSTL : SchedWriteRes<[M5UnitNSHF, 511 M5UnitNSHF, 512 M5UnitS, 513 M5UnitFST, 514 M5UnitS, 515 M5UnitFST]> { let Latency = 4; 516 let NumMicroOps = 4; 517 let ResourceCycles = [1, 1, 2, 1, 2, 1]; } 518def M5WriteVSTY : SchedWriteVariant<[SchedVar<ExynosScaledIdxPred, [M5WriteVSTK]>, 519 SchedVar<NoSchedPred, [WriteVST]>]>; 520 521// Special cases. 522def M5WriteCOPY : SchedWriteVariant<[SchedVar<ExynosFPPred, [M5WriteNALU2]>, 523 SchedVar<NoSchedPred, [M5WriteZ0]>]>; 524def M5WriteMOVI : SchedWriteVariant<[SchedVar<IsZeroFPIdiomPred, [M5WriteZ0]>, 525 SchedVar<NoSchedPred, [M5WriteNALU1]>]>; 526 527// Fast forwarding. 528def M5ReadFM1 : SchedReadAdvance<+1, [M5WriteF2]>; 529def M5ReadAESM2 : SchedReadAdvance<+2, [M5WriteNCRY2]>; 530def M5ReadFMACM1 : SchedReadAdvance<+1, [M5WriteFMAC4, 531 M5WriteFMAC5]>; 532def M5ReadNMULM1 : SchedReadAdvance<+1, [M5WriteNMUL3]>; 533 534//===----------------------------------------------------------------------===// 535// Coarse scheduling model. 536 537// Branch instructions. 538def : SchedAlias<WriteBr, M5WriteZ0>; 539def : SchedAlias<WriteBrReg, M5WriteC1>; 540 541// Arithmetic and logical integer instructions. 542def : SchedAlias<WriteI, M5WriteA1W>; 543def : SchedAlias<WriteIEReg, M5WriteA1W>; // FIXME: M5WriteAX crashes TableGen. 544def : SchedAlias<WriteISReg, M5WriteA1W>; // FIXME: M5WriteAX crashes TableGen. 545def : SchedAlias<WriteIS, M5WriteA1W>; 546 547// Move instructions. 548def : SchedAlias<WriteImm, M5WriteA1W>; 549 550// Divide and multiply instructions. 551def : SchedAlias<WriteID32, M5WriteD10>; 552def : SchedAlias<WriteID64, M5WriteD16>; 553def : SchedAlias<WriteIM32, M5WriteC2>; 554def : SchedAlias<WriteIM64, M5WriteCA>; 555 556// Miscellaneous instructions. 557def : SchedAlias<WriteExtr, M5WriteAYW>; 558 559// Addressing modes. 560def : SchedAlias<WriteAdr, M5WriteZ1>; 561def : SchedAlias<ReadAdrBase, M5ReadAdrBase>; 562 563// Load instructions. 564def : SchedAlias<WriteLD, M5WriteL4>; 565def : SchedAlias<WriteLDHi, M5WriteZ4>; 566def : SchedAlias<WriteLDIdx, M5WriteLX>; 567 568// Store instructions. 569def : SchedAlias<WriteST, M5WriteS1>; 570def : SchedAlias<WriteSTP, M5WriteS1>; 571def : SchedAlias<WriteSTX, M5WriteS1>; 572def : SchedAlias<WriteSTIdx, M5WriteSX>; 573 574// Atomic load and store instructions. 575def : SchedAlias<WriteAtomic, M5WriteLGW>; 576 577// FP data instructions. 578def : SchedAlias<WriteF, M5WriteFADD2>; 579def : SchedAlias<WriteFCmp, M5WriteNMSC2>; 580def : SchedAlias<WriteFDiv, M5WriteFDIV12>; 581def : SchedAlias<WriteFMul, M5WriteFMAC3>; 582 583// FP miscellaneous instructions. 584def : SchedAlias<WriteFCvt, M5WriteFCVT2>; 585def : SchedAlias<WriteFImm, M5WriteNALU1>; 586def : SchedAlias<WriteFCopy, M5WriteNALU2>; 587 588// FP load instructions. 589def : SchedAlias<WriteVLD, M5WriteL6>; 590 591// FP store instructions. 592def : SchedAlias<WriteVST, M5WriteVST1>; 593 594// ASIMD FP instructions. 595def : SchedAlias<WriteV, M5WriteNALU1>; 596 597// Other miscellaneous instructions. 598def : WriteRes<WriteBarrier, []> { let Latency = 1; } 599def : WriteRes<WriteHint, []> { let Latency = 1; } 600def : WriteRes<WriteSys, []> { let Latency = 1; } 601 602//===----------------------------------------------------------------------===// 603// Generic fast forwarding. 604 605// TODO: Add FP register forwarding rules. 606 607def : ReadAdvance<ReadI, 0>; 608def : ReadAdvance<ReadISReg, 0>; 609def : ReadAdvance<ReadIEReg, 0>; 610def : ReadAdvance<ReadIM, 0>; 611// TODO: The forwarding for 32 bits actually saves 2 cycles. 612def : ReadAdvance<ReadIMA, 3, [WriteIM32, WriteIM64]>; 613def : ReadAdvance<ReadID, 0>; 614def : ReadAdvance<ReadExtrHi, 0>; 615def : ReadAdvance<ReadAdrBase, 0>; 616def : ReadAdvance<ReadVLD, 0>; 617 618//===----------------------------------------------------------------------===// 619// Finer scheduling model. 620 621// Branch instructions 622def : InstRW<[M5WriteB1], (instrs Bcc)>; 623def : InstRW<[M5WriteAFX], (instrs BL)>; 624def : InstRW<[M5WriteBX], (instrs BLR)>; 625def : InstRW<[M5WriteC1], (instregex "^CBN?Z[WX]")>; 626def : InstRW<[M5WriteAD], (instregex "^TBN?ZW")>; 627def : InstRW<[M5WriteAB], (instregex "^TBN?ZX")>; 628 629// Arithmetic and logical integer instructions. 630def : InstRW<[M5WriteA1W], (instregex "^(ADC|SBC)S?Wr$")>; 631def : InstRW<[M5WriteA1X], (instregex "^(ADC|SBC)S?Xr$")>; 632def : InstRW<[M5WriteAXW], (instregex "^(ADD|AND|BIC|EON|EOR|ORN|SUB)Wrs$")>; 633def : InstRW<[M5WriteAXX], (instregex "^(ADD|AND|BIC|EON|EOR|ORN|SUB)Xrs$")>; 634def : InstRW<[M5WriteAUW], (instrs ORRWrs)>; 635def : InstRW<[M5WriteAUX], (instrs ORRXrs)>; 636def : InstRW<[M5WriteAXW], (instregex "^(ADD|AND|BIC|SUB)SWrs$")>; 637def : InstRW<[M5WriteAXX], (instregex "^(ADD|AND|BIC|SUB)SXrs$")>; 638def : InstRW<[M5WriteAXW], (instregex "^(ADD|SUB)S?Wrx(64)?$")>; 639def : InstRW<[M5WriteAXX], (instregex "^(ADD|SUB)S?Xrx(64)?$")>; 640def : InstRW<[M5WriteAVW], (instrs ADDWri, ORRWri)>; 641def : InstRW<[M5WriteAVX], (instrs ADDXri, ORRXri)>; 642def : InstRW<[M5WriteA1W], (instregex "^CCM[NP]W[ir]$")>; 643def : InstRW<[M5WriteA1X], (instregex "^CCM[NP]X[ir]$")>; 644def : InstRW<[M5WriteA1W], (instrs CSELWr, CSINCWr, CSINVWr, CSNEGWr)>; 645def : InstRW<[M5WriteA1X], (instrs CSELXr, CSINCXr, CSINVXr, CSNEGXr)>; 646 647// Move instructions. 648def : InstRW<[M5WriteCOPY], (instrs COPY)>; 649def : InstRW<[M5WriteZ0], (instrs ADR, ADRP)>; 650def : InstRW<[M5WriteZ0], (instregex "^MOV[NZ][WX]i$")>; 651 652// Shift instructions. 653def : InstRW<[M5WriteA1W], (instrs ASRVWr, LSLVWr, LSRVWr, RORVWr)>; 654def : InstRW<[M5WriteA1X], (instrs ASRVXr, LSLVXr, LSRVXr, RORVXr)>; 655 656// Miscellaneous instructions. 657def : InstRW<[M5WriteAYW], (instrs EXTRWrri)>; 658def : InstRW<[M5WriteAYX], (instrs EXTRXrri)>; 659def : InstRW<[M5WriteA1W], (instrs BFMWri, SBFMWri, UBFMWri)>; 660def : InstRW<[M5WriteA1X], (instrs BFMXri, SBFMXri, UBFMXri)>; 661def : InstRW<[M5WriteA1W], (instrs CLSWr, CLZWr)>; 662def : InstRW<[M5WriteA1X], (instrs CLSXr, CLZXr)>; 663def : InstRW<[M5WriteA1W], (instrs RBITWr, REVWr, REV16Wr)>; 664def : InstRW<[M5WriteA1X], (instrs RBITXr, REVXr, REV16Xr, REV32Xr)>; 665 666// Load instructions. 667def : InstRW<[M5WriteLD, 668 WriteLDHi, 669 WriteAdr], (instregex "^LDP(SW|W|X)(post|pre)")>; 670def : InstRW<[M5WriteL5, 671 ReadAdrBase], (instregex "^LDR(BB|SBW|SBX|HH|SHW|SHX|SW|W|X)roW")>; 672def : InstRW<[WriteLDIdx, 673 ReadAdrBase], (instregex "^LDR(BB|SBW|SBX|HH|SHW|SHX|SW|W|X)roX")>; 674def : InstRW<[M5WriteL5, 675 ReadAdrBase], (instrs PRFMroW)>; 676def : InstRW<[WriteLDIdx, 677 ReadAdrBase], (instrs PRFMroX)>; 678 679// Store instructions. 680def : InstRW<[M5WriteSB, 681 ReadAdrBase], (instregex "^STR(BB|HH|W|X)roW")>; 682def : InstRW<[WriteST, 683 ReadAdrBase], (instregex "^STR(BB|HH|W|X)roX")>; 684 685// Atomic load and store instructions. 686def : InstRW<[M5WriteLGW], (instregex "^CAS(A|AL|L)?[BHW]$")>; 687def : InstRW<[M5WriteLGX], (instregex "^CAS(A|AL|L)?X$")>; 688def : InstRW<[M5WriteLFW], (instregex "^CASP(A|AL|L)?W$")>; 689def : InstRW<[M5WriteLFX], (instregex "^CASP(A|AL|L)?X$")>; 690def : InstRW<[M5WriteLGW], (instregex "^LD(ADD|CLR|EOR|SET|[SU]MAX|[SU]MIN)(A|AL|L)?[BHW]$")>; 691def : InstRW<[M5WriteLGX], (instregex "^LD(ADD|CLR|EOR|SET|[SU]MAX|[SU]MIN)(A|AL|L)?X$")>; 692def : InstRW<[M5WriteLGW], (instregex "^SWP(A|AL|L)?[BHW]$")>; 693def : InstRW<[M5WriteLGX], (instregex "^SWP(A|AL|L)?X$")>; 694 695// FP data instructions. 696def : InstRW<[M5WriteNSHF1], (instrs FABSHr, FABSSr,FABSDr)>; 697def : InstRW<[M5WriteFADD2], (instregex "^F(ADD|SUB)[HSD]rr")>; 698def : InstRW<[M5WriteFADD2], (instregex "^FADDPv.i(16|32|64)")>; 699def : InstRW<[M5WriteNEONQ], (instregex "^FCCMPE?[HSD]rr")>; 700def : InstRW<[M5WriteNMSC2], (instregex "^FCMPE?[HSD]r[ir]")>; 701def : InstRW<[M5WriteNMSC1], (instregex "^F(AC|CM)(EQ|GE|GT|LE|LT)(16|32|64|v1)")>; 702def : InstRW<[M5WriteFDIV5], (instrs FDIVHrr)>; 703def : InstRW<[M5WriteFDIV7], (instrs FDIVSrr)>; 704def : InstRW<[M5WriteFDIV12], (instrs FDIVDrr)>; 705def : InstRW<[M5WriteNMSC1], (instregex "^F(MAX|MIN)(NM)?[HSD]rr")>; 706def : InstRW<[M5WriteFMAC3], (instregex "^FN?MUL[HSD]rr")>; 707def : InstRW<[M5WriteFMAC3], (instrs FMULX16, FMULX32, FMULX64)>; 708def : InstRW<[M5WriteFMAC4, 709 M5ReadFMACM1], (instregex "^FN?M(ADD|SUB)[HSD]rrr")>; 710def : InstRW<[M5WriteNALU2], (instrs FNEGHr, FNEGSr, FNEGDr)>; 711def : InstRW<[M5WriteFCVT3A], (instregex "^FRINT.+r")>; 712def : InstRW<[M5WriteNEONH], (instregex "^FCSEL[HSD]rrr")>; 713def : InstRW<[M5WriteFSQR5], (instrs FSQRTHr)>; 714def : InstRW<[M5WriteFSQR8], (instrs FSQRTSr)>; 715def : InstRW<[M5WriteFSQR12], (instrs FSQRTDr)>; 716 717// FP miscellaneous instructions. 718def : InstRW<[M5WriteFCVT2], (instregex "^FCVT[HSD][HSD]r")>; 719def : InstRW<[M5WriteFCVTC], (instregex "^[SU]CVTF[SU][XW][HSD]ri")>; 720def : InstRW<[M5WriteFCVTB], (instregex "^FCVT[AMNPZ][SU][SU][XW][HSD]r")>; 721def : InstRW<[M5WriteNALU1], (instregex "^FMOV[HSD]i")>; 722def : InstRW<[M5WriteNALU2], (instregex "^FMOV[HSD]r")>; 723def : InstRW<[M5WriteSA], (instregex "^FMOV[WX][HSD]r")>; 724def : InstRW<[M5WriteFCVTA], (instregex "^FMOV[HSD][WX]r")>; 725def : InstRW<[M5WriteNEONI], (instregex "^FMOVXDHighr")>; 726def : InstRW<[M5WriteNEONK], (instregex "^FMOVDXHighr")>; 727def : InstRW<[M5WriteFCVT3], (instregex "^F(RECP|RSQRT)Ev1(f16|i32|i64)")>; 728def : InstRW<[M5WriteNMSC1], (instregex "^FRECPXv1")>; 729def : InstRW<[M5WriteFMAC4], (instregex "^F(RECP|RSQRT)S(16|32|64)")>; 730 731// FP load instructions. 732def : InstRW<[WriteVLD], (instregex "^LDR[SDQ]l")>; 733def : InstRW<[WriteVLD], (instregex "^LDUR[BHSDQ]i")>; 734def : InstRW<[WriteVLD, 735 WriteAdr], (instregex "^LDR[BHSDQ](post|pre)")>; 736def : InstRW<[WriteVLD], (instregex "^LDR[BHSDQ]ui")>; 737def : InstRW<[M5WriteLE, 738 ReadAdrBase], (instregex "^LDR[BHSDQ]roW")>; 739def : InstRW<[WriteVLD, 740 ReadAdrBase], (instregex "^LDR[BHSD]roX")>; 741def : InstRW<[M5WriteLY, 742 ReadAdrBase], (instrs LDRQroX)>; 743def : InstRW<[WriteVLD, 744 M5WriteLH], (instregex "^LDN?P[SD]i")>; 745def : InstRW<[M5WriteLA, 746 M5WriteLH], (instregex "^LDN?PQi")>; 747def : InstRW<[M5WriteLB, 748 M5WriteLH, 749 WriteAdr], (instregex "^LDP[SD](post|pre)")>; 750def : InstRW<[M5WriteLC, 751 M5WriteLH, 752 WriteAdr], (instregex "^LDPQ(post|pre)")>; 753 754// FP store instructions. 755def : InstRW<[WriteVST], (instregex "^STUR[BHSDQ]i")>; 756def : InstRW<[WriteVST, 757 WriteAdr], (instregex "^STR[BHSDQ](post|pre)")>; 758def : InstRW<[WriteVST], (instregex "^STR[BHSDQ]ui")>; 759def : InstRW<[WriteVST, 760 ReadAdrBase], (instregex "^STR[BHSD]ro[WX]")>; 761def : InstRW<[M5WriteVSTK, 762 ReadAdrBase], (instregex "^STRQroW")>; 763def : InstRW<[M5WriteVSTY, 764 ReadAdrBase], (instregex "^STRQroX")>; 765def : InstRW<[WriteVST], (instregex "^STN?P[SD]i")>; 766def : InstRW<[M5WriteVSTH], (instregex "^STN?PQi")>; 767def : InstRW<[WriteVST, 768 WriteAdr], (instregex "^STP[SD](post|pre)")>; 769def : InstRW<[M5WriteVSTJ, 770 WriteAdr], (instregex "^STPQ(post|pre)")>; 771 772// ASIMD instructions. 773def : InstRW<[M5WriteNHAD1], (instregex "^[SU]ABDL?v")>; 774def : InstRW<[M5WriteNHAD3], (instregex "^[SU]ABAL?v")>; 775def : InstRW<[M5WriteNMSC1], (instregex "^ABSv")>; 776def : InstRW<[M5WriteNALU2], (instregex "^(ADD|NEG|SUB)v")>; 777def : InstRW<[M5WriteNHAD3], (instregex "^[SU]?ADDL?Pv")>; 778def : InstRW<[M5WriteNHAD3], (instregex "^[SU]H(ADD|SUB)v")>; 779def : InstRW<[M5WriteNHAD3], (instregex "^[SU](ADD|SUB)[LW]v")>; 780def : InstRW<[M5WriteNHAD3], (instregex "^R?(ADD|SUB)HN2?v")>; 781def : InstRW<[M5WriteNHAD3], (instregex "^[SU]Q(ADD|SUB)v")>; 782def : InstRW<[M5WriteNHAD3], (instregex "^(SU|US)QADDv")>; 783def : InstRW<[M5WriteNHAD3], (instregex "^[SU]RHADDv")>; 784def : InstRW<[M5WriteNMSC1], (instregex "^SQ(ABS|NEG)v")>; 785def : InstRW<[M5WriteNHAD3], (instregex "^[SU]?ADDL?Vv")>; 786def : InstRW<[M5WriteNMSC1], (instregex "^CM(EQ|GE|GT|HI|HS|LE|LT)v")>; 787def : InstRW<[M5WriteNALU2], (instregex "^CMTSTv")>; 788def : InstRW<[M5WriteNALU2], (instregex "^(AND|BIC|EOR|NOT|ORN|ORR)v")>; 789def : InstRW<[M5WriteNMSC1], (instregex "^[SU](MIN|MAX)v")>; 790def : InstRW<[M5WriteNMSC2], (instregex "^[SU](MIN|MAX)Pv")>; 791def : InstRW<[M5WriteNHAD3], (instregex "^[SU](MIN|MAX)Vv")>; 792def : InstRW<[M5WriteNMUL3], (instregex "^(SQR?D)?MULH?v")>; 793def : InstRW<[M5WriteNMUL3, 794 M5ReadNMULM1], (instregex "^ML[AS]v")>; 795def : InstRW<[M5WriteNMUL3, 796 M5ReadNMULM1], (instregex "^SQRDML[AS]H")>; 797def : InstRW<[M5WriteNMUL3], (instregex "^(S|U|SQD)ML[AS]L(v1(i32|i64)|v2i32|v4i16|v8i8)")>; 798def : InstRW<[M5WriteNMUL3, 799 M5ReadNMULM1], (instregex "^(S|U|SQD)ML[AS]L(v4i32|v8i16|v16i8)")>; 800def : InstRW<[M5WriteNMUL3, 801 M5ReadNMULM1], (instregex "^(S|U|SQD)MULL(v1(i32|i64)|v2i32|v4i16|v8i8)")>; 802def : InstRW<[M5WriteNMUL3, 803 M5ReadNMULM1], (instregex "^(S|U|SQD)MULL(v4i32|v8i16|v16i8)")>; 804def : InstRW<[M5WriteNDOT2], (instregex "^[SU]DOT(lane)?v")>; 805def : InstRW<[M5WriteNHAD3], (instregex "^[SU]ADALPv")>; 806def : InstRW<[M5WriteNSHT4A], (instregex "^[SU]R?SRA[dv]")>; 807def : InstRW<[M5WriteNSHT2], (instregex "^SHL[dv]")>; 808def : InstRW<[M5WriteNSHT2], (instregex "^S[LR]I[dv]")>; 809def : InstRW<[M5WriteNSHT2], (instregex "^[SU]SH[LR][dv]")>; 810def : InstRW<[M5WriteNSHT2], (instregex "^[SU]?SHLLv")>; 811def : InstRW<[M5WriteNSHT4A], (instregex "^[SU]?Q?R?SHRU?N[bhsv]")>; 812def : InstRW<[M5WriteNSHT4A], (instregex "^[SU]RSH[LR][dv]")>; 813def : InstRW<[M5WriteNSHT4A], (instregex "^[SU]QR?SHLU?[bhsdv]")>; 814 815// ASIMD FP instructions. 816def : InstRW<[M5WriteNSHF2], (instregex "^FABSv.f(16|32|64)")>; 817def : InstRW<[M5WriteFADD2], (instregex "^F(ABD|ADD|SUB)v.f(16|32|64)")>; 818def : InstRW<[M5WriteFADD2], (instregex "^FADDPv.f(16|32|64)")>; 819def : InstRW<[M5WriteNMSC1], (instregex "^F(AC|CM)(EQ|GE|GT|LE|LT)v[^1]")>; 820def : InstRW<[M5WriteFCVT2], (instregex "^FCVT(L|N|XN)v")>; 821def : InstRW<[M5WriteFCVT2A], (instregex "^FCVT[AMNPZ][SU]v")>; 822def : InstRW<[M5WriteFCVT2], (instregex "^[SU]CVTFv.[fi](16|32|64)")>; 823def : InstRW<[M5WriteFDIV7], (instrs FDIVv4f16)>; 824def : InstRW<[M5WriteNEONV], (instrs FDIVv8f16)>; 825def : InstRW<[M5WriteFDIV7], (instrs FDIVv2f32)>; 826def : InstRW<[M5WriteNEONV], (instrs FDIVv4f32)>; 827def : InstRW<[M5WriteNEONW], (instrs FDIVv2f64)>; 828def : InstRW<[M5WriteNMSC1], (instregex "^F(MAX|MIN)(NM)?v")>; 829def : InstRW<[M5WriteNMSC2], (instregex "^F(MAX|MIN)(NM)?Pv")>; 830def : InstRW<[M5WriteNEONZ], (instregex "^F(MAX|MIN)(NM)?Vv")>; 831def : InstRW<[M5WriteFMAC3], (instregex "^FMULX?v.[fi](16|32|64)")>; 832def : InstRW<[M5WriteFMAC4, 833 M5ReadFMACM1], (instregex "^FML[AS]v.[fi](16|32|64)")>; 834def : InstRW<[M5WriteNALU2], (instregex "^FNEGv.f(16|32|64)")>; 835def : InstRW<[M5WriteFCVT3A], (instregex "^FRINT[AIMNPXZ]v")>; 836def : InstRW<[M5WriteFSQR7], (instrs FSQRTv4f16)>; 837def : InstRW<[M5WriteNEONU], (instrs FSQRTv8f16)>; 838def : InstRW<[M5WriteFSQR8], (instrs FSQRTv2f32)>; 839def : InstRW<[M5WriteNEONX], (instrs FSQRTv4f32)>; 840def : InstRW<[M5WriteNEONY], (instrs FSQRTv2f64)>; 841 842// ASIMD miscellaneous instructions. 843def : InstRW<[M5WriteNALU2], (instregex "^RBITv")>; 844def : InstRW<[M5WriteNALU2], (instregex "^(BIF|BIT|BSL)v")>; 845def : InstRW<[M5WriteNALU2], (instregex "^CL[STZ]v")>; 846def : InstRW<[M5WriteNEONB], (instregex "^DUPv.+gpr")>; 847def : InstRW<[M5WriteNSHF2], (instregex "^CPY")>; 848def : InstRW<[M5WriteNSHF2], (instregex "^DUPv.+lane")>; 849def : InstRW<[M5WriteNSHF2], (instregex "^EXTv")>; 850def : InstRW<[M5WriteNSHT4A], (instregex "^XTNv")>; 851def : InstRW<[M5WriteNSHT4A], (instregex "^[SU]?QXTU?Nv")>; 852def : InstRW<[M5WriteNEONB], (instregex "^INSv.+gpr")>; 853def : InstRW<[M5WriteNSHF2], (instregex "^INSv.+lane")>; 854def : InstRW<[M5WriteMOVI], (instregex "^(MOV|MVN)I")>; 855def : InstRW<[M5WriteNALU1], (instregex "^FMOVv.f(16|32|64)")>; 856def : InstRW<[M5WriteFCVT3], (instregex "^F(RECP|RSQRT)Ev[248]f(16|32|64)")>; 857def : InstRW<[M5WriteFCVT3], (instregex "^U(RECP|RSQRT)Ev[24]i32")>; 858def : InstRW<[M5WriteFMAC4], (instregex "^F(RECP|RSQRT)Sv.f(16|32|64)")>; 859def : InstRW<[M5WriteNSHF2], (instregex "^REV(16|32|64)v")>; 860def : InstRW<[M5WriteNSHFA], (instregex "^TB[LX]v(8|16)i8One")>; 861def : InstRW<[M5WriteNSHFB], (instregex "^TB[LX]v(8|16)i8Two")>; 862def : InstRW<[M5WriteNSHFC], (instregex "^TB[LX]v(8|16)i8Three")>; 863def : InstRW<[M5WriteNSHFD], (instregex "^TB[LX]v(8|16)i8Four")>; 864def : InstRW<[M5WriteNEONP], (instregex "^[SU]MOVv")>; 865def : InstRW<[M5WriteNSHF2], (instregex "^(TRN|UZP|ZIP)[12]v")>; 866 867// ASIMD load instructions. 868def : InstRW<[WriteVLD], (instregex "LD1Onev(8b|16b|4h|8h|2s|4s|1d|2d)$")>; 869def : InstRW<[WriteVLD, 870 M5WriteA1X, 871 WriteAdr], (instregex "LD1Onev(8b|16b|4h|8h|2s|4s|1d|2d)_POST$")>; 872def : InstRW<[M5WriteVLDA], (instregex "LD1Twov(8b|16b|4h|8h|2s|4s|1d|2d)$")>; 873def : InstRW<[M5WriteVLDA, 874 M5WriteA1X, 875 WriteAdr], (instregex "LD1Twov(8b|16b|4h|8h|2s|4s|1d|2d)_POST$")>; 876def : InstRW<[M5WriteVLDB], (instregex "LD1Threev(8b|16b|4h|8h|2s|4s|1d|2d)$")>; 877def : InstRW<[M5WriteVLDB, 878 M5WriteA1X, 879 WriteAdr], (instregex "LD1Threev(8b|16b|4h|8h|2s|4s|1d|2d)_POST$")>; 880def : InstRW<[M5WriteVLDC], (instregex "LD1Fourv(8b|16b|4h|8h|2s|4s|1d|2d)$")>; 881def : InstRW<[M5WriteVLDC, 882 M5WriteA1X, 883 WriteAdr], (instregex "LD1Fourv(8b|16b|4h|8h|2s|4s|1d|2d)_POST$")>; 884def : InstRW<[M5WriteVLDD], (instregex "LD1i(8|16|32|64)$")>; 885def : InstRW<[M5WriteVLDD, 886 M5WriteA1X, 887 WriteAdr], (instregex "LD1i(8|16|32|64)_POST$")>; 888def : InstRW<[WriteVLD], (instregex "LD1Rv(8b|16b|4h|8h|2s|4s|1d|2d)$")>; 889def : InstRW<[WriteVLD, 890 M5WriteA1X, 891 WriteAdr], (instregex "LD1Rv(8b|16b|4h|8h|2s|4s|1d|2d)_POST$")>; 892def : InstRW<[M5WriteVLDF], (instregex "LD2Twov(8b|16b|4h|8h|2s|4s|2d)$")>; 893def : InstRW<[M5WriteVLDF, 894 M5WriteA1X, 895 WriteAdr], (instregex "LD2Twov(8b|16b|4h|8h|2s|4s|2d)_POST$")>; 896def : InstRW<[M5WriteVLDG], (instregex "LD2i(8|16|32|64)$")>; 897def : InstRW<[M5WriteVLDG, 898 M5WriteA1X, 899 WriteAdr], (instregex "LD2i(8|16|32|64)_POST$")>; 900def : InstRW<[M5WriteVLDA], (instregex "LD2Rv(8b|16b|4h|8h|2s|4s|1d|2d)$")>; 901def : InstRW<[M5WriteVLDA, 902 M5WriteA1X, 903 WriteAdr], (instregex "LD2Rv(8b|16b|4h|8h|2s|4s|1d|2d)_POST$")>; 904def : InstRW<[M5WriteVLDI], (instregex "LD3Threev(8b|16b|4h|8h|2s|4s|2d)$")>; 905def : InstRW<[M5WriteVLDI, 906 M5WriteA1X, 907 WriteAdr], (instregex "LD3Threev(8b|16b|4h|8h|2s|4s|2d)_POST$")>; 908def : InstRW<[M5WriteVLDJ], (instregex "LD3i(8|16|32)$")>; 909def : InstRW<[M5WriteVLDJ, 910 M5WriteA1X, 911 WriteAdr], (instregex "LD3i(8|16|32)_POST$")>; 912def : InstRW<[M5WriteVLDL], (instregex "LD3i64$")>; 913def : InstRW<[M5WriteVLDL, 914 M5WriteA1X, 915 WriteAdr], (instregex "LD3i64_POST$")>; 916def : InstRW<[M5WriteVLDB], (instregex "LD3Rv(8b|16b|4h|8h|2s|4s|1d|2d)$")>; 917def : InstRW<[M5WriteVLDB, 918 M5WriteA1X], (instregex "LD3Rv(8b|16b|4h|8h|2s|4s|1d|2d)_POST$")>; 919def : InstRW<[M5WriteVLDN], (instregex "LD4Fourv(8b|16b|4h|8h|2s|4s|2d)$")>; 920def : InstRW<[M5WriteVLDN, 921 M5WriteA1X, 922 WriteAdr], (instregex "LD4Fourv(8b|16b|4h|8h|2s|4s|2d)_POST$")>; 923def : InstRW<[M5WriteVLDK], (instregex "LD4i(8|16|32)$")>; 924def : InstRW<[M5WriteVLDK, 925 M5WriteA1X, 926 WriteAdr], (instregex "LD4i(8|16|32)_POST$")>; 927def : InstRW<[M5WriteVLDM], (instregex "LD4i64$")>; 928def : InstRW<[M5WriteVLDM, 929 M5WriteA1X, 930 WriteAdr], (instregex "LD4i64_POST$")>; 931def : InstRW<[M5WriteVLDC], (instregex "LD4Rv(8b|16b|4h|8h|2s|4s|1d|2d)$")>; 932def : InstRW<[M5WriteVLDC, 933 M5WriteA1X, 934 WriteAdr], (instregex "LD4Rv(8b|16b|4h|8h|2s|4s|1d|2d)_POST$")>; 935 936// ASIMD store instructions. 937def : InstRW<[WriteVST], (instregex "ST1Onev(8b|16b|4h|8h|2s|4s|1d|2d)$")>; 938def : InstRW<[WriteVST, 939 M5WriteA1X, 940 WriteAdr], (instregex "ST1Onev(8b|16b|4h|8h|2s|4s|1d|2d)_POST$")>; 941def : InstRW<[M5WriteVSTA], (instregex "ST1Twov(8b|16b|4h|8h|2s|4s|1d|2d)$")>; 942def : InstRW<[M5WriteVSTA, 943 M5WriteA1X, 944 WriteAdr], (instregex "ST1Twov(8b|16b|4h|8h|2s|4s|1d|2d)_POST$")>; 945 946def : InstRW<[M5WriteVSTB], (instregex "ST1Threev(8b|16b|4h|8h|2s|4s|1d|2d)$")>; 947def : InstRW<[M5WriteVSTB, 948 M5WriteA1X, 949 WriteAdr], (instregex "ST1Threev(8b|16b|4h|8h|2s|4s|1d|2d)_POST$")>; 950def : InstRW<[M5WriteVSTC], (instregex "ST1Fourv(8b|16b|4h|8h|2s|4s|1d|2d)$")>; 951def : InstRW<[M5WriteVSTC, 952 M5WriteA1X, 953 WriteAdr], (instregex "ST1Fourv(8b|16b|4h|8h|2s|4s|1d|2d)_POST$")>; 954def : InstRW<[WriteVST], (instregex "ST1i(8|16|32|64)$")>; 955def : InstRW<[WriteVST, 956 M5WriteA1X, 957 WriteAdr], (instregex "ST1i(8|16|32|64)_POST$")>; 958def : InstRW<[M5WriteVSTD], (instregex "ST2Twov(8b|4h|2s)$")>; 959def : InstRW<[M5WriteVSTD, 960 M5WriteA1X, 961 WriteAdr], (instregex "ST2Twov(8b|4h|2s)_POST$")>; 962def : InstRW<[M5WriteVSTE], (instregex "ST2Twov(16b|8h|4s|2d)$")>; 963def : InstRW<[M5WriteVSTE, 964 M5WriteA1X, 965 WriteAdr], (instregex "ST2Twov(16b|8h|4s|2d)_POST$")>; 966def : InstRW<[M5WriteVSTD], (instregex "ST2i(8|16|32|64)$")>; 967def : InstRW<[M5WriteVSTD, 968 M5WriteA1X, 969 WriteAdr], (instregex "ST2i(8|16|32|64)_POST$")>; 970def : InstRW<[M5WriteVSTF], (instregex "ST3Threev(8b|4h|2s)$")>; 971def : InstRW<[M5WriteVSTF, 972 M5WriteA1X, 973 WriteAdr], (instregex "ST3Threev(8b|4h|2s)_POST$")>; 974def : InstRW<[M5WriteVSTG], (instregex "ST3Threev(16b|8h|4s|2d)$")>; 975def : InstRW<[M5WriteVSTG, 976 M5WriteA1X, 977 WriteAdr], (instregex "ST3Threev(16b|8h|4s|2d)_POST$")>; 978def : InstRW<[M5WriteVSTA], (instregex "ST3i(8|16|32|64)$")>; 979def : InstRW<[M5WriteVSTA, 980 M5WriteA1X, 981 WriteAdr], (instregex "ST3i(8|16|32|64)_POST$")>; 982def : InstRW<[M5WriteVSTL], (instregex "ST4Fourv(8b|4h|2s)$")>; 983def : InstRW<[M5WriteVSTL, 984 M5WriteA1X, 985 WriteAdr], (instregex "ST4Fourv(8b|4h|2s)_POST$")>; 986def : InstRW<[M5WriteVSTI], (instregex "ST4Fourv(16b|8h|4s|2d)$")>; 987def : InstRW<[M5WriteVSTI, 988 M5WriteA1X, 989 WriteAdr], (instregex "ST4Fourv(16b|8h|4s|2d)_POST$")>; 990def : InstRW<[M5WriteVSTA], (instregex "ST4i(8|16|32|64)$")>; 991def : InstRW<[M5WriteVSTA, 992 M5WriteA1X, 993 WriteAdr], (instregex "ST4i(8|16|32|64)_POST$")>; 994 995// Cryptography instructions. 996def : InstRW<[M5WriteNCRY2], (instregex "^AES[DE]")>; 997def : InstRW<[M5WriteNCRY2, 998 M5ReadAESM2], (instregex "^AESI?MC")>; 999def : InstRW<[M5WriteNCRY2A], (instregex "^PMULv")>; 1000def : InstRW<[M5WriteNCRY1A], (instregex "^PMULLv(1|8)i")>; 1001def : InstRW<[M5WriteNCRY3A], (instregex "^PMULLv(2|16)i")>; 1002def : InstRW<[M5WriteNCRY2A], (instregex "^SHA1(H|SU[01])")>; 1003def : InstRW<[M5WriteNCRY5A], (instregex "^SHA1[CMP]")>; 1004def : InstRW<[M5WriteNCRY2A], (instrs SHA256SU0rr)>; 1005def : InstRW<[M5WriteNCRY5A], (instrs SHA256SU1rrr)>; 1006def : InstRW<[M5WriteNCRY5A], (instregex "^SHA256H2?")>; 1007 1008// CRC instructions. 1009def : InstRW<[M5WriteF2, 1010 M5ReadFM1], (instregex "^CRC32C?[BHWX]")>; 1011 1012} // SchedModel = ExynosM5Model 1013