AArch64SchedExynosM4.td revision 363496
1//=- AArch64SchedExynosM4.td - Samsung Exynos M4 Sched Defs --*- tablegen -*-=// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file defines the machine model for the Samsung Exynos M4 to support 10// instruction scheduling and other instruction cost heuristics. 11// 12//===----------------------------------------------------------------------===// 13 14//===----------------------------------------------------------------------===// 15// The Exynos-M4 is an advanced superscalar microprocessor with a 6-wide 16// in-order stage for decode and dispatch and a wider issue stage. 17// The execution units and loads and stores are out-of-order. 18 19def ExynosM4Model : SchedMachineModel { 20 let IssueWidth = 6; // Up to 6 uops per cycle. 21 let MicroOpBufferSize = 228; // ROB size. 22 let LoopMicroOpBufferSize = 48; // Based on the instruction queue size. 23 let LoadLatency = 4; // Optimistic load cases. 24 let MispredictPenalty = 16; // Minimum branch misprediction penalty. 25 let CompleteModel = 1; // Use the default model otherwise. 26 27 list<Predicate> UnsupportedFeatures = !listconcat(SVEUnsupported.F, 28 PAUnsupported.F); 29} 30 31//===----------------------------------------------------------------------===// 32// Define each kind of processor resource and number available on the Exynos-M4. 33 34let SchedModel = ExynosM4Model in { 35 36def M4UnitA : ProcResource<2>; // Simple integer 37def M4UnitC : ProcResource<2>; // Simple and complex integer 38let Super = M4UnitC, BufferSize = 1 in 39def M4UnitD : ProcResource<1>; // Integer division (inside C0, serialized) 40let Super = M4UnitC in 41def M4UnitE : ProcResource<1>; // CRC (inside C0) 42def M4UnitB : ProcResource<2>; // Branch 43def M4UnitL0 : ProcResource<1>; // Load 44def M4UnitS0 : ProcResource<1>; // Store 45def M4PipeLS : ProcResource<1>; // Load/Store 46let Super = M4PipeLS in { 47 def M4UnitL1 : ProcResource<1>; 48 def M4UnitS1 : ProcResource<1>; 49} 50def M4PipeF0 : ProcResource<1>; // FP #0 51let Super = M4PipeF0 in { 52 def M4UnitFMAC0 : ProcResource<1>; // FP multiplication 53 def M4UnitFADD0 : ProcResource<1>; // Simple FP 54 def M4UnitFCVT0 : ProcResource<1>; // FP conversion 55 def M4UnitNALU0 : ProcResource<1>; // Simple vector 56 def M4UnitNHAD : ProcResource<1>; // Horizontal vector 57 def M4UnitNMSC : ProcResource<1>; // FP and vector miscellanea 58 def M4UnitNMUL0 : ProcResource<1>; // Vector multiplication 59 def M4UnitNSHT0 : ProcResource<1>; // Vector shifting 60 def M4UnitNSHF0 : ProcResource<1>; // Vector shuffling 61 def M4UnitNCRY0 : ProcResource<1>; // Cryptographic 62} 63def M4PipeF1 : ProcResource<1>; // FP #1 64let Super = M4PipeF1 in { 65 def M4UnitFMAC1 : ProcResource<1>; // FP multiplication 66 def M4UnitFADD1 : ProcResource<1>; // Simple FP 67 def M4UnitFDIV0 : ProcResource<2>; // FP division (serialized) 68 def M4UnitFSQR0 : ProcResource<2>; // FP square root (serialized) 69 def M4UnitFST0 : ProcResource<1>; // FP store 70 def M4UnitNALU1 : ProcResource<1>; // Simple vector 71 def M4UnitNSHT1 : ProcResource<1>; // Vector shifting 72 def M4UnitNSHF1 : ProcResource<1>; // Vector shuffling 73} 74def M4PipeF2 : ProcResource<1>; // FP #2 75let Super = M4PipeF2 in { 76 def M4UnitFMAC2 : ProcResource<1>; // FP multiplication 77 def M4UnitFADD2 : ProcResource<1>; // Simple FP 78 def M4UnitFCVT1 : ProcResource<1>; // FP conversion 79 def M4UnitFDIV1 : ProcResource<2>; // FP division (serialized) 80 def M4UnitFSQR1 : ProcResource<2>; // FP square root (serialized) 81 def M4UnitFST1 : ProcResource<1>; // FP store 82 def M4UnitNALU2 : ProcResource<1>; // Simple vector 83 def M4UnitNMUL1 : ProcResource<1>; // Vector multiplication 84 def M4UnitNSHT2 : ProcResource<1>; // Vector shifting 85 def M4UnitNCRY1 : ProcResource<1>; // Cryptographic 86} 87 88def M4UnitALU : ProcResGroup<[M4UnitA, 89 M4UnitC]>; 90def M4UnitL : ProcResGroup<[M4UnitL0, 91 M4UnitL1]>; 92def M4UnitS : ProcResGroup<[M4UnitS0, 93 M4UnitS1]>; 94def M4UnitFMAC : ProcResGroup<[M4UnitFMAC0, 95 M4UnitFMAC1, 96 M4UnitFMAC2]>; 97def M4UnitFMACH : ProcResGroup<[M4UnitFMAC0, 98 M4UnitFMAC1]>; 99def M4UnitFADD : ProcResGroup<[M4UnitFADD0, 100 M4UnitFADD1, 101 M4UnitFADD2]>; 102def M4UnitFADDH : ProcResGroup<[M4UnitFADD0, 103 M4UnitFADD1]>; 104def M4UnitFCVT : ProcResGroup<[M4UnitFCVT0, 105 M4UnitFCVT1]>; 106def M4UnitFCVTH : ProcResGroup<[M4UnitFCVT0]>; 107def M4UnitFDIV : ProcResGroup<[M4UnitFDIV0, 108 M4UnitFDIV1]>; 109def M4UnitFDIVH : ProcResGroup<[M4UnitFDIV0]>; 110def M4UnitFSQR : ProcResGroup<[M4UnitFSQR0, 111 M4UnitFSQR1]>; 112def M4UnitFSQRH : ProcResGroup<[M4UnitFSQR0]>; 113def M4UnitFST : ProcResGroup<[M4UnitFST0, 114 M4UnitFST1]>; 115def M4UnitNALU : ProcResGroup<[M4UnitNALU0, 116 M4UnitNALU1, 117 M4UnitNALU2]>; 118def M4UnitNALUH : ProcResGroup<[M4UnitNALU0, 119 M4UnitNALU1]>; 120def M4UnitNMUL : ProcResGroup<[M4UnitNMUL0, 121 M4UnitNMUL1]>; 122def M4UnitNSHT : ProcResGroup<[M4UnitNSHT0, 123 M4UnitNSHT1, 124 M4UnitNSHT2]>; 125def M4UnitNSHF : ProcResGroup<[M4UnitNSHF0, 126 M4UnitNSHF1]>; 127def M4UnitNSHFH : ProcResGroup<[M4UnitNSHF0]>; 128def M4UnitNCRY : ProcResGroup<[M4UnitNCRY0, 129 M4UnitNCRY1]>; 130 131//===----------------------------------------------------------------------===// 132// Resources details. 133 134def M4WriteZ0 : SchedWriteRes<[]> { let Latency = 0; } 135def M4WriteZ1 : SchedWriteRes<[]> { let Latency = 1; 136 let NumMicroOps = 0; } 137def M4WriteZ4 : SchedWriteRes<[]> { let Latency = 4; 138 let NumMicroOps = 0; } 139 140def M4WriteA1 : SchedWriteRes<[M4UnitALU]> { let Latency = 1; } 141def M4WriteA2 : SchedWriteRes<[M4UnitALU]> { let Latency = 2; } 142def M4WriteAA : SchedWriteRes<[M4UnitALU]> { let Latency = 2; 143 let ResourceCycles = [2]; } 144def M4WriteAB : SchedWriteRes<[M4UnitALU, 145 M4UnitC]> { let Latency = 2; 146 let NumMicroOps = 2; } 147def M4WriteAC : SchedWriteRes<[M4UnitALU, 148 M4UnitALU, 149 M4UnitC]> { let Latency = 3; 150 let NumMicroOps = 3; } 151def M4WriteAD : SchedWriteRes<[M4UnitALU, 152 M4UnitC]> { let Latency = 2; 153 let NumMicroOps = 2; } 154def M4WriteAF : SchedWriteRes<[M4UnitALU]> { let Latency = 2; 155 let NumMicroOps = 2; } 156def M4WriteAU : SchedWriteVariant<[SchedVar<IsCopyIdiomPred, [M4WriteZ0]>, 157 SchedVar<ExynosArithPred, [M4WriteA1]>, 158 SchedVar<ExynosLogicExPred, [M4WriteA1]>, 159 SchedVar<NoSchedPred, [M4WriteAA]>]>; 160def M4WriteAV : SchedWriteVariant<[SchedVar<ExynosResetPred, [M4WriteZ0]>, 161 SchedVar<ExynosArithPred, [M4WriteA1]>, 162 SchedVar<ExynosLogicExPred, [M4WriteA1]>, 163 SchedVar<NoSchedPred, [M4WriteAA]>]>; 164def M4WriteAX : SchedWriteVariant<[SchedVar<ExynosArithPred, [M4WriteA1]>, 165 SchedVar<ExynosLogicExPred, [M4WriteA1]>, 166 SchedVar<NoSchedPred, [M4WriteAA]>]>; 167def M4WriteAY : SchedWriteVariant<[SchedVar<ExynosRotateRightImmPred, [M4WriteA1]>, 168 SchedVar<NoSchedPred, [M4WriteAF]>]>; 169 170def M4WriteB1 : SchedWriteRes<[M4UnitB]> { let Latency = 1; } 171def M4WriteBX : SchedWriteVariant<[SchedVar<ExynosBranchLinkLRPred, [M4WriteAC]>, 172 SchedVar<NoSchedPred, [M4WriteAB]>]>; 173 174def M4WriteC1 : SchedWriteRes<[M4UnitC]> { let Latency = 1; } 175def M4WriteC3 : SchedWriteRes<[M4UnitC]> { let Latency = 3; } 176def M4WriteCA : SchedWriteRes<[M4UnitC]> { let Latency = 4; 177 let ResourceCycles = [2]; } 178 179def M4WriteD12 : SchedWriteRes<[M4UnitD]> { let Latency = 12; 180 let ResourceCycles = [12]; } 181def M4WriteD21 : SchedWriteRes<[M4UnitD]> { let Latency = 21; 182 let ResourceCycles = [21]; } 183 184def M4WriteE2 : SchedWriteRes<[M4UnitE]> { let Latency = 2; } 185 186def M4WriteL4 : SchedWriteRes<[M4UnitL]> { let Latency = 4; } 187def M4WriteL5 : SchedWriteRes<[M4UnitL]> { let Latency = 5; } 188def M4WriteLA : SchedWriteRes<[M4UnitL, 189 M4UnitL]> { let Latency = 5; 190 let NumMicroOps = 1; } 191def M4WriteLB : SchedWriteRes<[M4UnitA, 192 M4UnitL]> { let Latency = 5; 193 let NumMicroOps = 2; } 194def M4WriteLC : SchedWriteRes<[M4UnitA, 195 M4UnitL, 196 M4UnitL]> { let Latency = 5; 197 let NumMicroOps = 2; } 198def M4WriteLD : SchedWriteRes<[M4UnitA, 199 M4UnitL]> { let Latency = 4; 200 let NumMicroOps = 2; } 201def M4WriteLE : SchedWriteRes<[M4UnitA, 202 M4UnitL]> { let Latency = 6; 203 let NumMicroOps = 2; } 204def M4WriteLH : SchedWriteRes<[]> { let Latency = 5; 205 let NumMicroOps = 0; } 206def M4WriteLX : SchedWriteVariant<[SchedVar<ExynosScaledIdxPred, [M4WriteL5]>, 207 SchedVar<NoSchedPred, [M4WriteL4]>]>; 208def M4WriteLY : SchedWriteVariant<[SchedVar<ExynosScaledIdxPred, [M4WriteLE]>, 209 SchedVar<NoSchedPred, [M4WriteL5]>]>; 210 211def M4WriteS1 : SchedWriteRes<[M4UnitS]> { let Latency = 1; } 212def M4WriteSA : SchedWriteRes<[M4UnitS0]> { let Latency = 3; } 213def M4WriteSB : SchedWriteRes<[M4UnitA, 214 M4UnitS]> { let Latency = 2; 215 let NumMicroOps = 1; } 216def M4WriteSX : SchedWriteVariant<[SchedVar<ExynosScaledIdxPred, [M4WriteSB]>, 217 SchedVar<NoSchedPred, [M4WriteS1]>]>; 218 219def M4ReadAdrBase : SchedReadVariant<[SchedVar< 220 MCSchedPredicate< 221 CheckAny< 222 [ScaledIdxFn, 223 ExynosScaledIdxFn]>>, [ReadDefault]>, 224 SchedVar<NoSchedPred, [ReadDefault]>]>; 225 226def M4WriteNEONA : SchedWriteRes<[M4UnitNSHF, 227 M4UnitFADD]> { let Latency = 3; 228 let NumMicroOps = 2; } 229def M4WriteNEONB : SchedWriteRes<[M4UnitNALU, 230 M4UnitS0]> { let Latency = 5; 231 let NumMicroOps = 2; } 232def M4WriteNEOND : SchedWriteRes<[M4UnitNSHF, 233 M4UnitFST]> { let Latency = 6; 234 let NumMicroOps = 2; } 235def M4WriteNEONH : SchedWriteRes<[M4UnitNALU, 236 M4UnitS0]> { let Latency = 5; 237 let NumMicroOps = 2; } 238def M4WriteNEONI : SchedWriteRes<[M4UnitNSHF, 239 M4UnitS0]> { let Latency = 2; 240 let NumMicroOps = 2; } 241def M4WriteNEONJ : SchedWriteRes<[M4UnitNMSC, 242 M4UnitS0]> { let Latency = 4; } 243def M4WriteNEONK : SchedWriteRes<[M4UnitNSHF, 244 M4UnitNMSC, 245 M4UnitS0]> { let Latency = 5; 246 let NumMicroOps = 2; } 247def M4WriteNEONL : SchedWriteRes<[M4UnitNMUL]> { let Latency = 3; } 248def M4WriteNEONN : SchedWriteRes<[M4UnitNMSC, 249 M4UnitNMSC]> { let Latency = 5; 250 let NumMicroOps = 2; } 251def M4WriteNEONO : SchedWriteRes<[M4UnitNMSC, 252 M4UnitNMSC, 253 M4UnitNMSC]> { let Latency = 8; 254 let NumMicroOps = 3; } 255def M4WriteNEONP : SchedWriteRes<[M4UnitNSHF, 256 M4UnitNMSC]> { let Latency = 4; 257 let NumMicroOps = 2; } 258def M4WriteNEONQ : SchedWriteRes<[M4UnitNMSC, 259 M4UnitC]> { let Latency = 3; 260 let NumMicroOps = 1; } 261def M4WriteNEONR : SchedWriteRes<[M4UnitFCVT0, 262 M4UnitS0]> { let Latency = 4; 263 let NumMicroOps = 1; } 264def M4WriteNEONV : SchedWriteRes<[M4UnitFDIV, 265 M4UnitFDIV]> { let Latency = 7; 266 let ResourceCycles = [6, 6]; } 267def M4WriteNEONVH : SchedWriteRes<[M4UnitFDIVH, 268 M4UnitFDIVH]> { let Latency = 7; 269 let ResourceCycles = [6, 6]; } 270def M4WriteNEONW : SchedWriteRes<[M4UnitFDIV, 271 M4UnitFDIV]> { let Latency = 12; 272 let ResourceCycles = [9, 9]; } 273def M4WriteNEONX : SchedWriteRes<[M4UnitFSQR, 274 M4UnitFSQR]> { let Latency = 8; 275 let ResourceCycles = [7, 7]; } 276def M4WriteNEONXH : SchedWriteRes<[M4UnitFSQRH, 277 M4UnitFSQRH]> { let Latency = 7; 278 let ResourceCycles = [6, 6]; } 279def M4WriteNEONY : SchedWriteRes<[M4UnitFSQR, 280 M4UnitFSQR]> { let Latency = 12; 281 let ResourceCycles = [9, 9]; } 282def M4WriteNEONZ : SchedWriteVariant<[SchedVar<ExynosQFormPred, [M4WriteNEONO]>, 283 SchedVar<NoSchedPred, [M4WriteNEONN]>]>; 284 285def M4WriteFADD2 : SchedWriteRes<[M4UnitFADD]> { let Latency = 2; } 286def M4WriteFADD2H : SchedWriteRes<[M4UnitFADDH]> { let Latency = 2; } 287 288def M4WriteFCVT2 : SchedWriteRes<[M4UnitFCVT]> { let Latency = 2; } 289def M4WriteFCVT2A : SchedWriteRes<[M4UnitFCVT0]> { let Latency = 2; } 290def M4WriteFCVT2H : SchedWriteRes<[M4UnitFCVTH]> { let Latency = 2; } 291def M4WriteFCVT3 : SchedWriteRes<[M4UnitFCVT]> { let Latency = 3; } 292def M4WriteFCVT3A : SchedWriteRes<[M4UnitFCVT0]> { let Latency = 3; } 293def M4WriteFCVT3H : SchedWriteRes<[M4UnitFCVTH]> { let Latency = 3; } 294def M4WriteFCVT4 : SchedWriteRes<[M4UnitFCVT]> { let Latency = 4; } 295def M4WriteFCVT4A : SchedWriteRes<[M4UnitFCVT0]> { let Latency = 4; } 296def M4WriteFCVT6A : SchedWriteRes<[M4UnitFCVT0]> { let Latency = 6; } 297 298def M4WriteFDIV7 : SchedWriteRes<[M4UnitFDIV]> { let Latency = 7; 299 let ResourceCycles = [6]; } 300def M4WriteFDIV7H : SchedWriteRes<[M4UnitFDIVH]> { let Latency = 7; 301 let ResourceCycles = [6]; } 302def M4WriteFDIV12 : SchedWriteRes<[M4UnitFDIV]> { let Latency = 12; 303 let ResourceCycles = [9]; } 304 305def M4WriteFMAC2H : SchedWriteRes<[M4UnitFMACH]> { let Latency = 2; } 306def M4WriteFMAC3H : SchedWriteRes<[M4UnitFMACH]> { let Latency = 3; } 307def M4WriteFMAC3 : SchedWriteRes<[M4UnitFMAC]> { let Latency = 3; } 308def M4WriteFMAC4 : SchedWriteRes<[M4UnitFMAC]> { let Latency = 4; } 309def M4WriteFMAC4H : SchedWriteRes<[M4UnitFMACH]> { let Latency = 4; } 310def M4WriteFMAC5 : SchedWriteRes<[M4UnitFMAC]> { let Latency = 5; } 311 312def M4WriteFSQR7H : SchedWriteRes<[M4UnitFSQRH]> { let Latency = 7; 313 let ResourceCycles = [6]; } 314def M4WriteFSQR8 : SchedWriteRes<[M4UnitFSQR]> { let Latency = 8; 315 let ResourceCycles = [7]; } 316def M4WriteFSQR12 : SchedWriteRes<[M4UnitFSQR]> { let Latency = 12; 317 let ResourceCycles = [9]; } 318 319def M4WriteNALU1 : SchedWriteRes<[M4UnitNALU]> { let Latency = 1; } 320def M4WriteNALU1H : SchedWriteRes<[M4UnitNALUH]> { let Latency = 1; } 321 322def M4WriteNCRY1 : SchedWriteRes<[M4UnitNCRY]> { let Latency = 1; } 323def M4WriteNCRY1A : SchedWriteRes<[M4UnitNCRY0]> { let Latency = 1; } 324def M4WriteNCRY3A : SchedWriteRes<[M4UnitNCRY0]> { let Latency = 3; } 325def M4WriteNCRY5A : SchedWriteRes<[M4UnitNCRY]> { let Latency = 5; } 326 327def M4WriteNHAD1 : SchedWriteRes<[M4UnitNHAD]> { let Latency = 1; } 328def M4WriteNHAD3 : SchedWriteRes<[M4UnitNHAD]> { let Latency = 3; } 329 330def M4WriteNMSC1 : SchedWriteRes<[M4UnitNMSC]> { let Latency = 1; } 331def M4WriteNMSC2 : SchedWriteRes<[M4UnitNMSC]> { let Latency = 2; } 332def M4WriteNMSC3 : SchedWriteRes<[M4UnitNMSC]> { let Latency = 3; } 333 334def M4WriteNMUL3 : SchedWriteRes<[M4UnitNMUL]> { let Latency = 3; } 335 336def M4WriteNSHF1 : SchedWriteRes<[M4UnitNSHF]> { let Latency = 1; } 337def M4WriteNSHF1H : SchedWriteRes<[M4UnitNSHFH]> { let Latency = 1; } 338def M4WriteNSHF3 : SchedWriteRes<[M4UnitNSHF]> { let Latency = 3; } 339def M4WriteNSHFA : SchedWriteRes<[M4UnitNSHF]> { let Latency = 1; 340 let ResourceCycles = [2]; } 341def M4WriteNSHFB : SchedWriteRes<[M4UnitNSHF]> { let Latency = 2; 342 let NumMicroOps = 2; 343 let ResourceCycles = [2]; } 344def M4WriteNSHFC : SchedWriteRes<[M4UnitNSHF]> { let Latency = 3; 345 let NumMicroOps = 3; 346 let ResourceCycles = [4]; } 347def M4WriteNSHFD : SchedWriteRes<[M4UnitNSHF]> { let Latency = 4; 348 let NumMicroOps = 4; 349 let ResourceCycles = [4]; } 350 351def M4WriteNSHT1 : SchedWriteRes<[M4UnitNSHT]> { let Latency = 1; } 352def M4WriteNSHT2 : SchedWriteRes<[M4UnitNSHT]> { let Latency = 2; } 353def M4WriteNSHT3 : SchedWriteRes<[M4UnitNSHT]> { let Latency = 3; } 354def M4WriteNSHT4A : SchedWriteRes<[M4UnitNSHT1]> { let Latency = 4; } 355 356def M4WriteVLDA : SchedWriteRes<[M4UnitL, 357 M4UnitL]> { let Latency = 5; 358 let NumMicroOps = 2; } 359def M4WriteVLDB : SchedWriteRes<[M4UnitL, 360 M4UnitL, 361 M4UnitL]> { let Latency = 6; 362 let NumMicroOps = 3; } 363def M4WriteVLDC : SchedWriteRes<[M4UnitL, 364 M4UnitL, 365 M4UnitL, 366 M4UnitL]> { let Latency = 6; 367 let NumMicroOps = 4; } 368def M4WriteVLDD : SchedWriteRes<[M4UnitL, 369 M4UnitNSHF]> { let Latency = 6; 370 let NumMicroOps = 2; 371 let ResourceCycles = [2, 1]; } 372def M4WriteVLDF : SchedWriteRes<[M4UnitL, 373 M4UnitL]> { let Latency = 10; 374 let NumMicroOps = 2; 375 let ResourceCycles = [3, 3]; } 376def M4WriteVLDG : SchedWriteRes<[M4UnitL, 377 M4UnitNSHF, 378 M4UnitNSHF]> { let Latency = 6; 379 let NumMicroOps = 3; 380 let ResourceCycles = [2, 1, 1]; } 381def M4WriteVLDI : SchedWriteRes<[M4UnitL, 382 M4UnitL, 383 M4UnitL]> { let Latency = 12; 384 let NumMicroOps = 3; 385 let ResourceCycles = [3, 3, 3]; } 386def M4WriteVLDJ : SchedWriteRes<[M4UnitL, 387 M4UnitNSHF, 388 M4UnitNSHF, 389 M4UnitNSHF]> { let Latency = 7; 390 let NumMicroOps = 4; 391 let ResourceCycles = [3, 1, 1, 1]; } 392def M4WriteVLDK : SchedWriteRes<[M4UnitL, 393 M4UnitNSHF, 394 M4UnitNSHF, 395 M4UnitNSHF, 396 M4UnitNSHF]> { let Latency = 7; 397 let NumMicroOps = 5; 398 let ResourceCycles = [3, 1, 1, 1, 1]; } 399def M4WriteVLDL : SchedWriteRes<[M4UnitL, 400 M4UnitNSHF, 401 M4UnitNSHF, 402 M4UnitL, 403 M4UnitNSHF]> { let Latency = 7; 404 let NumMicroOps = 5; 405 let ResourceCycles = [3, 1, 1, 6, 1]; } 406def M4WriteVLDM : SchedWriteRes<[M4UnitL, 407 M4UnitNSHF, 408 M4UnitNSHF, 409 M4UnitL, 410 M4UnitNSHF, 411 M4UnitNSHF]> { let Latency = 7; 412 let NumMicroOps = 6; 413 let ResourceCycles = [3, 1, 1, 3, 1, 1]; } 414def M4WriteVLDN : SchedWriteRes<[M4UnitL, 415 M4UnitL, 416 M4UnitL, 417 M4UnitL]> { let Latency = 14; 418 let NumMicroOps = 4; 419 let ResourceCycles = [3, 3, 3, 3]; } 420 421def M4WriteVST1 : SchedWriteRes<[M4UnitS, 422 M4UnitFST]> { let Latency = 1; 423 let NumMicroOps = 1; } 424def M4WriteVSTA : WriteSequence<[WriteVST], 2>; 425def M4WriteVSTB : WriteSequence<[WriteVST], 3>; 426def M4WriteVSTC : WriteSequence<[WriteVST], 4>; 427def M4WriteVSTD : SchedWriteRes<[M4UnitS, 428 M4UnitFST]> { let Latency = 2; } 429def M4WriteVSTE : SchedWriteRes<[M4UnitS, 430 M4UnitFST, 431 M4UnitS, 432 M4UnitFST]> { let Latency = 2; 433 let NumMicroOps = 2; } 434def M4WriteVSTF : SchedWriteRes<[M4UnitNSHF, 435 M4UnitS, 436 M4UnitFST, 437 M4UnitS, 438 M4UnitFST]> { let Latency = 4; 439 let NumMicroOps = 4; 440 let ResourceCycles = [1, 2, 1, 2, 1]; } 441def M4WriteVSTG : SchedWriteRes<[M4UnitNSHF, 442 M4UnitNSHF, 443 M4UnitNSHF, 444 M4UnitS, 445 M4UnitFST, 446 M4UnitS, 447 M4UnitFST, 448 M4UnitS, 449 M4UnitFST]> { let Latency = 5; 450 let NumMicroOps = 6; 451 let ResourceCycles = [1, 1, 1, 2, 1, 2, 1, 2, 1]; } 452def M4WriteVSTI : SchedWriteRes<[M4UnitNSHF, 453 M4UnitNSHF, 454 M4UnitNSHF, 455 M4UnitNSHF, 456 M4UnitS, 457 M4UnitFST, 458 M4UnitS, 459 M4UnitFST, 460 M4UnitS, 461 M4UnitFST, 462 M4UnitS, 463 M4UnitFST]> { let Latency = 8; 464 let NumMicroOps = 5; 465 let ResourceCycles = [1, 1, 1, 1, 2, 1, 2, 1, 2, 1, 2, 1]; } 466def M4WriteVSTJ : SchedWriteRes<[M4UnitA, 467 M4UnitS, 468 M4UnitFST, 469 M4UnitS, 470 M4UnitFST]> { let Latency = 1; 471 let NumMicroOps = 2; } 472def M4WriteVSTK : SchedWriteRes<[M4UnitA, 473 M4UnitS, 474 M4UnitFST]> { let Latency = 3; 475 let NumMicroOps = 2; } 476def M4WriteVSTL : SchedWriteRes<[M4UnitNSHF, 477 M4UnitNSHF, 478 M4UnitS, 479 M4UnitFST, 480 M4UnitS, 481 M4UnitFST]> { let Latency = 4; 482 let NumMicroOps = 4; 483 let ResourceCycles = [1, 1, 2, 1, 2, 1]; } 484def M4WriteVSTY : SchedWriteVariant<[SchedVar<ExynosScaledIdxPred, [M4WriteVSTK]>, 485 SchedVar<NoSchedPred, [WriteVST]>]>; 486 487// Special cases. 488def M4WriteCOPY : SchedWriteVariant<[SchedVar<ExynosFPPred, [M4WriteNALU1]>, 489 SchedVar<NoSchedPred, [M4WriteZ0]>]>; 490def M4WriteMOVI : SchedWriteVariant<[SchedVar<IsZeroFPIdiomPred, [M4WriteZ0]>, 491 SchedVar<NoSchedPred, [M4WriteNALU1]>]>; 492 493// Fast forwarding. 494def M4ReadAESM1 : SchedReadAdvance<+1, [M4WriteNCRY1]>; 495def M4ReadFMACM1 : SchedReadAdvance<+1, [M4WriteFMAC4, 496 M4WriteFMAC4H, 497 M4WriteFMAC5]>; 498def M4ReadNMULM1 : SchedReadAdvance<+1, [M4WriteNMUL3]>; 499def M4ReadNMULP2 : SchedReadAdvance<-2, [M4WriteNMUL3]>; 500 501 502//===----------------------------------------------------------------------===// 503// Coarse scheduling model. 504 505// Branch instructions. 506def : SchedAlias<WriteBr, M4WriteZ0>; 507def : SchedAlias<WriteBrReg, M4WriteC1>; 508 509// Arithmetic and logical integer instructions. 510def : SchedAlias<WriteI, M4WriteA1>; 511def : SchedAlias<WriteIEReg, M4WriteAA>; // FIXME: M4WriteAX crashes TableGen. 512def : SchedAlias<WriteISReg, M4WriteAA>; // FIXME: M4WriteAX crashes TableGen. 513def : SchedAlias<WriteIS, M4WriteA1>; 514 515// Move instructions. 516def : SchedAlias<WriteImm, M4WriteA1>; 517 518// Divide and multiply instructions. 519def : SchedAlias<WriteID32, M4WriteD12>; 520def : SchedAlias<WriteID64, M4WriteD21>; 521def : SchedAlias<WriteIM32, M4WriteC3>; 522def : SchedAlias<WriteIM64, M4WriteCA>; 523 524// Miscellaneous instructions. 525def : SchedAlias<WriteExtr, M4WriteAY>; 526 527// Addressing modes. 528def : SchedAlias<WriteAdr, M4WriteZ1>; 529def : SchedAlias<ReadAdrBase, M4ReadAdrBase>; 530 531// Load instructions. 532def : SchedAlias<WriteLD, M4WriteL4>; 533def : SchedAlias<WriteLDHi, M4WriteZ4>; 534def : SchedAlias<WriteLDIdx, M4WriteLX>; 535 536// Store instructions. 537def : SchedAlias<WriteST, M4WriteS1>; 538def : SchedAlias<WriteSTP, M4WriteS1>; 539def : SchedAlias<WriteSTX, M4WriteS1>; 540def : SchedAlias<WriteSTIdx, M4WriteSX>; 541 542// FP data instructions. 543def : SchedAlias<WriteF, M4WriteFADD2>; 544def : SchedAlias<WriteFCmp, M4WriteNMSC2>; 545def : SchedAlias<WriteFDiv, M4WriteFDIV12>; 546def : SchedAlias<WriteFMul, M4WriteFMAC3>; 547 548// FP miscellaneous instructions. 549def : SchedAlias<WriteFCvt, M4WriteFCVT2>; 550def : SchedAlias<WriteFImm, M4WriteNALU1>; 551def : SchedAlias<WriteFCopy, M4WriteNALU1>; 552 553// FP load instructions. 554def : SchedAlias<WriteVLD, M4WriteL5>; 555 556// FP store instructions. 557def : SchedAlias<WriteVST, M4WriteVST1>; 558 559// ASIMD FP instructions. 560def : SchedAlias<WriteV, M4WriteNALU1>; 561 562// Other miscellaneous instructions. 563def : WriteRes<WriteAtomic, []> { let Unsupported = 1; } 564def : WriteRes<WriteBarrier, []> { let Latency = 1; } 565def : WriteRes<WriteHint, []> { let Latency = 1; } 566def : WriteRes<WriteSys, []> { let Latency = 1; } 567 568//===----------------------------------------------------------------------===// 569// Generic fast forwarding. 570 571// TODO: Add FP register forwarding rules. 572 573def : ReadAdvance<ReadI, 0>; 574def : ReadAdvance<ReadISReg, 0>; 575def : ReadAdvance<ReadIEReg, 0>; 576def : ReadAdvance<ReadIM, 0>; 577// TODO: The forwarding for 32 bits actually saves 2 cycles. 578def : ReadAdvance<ReadIMA, 3, [WriteIM32, WriteIM64]>; 579def : ReadAdvance<ReadID, 0>; 580def : ReadAdvance<ReadExtrHi, 0>; 581def : ReadAdvance<ReadAdrBase, 0>; 582def : ReadAdvance<ReadVLD, 0>; 583 584//===----------------------------------------------------------------------===// 585// Finer scheduling model. 586 587// Branch instructions 588def : InstRW<[M4WriteB1], (instrs Bcc)>; 589def : InstRW<[M4WriteAF], (instrs BL)>; 590def : InstRW<[M4WriteBX], (instrs BLR)>; 591def : InstRW<[M4WriteC1], (instregex "^CBN?Z[WX]")>; 592def : InstRW<[M4WriteAD], (instregex "^TBN?Z[WX]")>; 593 594// Arithmetic and logical integer instructions. 595def : InstRW<[M4WriteAX], (instregex "^(ADD|AND|BIC|EON|EOR|ORN|SUB)[WX]rs$")>; 596def : InstRW<[M4WriteAU], (instrs ORRWrs, ORRXrs)>; 597def : InstRW<[M4WriteAX], (instregex "^(ADD|AND|BIC|SUB)S[WX]rs$")>; 598def : InstRW<[M4WriteAX], (instregex "^(ADD|SUB)S?[WX]rx(64)?$")>; 599def : InstRW<[M4WriteAV], (instrs ADDWri, ADDXri, ORRWri, ORRXri)>; 600 601// Move instructions. 602def : InstRW<[M4WriteCOPY], (instrs COPY)>; 603def : InstRW<[M4WriteZ0], (instrs ADR, ADRP)>; 604def : InstRW<[M4WriteZ0], (instregex "^MOV[NZ][WX]i")>; 605 606// Divide and multiply instructions. 607 608// Miscellaneous instructions. 609 610// Load instructions. 611def : InstRW<[M4WriteLD, 612 WriteLDHi, 613 WriteAdr], (instregex "^LDP(SW|W|X)(post|pre)")>; 614def : InstRW<[M4WriteL5, 615 ReadAdrBase], (instregex "^LDR(BB|SBW|SBX|HH|SHW|SHX|SW|W|X)roW")>; 616def : InstRW<[WriteLDIdx, 617 ReadAdrBase], (instregex "^LDR(BB|SBW|SBX|HH|SHW|SHX|SW|W|X)roX")>; 618def : InstRW<[M4WriteL5, 619 ReadAdrBase], (instrs PRFMroW)>; 620def : InstRW<[WriteLDIdx, 621 ReadAdrBase], (instrs PRFMroX)>; 622 623// Store instructions. 624def : InstRW<[M4WriteSB, 625 ReadAdrBase], (instregex "^STR(BB|HH|W|X)roW")>; 626def : InstRW<[WriteST, 627 ReadAdrBase], (instregex "^STR(BB|HH|W|X)roX")>; 628 629// FP data instructions. 630def : InstRW<[M4WriteNSHF1H], (instrs FABSHr)>; 631def : InstRW<[M4WriteNSHF1], (instregex "^FABS[SD]r")>; 632def : InstRW<[M4WriteFADD2H], (instregex "^F(ADD|SUB)Hrr")>; 633def : InstRW<[M4WriteFADD2], (instregex "^F(ADD|SUB)[SD]rr")>; 634def : InstRW<[M4WriteFADD2H], (instregex "^FADDPv.i16")>; 635def : InstRW<[M4WriteFADD2], (instregex "^FADDPv.i(32|64)")>; 636def : InstRW<[M4WriteNEONQ], (instregex "^FCCMPE?[HSD]rr")>; 637def : InstRW<[M4WriteNMSC2], (instregex "^FCMPE?[HSD]r[ir]")>; 638def : InstRW<[M4WriteNMSC1], (instregex "^F(AC|CM)(EQ|GE|GT|LE|LT)(16|32|64|v1)")>; 639def : InstRW<[M4WriteFDIV7H], (instrs FDIVHrr)>; 640def : InstRW<[M4WriteFDIV7], (instrs FDIVSrr)>; 641def : InstRW<[M4WriteFDIV12], (instrs FDIVDrr)>; 642def : InstRW<[M4WriteNMSC1], (instregex "^F(MAX|MIN)(NM)?[HSD]rr")>; 643def : InstRW<[M4WriteFMAC3H], (instregex "^FN?MULHrr")>; 644def : InstRW<[M4WriteFMAC3], (instregex "^FN?MUL[SD]rr")>; 645def : InstRW<[M4WriteFMAC3H], (instrs FMULX16)>; 646def : InstRW<[M4WriteFMAC3], (instregex "^FMULX(32|64)")>; 647def : InstRW<[M4WriteFMAC4H, 648 M4ReadFMACM1], (instregex "^FN?M(ADD|SUB)Hrrr")>; 649def : InstRW<[M4WriteFMAC4, 650 M4ReadFMACM1], (instregex "^FN?M(ADD|SUB)[SD]rrr")>; 651def : InstRW<[M4WriteNALU1H], (instrs FNEGHr)>; 652def : InstRW<[M4WriteNALU1], (instregex "^FNEG[SD]r")>; 653def : InstRW<[M4WriteFCVT3A], (instregex "^FRINT.+r")>; 654def : InstRW<[M4WriteNEONH], (instregex "^FCSEL[HSD]rrr")>; 655def : InstRW<[M4WriteFSQR7H], (instrs FSQRTHr)>; 656def : InstRW<[M4WriteFSQR8], (instrs FSQRTSr)>; 657def : InstRW<[M4WriteFSQR12], (instrs FSQRTDr)>; 658 659// FP miscellaneous instructions. 660def : InstRW<[M4WriteFCVT2H], (instregex "^FCVTH[SD]r")>; 661def : InstRW<[M4WriteFCVT2H], (instregex "^FCVT[SD]Hr")>; 662def : InstRW<[M4WriteFCVT2], (instregex "^FCVT[SD][SD]r")>; 663def : InstRW<[M4WriteFCVT6A], (instregex "^[SU]CVTF[SU][XW][HSD]ri")>; 664def : InstRW<[M4WriteNEONR], (instregex "^FCVT[AMNPZ][SU][SU][XW][HSD]r")>; 665def : InstRW<[M4WriteNALU1], (instregex "^FMOV[HSD][ir]")>; 666def : InstRW<[M4WriteSA], (instregex "^FMOV[WX][HSD]r")>; 667def : InstRW<[M4WriteNEONJ], (instregex "^FMOV[HSD][WX]r")>; 668def : InstRW<[M4WriteNEONI], (instregex "^FMOVXDHighr")>; 669def : InstRW<[M4WriteNEONK], (instregex "^FMOVDXHighr")>; 670def : InstRW<[M4WriteFCVT3H], (instregex "^F(RECP|RSQRT)Ev1f16")>; 671def : InstRW<[M4WriteFCVT3], (instregex "^F(RECP|RSQRT)Ev1i(32|64)")>; 672def : InstRW<[M4WriteNMSC1], (instregex "^FRECPXv1")>; 673def : InstRW<[M4WriteFMAC4H], (instregex "^F(RECP|RSQRT)S16")>; 674def : InstRW<[M4WriteFMAC4], (instregex "^F(RECP|RSQRT)S(32|64)")>; 675 676// FP load instructions. 677def : InstRW<[WriteVLD], (instregex "^LDR[SDQ]l")>; 678def : InstRW<[WriteVLD], (instregex "^LDUR[BHSDQ]i")>; 679def : InstRW<[WriteVLD, 680 WriteAdr], (instregex "^LDR[BHSDQ](post|pre)")>; 681def : InstRW<[WriteVLD], (instregex "^LDR[BHSDQ]ui")>; 682def : InstRW<[M4WriteLE, 683 ReadAdrBase], (instregex "^LDR[BHSDQ]roW")>; 684def : InstRW<[WriteVLD, 685 ReadAdrBase], (instregex "^LDR[BHSD]roX")>; 686def : InstRW<[M4WriteLY, 687 ReadAdrBase], (instrs LDRQroX)>; 688def : InstRW<[WriteVLD, 689 M4WriteLH], (instregex "^LDN?P[SD]i")>; 690def : InstRW<[M4WriteLA, 691 M4WriteLH], (instregex "^LDN?PQi")>; 692def : InstRW<[M4WriteL5, 693 M4WriteLH, 694 WriteAdr], (instregex "^LDP[SD]post")>; 695def : InstRW<[M4WriteLB, 696 M4WriteLH, 697 WriteAdr], (instrs LDPQpost)>; 698def : InstRW<[M4WriteLB, 699 M4WriteLH, 700 WriteAdr], (instregex "^LDP[SD]pre")>; 701def : InstRW<[M4WriteLC, 702 M4WriteLH, 703 WriteAdr], (instrs LDPQpre)>; 704 705// FP store instructions. 706def : InstRW<[WriteVST], (instregex "^STUR[BHSDQ]i")>; 707def : InstRW<[WriteVST, 708 WriteAdr], (instregex "^STR[BHSDQ](post|pre)")>; 709def : InstRW<[WriteVST], (instregex "^STR[BHSDQ]ui")>; 710def : InstRW<[M4WriteVSTK, 711 ReadAdrBase], (instregex "^STR[BHSD]roW")>; 712def : InstRW<[M4WriteVSTK, 713 ReadAdrBase], (instrs STRQroW)>; 714def : InstRW<[WriteVST, 715 ReadAdrBase], (instregex "^STR[BHSD]roX")>; 716def : InstRW<[M4WriteVSTY, 717 ReadAdrBase], (instrs STRQroX)>; 718def : InstRW<[WriteVST], (instregex "^STN?P[SD]i")>; 719def : InstRW<[M4WriteVSTJ], (instregex "^STN?PQi")>; 720def : InstRW<[WriteVST, 721 WriteAdr], (instregex "^STP[SD](post|pre)")>; 722def : InstRW<[M4WriteVSTJ, 723 WriteAdr], (instregex "^STPQ(post|pre)")>; 724 725// ASIMD instructions. 726def : InstRW<[M4WriteNHAD1], (instregex "^[SU]ABDL?v")>; 727def : InstRW<[M4WriteNHAD3], (instregex "^[SU]ABAL?v")>; 728def : InstRW<[M4WriteNMSC1], (instregex "^ABSv")>; 729def : InstRW<[M4WriteNALU1], (instregex "^(ADD|NEG|SUB)v")>; 730def : InstRW<[M4WriteNHAD3], (instregex "^[SU]?ADDL?Pv")>; 731def : InstRW<[M4WriteNHAD3], (instregex "^[SU]H(ADD|SUB)v")>; 732def : InstRW<[M4WriteNHAD3], (instregex "^[SU](ADD|SUB)[LW]v")>; 733def : InstRW<[M4WriteNHAD3], (instregex "^R?(ADD|SUB)HN2?v")>; 734def : InstRW<[M4WriteNHAD3], (instregex "^[SU]Q(ADD|SUB)v")>; 735def : InstRW<[M4WriteNHAD3], (instregex "^(SU|US)QADDv")>; 736def : InstRW<[M4WriteNHAD3], (instregex "^[SU]RHADDv")>; 737def : InstRW<[M4WriteNMSC1], (instregex "^SQ(ABS|NEG)v")>; 738def : InstRW<[M4WriteNHAD3], (instregex "^[SU]?ADDL?Vv")>; 739def : InstRW<[M4WriteNMSC1], (instregex "^CM(EQ|GE|GT|HI|HS|LE|LT)v")>; 740def : InstRW<[M4WriteNALU1], (instregex "^CMTSTv")>; 741def : InstRW<[M4WriteNALU1], (instregex "^(AND|BIC|EOR|NOT|ORN|ORR)v")>; 742def : InstRW<[M4WriteNMSC1], (instregex "^[SU](MIN|MAX)v")>; 743def : InstRW<[M4WriteNMSC2], (instregex "^[SU](MIN|MAX)Pv")>; 744def : InstRW<[M4WriteNHAD3], (instregex "^[SU](MIN|MAX)Vv")>; 745def : InstRW<[M4WriteNMUL3, 746 M4ReadNMULM1], (instregex "^ML[AS]v")>; 747def : InstRW<[M4WriteNMUL3, 748 M4ReadNMULM1], (instregex "^(SQR?D)?MULH?v")>; 749def : InstRW<[M4WriteNMUL3, 750 M4ReadNMULM1], (instregex "^SQRDML[AS]H")>; 751def : InstRW<[M4WriteNMUL3, 752 M4ReadNMULM1], (instregex "^(S|U|SQD)ML[AS]L(v1(i32|i64)|v2i32|v4i16|v8i8)")>; 753def : InstRW<[M4WriteNMUL3, 754 M4ReadNMULP2], (instregex "^(S|U|SQD)ML[AS]L(v4i32|v8i16|v16i8)")>; 755def : InstRW<[M4WriteNMUL3, 756 M4ReadNMULM1], (instregex "^(S|U|SQD)MULL(v1(i32|i64)|v2i32|v4i16|v8i8)")>; 757def : InstRW<[M4WriteNMUL3, 758 M4ReadNMULP2], (instregex "^(S|U|SQD)MULL(v4i32|v8i16|v16i8)")>; 759def : InstRW<[M4WriteNMUL3], (instregex "^[SU]DOT(lane)?v")>; 760def : InstRW<[M4WriteNHAD3], (instregex "^[SU]ADALPv")>; 761def : InstRW<[M4WriteNSHT4A], (instregex "^[SU]R?SRA[dv]")>; 762def : InstRW<[M4WriteNSHT1], (instregex "^SHL[dv]")>; 763def : InstRW<[M4WriteNSHT1], (instregex "^S[LR]I[dv]")>; 764def : InstRW<[M4WriteNSHT1], (instregex "^[SU]SH[LR][dv]")>; 765def : InstRW<[M4WriteNSHT2], (instregex "^[SU]?SHLLv")>; 766def : InstRW<[M4WriteNSHT4A], (instregex "^[SU]?Q?R?SHRU?N[bhsv]")>; 767def : InstRW<[M4WriteNSHT4A], (instregex "^[SU]RSH[LR][dv]")>; 768def : InstRW<[M4WriteNSHT4A], (instregex "^[SU]QR?SHLU?[bhsdv]")>; 769 770// ASIMD FP instructions. 771def : InstRW<[M4WriteNSHF1H], (instregex "^FABSv.f16")>; 772def : InstRW<[M4WriteNSHF1], (instregex "^FABSv.f(32|64)")>; 773def : InstRW<[M4WriteFADD2H], (instregex "^F(ABD|ADD|SUB)v.f16")>; 774def : InstRW<[M4WriteFADD2], (instregex "^F(ABD|ADD|SUB)v.f(32|64)")>; 775def : InstRW<[M4WriteFADD2H], (instregex "^FADDPv.f16")>; 776def : InstRW<[M4WriteFADD2], (instregex "^FADDPv.f(32|64)")>; 777def : InstRW<[M4WriteNMSC1], (instregex "^F(AC|CM)(EQ|GE|GT|LE|LT)v[^1]")>; 778def : InstRW<[M4WriteFCVT2], (instregex "^FCVT(L|N|XN)v")>; 779def : InstRW<[M4WriteFCVT2A], (instregex "^FCVT[AMNPZ][SU]v")>; 780def : InstRW<[M4WriteFCVT2H], (instregex "^[SU]CVTFv.[fi]16")>; 781def : InstRW<[M4WriteFCVT2], (instregex "^[SU]CVTFv.[fi](32|64)")>; 782def : InstRW<[M4WriteFDIV7H], (instrs FDIVv4f16)>; 783def : InstRW<[M4WriteNEONVH], (instrs FDIVv8f16)>; 784def : InstRW<[M4WriteFDIV7], (instrs FDIVv2f32)>; 785def : InstRW<[M4WriteNEONV], (instrs FDIVv4f32)>; 786def : InstRW<[M4WriteNEONW], (instrs FDIVv2f64)>; 787def : InstRW<[M4WriteNMSC1], (instregex "^F(MAX|MIN)(NM)?v")>; 788def : InstRW<[M4WriteNMSC2], (instregex "^F(MAX|MIN)(NM)?Pv")>; 789def : InstRW<[M4WriteNEONZ], (instregex "^F(MAX|MIN)(NM)?Vv")>; 790def : InstRW<[M4WriteFMAC2H], (instregex "^FMULX?v.[fi]16")>; 791def : InstRW<[M4WriteFMAC3], (instregex "^FMULX?v.[fi](32|64)")>; 792def : InstRW<[M4WriteFMAC4H, 793 M4ReadFMACM1], (instregex "^FML[AS]v.[fi]16")>; 794def : InstRW<[M4WriteFMAC4, 795 M4ReadFMACM1], (instregex "^FML[AS]v.[fi](32|64)")>; 796def : InstRW<[M4WriteNALU1H], (instregex "^FNEGv.f16")>; 797def : InstRW<[M4WriteNALU1], (instregex "^FNEGv.f(32|64)")>; 798def : InstRW<[M4WriteFCVT3A], (instregex "^FRINT[AIMNPXZ]v")>; 799def : InstRW<[M4WriteFSQR7H], (instrs FSQRTv4f16)>; 800def : InstRW<[M4WriteNEONXH], (instrs FSQRTv8f16)>; 801def : InstRW<[M4WriteFSQR8], (instrs FSQRTv2f32)>; 802def : InstRW<[M4WriteNEONX], (instrs FSQRTv4f32)>; 803def : InstRW<[M4WriteNEONY], (instrs FSQRTv2f64)>; 804 805// ASIMD miscellaneous instructions. 806def : InstRW<[M4WriteNALU1], (instregex "^RBITv")>; 807def : InstRW<[M4WriteNALU1], (instregex "^(BIF|BIT|BSL)v")>; 808def : InstRW<[M4WriteNALU1], (instregex "^CL[STZ]v")>; 809def : InstRW<[M4WriteNEONB], (instregex "^DUPv.+gpr")>; 810def : InstRW<[M4WriteNSHF1], (instregex "^CPY")>; 811def : InstRW<[M4WriteNSHF1], (instregex "^DUPv.+lane")>; 812def : InstRW<[M4WriteNSHF1], (instregex "^EXTv")>; 813def : InstRW<[M4WriteNSHT4A], (instregex "^XTNv")>; 814def : InstRW<[M4WriteNSHT4A], (instregex "^[SU]?QXTU?Nv")>; 815def : InstRW<[M4WriteNEONB], (instregex "^INSv.+gpr")>; 816def : InstRW<[M4WriteNSHF1], (instregex "^INSv.+lane")>; 817def : InstRW<[M4WriteMOVI], (instregex "^(MOV|MVN)I")>; 818def : InstRW<[M4WriteNALU1H], (instregex "^FMOVv.f16")>; 819def : InstRW<[M4WriteNALU1], (instregex "^FMOVv.f(32|64)")>; 820def : InstRW<[M4WriteFCVT3H], (instregex "^F(RECP|RSQRT)Ev[248]f16")>; 821def : InstRW<[M4WriteFCVT3], (instregex "^F(RECP|RSQRT)Ev[248]f(32|64)")>; 822def : InstRW<[M4WriteFCVT3], (instregex "^U(RECP|RSQRT)Ev[24]i32")>; 823def : InstRW<[M4WriteFMAC4H], (instregex "^F(RECP|RSQRT)Sv.f16")>; 824def : InstRW<[M4WriteFMAC4], (instregex "^F(RECP|RSQRT)Sv.f(32|64)")>; 825def : InstRW<[M4WriteNSHF1], (instregex "^REV(16|32|64)v")>; 826def : InstRW<[M4WriteNSHFA], (instregex "^TB[LX]v(8|16)i8One")>; 827def : InstRW<[M4WriteNSHFB], (instregex "^TB[LX]v(8|16)i8Two")>; 828def : InstRW<[M4WriteNSHFC], (instregex "^TB[LX]v(8|16)i8Three")>; 829def : InstRW<[M4WriteNSHFD], (instregex "^TB[LX]v(8|16)i8Four")>; 830def : InstRW<[M4WriteNEONP], (instregex "^[SU]MOVv")>; 831def : InstRW<[M4WriteNSHF1], (instregex "^(TRN|UZP|ZIP)[12]v")>; 832 833// ASIMD load instructions. 834def : InstRW<[WriteVLD], (instregex "LD1Onev(8b|4h|2s|1d)$")>; 835def : InstRW<[WriteVLD, 836 M4WriteA1], (instregex "LD1Onev(8b|4h|2s|1d)_POST$")>; 837def : InstRW<[WriteVLD], (instregex "LD1Onev(16b|8h|4s|2d)$")>; 838def : InstRW<[WriteVLD, 839 M4WriteA1], (instregex "LD1Onev(16b|8h|4s|2d)_POST$")>; 840 841def : InstRW<[M4WriteVLDA], (instregex "LD1Twov(8b|4h|2s|1d)$")>; 842def : InstRW<[M4WriteVLDA, 843 M4WriteA1], (instregex "LD1Twov(8b|4h|2s|1d)_POST$")>; 844def : InstRW<[M4WriteVLDA], (instregex "LD1Twov(16b|8h|4s|2d)$")>; 845def : InstRW<[M4WriteVLDA, 846 M4WriteA1], (instregex "LD1Twov(16b|8h|4s|2d)_POST$")>; 847 848def : InstRW<[M4WriteVLDB], (instregex "LD1Threev(8b|4h|2s|1d)$")>; 849def : InstRW<[M4WriteVLDB, 850 M4WriteA1], (instregex "LD1Threev(8b|4h|2s|1d)_POST$")>; 851def : InstRW<[M4WriteVLDB], (instregex "LD1Threev(16b|8h|4s|2d)$")>; 852def : InstRW<[M4WriteVLDB, 853 M4WriteA1], (instregex "LD1Threev(16b|8h|4s|2d)_POST$")>; 854 855def : InstRW<[M4WriteVLDC], (instregex "LD1Fourv(8b|4h|2s|1d)$")>; 856def : InstRW<[M4WriteVLDC, 857 M4WriteA1], (instregex "LD1Fourv(8b|4h|2s|1d)_POST$")>; 858def : InstRW<[M4WriteVLDC], (instregex "LD1Fourv(16b|8h|4s|2d)$")>; 859def : InstRW<[M4WriteVLDC, 860 M4WriteA1], (instregex "LD1Fourv(16b|8h|4s|2d)_POST$")>; 861 862def : InstRW<[M4WriteVLDD], (instregex "LD1i(8|16|32|64)$")>; 863def : InstRW<[M4WriteVLDD, 864 M4WriteA1], (instregex "LD1i(8|16|32|64)_POST$")>; 865 866def : InstRW<[WriteVLD], (instregex "LD1Rv(8b|4h|2s|1d)$")>; 867def : InstRW<[WriteVLD, 868 M4WriteA1], (instregex "LD1Rv(8b|4h|2s|1d)_POST$")>; 869def : InstRW<[WriteVLD], (instregex "LD1Rv(16b|8h|4s|2d)$")>; 870def : InstRW<[WriteVLD, 871 M4WriteA1], (instregex "LD1Rv(16b|8h|4s|2d)_POST$")>; 872 873def : InstRW<[M4WriteVLDF], (instregex "LD2Twov(8b|4h|2s)$")>; 874def : InstRW<[M4WriteVLDF, 875 M4WriteA1], (instregex "LD2Twov(8b|4h|2s)_POST$")>; 876def : InstRW<[M4WriteVLDF], (instregex "LD2Twov(16b|8h|4s|2d)$")>; 877def : InstRW<[M4WriteVLDF, 878 M4WriteA1], (instregex "LD2Twov(16b|8h|4s|2d)_POST$")>; 879 880def : InstRW<[M4WriteVLDG], (instregex "LD2i(8|16|32|64)$")>; 881def : InstRW<[M4WriteVLDG, 882 M4WriteA1], (instregex "LD2i(8|16|32|64)_POST$")>; 883 884def : InstRW<[M4WriteVLDA], (instregex "LD2Rv(8b|4h|2s|1d)$")>; 885def : InstRW<[M4WriteVLDA, 886 M4WriteA1], (instregex "LD2Rv(8b|4h|2s|1d)_POST$")>; 887def : InstRW<[M4WriteVLDA], (instregex "LD2Rv(16b|8h|4s|2d)$")>; 888def : InstRW<[M4WriteVLDA, 889 M4WriteA1], (instregex "LD2Rv(16b|8h|4s|2d)_POST$")>; 890 891def : InstRW<[M4WriteVLDI], (instregex "LD3Threev(8b|4h|2s)$")>; 892def : InstRW<[M4WriteVLDI, 893 M4WriteA1], (instregex "LD3Threev(8b|4h|2s)_POST$")>; 894def : InstRW<[M4WriteVLDI], (instregex "LD3Threev(16b|8h|4s|2d)$")>; 895def : InstRW<[M4WriteVLDI, 896 M4WriteA1], (instregex "LD3Threev(16b|8h|4s|2d)_POST$")>; 897 898def : InstRW<[M4WriteVLDJ], (instregex "LD3i(8|16|32)$")>; 899def : InstRW<[M4WriteVLDJ, 900 M4WriteA1], (instregex "LD3i(8|16|32)_POST$")>; 901def : InstRW<[M4WriteVLDL], (instregex "LD3i64$")>; 902def : InstRW<[M4WriteVLDL, 903 M4WriteA1], (instregex "LD3i64_POST$")>; 904 905def : InstRW<[M4WriteVLDB], (instregex "LD3Rv(8b|4h|2s|1d)$")>; 906def : InstRW<[M4WriteVLDB, 907 M4WriteA1], (instregex "LD3Rv(8b|4h|2s|1d)_POST$")>; 908def : InstRW<[M4WriteVLDB], (instregex "LD3Rv(16b|8h|4s|2d)$")>; 909def : InstRW<[M4WriteVLDB, 910 M4WriteA1], (instregex "LD3Rv(16b|8h|4s|2d)_POST$")>; 911 912def : InstRW<[M4WriteVLDN], (instregex "LD4Fourv(8b|4h|2s)$")>; 913def : InstRW<[M4WriteVLDN, 914 M4WriteA1], (instregex "LD4Fourv(8b|4h|2s)_POST$")>; 915def : InstRW<[M4WriteVLDN], (instregex "LD4Fourv(16b|8h|4s|2d)$")>; 916def : InstRW<[M4WriteVLDN, 917 M4WriteA1], (instregex "LD4Fourv(16b|8h|4s|2d)_POST$")>; 918 919def : InstRW<[M4WriteVLDK], (instregex "LD4i(8|16|32)$")>; 920def : InstRW<[M4WriteVLDK, 921 M4WriteA1], (instregex "LD4i(8|16|32)_POST$")>; 922def : InstRW<[M4WriteVLDM], (instregex "LD4i64$")>; 923def : InstRW<[M4WriteVLDM, 924 M4WriteA1], (instregex "LD4i64_POST$")>; 925 926def : InstRW<[M4WriteVLDC], (instregex "LD4Rv(8b|4h|2s|1d)$")>; 927def : InstRW<[M4WriteVLDC, 928 M4WriteA1], (instregex "LD4Rv(8b|4h|2s|1d)_POST$")>; 929def : InstRW<[M4WriteVLDC], (instregex "LD4Rv(16b|8h|4s|2d)$")>; 930def : InstRW<[M4WriteVLDC, 931 M4WriteA1], (instregex "LD4Rv(16b|8h|4s|2d)_POST$")>; 932 933// ASIMD store instructions. 934def : InstRW<[WriteVST], (instregex "ST1Onev(8b|4h|2s|1d)$")>; 935def : InstRW<[WriteVST, 936 M4WriteA1], (instregex "ST1Onev(8b|4h|2s|1d)_POST$")>; 937def : InstRW<[WriteVST], (instregex "ST1Onev(16b|8h|4s|2d)$")>; 938def : InstRW<[WriteVST, 939 M4WriteA1], (instregex "ST1Onev(16b|8h|4s|2d)_POST$")>; 940 941def : InstRW<[M4WriteVSTA], (instregex "ST1Twov(8b|4h|2s|1d)$")>; 942def : InstRW<[M4WriteVSTA, 943 M4WriteA1], (instregex "ST1Twov(8b|4h|2s|1d)_POST$")>; 944def : InstRW<[M4WriteVSTA], (instregex "ST1Twov(16b|8h|4s|2d)$")>; 945def : InstRW<[M4WriteVSTA, 946 M4WriteA1], (instregex "ST1Twov(16b|8h|4s|2d)_POST$")>; 947 948def : InstRW<[M4WriteVSTB], (instregex "ST1Threev(8b|4h|2s|1d)$")>; 949def : InstRW<[M4WriteVSTB, 950 M4WriteA1], (instregex "ST1Threev(8b|4h|2s|1d)_POST$")>; 951def : InstRW<[M4WriteVSTB], (instregex "ST1Threev(16b|8h|4s|2d)$")>; 952def : InstRW<[M4WriteVSTB, 953 M4WriteA1], (instregex "ST1Threev(16b|8h|4s|2d)_POST$")>; 954 955def : InstRW<[M4WriteVSTC], (instregex "ST1Fourv(8b|4h|2s|1d)$")>; 956def : InstRW<[M4WriteVSTC, 957 M4WriteA1], (instregex "ST1Fourv(8b|4h|2s|1d)_POST$")>; 958def : InstRW<[M4WriteVSTC], (instregex "ST1Fourv(16b|8h|4s|2d)$")>; 959def : InstRW<[M4WriteVSTC, 960 M4WriteA1], (instregex "ST1Fourv(16b|8h|4s|2d)_POST$")>; 961 962def : InstRW<[WriteVST], (instregex "ST1i(8|16|32|64)$")>; 963def : InstRW<[WriteVST, 964 M4WriteA1], (instregex "ST1i(8|16|32|64)_POST$")>; 965 966def : InstRW<[M4WriteVSTD], (instregex "ST2Twov(8b|4h|2s)$")>; 967def : InstRW<[M4WriteVSTD, 968 M4WriteA1], (instregex "ST2Twov(8b|4h|2s)_POST$")>; 969def : InstRW<[M4WriteVSTE], (instregex "ST2Twov(16b|8h|4s|2d)$")>; 970def : InstRW<[M4WriteVSTE, 971 M4WriteA1], (instregex "ST2Twov(16b|8h|4s|2d)_POST$")>; 972 973def : InstRW<[M4WriteVSTD], (instregex "ST2i(8|16|32|64)$")>; 974def : InstRW<[M4WriteVSTD, 975 M4WriteA1], (instregex "ST2i(8|16|32|64)_POST$")>; 976 977def : InstRW<[M4WriteVSTF], (instregex "ST3Threev(8b|4h|2s)$")>; 978def : InstRW<[M4WriteVSTF, 979 M4WriteA1], (instregex "ST3Threev(8b|4h|2s)_POST$")>; 980def : InstRW<[M4WriteVSTG], (instregex "ST3Threev(16b|8h|4s|2d)$")>; 981def : InstRW<[M4WriteVSTG, 982 M4WriteA1], (instregex "ST3Threev(16b|8h|4s|2d)_POST$")>; 983 984def : InstRW<[M4WriteVSTE], (instregex "ST3i(8|16|32|64)$")>; 985def : InstRW<[M4WriteVSTE, 986 M4WriteA1], (instregex "ST3i(8|16|32|64)_POST$")>; 987 988def : InstRW<[M4WriteVSTL], (instregex "ST4Fourv(8b|4h|2s)$")>; 989def : InstRW<[M4WriteVSTL, 990 M4WriteA1], (instregex "ST4Fourv(8b|4h|2s)_POST$")>; 991def : InstRW<[M4WriteVSTI], (instregex "ST4Fourv(16b|8h|4s|2d)$")>; 992def : InstRW<[M4WriteVSTI, 993 M4WriteA1], (instregex "ST4Fourv(16b|8h|4s|2d)_POST$")>; 994 995def : InstRW<[M4WriteVSTE], (instregex "ST4i(8|16|32|64)$")>; 996def : InstRW<[M4WriteVSTE, 997 M4WriteA1], (instregex "ST4i(8|16|32|64)_POST$")>; 998 999// Cryptography instructions. 1000def : InstRW<[M4WriteNCRY1], (instregex "^AES[DE]")>; 1001def : InstRW<[M4WriteNCRY1, 1002 M4ReadAESM1], (instregex "^AESI?MC")>; 1003def : InstRW<[M4WriteNCRY1A], (instregex "^PMULv")>; 1004def : InstRW<[M4WriteNCRY1A], (instregex "^PMULLv(1|8)i")>; 1005def : InstRW<[M4WriteNCRY3A], (instregex "^PMULLv(2|16)i")>; 1006def : InstRW<[M4WriteNCRY1A], (instregex "^SHA1([CHMP]|SU[01])")>; 1007def : InstRW<[M4WriteNCRY1A], (instrs SHA256SU0rr)>; 1008def : InstRW<[M4WriteNCRY5A], (instrs SHA256SU1rrr)>; 1009def : InstRW<[M4WriteNCRY5A], (instrs SHA256H2rrr)>; 1010 1011// CRC instructions. 1012def : InstRW<[M4WriteE2], (instregex "^CRC32C?[BHWX]rr$")>; 1013 1014} // SchedModel = ExynosM4Model 1015