AArch64SchedExynosM4.td revision 360660
1//=- AArch64SchedExynosM4.td - Samsung Exynos M4 Sched Defs --*- tablegen -*-=// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file defines the machine model for the Samsung Exynos M4 to support 10// instruction scheduling and other instruction cost heuristics. 11// 12//===----------------------------------------------------------------------===// 13 14//===----------------------------------------------------------------------===// 15// The Exynos-M4 is an advanced superscalar microprocessor with a 6-wide 16// in-order stage for decode and dispatch and a wider issue stage. 17// The execution units and loads and stores are out-of-order. 18 19def ExynosM4Model : SchedMachineModel { 20 let IssueWidth = 6; // Up to 6 uops per cycle. 21 let MicroOpBufferSize = 228; // ROB size. 22 let LoopMicroOpBufferSize = 48; // Based on the instruction queue size. 23 let LoadLatency = 4; // Optimistic load cases. 24 let MispredictPenalty = 16; // Minimum branch misprediction penalty. 25 let CompleteModel = 1; // Use the default model otherwise. 26 27 list<Predicate> UnsupportedFeatures = SVEUnsupported.F; 28} 29 30//===----------------------------------------------------------------------===// 31// Define each kind of processor resource and number available on the Exynos-M4. 32 33let SchedModel = ExynosM4Model in { 34 35def M4UnitA : ProcResource<2>; // Simple integer 36def M4UnitC : ProcResource<2>; // Simple and complex integer 37let Super = M4UnitC, BufferSize = 1 in 38def M4UnitD : ProcResource<1>; // Integer division (inside C0, serialized) 39let Super = M4UnitC in 40def M4UnitE : ProcResource<1>; // CRC (inside C0) 41def M4UnitB : ProcResource<2>; // Branch 42def M4UnitL0 : ProcResource<1>; // Load 43def M4UnitS0 : ProcResource<1>; // Store 44def M4PipeLS : ProcResource<1>; // Load/Store 45let Super = M4PipeLS in { 46 def M4UnitL1 : ProcResource<1>; 47 def M4UnitS1 : ProcResource<1>; 48} 49def M4PipeF0 : ProcResource<1>; // FP #0 50let Super = M4PipeF0 in { 51 def M4UnitFMAC0 : ProcResource<1>; // FP multiplication 52 def M4UnitFADD0 : ProcResource<1>; // Simple FP 53 def M4UnitFCVT0 : ProcResource<1>; // FP conversion 54 def M4UnitNALU0 : ProcResource<1>; // Simple vector 55 def M4UnitNHAD : ProcResource<1>; // Horizontal vector 56 def M4UnitNMSC : ProcResource<1>; // FP and vector miscellanea 57 def M4UnitNMUL0 : ProcResource<1>; // Vector multiplication 58 def M4UnitNSHT0 : ProcResource<1>; // Vector shifting 59 def M4UnitNSHF0 : ProcResource<1>; // Vector shuffling 60 def M4UnitNCRY0 : ProcResource<1>; // Cryptographic 61} 62def M4PipeF1 : ProcResource<1>; // FP #1 63let Super = M4PipeF1 in { 64 def M4UnitFMAC1 : ProcResource<1>; // FP multiplication 65 def M4UnitFADD1 : ProcResource<1>; // Simple FP 66 def M4UnitFDIV0 : ProcResource<2>; // FP division (serialized) 67 def M4UnitFSQR0 : ProcResource<2>; // FP square root (serialized) 68 def M4UnitFST0 : ProcResource<1>; // FP store 69 def M4UnitNALU1 : ProcResource<1>; // Simple vector 70 def M4UnitNSHT1 : ProcResource<1>; // Vector shifting 71 def M4UnitNSHF1 : ProcResource<1>; // Vector shuffling 72} 73def M4PipeF2 : ProcResource<1>; // FP #2 74let Super = M4PipeF2 in { 75 def M4UnitFMAC2 : ProcResource<1>; // FP multiplication 76 def M4UnitFADD2 : ProcResource<1>; // Simple FP 77 def M4UnitFCVT1 : ProcResource<1>; // FP conversion 78 def M4UnitFDIV1 : ProcResource<2>; // FP division (serialized) 79 def M4UnitFSQR1 : ProcResource<2>; // FP square root (serialized) 80 def M4UnitFST1 : ProcResource<1>; // FP store 81 def M4UnitNALU2 : ProcResource<1>; // Simple vector 82 def M4UnitNMUL1 : ProcResource<1>; // Vector multiplication 83 def M4UnitNSHT2 : ProcResource<1>; // Vector shifting 84 def M4UnitNCRY1 : ProcResource<1>; // Cryptographic 85} 86 87def M4UnitALU : ProcResGroup<[M4UnitA, 88 M4UnitC]>; 89def M4UnitL : ProcResGroup<[M4UnitL0, 90 M4UnitL1]>; 91def M4UnitS : ProcResGroup<[M4UnitS0, 92 M4UnitS1]>; 93def M4UnitFMAC : ProcResGroup<[M4UnitFMAC0, 94 M4UnitFMAC1, 95 M4UnitFMAC2]>; 96def M4UnitFMACH : ProcResGroup<[M4UnitFMAC0, 97 M4UnitFMAC1]>; 98def M4UnitFADD : ProcResGroup<[M4UnitFADD0, 99 M4UnitFADD1, 100 M4UnitFADD2]>; 101def M4UnitFADDH : ProcResGroup<[M4UnitFADD0, 102 M4UnitFADD1]>; 103def M4UnitFCVT : ProcResGroup<[M4UnitFCVT0, 104 M4UnitFCVT1]>; 105def M4UnitFCVTH : ProcResGroup<[M4UnitFCVT0]>; 106def M4UnitFDIV : ProcResGroup<[M4UnitFDIV0, 107 M4UnitFDIV1]>; 108def M4UnitFDIVH : ProcResGroup<[M4UnitFDIV0]>; 109def M4UnitFSQR : ProcResGroup<[M4UnitFSQR0, 110 M4UnitFSQR1]>; 111def M4UnitFSQRH : ProcResGroup<[M4UnitFSQR0]>; 112def M4UnitFST : ProcResGroup<[M4UnitFST0, 113 M4UnitFST1]>; 114def M4UnitNALU : ProcResGroup<[M4UnitNALU0, 115 M4UnitNALU1, 116 M4UnitNALU2]>; 117def M4UnitNALUH : ProcResGroup<[M4UnitNALU0, 118 M4UnitNALU1]>; 119def M4UnitNMUL : ProcResGroup<[M4UnitNMUL0, 120 M4UnitNMUL1]>; 121def M4UnitNSHT : ProcResGroup<[M4UnitNSHT0, 122 M4UnitNSHT1, 123 M4UnitNSHT2]>; 124def M4UnitNSHF : ProcResGroup<[M4UnitNSHF0, 125 M4UnitNSHF1]>; 126def M4UnitNSHFH : ProcResGroup<[M4UnitNSHF0]>; 127def M4UnitNCRY : ProcResGroup<[M4UnitNCRY0, 128 M4UnitNCRY1]>; 129 130//===----------------------------------------------------------------------===// 131// Resources details. 132 133def M4WriteZ0 : SchedWriteRes<[]> { let Latency = 0; } 134def M4WriteZ1 : SchedWriteRes<[]> { let Latency = 1; 135 let NumMicroOps = 0; } 136def M4WriteZ4 : SchedWriteRes<[]> { let Latency = 4; 137 let NumMicroOps = 0; } 138 139def M4WriteA1 : SchedWriteRes<[M4UnitALU]> { let Latency = 1; } 140def M4WriteA2 : SchedWriteRes<[M4UnitALU]> { let Latency = 2; } 141def M4WriteAA : SchedWriteRes<[M4UnitALU]> { let Latency = 2; 142 let ResourceCycles = [2]; } 143def M4WriteAB : SchedWriteRes<[M4UnitALU, 144 M4UnitC]> { let Latency = 2; 145 let NumMicroOps = 2; } 146def M4WriteAC : SchedWriteRes<[M4UnitALU, 147 M4UnitALU, 148 M4UnitC]> { let Latency = 3; 149 let NumMicroOps = 3; } 150def M4WriteAD : SchedWriteRes<[M4UnitALU, 151 M4UnitC]> { let Latency = 2; 152 let NumMicroOps = 2; } 153def M4WriteAF : SchedWriteRes<[M4UnitALU]> { let Latency = 2; 154 let NumMicroOps = 2; } 155def M4WriteAU : SchedWriteVariant<[SchedVar<IsCopyIdiomPred, [M4WriteZ0]>, 156 SchedVar<ExynosArithPred, [M4WriteA1]>, 157 SchedVar<ExynosLogicExPred, [M4WriteA1]>, 158 SchedVar<NoSchedPred, [M4WriteAA]>]>; 159def M4WriteAV : SchedWriteVariant<[SchedVar<ExynosResetPred, [M4WriteZ0]>, 160 SchedVar<NoSchedPred, [M4WriteAA]>]>; 161def M4WriteAX : SchedWriteVariant<[SchedVar<ExynosArithPred, [M4WriteA1]>, 162 SchedVar<ExynosLogicExPred, [M4WriteA1]>, 163 SchedVar<NoSchedPred, [M4WriteAA]>]>; 164def M4WriteAY : SchedWriteVariant<[SchedVar<ExynosRotateRightImmPred, [M4WriteA1]>, 165 SchedVar<NoSchedPred, [M4WriteAF]>]>; 166 167def M4WriteB1 : SchedWriteRes<[M4UnitB]> { let Latency = 1; } 168def M4WriteBX : SchedWriteVariant<[SchedVar<ExynosBranchLinkLRPred, [M4WriteAC]>, 169 SchedVar<NoSchedPred, [M4WriteAB]>]>; 170 171def M4WriteC1 : SchedWriteRes<[M4UnitC]> { let Latency = 1; } 172def M4WriteC3 : SchedWriteRes<[M4UnitC]> { let Latency = 3; } 173def M4WriteCA : SchedWriteRes<[M4UnitC]> { let Latency = 4; 174 let ResourceCycles = [2]; } 175 176def M4WriteD12 : SchedWriteRes<[M4UnitD]> { let Latency = 12; } 177def M4WriteD21 : SchedWriteRes<[M4UnitD]> { let Latency = 21; } 178 179def M4WriteE2 : SchedWriteRes<[M4UnitE]> { let Latency = 2; } 180 181def M4WriteL4 : SchedWriteRes<[M4UnitL]> { let Latency = 4; } 182def M4WriteL5 : SchedWriteRes<[M4UnitL]> { let Latency = 5; } 183def M4WriteLA : SchedWriteRes<[M4UnitL, 184 M4UnitL]> { let Latency = 5; 185 let NumMicroOps = 1; } 186def M4WriteLB : SchedWriteRes<[M4UnitA, 187 M4UnitL]> { let Latency = 5; 188 let NumMicroOps = 2; } 189def M4WriteLC : SchedWriteRes<[M4UnitA, 190 M4UnitL, 191 M4UnitL]> { let Latency = 5; 192 let NumMicroOps = 2; } 193def M4WriteLD : SchedWriteRes<[M4UnitA, 194 M4UnitL]> { let Latency = 4; 195 let NumMicroOps = 2; } 196def M4WriteLE : SchedWriteRes<[M4UnitA, 197 M4UnitL]> { let Latency = 6; 198 let NumMicroOps = 2; } 199def M4WriteLH : SchedWriteRes<[]> { let Latency = 5; 200 let NumMicroOps = 0; } 201def M4WriteLX : SchedWriteVariant<[SchedVar<ScaledIdxPred, [M4WriteL5]>, 202 SchedVar<NoSchedPred, [M4WriteL4]>]>; 203 204def M4WriteS1 : SchedWriteRes<[M4UnitS]> { let Latency = 1; } 205def M4WriteSA : SchedWriteRes<[M4UnitS0]> { let Latency = 3; } 206def M4WriteSB : SchedWriteRes<[M4UnitA, 207 M4UnitS]> { let Latency = 2; 208 let NumMicroOps = 1; } 209def M4WriteSX : SchedWriteVariant<[SchedVar<ExynosScaledIdxPred, [M4WriteSB]>, 210 SchedVar<NoSchedPred, [M4WriteS1]>]>; 211 212def M4ReadAdrBase : SchedReadVariant<[SchedVar< 213 MCSchedPredicate< 214 CheckAny< 215 [ScaledIdxFn, 216 ExynosScaledIdxFn]>>, [ReadDefault]>, 217 SchedVar<NoSchedPred, [ReadDefault]>]>; 218 219def M4WriteNEONA : SchedWriteRes<[M4UnitNSHF, 220 M4UnitFADD]> { let Latency = 3; 221 let NumMicroOps = 2; } 222def M4WriteNEONB : SchedWriteRes<[M4UnitNALU, 223 M4UnitS0]> { let Latency = 5; 224 let NumMicroOps = 2; } 225def M4WriteNEOND : SchedWriteRes<[M4UnitNSHF, 226 M4UnitFST]> { let Latency = 6; 227 let NumMicroOps = 2; } 228def M4WriteNEONH : SchedWriteRes<[M4UnitNALU, 229 M4UnitS0]> { let Latency = 5; 230 let NumMicroOps = 2; } 231def M4WriteNEONI : SchedWriteRes<[M4UnitNSHF, 232 M4UnitS0]> { let Latency = 2; 233 let NumMicroOps = 2; } 234def M4WriteNEONJ : SchedWriteRes<[M4UnitNMSC, 235 M4UnitS0]> { let Latency = 4; } 236def M4WriteNEONK : SchedWriteRes<[M4UnitNSHF, 237 M4UnitNMSC, 238 M4UnitS0]> { let Latency = 5; 239 let NumMicroOps = 2; } 240def M4WriteNEONL : SchedWriteRes<[M4UnitNMUL]> { let Latency = 3; } 241def M4WriteNEONN : SchedWriteRes<[M4UnitNMSC, 242 M4UnitNMSC]> { let Latency = 5; 243 let NumMicroOps = 2; } 244def M4WriteNEONO : SchedWriteRes<[M4UnitNMSC, 245 M4UnitNMSC, 246 M4UnitNMSC]> { let Latency = 8; 247 let NumMicroOps = 3; } 248def M4WriteNEONP : SchedWriteRes<[M4UnitNSHF, 249 M4UnitNMSC]> { let Latency = 4; 250 let NumMicroOps = 2; } 251def M4WriteNEONQ : SchedWriteRes<[M4UnitNMSC, 252 M4UnitC]> { let Latency = 3; 253 let NumMicroOps = 1; } 254def M4WriteNEONR : SchedWriteRes<[M4UnitFCVT0, 255 M4UnitS0]> { let Latency = 4; 256 let NumMicroOps = 1; } 257def M4WriteNEONV : SchedWriteRes<[M4UnitFDIV, 258 M4UnitFDIV]> { let Latency = 7; 259 let ResourceCycles = [6, 6]; } 260def M4WriteNEONVH : SchedWriteRes<[M4UnitFDIVH, 261 M4UnitFDIVH]> { let Latency = 7; 262 let ResourceCycles = [6, 6]; } 263def M4WriteNEONW : SchedWriteRes<[M4UnitFDIV, 264 M4UnitFDIV]> { let Latency = 12; 265 let ResourceCycles = [9, 9]; } 266def M4WriteNEONX : SchedWriteRes<[M4UnitFSQR, 267 M4UnitFSQR]> { let Latency = 8; 268 let ResourceCycles = [7, 7]; } 269def M4WriteNEONXH : SchedWriteRes<[M4UnitFSQRH, 270 M4UnitFSQRH]> { let Latency = 7; 271 let ResourceCycles = [6, 6]; } 272def M4WriteNEONY : SchedWriteRes<[M4UnitFSQR, 273 M4UnitFSQR]> { let Latency = 12; 274 let ResourceCycles = [9, 9]; } 275def M4WriteNEONZ : SchedWriteVariant<[SchedVar<ExynosQFormPred, [M4WriteNEONO]>, 276 SchedVar<NoSchedPred, [M4WriteNEONN]>]>; 277 278def M4WriteFADD2 : SchedWriteRes<[M4UnitFADD]> { let Latency = 2; } 279def M4WriteFADD2H : SchedWriteRes<[M4UnitFADDH]> { let Latency = 2; } 280 281def M4WriteFCVT2 : SchedWriteRes<[M4UnitFCVT]> { let Latency = 2; } 282def M4WriteFCVT2A : SchedWriteRes<[M4UnitFCVT0]> { let Latency = 2; } 283def M4WriteFCVT2H : SchedWriteRes<[M4UnitFCVTH]> { let Latency = 2; } 284def M4WriteFCVT3 : SchedWriteRes<[M4UnitFCVT]> { let Latency = 3; } 285def M4WriteFCVT3A : SchedWriteRes<[M4UnitFCVT0]> { let Latency = 3; } 286def M4WriteFCVT3H : SchedWriteRes<[M4UnitFCVTH]> { let Latency = 3; } 287def M4WriteFCVT4 : SchedWriteRes<[M4UnitFCVT]> { let Latency = 4; } 288def M4WriteFCVT4A : SchedWriteRes<[M4UnitFCVT0]> { let Latency = 4; } 289def M4WriteFCVT6A : SchedWriteRes<[M4UnitFCVT0]> { let Latency = 6; } 290 291def M4WriteFDIV7 : SchedWriteRes<[M4UnitFDIV]> { let Latency = 7; 292 let ResourceCycles = [6]; } 293def M4WriteFDIV7H : SchedWriteRes<[M4UnitFDIVH]> { let Latency = 7; 294 let ResourceCycles = [6]; } 295def M4WriteFDIV12 : SchedWriteRes<[M4UnitFDIV]> { let Latency = 12; 296 let ResourceCycles = [9]; } 297 298def M4WriteFMAC2H : SchedWriteRes<[M4UnitFMACH]> { let Latency = 2; } 299def M4WriteFMAC3H : SchedWriteRes<[M4UnitFMACH]> { let Latency = 3; } 300def M4WriteFMAC3 : SchedWriteRes<[M4UnitFMAC]> { let Latency = 3; } 301def M4WriteFMAC4 : SchedWriteRes<[M4UnitFMAC]> { let Latency = 4; } 302def M4WriteFMAC4H : SchedWriteRes<[M4UnitFMACH]> { let Latency = 4; } 303def M4WriteFMAC5 : SchedWriteRes<[M4UnitFMAC]> { let Latency = 5; } 304 305def M4WriteFSQR7H : SchedWriteRes<[M4UnitFSQRH]> { let Latency = 7; 306 let ResourceCycles = [6]; } 307def M4WriteFSQR8 : SchedWriteRes<[M4UnitFSQR]> { let Latency = 8; 308 let ResourceCycles = [7]; } 309def M4WriteFSQR12 : SchedWriteRes<[M4UnitFSQR]> { let Latency = 12; 310 let ResourceCycles = [9]; } 311 312def M4WriteNALU1 : SchedWriteRes<[M4UnitNALU]> { let Latency = 1; } 313def M4WriteNALU1H : SchedWriteRes<[M4UnitNALUH]> { let Latency = 1; } 314 315def M4WriteNCRY1 : SchedWriteRes<[M4UnitNCRY]> { let Latency = 1; } 316def M4WriteNCRY1A : SchedWriteRes<[M4UnitNCRY0]> { let Latency = 1; } 317def M4WriteNCRY3A : SchedWriteRes<[M4UnitNCRY0]> { let Latency = 3; } 318def M4WriteNCRY5A : SchedWriteRes<[M4UnitNCRY]> { let Latency = 5; } 319 320def M4WriteNHAD1 : SchedWriteRes<[M4UnitNHAD]> { let Latency = 1; } 321def M4WriteNHAD3 : SchedWriteRes<[M4UnitNHAD]> { let Latency = 3; } 322 323def M4WriteNMSC1 : SchedWriteRes<[M4UnitNMSC]> { let Latency = 1; } 324def M4WriteNMSC2 : SchedWriteRes<[M4UnitNMSC]> { let Latency = 2; } 325def M4WriteNMSC3 : SchedWriteRes<[M4UnitNMSC]> { let Latency = 3; } 326 327def M4WriteNMUL3 : SchedWriteRes<[M4UnitNMUL]> { let Latency = 3; } 328 329def M4WriteNSHF1 : SchedWriteRes<[M4UnitNSHF]> { let Latency = 1; } 330def M4WriteNSHF1H : SchedWriteRes<[M4UnitNSHFH]> { let Latency = 1; } 331def M4WriteNSHF3 : SchedWriteRes<[M4UnitNSHF]> { let Latency = 3; } 332def M4WriteNSHFA : SchedWriteRes<[M4UnitNSHF]> { let Latency = 1; 333 let ResourceCycles = [2]; } 334def M4WriteNSHFB : SchedWriteRes<[M4UnitNSHF]> { let Latency = 2; 335 let NumMicroOps = 2; 336 let ResourceCycles = [2]; } 337def M4WriteNSHFC : SchedWriteRes<[M4UnitNSHF]> { let Latency = 3; 338 let NumMicroOps = 3; 339 let ResourceCycles = [4]; } 340def M4WriteNSHFD : SchedWriteRes<[M4UnitNSHF]> { let Latency = 4; 341 let NumMicroOps = 4; 342 let ResourceCycles = [4]; } 343 344def M4WriteNSHT1 : SchedWriteRes<[M4UnitNSHT]> { let Latency = 1; } 345def M4WriteNSHT2 : SchedWriteRes<[M4UnitNSHT]> { let Latency = 2; } 346def M4WriteNSHT3 : SchedWriteRes<[M4UnitNSHT]> { let Latency = 3; } 347def M4WriteNSHT4A : SchedWriteRes<[M4UnitNSHT1]> { let Latency = 4; } 348 349def M4WriteVLDA : SchedWriteRes<[M4UnitL, 350 M4UnitL]> { let Latency = 5; 351 let NumMicroOps = 2; } 352def M4WriteVLDB : SchedWriteRes<[M4UnitL, 353 M4UnitL, 354 M4UnitL]> { let Latency = 6; 355 let NumMicroOps = 3; } 356def M4WriteVLDC : SchedWriteRes<[M4UnitL, 357 M4UnitL, 358 M4UnitL, 359 M4UnitL]> { let Latency = 6; 360 let NumMicroOps = 4; } 361def M4WriteVLDD : SchedWriteRes<[M4UnitL, 362 M4UnitNSHF]> { let Latency = 6; 363 let NumMicroOps = 2; 364 let ResourceCycles = [2, 1]; } 365def M4WriteVLDF : SchedWriteRes<[M4UnitL, 366 M4UnitL]> { let Latency = 10; 367 let NumMicroOps = 2; 368 let ResourceCycles = [3, 3]; } 369def M4WriteVLDG : SchedWriteRes<[M4UnitL, 370 M4UnitNSHF, 371 M4UnitNSHF]> { let Latency = 6; 372 let NumMicroOps = 3; 373 let ResourceCycles = [2, 1, 1]; } 374def M4WriteVLDI : SchedWriteRes<[M4UnitL, 375 M4UnitL, 376 M4UnitL]> { let Latency = 12; 377 let NumMicroOps = 3; 378 let ResourceCycles = [3, 3, 3]; } 379def M4WriteVLDJ : SchedWriteRes<[M4UnitL, 380 M4UnitNSHF, 381 M4UnitNSHF, 382 M4UnitNSHF]> { let Latency = 7; 383 let NumMicroOps = 4; 384 let ResourceCycles = [3, 1, 1, 1]; } 385def M4WriteVLDK : SchedWriteRes<[M4UnitL, 386 M4UnitNSHF, 387 M4UnitNSHF, 388 M4UnitNSHF, 389 M4UnitNSHF]> { let Latency = 7; 390 let NumMicroOps = 5; 391 let ResourceCycles = [3, 1, 1, 1, 1]; } 392def M4WriteVLDL : SchedWriteRes<[M4UnitL, 393 M4UnitNSHF, 394 M4UnitNSHF, 395 M4UnitL, 396 M4UnitNSHF]> { let Latency = 7; 397 let NumMicroOps = 5; 398 let ResourceCycles = [3, 1, 1, 6, 1]; } 399def M4WriteVLDM : SchedWriteRes<[M4UnitL, 400 M4UnitNSHF, 401 M4UnitNSHF, 402 M4UnitL, 403 M4UnitNSHF, 404 M4UnitNSHF]> { let Latency = 7; 405 let NumMicroOps = 6; 406 let ResourceCycles = [3, 1, 1, 3, 1, 1]; } 407def M4WriteVLDN : SchedWriteRes<[M4UnitL, 408 M4UnitL, 409 M4UnitL, 410 M4UnitL]> { let Latency = 14; 411 let NumMicroOps = 4; 412 let ResourceCycles = [3, 3, 3, 3]; } 413 414def M4WriteVST1 : SchedWriteRes<[M4UnitS, 415 M4UnitFST]> { let Latency = 1; 416 let NumMicroOps = 1; } 417def M4WriteVSTA : WriteSequence<[WriteVST], 2>; 418def M4WriteVSTB : WriteSequence<[WriteVST], 3>; 419def M4WriteVSTC : WriteSequence<[WriteVST], 4>; 420def M4WriteVSTD : SchedWriteRes<[M4UnitS, 421 M4UnitFST]> { let Latency = 2; } 422def M4WriteVSTE : SchedWriteRes<[M4UnitS, 423 M4UnitFST, 424 M4UnitS, 425 M4UnitFST]> { let Latency = 2; 426 let NumMicroOps = 2; } 427def M4WriteVSTF : SchedWriteRes<[M4UnitNSHF, 428 M4UnitS, 429 M4UnitFST, 430 M4UnitS, 431 M4UnitFST]> { let Latency = 4; 432 let NumMicroOps = 4; 433 let ResourceCycles = [1, 2, 1, 2, 1]; } 434def M4WriteVSTG : SchedWriteRes<[M4UnitNSHF, 435 M4UnitNSHF, 436 M4UnitNSHF, 437 M4UnitS, 438 M4UnitFST, 439 M4UnitS, 440 M4UnitFST, 441 M4UnitS, 442 M4UnitFST]> { let Latency = 5; 443 let NumMicroOps = 6; 444 let ResourceCycles = [1, 1, 1, 2, 1, 2, 1, 2, 1]; } 445def M4WriteVSTI : SchedWriteRes<[M4UnitNSHF, 446 M4UnitNSHF, 447 M4UnitNSHF, 448 M4UnitNSHF, 449 M4UnitS, 450 M4UnitFST, 451 M4UnitS, 452 M4UnitFST, 453 M4UnitS, 454 M4UnitFST, 455 M4UnitS, 456 M4UnitFST]> { let Latency = 8; 457 let NumMicroOps = 5; 458 let ResourceCycles = [1, 1, 1, 1, 2, 1, 2, 1, 2, 1, 2, 1]; } 459def M4WriteVSTJ : SchedWriteRes<[M4UnitA, 460 M4UnitS, 461 M4UnitFST]> { let Latency = 1; 462 let NumMicroOps = 2; } 463def M4WriteVSTK : SchedWriteRes<[M4UnitA, 464 M4UnitS, 465 M4UnitFST]> { let Latency = 3; 466 let NumMicroOps = 2; } 467def M4WriteVSTL : SchedWriteRes<[M4UnitNSHF, 468 M4UnitNSHF, 469 M4UnitS, 470 M4UnitFST, 471 M4UnitS, 472 M4UnitFST]> { let Latency = 4; 473 let NumMicroOps = 4; 474 let ResourceCycles = [1, 1, 2, 1, 2, 1]; } 475 476// Special cases. 477def M4WriteCOPY : SchedWriteVariant<[SchedVar<ExynosFPPred, [M4WriteNALU1]>, 478 SchedVar<NoSchedPred, [M4WriteZ0]>]>; 479def M4WriteMOVI : SchedWriteVariant<[SchedVar<IsZeroFPIdiomPred, [M4WriteZ0]>, 480 SchedVar<NoSchedPred, [M4WriteNALU1]>]>; 481 482// Fast forwarding. 483def M4ReadAESM1 : SchedReadAdvance<+1, [M4WriteNCRY1]>; 484def M4ReadFMACM1 : SchedReadAdvance<+1, [M4WriteFMAC4, 485 M4WriteFMAC4H, 486 M4WriteFMAC5]>; 487def M4ReadNMULM1 : SchedReadAdvance<+1, [M4WriteNMUL3]>; 488def M4ReadNMULP2 : SchedReadAdvance<-2, [M4WriteNMUL3]>; 489 490 491//===----------------------------------------------------------------------===// 492// Coarse scheduling model. 493 494// Branch instructions. 495def : SchedAlias<WriteBr, M4WriteZ0>; 496def : SchedAlias<WriteBrReg, M4WriteC1>; 497 498// Arithmetic and logical integer instructions. 499def : SchedAlias<WriteI, M4WriteA1>; 500def : SchedAlias<WriteIEReg, M4WriteAA>; // FIXME: M4WriteAX crashes TableGen. 501def : SchedAlias<WriteISReg, M4WriteAA>; // FIXME: M4WriteAX crashes TableGen. 502def : SchedAlias<WriteIS, M4WriteA1>; 503 504// Move instructions. 505def : SchedAlias<WriteImm, M4WriteA1>; 506 507// Divide and multiply instructions. 508def : SchedAlias<WriteID32, M4WriteD12>; 509def : SchedAlias<WriteID64, M4WriteD21>; 510def : SchedAlias<WriteIM32, M4WriteC3>; 511def : SchedAlias<WriteIM64, M4WriteCA>; 512 513// Miscellaneous instructions. 514def : SchedAlias<WriteExtr, M4WriteAY>; 515 516// Addressing modes. 517def : SchedAlias<WriteAdr, M4WriteZ1>; 518def : SchedAlias<ReadAdrBase, M4ReadAdrBase>; 519 520// Load instructions. 521def : SchedAlias<WriteLD, M4WriteL4>; 522def : SchedAlias<WriteLDHi, M4WriteZ4>; 523def : SchedAlias<WriteLDIdx, M4WriteLX>; 524 525// Store instructions. 526def : SchedAlias<WriteST, M4WriteS1>; 527def : SchedAlias<WriteSTP, M4WriteS1>; 528def : SchedAlias<WriteSTX, M4WriteS1>; 529def : SchedAlias<WriteSTIdx, M4WriteSX>; 530 531// FP data instructions. 532def : SchedAlias<WriteF, M4WriteFADD2>; 533def : SchedAlias<WriteFCmp, M4WriteNMSC2>; 534def : SchedAlias<WriteFDiv, M4WriteFDIV12>; 535def : SchedAlias<WriteFMul, M4WriteFMAC3>; 536 537// FP miscellaneous instructions. 538def : SchedAlias<WriteFCvt, M4WriteFCVT2>; 539def : SchedAlias<WriteFImm, M4WriteNALU1>; 540def : SchedAlias<WriteFCopy, M4WriteCOPY>; 541 542// FP load instructions. 543def : SchedAlias<WriteVLD, M4WriteL5>; 544 545// FP store instructions. 546def : SchedAlias<WriteVST, M4WriteVST1>; 547 548// ASIMD FP instructions. 549def : SchedAlias<WriteV, M4WriteNALU1>; 550 551// Other miscellaneous instructions. 552def : WriteRes<WriteAtomic, []> { let Unsupported = 1; } 553def : WriteRes<WriteBarrier, []> { let Latency = 1; } 554def : WriteRes<WriteHint, []> { let Latency = 1; } 555def : WriteRes<WriteSys, []> { let Latency = 1; } 556 557//===----------------------------------------------------------------------===// 558// Generic fast forwarding. 559 560// TODO: Add FP register forwarding rules. 561 562def : ReadAdvance<ReadI, 0>; 563def : ReadAdvance<ReadISReg, 0>; 564def : ReadAdvance<ReadIEReg, 0>; 565def : ReadAdvance<ReadIM, 0>; 566// TODO: The forwarding for 32 bits actually saves 2 cycles. 567def : ReadAdvance<ReadIMA, 3, [WriteIM32, WriteIM64]>; 568def : ReadAdvance<ReadID, 0>; 569def : ReadAdvance<ReadExtrHi, 0>; 570def : ReadAdvance<ReadAdrBase, 0>; 571def : ReadAdvance<ReadVLD, 0>; 572 573//===----------------------------------------------------------------------===// 574// Finer scheduling model. 575 576// Branch instructions 577def : InstRW<[M4WriteB1], (instrs Bcc)>; 578def : InstRW<[M4WriteAF], (instrs BL)>; 579def : InstRW<[M4WriteBX], (instrs BLR)>; 580def : InstRW<[M4WriteC1], (instregex "^CBN?Z[WX]")>; 581def : InstRW<[M4WriteAD], (instregex "^TBN?Z[WX]")>; 582 583// Arithmetic and logical integer instructions. 584def : InstRW<[M4WriteAX], (instregex "^(ADD|AND|BIC|EON|EOR|ORN|SUB)[WX]rs$")>; 585def : InstRW<[M4WriteAU], (instrs ORRWrs, ORRXrs)>; 586def : InstRW<[M4WriteAX], (instregex "^(ADD|AND|BIC|SUB)S[WX]rs$")>; 587def : InstRW<[M4WriteAX], (instregex "^(ADD|SUB)S?[WX]rx(64)?$")>; 588def : InstRW<[M4WriteAV], (instrs ADDWri, ADDXri, ORRWri, ORRXri)>; 589 590// Move instructions. 591def : InstRW<[M4WriteCOPY], (instrs COPY)>; 592def : InstRW<[M4WriteZ0], (instrs ADR, ADRP)>; 593def : InstRW<[M4WriteZ0], (instregex "^MOV[NZ][WX]i")>; 594 595// Divide and multiply instructions. 596 597// Miscellaneous instructions. 598 599// Load instructions. 600def : InstRW<[M4WriteLD, 601 WriteLDHi, 602 WriteAdr], (instregex "^LDP(SW|W|X)(post|pre)")>; 603def : InstRW<[M4WriteL5, 604 ReadAdrBase], (instregex "^LDR(BB|SBW|SBX|HH|SHW|SHX|SW|W|X)roW")>; 605def : InstRW<[WriteLDIdx, 606 ReadAdrBase], (instregex "^LDR(BB|SBW|SBX|HH|SHW|SHX|SW|W|X)roX")>; 607def : InstRW<[M4WriteL5, 608 ReadAdrBase], (instrs PRFMroW)>; 609def : InstRW<[WriteLDIdx, 610 ReadAdrBase], (instrs PRFMroX)>; 611 612// Store instructions. 613def : InstRW<[M4WriteSB, 614 ReadAdrBase], (instregex "^STR(BB|HH|W|X)roW")>; 615def : InstRW<[WriteST, 616 ReadAdrBase], (instregex "^STR(BB|HH|W|X)roX")>; 617 618// FP data instructions. 619def : InstRW<[M4WriteNSHF1H], (instrs FABSHr)>; 620def : InstRW<[M4WriteNSHF1], (instregex "^FABS[SD]r")>; 621def : InstRW<[M4WriteFADD2H], (instregex "^F(ADD|SUB)Hrr")>; 622def : InstRW<[M4WriteFADD2], (instregex "^F(ADD|SUB)[SD]rr")>; 623def : InstRW<[M4WriteFADD2H], (instregex "^FADDPv.i16")>; 624def : InstRW<[M4WriteFADD2], (instregex "^FADDPv.i(32|64)")>; 625def : InstRW<[M4WriteNEONQ], (instregex "^FCCMPE?[HSD]rr")>; 626def : InstRW<[M4WriteNMSC2], (instregex "^FCMPE?[HSD]r[ir]")>; 627def : InstRW<[M4WriteNMSC1], (instregex "^F(AC|CM)(EQ|GE|GT|LE|LT)(16|32|64|v1)")>; 628def : InstRW<[M4WriteFDIV7H], (instrs FDIVHrr)>; 629def : InstRW<[M4WriteFDIV7], (instrs FDIVSrr)>; 630def : InstRW<[M4WriteFDIV12], (instrs FDIVDrr)>; 631def : InstRW<[M4WriteNMSC1], (instregex "^F(MAX|MIN)(NM)?[HSD]rr")>; 632def : InstRW<[M4WriteFMAC3H], (instregex "^FN?MULHrr")>; 633def : InstRW<[M4WriteFMAC3], (instregex "^FN?MUL[SD]rr")>; 634def : InstRW<[M4WriteFMAC3H], (instrs FMULX16)>; 635def : InstRW<[M4WriteFMAC3], (instregex "^FMULX(32|64)")>; 636def : InstRW<[M4WriteFMAC4H, 637 M4ReadFMACM1], (instregex "^FN?M(ADD|SUB)Hrrr")>; 638def : InstRW<[M4WriteFMAC4, 639 M4ReadFMACM1], (instregex "^FN?M(ADD|SUB)[SD]rrr")>; 640def : InstRW<[M4WriteNALU1H], (instrs FNEGHr)>; 641def : InstRW<[M4WriteNALU1], (instregex "^FNEG[SD]r")>; 642def : InstRW<[M4WriteFCVT3A], (instregex "^FRINT.+r")>; 643def : InstRW<[M4WriteNEONH], (instregex "^FCSEL[HSD]rrr")>; 644def : InstRW<[M4WriteFSQR7H], (instrs FSQRTHr)>; 645def : InstRW<[M4WriteFSQR8], (instrs FSQRTSr)>; 646def : InstRW<[M4WriteFSQR12], (instrs FSQRTDr)>; 647 648// FP miscellaneous instructions. 649def : InstRW<[M4WriteFCVT2H], (instregex "^FCVTH[SD]r")>; 650def : InstRW<[M4WriteFCVT2H], (instregex "^FCVT[SD]Hr")>; 651def : InstRW<[M4WriteFCVT2], (instregex "^FCVT[SD][SD]r")>; 652def : InstRW<[M4WriteFCVT6A], (instregex "^[SU]CVTF[SU][XW][HSD]ri")>; 653def : InstRW<[M4WriteNEONR], (instregex "^FCVT[AMNPZ][SU][SU][XW][HSD]r")>; 654def : InstRW<[M4WriteNALU1], (instregex "^FMOV[HSD][ir]")>; 655def : InstRW<[M4WriteSA], (instregex "^FMOV[WX][HSD]r")>; 656def : InstRW<[M4WriteNEONJ], (instregex "^FMOV[HSD][WX]r")>; 657def : InstRW<[M4WriteNEONI], (instregex "^FMOVXDHighr")>; 658def : InstRW<[M4WriteNEONK], (instregex "^FMOVDXHighr")>; 659def : InstRW<[M4WriteFCVT3H], (instregex "^F(RECP|RSQRT)Ev1f16")>; 660def : InstRW<[M4WriteFCVT3], (instregex "^F(RECP|RSQRT)Ev1i(32|64)")>; 661def : InstRW<[M4WriteNMSC1], (instregex "^FRECPXv1")>; 662def : InstRW<[M4WriteFMAC4H], (instregex "^F(RECP|RSQRT)S16")>; 663def : InstRW<[M4WriteFMAC4], (instregex "^F(RECP|RSQRT)S(32|64)")>; 664 665// FP load instructions. 666def : InstRW<[WriteVLD], (instregex "^LDR[SDQ]l")>; 667def : InstRW<[WriteVLD], (instregex "^LDUR[BHSDQ]i")>; 668def : InstRW<[WriteVLD, 669 WriteAdr], (instregex "^LDR[BHSDQ](post|pre)")>; 670def : InstRW<[WriteVLD], (instregex "^LDR[BHSDQ]ui")>; 671def : InstRW<[M4WriteLE, 672 ReadAdrBase], (instregex "^LDR[BHSDQ]roW")>; 673def : InstRW<[WriteVLD, 674 ReadAdrBase], (instregex "^LDR[BHSD]roX")>; 675def : InstRW<[M4WriteLE, 676 ReadAdrBase], (instrs LDRQroX)>; 677def : InstRW<[WriteVLD, 678 M4WriteLH], (instregex "^LDN?P[SD]i")>; 679def : InstRW<[M4WriteLA, 680 M4WriteLH], (instregex "^LDN?PQi")>; 681def : InstRW<[M4WriteL5, 682 M4WriteLH, 683 WriteAdr], (instregex "^LDP[SD]post")>; 684def : InstRW<[M4WriteLB, 685 M4WriteLH, 686 WriteAdr], (instrs LDPQpost)>; 687def : InstRW<[M4WriteLB, 688 M4WriteLH, 689 WriteAdr], (instregex "^LDP[SD]pre")>; 690def : InstRW<[M4WriteLC, 691 M4WriteLH, 692 WriteAdr], (instrs LDPQpre)>; 693 694// FP store instructions. 695def : InstRW<[WriteVST], (instregex "^STUR[BHSDQ]i")>; 696def : InstRW<[WriteVST, 697 WriteAdr], (instregex "^STR[BHSDQ](post|pre)")>; 698def : InstRW<[WriteVST], (instregex "^STR[BHSDQ]ui")>; 699def : InstRW<[M4WriteVSTJ, 700 ReadAdrBase], (instregex "^STR[BHSD]roW")>; 701def : InstRW<[M4WriteVSTK, 702 ReadAdrBase], (instrs STRQroW)>; 703def : InstRW<[WriteVST, 704 ReadAdrBase], (instregex "^STR[BHSD]roX")>; 705def : InstRW<[M4WriteVSTK, 706 ReadAdrBase], (instrs STRQroX)>; 707def : InstRW<[WriteVST], (instregex "^STN?P[SD]i")>; 708def : InstRW<[M4WriteVSTA], (instregex "^STN?PQi")>; 709def : InstRW<[WriteVST, 710 WriteAdr], (instregex "^STP[SD](post|pre)")>; 711def : InstRW<[M4WriteVSTJ, 712 WriteAdr], (instregex "^STPQ(post|pre)")>; 713 714// ASIMD instructions. 715def : InstRW<[M4WriteNHAD1], (instregex "^[SU]ABDL?v")>; 716def : InstRW<[M4WriteNHAD3], (instregex "^[SU]ABAL?v")>; 717def : InstRW<[M4WriteNMSC1], (instregex "^ABSv")>; 718def : InstRW<[M4WriteNALU1], (instregex "^(ADD|NEG|SUB)v")>; 719def : InstRW<[M4WriteNHAD3], (instregex "^[SU]?ADDL?Pv")>; 720def : InstRW<[M4WriteNHAD3], (instregex "^[SU]H(ADD|SUB)v")>; 721def : InstRW<[M4WriteNHAD3], (instregex "^[SU](ADD|SUB)[LW]v")>; 722def : InstRW<[M4WriteNHAD3], (instregex "^R?(ADD|SUB)HN2?v")>; 723def : InstRW<[M4WriteNHAD3], (instregex "^[SU]Q(ADD|SUB)v")>; 724def : InstRW<[M4WriteNHAD3], (instregex "^(SU|US)QADDv")>; 725def : InstRW<[M4WriteNHAD3], (instregex "^[SU]RHADDv")>; 726def : InstRW<[M4WriteNMSC1], (instregex "^SQ(ABS|NEG)v")>; 727def : InstRW<[M4WriteNHAD3], (instregex "^[SU]?ADDL?Vv")>; 728def : InstRW<[M4WriteNMSC1], (instregex "^CM(EQ|GE|GT|HI|HS|LE|LT)v")>; 729def : InstRW<[M4WriteNALU1], (instregex "^CMTSTv")>; 730def : InstRW<[M4WriteNALU1], (instregex "^(AND|BIC|EOR|NOT|ORN|ORR)v")>; 731def : InstRW<[M4WriteNMSC1], (instregex "^[SU](MIN|MAX)v")>; 732def : InstRW<[M4WriteNMSC2], (instregex "^[SU](MIN|MAX)Pv")>; 733def : InstRW<[M4WriteNHAD3], (instregex "^[SU](MIN|MAX)Vv")>; 734def : InstRW<[M4WriteNMUL3, 735 M4ReadNMULM1], (instregex "^ML[AS]v")>; 736def : InstRW<[M4WriteNMUL3, 737 M4ReadNMULM1], (instregex "^(SQR?D)?MULH?v")>; 738def : InstRW<[M4WriteNMUL3, 739 M4ReadNMULM1], (instregex "^SQRDML[AS]H")>; 740def : InstRW<[M4WriteNMUL3, 741 M4ReadNMULM1], (instregex "^(S|U|SQD)ML[AS]L(v1(i32|i64)|v2i32|v4i16|v8i8)")>; 742def : InstRW<[M4WriteNMUL3, 743 M4ReadNMULP2], (instregex "^(S|U|SQD)ML[AS]L(v4i32|v8i16|v16i8)")>; 744def : InstRW<[M4WriteNMUL3, 745 M4ReadNMULM1], (instregex "^(S|U|SQD)MULL(v1(i32|i64)|v2i32|v4i16|v8i8)")>; 746def : InstRW<[M4WriteNMUL3, 747 M4ReadNMULP2], (instregex "^(S|U|SQD)MULL(v4i32|v8i16|v16i8)")>; 748def : InstRW<[M4WriteNMUL3], (instregex "^[SU]DOT(lane)?v")>; 749def : InstRW<[M4WriteNHAD3], (instregex "^[SU]ADALPv")>; 750def : InstRW<[M4WriteNSHT4A], (instregex "^[SU]R?SRA[dv]")>; 751def : InstRW<[M4WriteNSHT1], (instregex "^SHL[dv]")>; 752def : InstRW<[M4WriteNSHT1], (instregex "^S[LR]I[dv]")>; 753def : InstRW<[M4WriteNSHT1], (instregex "^[SU]SH[LR][dv]")>; 754def : InstRW<[M4WriteNSHT2], (instregex "^[SU]?SHLLv")>; 755def : InstRW<[M4WriteNSHT4A], (instregex "^[SU]?Q?R?SHRU?N[bhsv]")>; 756def : InstRW<[M4WriteNSHT4A], (instregex "^[SU]RSH[LR][dv]")>; 757def : InstRW<[M4WriteNSHT4A], (instregex "^[SU]QR?SHLU?[bhsdv]")>; 758 759// ASIMD FP instructions. 760def : InstRW<[M4WriteNSHF1H], (instregex "^FABSv.f16")>; 761def : InstRW<[M4WriteNSHF1], (instregex "^FABSv.f(32|64)")>; 762def : InstRW<[M4WriteFADD2H], (instregex "^F(ABD|ADD|SUB)v.f16")>; 763def : InstRW<[M4WriteFADD2], (instregex "^F(ABD|ADD|SUB)v.f(32|64)")>; 764def : InstRW<[M4WriteFADD2H], (instregex "^FADDPv.f16")>; 765def : InstRW<[M4WriteFADD2], (instregex "^FADDPv.f(32|64)")>; 766def : InstRW<[M4WriteNMSC1], (instregex "^F(AC|CM)(EQ|GE|GT|LE|LT)v[^1]")>; 767def : InstRW<[M4WriteFCVT2], (instregex "^FCVT(L|N|XN)v")>; 768def : InstRW<[M4WriteFCVT2A], (instregex "^FCVT[AMNPZ][SU]v")>; 769def : InstRW<[M4WriteFCVT2H], (instregex "^[SU]CVTFv.[fi]16")>; 770def : InstRW<[M4WriteFCVT2], (instregex "^[SU]CVTFv.[fi](32|64)")>; 771def : InstRW<[M4WriteFDIV7H], (instrs FDIVv4f16)>; 772def : InstRW<[M4WriteNEONVH], (instrs FDIVv8f16)>; 773def : InstRW<[M4WriteFDIV7], (instrs FDIVv2f32)>; 774def : InstRW<[M4WriteNEONV], (instrs FDIVv4f32)>; 775def : InstRW<[M4WriteNEONW], (instrs FDIVv2f64)>; 776def : InstRW<[M4WriteNMSC1], (instregex "^F(MAX|MIN)(NM)?v")>; 777def : InstRW<[M4WriteNMSC2], (instregex "^F(MAX|MIN)(NM)?Pv")>; 778def : InstRW<[M4WriteNEONZ], (instregex "^F(MAX|MIN)(NM)?Vv")>; 779def : InstRW<[M4WriteFMAC2H], (instregex "^FMULX?v.[fi]16")>; 780def : InstRW<[M4WriteFMAC3], (instregex "^FMULX?v.[fi](32|64)")>; 781def : InstRW<[M4WriteFMAC4H, 782 M4ReadFMACM1], (instregex "^FML[AS]v.[fi]16")>; 783def : InstRW<[M4WriteFMAC4, 784 M4ReadFMACM1], (instregex "^FML[AS]v.[fi](32|64)")>; 785def : InstRW<[M4WriteNALU1H], (instregex "^FNEGv.f16")>; 786def : InstRW<[M4WriteNALU1], (instregex "^FNEGv.f(32|64)")>; 787def : InstRW<[M4WriteFCVT3A], (instregex "^FRINT[AIMNPXZ]v")>; 788def : InstRW<[M4WriteFSQR7H], (instrs FSQRTv4f16)>; 789def : InstRW<[M4WriteNEONXH], (instrs FSQRTv8f16)>; 790def : InstRW<[M4WriteFSQR8], (instrs FSQRTv2f32)>; 791def : InstRW<[M4WriteNEONX], (instrs FSQRTv4f32)>; 792def : InstRW<[M4WriteNEONY], (instrs FSQRTv2f64)>; 793 794// ASIMD miscellaneous instructions. 795def : InstRW<[M4WriteNALU1], (instregex "^RBITv")>; 796def : InstRW<[M4WriteNALU1], (instregex "^(BIF|BIT|BSL)v")>; 797def : InstRW<[M4WriteNALU1], (instregex "^CL[STZ]v")>; 798def : InstRW<[M4WriteNEONB], (instregex "^DUPv.+gpr")>; 799def : InstRW<[M4WriteNSHF1], (instregex "^CPY")>; 800def : InstRW<[M4WriteNSHF1], (instregex "^DUPv.+lane")>; 801def : InstRW<[M4WriteNSHF1], (instregex "^EXTv")>; 802def : InstRW<[M4WriteNSHT4A], (instregex "^XTNv")>; 803def : InstRW<[M4WriteNSHT4A], (instregex "^[SU]?QXTU?Nv")>; 804def : InstRW<[M4WriteNEONB], (instregex "^INSv.+gpr")>; 805def : InstRW<[M4WriteNSHF1], (instregex "^INSv.+lane")>; 806def : InstRW<[M4WriteMOVI], (instregex "^(MOV|MVN)I")>; 807def : InstRW<[M4WriteNALU1H], (instregex "^FMOVv.f16")>; 808def : InstRW<[M4WriteNALU1], (instregex "^FMOVv.f(32|64)")>; 809def : InstRW<[M4WriteFCVT3H], (instregex "^F(RECP|RSQRT)Ev[248]f16")>; 810def : InstRW<[M4WriteFCVT3], (instregex "^F(RECP|RSQRT)Ev[248]f(32|64)")>; 811def : InstRW<[M4WriteFCVT3], (instregex "^U(RECP|RSQRT)Ev[24]i32")>; 812def : InstRW<[M4WriteFMAC4H], (instregex "^F(RECP|RSQRT)Sv.f16")>; 813def : InstRW<[M4WriteFMAC4], (instregex "^F(RECP|RSQRT)Sv.f(32|64)")>; 814def : InstRW<[M4WriteNSHF1], (instregex "^REV(16|32|64)v")>; 815def : InstRW<[M4WriteNSHFA], (instregex "^TB[LX]v(8|16)i8One")>; 816def : InstRW<[M4WriteNSHFB], (instregex "^TB[LX]v(8|16)i8Two")>; 817def : InstRW<[M4WriteNSHFC], (instregex "^TB[LX]v(8|16)i8Three")>; 818def : InstRW<[M4WriteNSHFD], (instregex "^TB[LX]v(8|16)i8Four")>; 819def : InstRW<[M4WriteNEONP], (instregex "^[SU]MOVv")>; 820def : InstRW<[M4WriteNSHF1], (instregex "^(TRN|UZP|ZIP)[12]v")>; 821 822// ASIMD load instructions. 823def : InstRW<[WriteVLD], (instregex "LD1Onev(8b|4h|2s|1d)$")>; 824def : InstRW<[WriteVLD, 825 M4WriteA1], (instregex "LD1Onev(8b|4h|2s|1d)_POST$")>; 826def : InstRW<[WriteVLD], (instregex "LD1Onev(16b|8h|4s|2d)$")>; 827def : InstRW<[WriteVLD, 828 M4WriteA1], (instregex "LD1Onev(16b|8h|4s|2d)_POST$")>; 829 830def : InstRW<[M4WriteVLDA], (instregex "LD1Twov(8b|4h|2s|1d)$")>; 831def : InstRW<[M4WriteVLDA, 832 M4WriteA1], (instregex "LD1Twov(8b|4h|2s|1d)_POST$")>; 833def : InstRW<[M4WriteVLDA], (instregex "LD1Twov(16b|8h|4s|2d)$")>; 834def : InstRW<[M4WriteVLDA, 835 M4WriteA1], (instregex "LD1Twov(16b|8h|4s|2d)_POST$")>; 836 837def : InstRW<[M4WriteVLDB], (instregex "LD1Threev(8b|4h|2s|1d)$")>; 838def : InstRW<[M4WriteVLDB, 839 M4WriteA1], (instregex "LD1Threev(8b|4h|2s|1d)_POST$")>; 840def : InstRW<[M4WriteVLDB], (instregex "LD1Threev(16b|8h|4s|2d)$")>; 841def : InstRW<[M4WriteVLDB, 842 M4WriteA1], (instregex "LD1Threev(16b|8h|4s|2d)_POST$")>; 843 844def : InstRW<[M4WriteVLDC], (instregex "LD1Fourv(8b|4h|2s|1d)$")>; 845def : InstRW<[M4WriteVLDC, 846 M4WriteA1], (instregex "LD1Fourv(8b|4h|2s|1d)_POST$")>; 847def : InstRW<[M4WriteVLDC], (instregex "LD1Fourv(16b|8h|4s|2d)$")>; 848def : InstRW<[M4WriteVLDC, 849 M4WriteA1], (instregex "LD1Fourv(16b|8h|4s|2d)_POST$")>; 850 851def : InstRW<[M4WriteVLDD], (instregex "LD1i(8|16|32|64)$")>; 852def : InstRW<[M4WriteVLDD, 853 M4WriteA1], (instregex "LD1i(8|16|32|64)_POST$")>; 854 855def : InstRW<[WriteVLD], (instregex "LD1Rv(8b|4h|2s|1d)$")>; 856def : InstRW<[WriteVLD, 857 M4WriteA1], (instregex "LD1Rv(8b|4h|2s|1d)_POST$")>; 858def : InstRW<[WriteVLD], (instregex "LD1Rv(16b|8h|4s|2d)$")>; 859def : InstRW<[WriteVLD, 860 M4WriteA1], (instregex "LD1Rv(16b|8h|4s|2d)_POST$")>; 861 862def : InstRW<[M4WriteVLDF], (instregex "LD2Twov(8b|4h|2s)$")>; 863def : InstRW<[M4WriteVLDF, 864 M4WriteA1], (instregex "LD2Twov(8b|4h|2s)_POST$")>; 865def : InstRW<[M4WriteVLDF], (instregex "LD2Twov(16b|8h|4s|2d)$")>; 866def : InstRW<[M4WriteVLDF, 867 M4WriteA1], (instregex "LD2Twov(16b|8h|4s|2d)_POST$")>; 868 869def : InstRW<[M4WriteVLDG], (instregex "LD2i(8|16|32|64)$")>; 870def : InstRW<[M4WriteVLDG, 871 M4WriteA1], (instregex "LD2i(8|16|32|64)_POST$")>; 872 873def : InstRW<[M4WriteVLDA], (instregex "LD2Rv(8b|4h|2s|1d)$")>; 874def : InstRW<[M4WriteVLDA, 875 M4WriteA1], (instregex "LD2Rv(8b|4h|2s|1d)_POST$")>; 876def : InstRW<[M4WriteVLDA], (instregex "LD2Rv(16b|8h|4s|2d)$")>; 877def : InstRW<[M4WriteVLDA, 878 M4WriteA1], (instregex "LD2Rv(16b|8h|4s|2d)_POST$")>; 879 880def : InstRW<[M4WriteVLDI], (instregex "LD3Threev(8b|4h|2s)$")>; 881def : InstRW<[M4WriteVLDI, 882 M4WriteA1], (instregex "LD3Threev(8b|4h|2s)_POST$")>; 883def : InstRW<[M4WriteVLDI], (instregex "LD3Threev(16b|8h|4s|2d)$")>; 884def : InstRW<[M4WriteVLDI, 885 M4WriteA1], (instregex "LD3Threev(16b|8h|4s|2d)_POST$")>; 886 887def : InstRW<[M4WriteVLDJ], (instregex "LD3i(8|16|32)$")>; 888def : InstRW<[M4WriteVLDJ, 889 M4WriteA1], (instregex "LD3i(8|16|32)_POST$")>; 890def : InstRW<[M4WriteVLDL], (instregex "LD3i64$")>; 891def : InstRW<[M4WriteVLDL, 892 M4WriteA1], (instregex "LD3i64_POST$")>; 893 894def : InstRW<[M4WriteVLDB], (instregex "LD3Rv(8b|4h|2s|1d)$")>; 895def : InstRW<[M4WriteVLDB, 896 M4WriteA1], (instregex "LD3Rv(8b|4h|2s|1d)_POST$")>; 897def : InstRW<[M4WriteVLDB], (instregex "LD3Rv(16b|8h|4s|2d)$")>; 898def : InstRW<[M4WriteVLDB, 899 M4WriteA1], (instregex "LD3Rv(16b|8h|4s|2d)_POST$")>; 900 901def : InstRW<[M4WriteVLDN], (instregex "LD4Fourv(8b|4h|2s)$")>; 902def : InstRW<[M4WriteVLDN, 903 M4WriteA1], (instregex "LD4Fourv(8b|4h|2s)_POST$")>; 904def : InstRW<[M4WriteVLDN], (instregex "LD4Fourv(16b|8h|4s|2d)$")>; 905def : InstRW<[M4WriteVLDN, 906 M4WriteA1], (instregex "LD4Fourv(16b|8h|4s|2d)_POST$")>; 907 908def : InstRW<[M4WriteVLDK], (instregex "LD4i(8|16|32)$")>; 909def : InstRW<[M4WriteVLDK, 910 M4WriteA1], (instregex "LD4i(8|16|32)_POST$")>; 911def : InstRW<[M4WriteVLDM], (instregex "LD4i64$")>; 912def : InstRW<[M4WriteVLDM, 913 M4WriteA1], (instregex "LD4i64_POST$")>; 914 915def : InstRW<[M4WriteVLDC], (instregex "LD4Rv(8b|4h|2s|1d)$")>; 916def : InstRW<[M4WriteVLDC, 917 M4WriteA1], (instregex "LD4Rv(8b|4h|2s|1d)_POST$")>; 918def : InstRW<[M4WriteVLDC], (instregex "LD4Rv(16b|8h|4s|2d)$")>; 919def : InstRW<[M4WriteVLDC, 920 M4WriteA1], (instregex "LD4Rv(16b|8h|4s|2d)_POST$")>; 921 922// ASIMD store instructions. 923def : InstRW<[WriteVST], (instregex "ST1Onev(8b|4h|2s|1d)$")>; 924def : InstRW<[WriteVST, 925 M4WriteA1], (instregex "ST1Onev(8b|4h|2s|1d)_POST$")>; 926def : InstRW<[WriteVST], (instregex "ST1Onev(16b|8h|4s|2d)$")>; 927def : InstRW<[WriteVST, 928 M4WriteA1], (instregex "ST1Onev(16b|8h|4s|2d)_POST$")>; 929 930def : InstRW<[M4WriteVSTA], (instregex "ST1Twov(8b|4h|2s|1d)$")>; 931def : InstRW<[M4WriteVSTA, 932 M4WriteA1], (instregex "ST1Twov(8b|4h|2s|1d)_POST$")>; 933def : InstRW<[M4WriteVSTA], (instregex "ST1Twov(16b|8h|4s|2d)$")>; 934def : InstRW<[M4WriteVSTA, 935 M4WriteA1], (instregex "ST1Twov(16b|8h|4s|2d)_POST$")>; 936 937def : InstRW<[M4WriteVSTB], (instregex "ST1Threev(8b|4h|2s|1d)$")>; 938def : InstRW<[M4WriteVSTB, 939 M4WriteA1], (instregex "ST1Threev(8b|4h|2s|1d)_POST$")>; 940def : InstRW<[M4WriteVSTB], (instregex "ST1Threev(16b|8h|4s|2d)$")>; 941def : InstRW<[M4WriteVSTB, 942 M4WriteA1], (instregex "ST1Threev(16b|8h|4s|2d)_POST$")>; 943 944def : InstRW<[M4WriteVSTC], (instregex "ST1Fourv(8b|4h|2s|1d)$")>; 945def : InstRW<[M4WriteVSTC, 946 M4WriteA1], (instregex "ST1Fourv(8b|4h|2s|1d)_POST$")>; 947def : InstRW<[M4WriteVSTC], (instregex "ST1Fourv(16b|8h|4s|2d)$")>; 948def : InstRW<[M4WriteVSTC, 949 M4WriteA1], (instregex "ST1Fourv(16b|8h|4s|2d)_POST$")>; 950 951def : InstRW<[WriteVST], (instregex "ST1i(8|16|32|64)$")>; 952def : InstRW<[WriteVST, 953 M4WriteA1], (instregex "ST1i(8|16|32|64)_POST$")>; 954 955def : InstRW<[M4WriteVSTD], (instregex "ST2Twov(8b|4h|2s)$")>; 956def : InstRW<[M4WriteVSTD, 957 M4WriteA1], (instregex "ST2Twov(8b|4h|2s)_POST$")>; 958def : InstRW<[M4WriteVSTE], (instregex "ST2Twov(16b|8h|4s|2d)$")>; 959def : InstRW<[M4WriteVSTE, 960 M4WriteA1], (instregex "ST2Twov(16b|8h|4s|2d)_POST$")>; 961 962def : InstRW<[M4WriteVSTD], (instregex "ST2i(8|16|32|64)$")>; 963def : InstRW<[M4WriteVSTD, 964 M4WriteA1], (instregex "ST2i(8|16|32|64)_POST$")>; 965 966def : InstRW<[M4WriteVSTF], (instregex "ST3Threev(8b|4h|2s)$")>; 967def : InstRW<[M4WriteVSTF, 968 M4WriteA1], (instregex "ST3Threev(8b|4h|2s)_POST$")>; 969def : InstRW<[M4WriteVSTG], (instregex "ST3Threev(16b|8h|4s|2d)$")>; 970def : InstRW<[M4WriteVSTG, 971 M4WriteA1], (instregex "ST3Threev(16b|8h|4s|2d)_POST$")>; 972 973def : InstRW<[M4WriteVSTE], (instregex "ST3i(8|16|32|64)$")>; 974def : InstRW<[M4WriteVSTE, 975 M4WriteA1], (instregex "ST3i(8|16|32|64)_POST$")>; 976 977def : InstRW<[M4WriteVSTL], (instregex "ST4Fourv(8b|4h|2s)$")>; 978def : InstRW<[M4WriteVSTL, 979 M4WriteA1], (instregex "ST4Fourv(8b|4h|2s)_POST$")>; 980def : InstRW<[M4WriteVSTI], (instregex "ST4Fourv(16b|8h|4s|2d)$")>; 981def : InstRW<[M4WriteVSTI, 982 M4WriteA1], (instregex "ST4Fourv(16b|8h|4s|2d)_POST$")>; 983 984def : InstRW<[M4WriteVSTE], (instregex "ST4i(8|16|32|64)$")>; 985def : InstRW<[M4WriteVSTE, 986 M4WriteA1], (instregex "ST4i(8|16|32|64)_POST$")>; 987 988// Cryptography instructions. 989def : InstRW<[M4WriteNCRY1], (instregex "^AES[DE]")>; 990def : InstRW<[M4WriteNCRY1, 991 M4ReadAESM1], (instregex "^AESI?MC")>; 992def : InstRW<[M4WriteNCRY1A], (instregex "^PMULv")>; 993def : InstRW<[M4WriteNCRY1A], (instregex "^PMULLv(1|8)i")>; 994def : InstRW<[M4WriteNCRY3A], (instregex "^PMULLv(2|16)i")>; 995def : InstRW<[M4WriteNCRY1A], (instregex "^SHA1([CHMP]|SU[01])")>; 996def : InstRW<[M4WriteNCRY1A], (instrs SHA256SU0rr)>; 997def : InstRW<[M4WriteNCRY5A], (instrs SHA256SU1rrr)>; 998def : InstRW<[M4WriteNCRY5A], (instrs SHA256H2rrr)>; 999 1000// CRC instructions. 1001def : InstRW<[M4WriteE2], (instregex "^CRC32C?[BHWX]rr$")>; 1002 1003} // SchedModel = ExynosM4Model 1004