AArch64SchedExynosM4.td revision 343171
1//=- AArch64SchedExynosM4.td - Samsung Exynos M4 Sched Defs --*- tablegen -*-=// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines the machine model for the Samsung Exynos M4 to support 11// instruction scheduling and other instruction cost heuristics. 12// 13//===----------------------------------------------------------------------===// 14 15//===----------------------------------------------------------------------===// 16// The Exynos-M4 is an advanced superscalar microprocessor with a 6-wide 17// in-order stage for decode and dispatch and a wider issue stage. 18// The execution units and loads and stores are out-of-order. 19 20def ExynosM4Model : SchedMachineModel { 21 let IssueWidth = 6; // Up to 6 uops per cycle. 22 let MicroOpBufferSize = 228; // ROB size. 23 let LoopMicroOpBufferSize = 48; // Based on the instruction queue size. 24 let LoadLatency = 4; // Optimistic load cases. 25 let MispredictPenalty = 16; // Minimum branch misprediction penalty. 26 let CompleteModel = 1; // Use the default model otherwise. 27 28 list<Predicate> UnsupportedFeatures = [HasSVE]; 29} 30 31//===----------------------------------------------------------------------===// 32// Define each kind of processor resource and number available on the Exynos-M4. 33 34let SchedModel = ExynosM4Model in { 35 36def M4UnitA : ProcResource<2>; // Simple integer 37def M4UnitC : ProcResource<2>; // Simple and complex integer 38let Super = M4UnitC, BufferSize = 1 in 39def M4UnitD : ProcResource<1>; // Integer division (inside C0, serialized) 40let Super = M4UnitC in 41def M4UnitE : ProcResource<1>; // CRC (inside C0) 42def M4UnitB : ProcResource<2>; // Branch 43def M4UnitL0 : ProcResource<1>; // Load 44def M4UnitS0 : ProcResource<1>; // Store 45def M4PipeLS : ProcResource<1>; // Load/Store 46let Super = M4PipeLS in { 47 def M4UnitL1 : ProcResource<1>; 48 def M4UnitS1 : ProcResource<1>; 49} 50def M4PipeF0 : ProcResource<1>; // FP #0 51let Super = M4PipeF0 in { 52 def M4UnitFMAC0 : ProcResource<1>; // FP multiplication 53 def M4UnitFADD0 : ProcResource<1>; // Simple FP 54 def M4UnitFCVT0 : ProcResource<1>; // FP conversion 55 def M4UnitNALU0 : ProcResource<1>; // Simple vector 56 def M4UnitNHAD : ProcResource<1>; // Horizontal vector 57 def M4UnitNMSC : ProcResource<1>; // FP and vector miscellanea 58 def M4UnitNMUL0 : ProcResource<1>; // Vector multiplication 59 def M4UnitNSHT0 : ProcResource<1>; // Vector shifting 60 def M4UnitNSHF0 : ProcResource<1>; // Vector shuffling 61 def M4UnitNCRY0 : ProcResource<1>; // Cryptographic 62} 63def M4PipeF1 : ProcResource<1>; // FP #1 64let Super = M4PipeF1 in { 65 def M4UnitFMAC1 : ProcResource<1>; // FP multiplication 66 def M4UnitFADD1 : ProcResource<1>; // Simple FP 67 def M4UnitFDIV0 : ProcResource<2>; // FP division (serialized) 68 def M4UnitFSQR0 : ProcResource<2>; // FP square root (serialized) 69 def M4UnitFST0 : ProcResource<1>; // FP store 70 def M4UnitNALU1 : ProcResource<1>; // Simple vector 71 def M4UnitNSHT1 : ProcResource<1>; // Vector shifting 72 def M4UnitNSHF1 : ProcResource<1>; // Vector shuffling 73} 74def M4PipeF2 : ProcResource<1>; // FP #2 75let Super = M4PipeF2 in { 76 def M4UnitFMAC2 : ProcResource<1>; // FP multiplication 77 def M4UnitFADD2 : ProcResource<1>; // Simple FP 78 def M4UnitFCVT1 : ProcResource<1>; // FP conversion 79 def M4UnitFDIV1 : ProcResource<2>; // FP division (serialized) 80 def M4UnitFSQR1 : ProcResource<2>; // FP square root (serialized) 81 def M4UnitFST1 : ProcResource<1>; // FP store 82 def M4UnitNALU2 : ProcResource<1>; // Simple vector 83 def M4UnitNMUL1 : ProcResource<1>; // Vector multiplication 84 def M4UnitNSHT2 : ProcResource<1>; // Vector shifting 85 def M4UnitNCRY1 : ProcResource<1>; // Cryptographic 86} 87 88def M4UnitALU : ProcResGroup<[M4UnitA, 89 M4UnitC]>; 90def M4UnitL : ProcResGroup<[M4UnitL0, 91 M4UnitL1]>; 92def M4UnitS : ProcResGroup<[M4UnitS0, 93 M4UnitS1]>; 94def M4UnitFMAC : ProcResGroup<[M4UnitFMAC0, 95 M4UnitFMAC1, 96 M4UnitFMAC2]>; 97def M4UnitFMACH : ProcResGroup<[M4UnitFMAC0, 98 M4UnitFMAC1]>; 99def M4UnitFADD : ProcResGroup<[M4UnitFADD0, 100 M4UnitFADD1, 101 M4UnitFADD2]>; 102def M4UnitFADDH : ProcResGroup<[M4UnitFADD0, 103 M4UnitFADD1]>; 104def M4UnitFCVT : ProcResGroup<[M4UnitFCVT0, 105 M4UnitFCVT1]>; 106def M4UnitFCVTH : ProcResGroup<[M4UnitFCVT0]>; 107def M4UnitFDIV : ProcResGroup<[M4UnitFDIV0, 108 M4UnitFDIV1]>; 109def M4UnitFDIVH : ProcResGroup<[M4UnitFDIV0]>; 110def M4UnitFSQR : ProcResGroup<[M4UnitFSQR0, 111 M4UnitFSQR1]>; 112def M4UnitFSQRH : ProcResGroup<[M4UnitFSQR0]>; 113def M4UnitFST : ProcResGroup<[M4UnitFST0, 114 M4UnitFST1]>; 115def M4UnitNALU : ProcResGroup<[M4UnitNALU0, 116 M4UnitNALU1, 117 M4UnitNALU2]>; 118def M4UnitNALUH : ProcResGroup<[M4UnitNALU0, 119 M4UnitNALU1]>; 120def M4UnitNMUL : ProcResGroup<[M4UnitNMUL0, 121 M4UnitNMUL1]>; 122def M4UnitNSHT : ProcResGroup<[M4UnitNSHT0, 123 M4UnitNSHT1, 124 M4UnitNSHT2]>; 125def M4UnitNSHF : ProcResGroup<[M4UnitNSHF0, 126 M4UnitNSHF1]>; 127def M4UnitNSHFH : ProcResGroup<[M4UnitNSHF0]>; 128def M4UnitNCRY : ProcResGroup<[M4UnitNCRY0, 129 M4UnitNCRY1]>; 130 131//===----------------------------------------------------------------------===// 132// Resources details. 133 134def M4WriteZ0 : SchedWriteRes<[]> { let Latency = 0; } 135def M4WriteZ1 : SchedWriteRes<[]> { let Latency = 1; 136 let NumMicroOps = 0; } 137def M4WriteZ4 : SchedWriteRes<[]> { let Latency = 4; 138 let NumMicroOps = 0; } 139 140def M4WriteA1 : SchedWriteRes<[M4UnitALU]> { let Latency = 1; } 141def M4WriteA2 : SchedWriteRes<[M4UnitALU]> { let Latency = 2; } 142def M4WriteAA : SchedWriteRes<[M4UnitALU]> { let Latency = 2; 143 let ResourceCycles = [2]; } 144def M4WriteAB : SchedWriteRes<[M4UnitALU, 145 M4UnitC]> { let Latency = 2; 146 let NumMicroOps = 2; } 147def M4WriteAC : SchedWriteRes<[M4UnitALU, 148 M4UnitALU, 149 M4UnitC]> { let Latency = 3; 150 let NumMicroOps = 3; } 151def M4WriteAD : SchedWriteRes<[M4UnitALU, 152 M4UnitC]> { let Latency = 2; 153 let NumMicroOps = 2; } 154def M4WriteAF : SchedWriteRes<[M4UnitALU]> { let Latency = 2; 155 let NumMicroOps = 2; } 156def M4WriteAU : SchedWriteVariant<[SchedVar<IsCopyIdiomPred, [M4WriteZ0]>, 157 SchedVar<ExynosArithPred, [M4WriteA1]>, 158 SchedVar<ExynosLogicExPred, [M4WriteA1]>, 159 SchedVar<NoSchedPred, [M4WriteAA]>]>; 160def M4WriteAV : SchedWriteVariant<[SchedVar<ExynosResetPred, [M4WriteZ0]>, 161 SchedVar<NoSchedPred, [M4WriteAA]>]>; 162def M4WriteAX : SchedWriteVariant<[SchedVar<ExynosArithPred, [M4WriteA1]>, 163 SchedVar<ExynosLogicExPred, [M4WriteA1]>, 164 SchedVar<NoSchedPred, [M4WriteAA]>]>; 165def M4WriteAY : SchedWriteVariant<[SchedVar<ExynosRotateRightImmPred, [M4WriteA1]>, 166 SchedVar<NoSchedPred, [M4WriteAF]>]>; 167 168def M4WriteB1 : SchedWriteRes<[M4UnitB]> { let Latency = 1; } 169def M4WriteBX : SchedWriteVariant<[SchedVar<ExynosBranchLinkLRPred, [M4WriteAC]>, 170 SchedVar<NoSchedPred, [M4WriteAB]>]>; 171 172def M4WriteC1 : SchedWriteRes<[M4UnitC]> { let Latency = 1; } 173def M4WriteC3 : SchedWriteRes<[M4UnitC]> { let Latency = 3; } 174def M4WriteCA : SchedWriteRes<[M4UnitC]> { let Latency = 4; 175 let ResourceCycles = [2]; } 176 177def M4WriteD12 : SchedWriteRes<[M4UnitD]> { let Latency = 12; } 178def M4WriteD21 : SchedWriteRes<[M4UnitD]> { let Latency = 21; } 179 180def M4WriteE2 : SchedWriteRes<[M4UnitE]> { let Latency = 2; } 181 182def M4WriteL4 : SchedWriteRes<[M4UnitL]> { let Latency = 4; } 183def M4WriteL5 : SchedWriteRes<[M4UnitL]> { let Latency = 5; } 184def M4WriteLA : SchedWriteRes<[M4UnitL, 185 M4UnitL]> { let Latency = 5; 186 let NumMicroOps = 1; } 187def M4WriteLB : SchedWriteRes<[M4UnitA, 188 M4UnitL]> { let Latency = 5; 189 let NumMicroOps = 2; } 190def M4WriteLC : SchedWriteRes<[M4UnitA, 191 M4UnitL, 192 M4UnitL]> { let Latency = 5; 193 let NumMicroOps = 2; } 194def M4WriteLD : SchedWriteRes<[M4UnitA, 195 M4UnitL]> { let Latency = 4; 196 let NumMicroOps = 2; } 197def M4WriteLE : SchedWriteRes<[M4UnitA, 198 M4UnitL]> { let Latency = 6; 199 let NumMicroOps = 2; } 200def M4WriteLH : SchedWriteRes<[]> { let Latency = 5; 201 let NumMicroOps = 0; } 202def M4WriteLX : SchedWriteVariant<[SchedVar<ScaledIdxPred, [M4WriteL5]>, 203 SchedVar<NoSchedPred, [M4WriteL4]>]>; 204 205def M4WriteS1 : SchedWriteRes<[M4UnitS]> { let Latency = 1; } 206def M4WriteSA : SchedWriteRes<[M4UnitS0]> { let Latency = 3; } 207def M4WriteSB : SchedWriteRes<[M4UnitA, 208 M4UnitS]> { let Latency = 2; 209 let NumMicroOps = 1; } 210def M4WriteSX : SchedWriteVariant<[SchedVar<ExynosScaledIdxPred, [M4WriteSB]>, 211 SchedVar<NoSchedPred, [M4WriteS1]>]>; 212 213def M4ReadAdrBase : SchedReadVariant<[SchedVar< 214 MCSchedPredicate< 215 CheckAny< 216 [ScaledIdxFn, 217 ExynosScaledIdxFn]>>, [ReadDefault]>, 218 SchedVar<NoSchedPred, [ReadDefault]>]>; 219 220def M4WriteNEONA : SchedWriteRes<[M4UnitNSHF, 221 M4UnitFADD]> { let Latency = 3; 222 let NumMicroOps = 2; } 223def M4WriteNEONB : SchedWriteRes<[M4UnitNALU, 224 M4UnitS0]> { let Latency = 5; 225 let NumMicroOps = 2; } 226def M4WriteNEOND : SchedWriteRes<[M4UnitNSHF, 227 M4UnitFST]> { let Latency = 6; 228 let NumMicroOps = 2; } 229def M4WriteNEONH : SchedWriteRes<[M4UnitNALU, 230 M4UnitS0]> { let Latency = 5; 231 let NumMicroOps = 2; } 232def M4WriteNEONI : SchedWriteRes<[M4UnitNSHF, 233 M4UnitS0]> { let Latency = 2; 234 let NumMicroOps = 2; } 235def M4WriteNEONJ : SchedWriteRes<[M4UnitNMSC, 236 M4UnitS0]> { let Latency = 4; } 237def M4WriteNEONK : SchedWriteRes<[M4UnitNSHF, 238 M4UnitNMSC, 239 M4UnitS0]> { let Latency = 5; 240 let NumMicroOps = 2; } 241def M4WriteNEONL : SchedWriteRes<[M4UnitNMUL]> { let Latency = 3; } 242def M4WriteNEONM : SchedWriteRes<[M4UnitNMUL]> { let Latency = 3; } 243def M4WriteNEONN : SchedWriteRes<[M4UnitNMSC, 244 M4UnitNMSC]> { let Latency = 5; 245 let NumMicroOps = 2; } 246def M4WriteNEONO : SchedWriteRes<[M4UnitNMSC, 247 M4UnitNMSC, 248 M4UnitNMSC]> { let Latency = 8; 249 let NumMicroOps = 3; } 250def M4WriteNEONP : SchedWriteRes<[M4UnitNSHF, 251 M4UnitNMSC]> { let Latency = 4; 252 let NumMicroOps = 2; } 253def M4WriteNEONQ : SchedWriteRes<[M4UnitNMSC, 254 M4UnitC]> { let Latency = 3; 255 let NumMicroOps = 1; } 256def M4WriteNEONR : SchedWriteRes<[M4UnitFCVT0, 257 M4UnitS0]> { let Latency = 4; 258 let NumMicroOps = 1; } 259def M4WriteNEONV : SchedWriteRes<[M4UnitFDIV, 260 M4UnitFDIV]> { let Latency = 7; 261 let ResourceCycles = [6, 6]; } 262def M4WriteNEONVH : SchedWriteRes<[M4UnitFDIVH, 263 M4UnitFDIVH]> { let Latency = 7; 264 let ResourceCycles = [6, 6]; } 265def M4WriteNEONW : SchedWriteRes<[M4UnitFDIV, 266 M4UnitFDIV]> { let Latency = 12; 267 let ResourceCycles = [9, 9]; } 268def M4WriteNEONX : SchedWriteRes<[M4UnitFSQR, 269 M4UnitFSQR]> { let Latency = 8; 270 let ResourceCycles = [7, 7]; } 271def M4WriteNEONXH : SchedWriteRes<[M4UnitFSQRH, 272 M4UnitFSQRH]> { let Latency = 7; 273 let ResourceCycles = [6, 6]; } 274def M4WriteNEONY : SchedWriteRes<[M4UnitFSQR, 275 M4UnitFSQR]> { let Latency = 12; 276 let ResourceCycles = [9, 9]; } 277def M4WriteNEONZ : SchedWriteVariant<[SchedVar<ExynosQFormPred, [M4WriteNEONO]>, 278 SchedVar<NoSchedPred, [M4WriteNEONN]>]>; 279 280def M4WriteFADD2 : SchedWriteRes<[M4UnitFADD]> { let Latency = 2; } 281def M4WriteFADD2H : SchedWriteRes<[M4UnitFADDH]> { let Latency = 2; } 282 283def M4WriteFCVT2 : SchedWriteRes<[M4UnitFCVT]> { let Latency = 2; } 284def M4WriteFCVT2A : SchedWriteRes<[M4UnitFCVT0]> { let Latency = 2; } 285def M4WriteFCVT2H : SchedWriteRes<[M4UnitFCVTH]> { let Latency = 2; } 286def M4WriteFCVT3 : SchedWriteRes<[M4UnitFCVT]> { let Latency = 3; } 287def M4WriteFCVT3A : SchedWriteRes<[M4UnitFCVT0]> { let Latency = 3; } 288def M4WriteFCVT3H : SchedWriteRes<[M4UnitFCVTH]> { let Latency = 3; } 289def M4WriteFCVT4 : SchedWriteRes<[M4UnitFCVT]> { let Latency = 4; } 290def M4WriteFCVT4A : SchedWriteRes<[M4UnitFCVT0]> { let Latency = 4; } 291def M4WriteFCVT6A : SchedWriteRes<[M4UnitFCVT0]> { let Latency = 6; } 292 293def M4WriteFDIV7 : SchedWriteRes<[M4UnitFDIV]> { let Latency = 7; 294 let ResourceCycles = [6]; } 295def M4WriteFDIV7H : SchedWriteRes<[M4UnitFDIVH]> { let Latency = 7; 296 let ResourceCycles = [6]; } 297def M4WriteFDIV12 : SchedWriteRes<[M4UnitFDIV]> { let Latency = 12; 298 let ResourceCycles = [9]; } 299 300def M4WriteFMAC2H : SchedWriteRes<[M4UnitFMACH]> { let Latency = 2; } 301def M4WriteFMAC3H : SchedWriteRes<[M4UnitFMACH]> { let Latency = 3; } 302def M4WriteFMAC3 : SchedWriteRes<[M4UnitFMAC]> { let Latency = 3; } 303def M4WriteFMAC4 : SchedWriteRes<[M4UnitFMAC]> { let Latency = 4; } 304def M4WriteFMAC4H : SchedWriteRes<[M4UnitFMACH]> { let Latency = 4; } 305def M4WriteFMAC5 : SchedWriteRes<[M4UnitFMAC]> { let Latency = 5; } 306 307def M4WriteFSQR7H : SchedWriteRes<[M4UnitFSQRH]> { let Latency = 7; 308 let ResourceCycles = [6]; } 309def M4WriteFSQR8 : SchedWriteRes<[M4UnitFSQR]> { let Latency = 8; 310 let ResourceCycles = [7]; } 311def M4WriteFSQR12 : SchedWriteRes<[M4UnitFSQR]> { let Latency = 12; 312 let ResourceCycles = [9]; } 313 314def M4WriteNALU1 : SchedWriteRes<[M4UnitNALU]> { let Latency = 1; } 315def M4WriteNALU1H : SchedWriteRes<[M4UnitNALUH]> { let Latency = 1; } 316 317def M4WriteNCRY1 : SchedWriteRes<[M4UnitNCRY]> { let Latency = 1; } 318def M4WriteNCRY1A : SchedWriteRes<[M4UnitNCRY0]> { let Latency = 1; } 319def M4WriteNCRY3A : SchedWriteRes<[M4UnitNCRY0]> { let Latency = 3; } 320def M4WriteNCRY5A : SchedWriteRes<[M4UnitNCRY]> { let Latency = 5; } 321 322def M4WriteNHAD1 : SchedWriteRes<[M4UnitNHAD]> { let Latency = 1; } 323def M4WriteNHAD3 : SchedWriteRes<[M4UnitNHAD]> { let Latency = 3; } 324 325def M4WriteNMSC1 : SchedWriteRes<[M4UnitNMSC]> { let Latency = 1; } 326def M4WriteNMSC2 : SchedWriteRes<[M4UnitNMSC]> { let Latency = 2; } 327def M4WriteNMSC3 : SchedWriteRes<[M4UnitNMSC]> { let Latency = 3; } 328 329def M4WriteNMUL3 : SchedWriteRes<[M4UnitNMUL]> { let Latency = 3; } 330 331def M4WriteNSHF1 : SchedWriteRes<[M4UnitNSHF]> { let Latency = 1; } 332def M4WriteNSHF1H : SchedWriteRes<[M4UnitNSHFH]> { let Latency = 1; } 333def M4WriteNSHF3 : SchedWriteRes<[M4UnitNSHF]> { let Latency = 3; } 334def M4WriteNSHFA : SchedWriteRes<[M4UnitNSHF]> { let Latency = 1; 335 let ResourceCycles = [2]; } 336def M4WriteNSHFB : SchedWriteRes<[M4UnitNSHF]> { let Latency = 2; 337 let NumMicroOps = 2; 338 let ResourceCycles = [2]; } 339def M4WriteNSHFC : SchedWriteRes<[M4UnitNSHF]> { let Latency = 3; 340 let NumMicroOps = 3; 341 let ResourceCycles = [4]; } 342def M4WriteNSHFD : SchedWriteRes<[M4UnitNSHF]> { let Latency = 4; 343 let NumMicroOps = 4; 344 let ResourceCycles = [4]; } 345 346def M4WriteNSHT1 : SchedWriteRes<[M4UnitNSHT]> { let Latency = 1; } 347def M4WriteNSHT2 : SchedWriteRes<[M4UnitNSHT]> { let Latency = 2; } 348def M4WriteNSHT3 : SchedWriteRes<[M4UnitNSHT]> { let Latency = 3; } 349def M4WriteNSHT4A : SchedWriteRes<[M4UnitNSHT1]> { let Latency = 4; } 350 351def M4WriteVLDA : SchedWriteRes<[M4UnitL, 352 M4UnitL]> { let Latency = 5; 353 let NumMicroOps = 2; } 354def M4WriteVLDB : SchedWriteRes<[M4UnitL, 355 M4UnitL, 356 M4UnitL]> { let Latency = 6; 357 let NumMicroOps = 3; } 358def M4WriteVLDC : SchedWriteRes<[M4UnitL, 359 M4UnitL, 360 M4UnitL, 361 M4UnitL]> { let Latency = 6; 362 let NumMicroOps = 4; } 363def M4WriteVLDD : SchedWriteRes<[M4UnitL, 364 M4UnitNSHF]> { let Latency = 6; 365 let NumMicroOps = 2; 366 let ResourceCycles = [2, 1]; } 367def M4WriteVLDF : SchedWriteRes<[M4UnitL, 368 M4UnitL]> { let Latency = 10; 369 let NumMicroOps = 2; 370 let ResourceCycles = [3, 3]; } 371def M4WriteVLDG : SchedWriteRes<[M4UnitL, 372 M4UnitNSHF, 373 M4UnitNSHF]> { let Latency = 6; 374 let NumMicroOps = 3; 375 let ResourceCycles = [2, 1, 1]; } 376def M4WriteVLDI : SchedWriteRes<[M4UnitL, 377 M4UnitL, 378 M4UnitL]> { let Latency = 12; 379 let NumMicroOps = 3; 380 let ResourceCycles = [3, 3, 3]; } 381def M4WriteVLDJ : SchedWriteRes<[M4UnitL, 382 M4UnitNSHF, 383 M4UnitNSHF, 384 M4UnitNSHF]> { let Latency = 7; 385 let NumMicroOps = 4; 386 let ResourceCycles = [3, 1, 1, 1]; } 387def M4WriteVLDK : SchedWriteRes<[M4UnitL, 388 M4UnitNSHF, 389 M4UnitNSHF, 390 M4UnitNSHF, 391 M4UnitNSHF]> { let Latency = 7; 392 let NumMicroOps = 5; 393 let ResourceCycles = [3, 1, 1, 1, 1]; } 394def M4WriteVLDL : SchedWriteRes<[M4UnitL, 395 M4UnitNSHF, 396 M4UnitNSHF, 397 M4UnitL, 398 M4UnitNSHF]> { let Latency = 7; 399 let NumMicroOps = 5; 400 let ResourceCycles = [3, 1, 1, 6, 1]; } 401def M4WriteVLDM : SchedWriteRes<[M4UnitL, 402 M4UnitNSHF, 403 M4UnitNSHF, 404 M4UnitL, 405 M4UnitNSHF, 406 M4UnitNSHF]> { let Latency = 7; 407 let NumMicroOps = 6; 408 let ResourceCycles = [3, 1, 1, 3, 1, 1]; } 409def M4WriteVLDN : SchedWriteRes<[M4UnitL, 410 M4UnitL, 411 M4UnitL, 412 M4UnitL]> { let Latency = 14; 413 let NumMicroOps = 4; 414 let ResourceCycles = [3, 3, 3, 3]; } 415 416def M4WriteVST1 : SchedWriteRes<[M4UnitS, 417 M4UnitFST]> { let Latency = 1; 418 let NumMicroOps = 1; } 419def M4WriteVSTA : WriteSequence<[WriteVST], 2>; 420def M4WriteVSTB : WriteSequence<[WriteVST], 3>; 421def M4WriteVSTC : WriteSequence<[WriteVST], 4>; 422def M4WriteVSTD : SchedWriteRes<[M4UnitS, 423 M4UnitFST]> { let Latency = 2; } 424def M4WriteVSTE : SchedWriteRes<[M4UnitS, 425 M4UnitFST, 426 M4UnitS, 427 M4UnitFST]> { let Latency = 2; 428 let NumMicroOps = 2; } 429def M4WriteVSTF : SchedWriteRes<[M4UnitNSHF, 430 M4UnitS, 431 M4UnitFST, 432 M4UnitS, 433 M4UnitFST]> { let Latency = 4; 434 let NumMicroOps = 4; 435 let ResourceCycles = [1, 2, 1, 2, 1]; } 436def M4WriteVSTG : SchedWriteRes<[M4UnitNSHF, 437 M4UnitNSHF, 438 M4UnitNSHF, 439 M4UnitS, 440 M4UnitFST, 441 M4UnitS, 442 M4UnitFST, 443 M4UnitS, 444 M4UnitFST]> { let Latency = 5; 445 let NumMicroOps = 6; 446 let ResourceCycles = [1, 1, 1, 2, 1, 2, 1, 2, 1]; } 447def M4WriteVSTI : SchedWriteRes<[M4UnitNSHF, 448 M4UnitNSHF, 449 M4UnitNSHF, 450 M4UnitNSHF, 451 M4UnitS, 452 M4UnitFST, 453 M4UnitS, 454 M4UnitFST, 455 M4UnitS, 456 M4UnitFST, 457 M4UnitS, 458 M4UnitFST]> { let Latency = 8; 459 let NumMicroOps = 5; 460 let ResourceCycles = [1, 1, 1, 1, 2, 1, 2, 1, 2, 1, 2, 1]; } 461def M4WriteVSTJ : SchedWriteRes<[M4UnitA, 462 M4UnitS, 463 M4UnitFST]> { let Latency = 1; 464 let NumMicroOps = 2; } 465def M4WriteVSTK : SchedWriteRes<[M4UnitA, 466 M4UnitS, 467 M4UnitFST]> { let Latency = 3; 468 let NumMicroOps = 2; } 469def M4WriteVSTL : SchedWriteRes<[M4UnitNSHF, 470 M4UnitNSHF, 471 M4UnitS, 472 M4UnitFST, 473 M4UnitS, 474 M4UnitFST]> { let Latency = 4; 475 let NumMicroOps = 4; 476 let ResourceCycles = [1, 1, 2, 1, 2, 1]; } 477 478// Special cases. 479def M4WriteCOPY : SchedWriteVariant<[SchedVar<ExynosFPPred, [M4WriteNALU1]>, 480 SchedVar<NoSchedPred, [M4WriteZ0]>]>; 481def M4WriteMOVI : SchedWriteVariant<[SchedVar<IsZeroFPIdiomPred, [M4WriteZ0]>, 482 SchedVar<NoSchedPred, [M4WriteNALU1]>]>; 483def M4WriteMULL : SchedWriteVariant<[SchedVar<ExynosLongVectorUpperPred, [M4WriteNEONM]>, 484 SchedVar<NoSchedPred, [M4WriteNMUL3]>]>; 485 486// Fast forwarding. 487def M4ReadAESM1 : SchedReadAdvance<+1, [M4WriteNCRY1]>; 488def M4ReadFMACM1 : SchedReadAdvance<+1, [M4WriteFMAC4, 489 M4WriteFMAC4H, 490 M4WriteFMAC5]>; 491def M4ReadNMULM1 : SchedReadAdvance<+1, [M4WriteNMUL3]>; 492def M4ReadMULLP2 : SchedReadAdvance<-2, [M4WriteNEONM]>; 493 494//===----------------------------------------------------------------------===// 495// Coarse scheduling model. 496 497// Branch instructions. 498def : SchedAlias<WriteBr, M4WriteZ0>; 499def : SchedAlias<WriteBrReg, M4WriteC1>; 500 501// Arithmetic and logical integer instructions. 502def : SchedAlias<WriteI, M4WriteA1>; 503def : SchedAlias<WriteIEReg, M4WriteAA>; // FIXME: M4WriteAX crashes TableGen. 504def : SchedAlias<WriteISReg, M4WriteAA>; // FIXME: M4WriteAX crashes TableGen. 505def : SchedAlias<WriteIS, M4WriteA1>; 506 507// Move instructions. 508def : SchedAlias<WriteImm, M4WriteA1>; 509 510// Divide and multiply instructions. 511def : SchedAlias<WriteID32, M4WriteD12>; 512def : SchedAlias<WriteID64, M4WriteD21>; 513def : SchedAlias<WriteIM32, M4WriteC3>; 514def : SchedAlias<WriteIM64, M4WriteCA>; 515 516// Miscellaneous instructions. 517def : SchedAlias<WriteExtr, M4WriteAY>; 518 519// Addressing modes. 520def : SchedAlias<WriteAdr, M4WriteZ1>; 521def : SchedAlias<ReadAdrBase, M4ReadAdrBase>; 522 523// Load instructions. 524def : SchedAlias<WriteLD, M4WriteL4>; 525def : SchedAlias<WriteLDHi, M4WriteZ4>; 526def : SchedAlias<WriteLDIdx, M4WriteLX>; 527 528// Store instructions. 529def : SchedAlias<WriteST, M4WriteS1>; 530def : SchedAlias<WriteSTP, M4WriteS1>; 531def : SchedAlias<WriteSTX, M4WriteS1>; 532def : SchedAlias<WriteSTIdx, M4WriteSX>; 533 534// FP data instructions. 535def : SchedAlias<WriteF, M4WriteFADD2>; 536def : SchedAlias<WriteFCmp, M4WriteNMSC2>; 537def : SchedAlias<WriteFDiv, M4WriteFDIV12>; 538def : SchedAlias<WriteFMul, M4WriteFMAC3>; 539 540// FP miscellaneous instructions. 541def : SchedAlias<WriteFCvt, M4WriteFCVT2>; 542def : SchedAlias<WriteFImm, M4WriteNALU1>; 543def : SchedAlias<WriteFCopy, M4WriteCOPY>; 544 545// FP load instructions. 546def : SchedAlias<WriteVLD, M4WriteL5>; 547 548// FP store instructions. 549def : SchedAlias<WriteVST, M4WriteVST1>; 550 551// ASIMD FP instructions. 552def : SchedAlias<WriteV, M4WriteNALU1>; 553 554// Other miscellaneous instructions. 555def : WriteRes<WriteAtomic, []> { let Unsupported = 1; } 556def : WriteRes<WriteBarrier, []> { let Latency = 1; } 557def : WriteRes<WriteHint, []> { let Latency = 1; } 558def : WriteRes<WriteSys, []> { let Latency = 1; } 559 560//===----------------------------------------------------------------------===// 561// Generic fast forwarding. 562 563// TODO: Add FP register forwarding rules. 564 565def : ReadAdvance<ReadI, 0>; 566def : ReadAdvance<ReadISReg, 0>; 567def : ReadAdvance<ReadIEReg, 0>; 568def : ReadAdvance<ReadIM, 0>; 569// TODO: The forwarding for 32 bits actually saves 2 cycles. 570def : ReadAdvance<ReadIMA, 3, [WriteIM32, WriteIM64]>; 571def : ReadAdvance<ReadID, 0>; 572def : ReadAdvance<ReadExtrHi, 0>; 573def : ReadAdvance<ReadAdrBase, 0>; 574def : ReadAdvance<ReadVLD, 0>; 575 576//===----------------------------------------------------------------------===// 577// Finer scheduling model. 578 579// Branch instructions 580def : InstRW<[M4WriteB1], (instrs Bcc)>; 581def : InstRW<[M4WriteAF], (instrs BL)>; 582def : InstRW<[M4WriteBX], (instrs BLR)>; 583def : InstRW<[M4WriteC1], (instregex "^CBN?Z[WX]")>; 584def : InstRW<[M4WriteAD], (instregex "^TBN?Z[WX]")>; 585 586// Arithmetic and logical integer instructions. 587def : InstRW<[M4WriteAX], (instregex "^(ADD|AND|BIC|EON|EOR|ORN|SUB)[WX]rs$")>; 588def : InstRW<[M4WriteAU], (instrs ORRWrs, ORRXrs)>; 589def : InstRW<[M4WriteAX], (instregex "^(ADD|AND|BIC|SUB)S[WX]rs$")>; 590def : InstRW<[M4WriteAX], (instregex "^(ADD|SUB)S?[WX]rx(64)?$")>; 591def : InstRW<[M4WriteAV], (instrs ADDWri, ADDXri, ORRWri, ORRXri)>; 592 593// Move instructions. 594def : InstRW<[M4WriteCOPY], (instrs COPY)>; 595def : InstRW<[M4WriteZ0], (instrs ADR, ADRP)>; 596def : InstRW<[M4WriteZ0], (instregex "^MOV[NZ][WX]i")>; 597 598// Divide and multiply instructions. 599 600// Miscellaneous instructions. 601 602// Load instructions. 603def : InstRW<[M4WriteLD, 604 WriteLDHi, 605 WriteAdr], (instregex "^LDP(SW|W|X)(post|pre)")>; 606def : InstRW<[M4WriteL5, 607 ReadAdrBase], (instregex "^LDR(BB|SBW|SBX|HH|SHW|SHX|SW|W|X)roW")>; 608def : InstRW<[WriteLDIdx, 609 ReadAdrBase], (instregex "^LDR(BB|SBW|SBX|HH|SHW|SHX|SW|W|X)roX")>; 610def : InstRW<[M4WriteL5, 611 ReadAdrBase], (instrs PRFMroW)>; 612def : InstRW<[WriteLDIdx, 613 ReadAdrBase], (instrs PRFMroX)>; 614 615// Store instructions. 616def : InstRW<[M4WriteSB, 617 ReadAdrBase], (instregex "^STR(BB|HH|W|X)roW")>; 618def : InstRW<[WriteST, 619 ReadAdrBase], (instregex "^STR(BB|HH|W|X)roX")>; 620 621// FP data instructions. 622def : InstRW<[M4WriteNSHF1H], (instrs FABSHr)>; 623def : InstRW<[M4WriteNSHF1], (instregex "^FABS[SD]r")>; 624def : InstRW<[M4WriteFADD2H], (instregex "^F(ADD|SUB)Hrr")>; 625def : InstRW<[M4WriteFADD2], (instregex "^F(ADD|SUB)[SD]rr")>; 626def : InstRW<[M4WriteFADD2H], (instregex "^FADDPv.i16")>; 627def : InstRW<[M4WriteFADD2], (instregex "^FADDPv.i(32|64)")>; 628def : InstRW<[M4WriteNEONQ], (instregex "^FCCMPE?[HSD]rr")>; 629def : InstRW<[M4WriteNMSC2], (instregex "^FCMPE?[HSD]r[ir]")>; 630def : InstRW<[M4WriteNMSC1], (instregex "^F(AC|CM)(EQ|GE|GT|LE|LT)(16|32|64|v1)")>; 631def : InstRW<[M4WriteFDIV7H], (instrs FDIVHrr)>; 632def : InstRW<[M4WriteFDIV7], (instrs FDIVSrr)>; 633def : InstRW<[M4WriteFDIV12], (instrs FDIVDrr)>; 634def : InstRW<[M4WriteNMSC1], (instregex "^F(MAX|MIN)(NM)?[HSD]rr")>; 635def : InstRW<[M4WriteFMAC3H], (instregex "^FN?MULHrr")>; 636def : InstRW<[M4WriteFMAC3], (instregex "^FN?MUL[SD]rr")>; 637def : InstRW<[M4WriteFMAC3H], (instrs FMULX16)>; 638def : InstRW<[M4WriteFMAC3], (instregex "^FMULX(32|64)")>; 639def : InstRW<[M4WriteFMAC4H, 640 M4ReadFMACM1], (instregex "^FN?M(ADD|SUB)Hrrr")>; 641def : InstRW<[M4WriteFMAC4, 642 M4ReadFMACM1], (instregex "^FN?M(ADD|SUB)[SD]rrr")>; 643def : InstRW<[M4WriteNALU1H], (instrs FNEGHr)>; 644def : InstRW<[M4WriteNALU1], (instregex "^FNEG[SD]r")>; 645def : InstRW<[M4WriteFCVT3A], (instregex "^FRINT.+r")>; 646def : InstRW<[M4WriteNEONH], (instregex "^FCSEL[HSD]rrr")>; 647def : InstRW<[M4WriteFSQR7H], (instrs FSQRTHr)>; 648def : InstRW<[M4WriteFSQR8], (instrs FSQRTSr)>; 649def : InstRW<[M4WriteFSQR12], (instrs FSQRTDr)>; 650 651// FP miscellaneous instructions. 652def : InstRW<[M4WriteFCVT2H], (instregex "^FCVTH[SD]r")>; 653def : InstRW<[M4WriteFCVT2H], (instregex "^FCVT[SD]Hr")>; 654def : InstRW<[M4WriteFCVT2], (instregex "^FCVT[SD][SD]r")>; 655def : InstRW<[M4WriteFCVT6A], (instregex "^[SU]CVTF[SU][XW][HSD]ri")>; 656def : InstRW<[M4WriteNEONR], (instregex "^FCVT[AMNPZ][SU][SU][XW][HSD]r")>; 657def : InstRW<[M4WriteNALU1], (instregex "^FMOV[HSD][ir]")>; 658def : InstRW<[M4WriteSA], (instregex "^FMOV[WX][HSD]r")>; 659def : InstRW<[M4WriteNEONJ], (instregex "^FMOV[HSD][WX]r")>; 660def : InstRW<[M4WriteNEONI], (instregex "^FMOVXDHighr")>; 661def : InstRW<[M4WriteNEONK], (instregex "^FMOVDXHighr")>; 662def : InstRW<[M4WriteFCVT3H], (instregex "^F(RECP|RSQRT)Ev1f16")>; 663def : InstRW<[M4WriteFCVT3], (instregex "^F(RECP|RSQRT)Ev1i(32|64)")>; 664def : InstRW<[M4WriteNMSC1], (instregex "^FRECPXv1")>; 665def : InstRW<[M4WriteFMAC4H, 666 M4ReadFMACM1], (instregex "^F(RECP|RSQRT)S16")>; 667def : InstRW<[M4WriteFMAC4, 668 M4ReadFMACM1], (instregex "^F(RECP|RSQRT)S(32|64)")>; 669 670// FP load instructions. 671def : InstRW<[WriteVLD], (instregex "^LDR[SDQ]l")>; 672def : InstRW<[WriteVLD], (instregex "^LDUR[BHSDQ]i")>; 673def : InstRW<[WriteVLD, 674 WriteAdr], (instregex "^LDR[BHSDQ](post|pre)")>; 675def : InstRW<[WriteVLD], (instregex "^LDR[BHSDQ]ui")>; 676def : InstRW<[M4WriteLE, 677 ReadAdrBase], (instregex "^LDR[BHSDQ]roW")>; 678def : InstRW<[WriteVLD, 679 ReadAdrBase], (instregex "^LDR[BHSD]roX")>; 680def : InstRW<[M4WriteLE, 681 ReadAdrBase], (instrs LDRQroX)>; 682def : InstRW<[WriteVLD, 683 M4WriteLH], (instregex "^LDN?P[SD]i")>; 684def : InstRW<[M4WriteLA, 685 M4WriteLH], (instregex "^LDN?PQi")>; 686def : InstRW<[M4WriteL5, 687 M4WriteLH, 688 WriteAdr], (instregex "^LDP[SD]post")>; 689def : InstRW<[M4WriteLB, 690 M4WriteLH, 691 WriteAdr], (instrs LDPQpost)>; 692def : InstRW<[M4WriteLB, 693 M4WriteLH, 694 WriteAdr], (instregex "^LDP[SD]pre")>; 695def : InstRW<[M4WriteLC, 696 M4WriteLH, 697 WriteAdr], (instrs LDPQpre)>; 698 699// FP store instructions. 700def : InstRW<[WriteVST], (instregex "^STUR[BHSDQ]i")>; 701def : InstRW<[WriteVST, 702 WriteAdr], (instregex "^STR[BHSDQ](post|pre)")>; 703def : InstRW<[WriteVST], (instregex "^STR[BHSDQ]ui")>; 704def : InstRW<[M4WriteVSTJ, 705 ReadAdrBase], (instregex "^STR[BHSD]roW")>; 706def : InstRW<[M4WriteVSTK, 707 ReadAdrBase], (instrs STRQroW)>; 708def : InstRW<[WriteVST, 709 ReadAdrBase], (instregex "^STR[BHSD]roX")>; 710def : InstRW<[M4WriteVSTK, 711 ReadAdrBase], (instrs STRQroX)>; 712def : InstRW<[WriteVST], (instregex "^STN?P[SD]i")>; 713def : InstRW<[M4WriteVSTA], (instregex "^STN?PQi")>; 714def : InstRW<[WriteVST, 715 WriteAdr], (instregex "^STP[SD](post|pre)")>; 716def : InstRW<[M4WriteVSTJ, 717 WriteAdr], (instregex "^STPQ(post|pre)")>; 718 719// ASIMD instructions. 720def : InstRW<[M4WriteNHAD1], (instregex "^[SU]ABDL?v")>; 721def : InstRW<[M4WriteNHAD3], (instregex "^[SU]ABAL?v")>; 722def : InstRW<[M4WriteNMSC1], (instregex "^ABSv")>; 723def : InstRW<[M4WriteNALU1], (instregex "^(ADD|NEG|SUB)v")>; 724def : InstRW<[M4WriteNHAD3], (instregex "^[SU]?ADDL?Pv")>; 725def : InstRW<[M4WriteNHAD3], (instregex "^[SU]H(ADD|SUB)v")>; 726def : InstRW<[M4WriteNHAD3], (instregex "^[SU](ADD|SUB)[LW]v")>; 727def : InstRW<[M4WriteNHAD3], (instregex "^R?(ADD|SUB)HN2?v")>; 728def : InstRW<[M4WriteNHAD3], (instregex "^[SU]Q(ADD|SUB)v")>; 729def : InstRW<[M4WriteNHAD3], (instregex "^(SU|US)QADDv")>; 730def : InstRW<[M4WriteNHAD3], (instregex "^[SU]RHADDv")>; 731def : InstRW<[M4WriteNMSC1], (instregex "^SQ(ABS|NEG)v")>; 732def : InstRW<[M4WriteNHAD3], (instregex "^[SU]?ADDL?Vv")>; 733def : InstRW<[M4WriteNMSC1], (instregex "^CM(EQ|GE|GT|HI|HS|LE|LT)v")>; 734def : InstRW<[M4WriteNALU1], (instregex "^CMTSTv")>; 735def : InstRW<[M4WriteNALU1], (instregex "^(AND|BIC|EOR|NOT|ORN|ORR)v")>; 736def : InstRW<[M4WriteNMSC1], (instregex "^[SU](MIN|MAX)v")>; 737def : InstRW<[M4WriteNMSC2], (instregex "^[SU](MIN|MAX)Pv")>; 738def : InstRW<[M4WriteNHAD3], (instregex "^[SU](MIN|MAX)Vv")>; 739def : InstRW<[M4WriteNMUL3], (instregex "^(SQR?D)?MULH?v")>; 740def : InstRW<[M4WriteNMUL3, 741 M4ReadNMULM1], (instregex "^ML[AS]v")>; 742def : InstRW<[M4WriteNMUL3], (instregex "^SQRDML[AS]H")>; 743def : InstRW<[M4WriteMULL, 744 M4ReadMULLP2], (instregex "^(S|U|SQD)ML[AS]Lv")>; 745def : InstRW<[M4WriteMULL, 746 M4ReadMULLP2], (instregex "^(S|U|SQD)MULLv")>; 747def : InstRW<[M4WriteNMUL3], (instregex "^[SU]DOT(lane)?v")>; 748def : InstRW<[M4WriteNHAD3], (instregex "^[SU]ADALPv")>; 749def : InstRW<[M4WriteNSHT4A], (instregex "^[SU]R?SRA[dv]")>; 750def : InstRW<[M4WriteNSHT1], (instregex "^SHL[dv]")>; 751def : InstRW<[M4WriteNSHT1], (instregex "^S[LR]I[dv]")>; 752def : InstRW<[M4WriteNSHT1], (instregex "^[SU]SH[LR][dv]")>; 753def : InstRW<[M4WriteNSHT2], (instregex "^[SU]?SHLLv")>; 754def : InstRW<[M4WriteNSHT4A], (instregex "^[SU]?Q?R?SHRU?N[bhsv]")>; 755def : InstRW<[M4WriteNSHT4A], (instregex "^[SU]RSH[LR][dv]")>; 756def : InstRW<[M4WriteNSHT4A], (instregex "^[SU]QR?SHLU?[bhsdv]")>; 757 758// ASIMD FP instructions. 759def : InstRW<[M4WriteNSHF1H], (instregex "^FABSv.f16")>; 760def : InstRW<[M4WriteNSHF1], (instregex "^FABSv.f(32|64)")>; 761def : InstRW<[M4WriteFADD2H], (instregex "^F(ABD|ADD|SUB)v.f16")>; 762def : InstRW<[M4WriteFADD2], (instregex "^F(ABD|ADD|SUB)v.f(32|64)")>; 763def : InstRW<[M4WriteFADD2H], (instregex "^FADDPv.f16")>; 764def : InstRW<[M4WriteFADD2], (instregex "^FADDPv.f(32|64)")>; 765def : InstRW<[M4WriteNMSC1], (instregex "^F(AC|CM)(EQ|GE|GT|LE|LT)v[^1]")>; 766def : InstRW<[M4WriteFCVT2], (instregex "^FCVT(L|N|XN)v")>; 767def : InstRW<[M4WriteFCVT2A], (instregex "^FCVT[AMNPZ][SU]v")>; 768def : InstRW<[M4WriteFCVT2H], (instregex "^[SU]CVTFv.[fi]16")>; 769def : InstRW<[M4WriteFCVT2], (instregex "^[SU]CVTFv.[fi](32|64)")>; 770def : InstRW<[M4WriteFDIV7H], (instrs FDIVv4f16)>; 771def : InstRW<[M4WriteNEONVH], (instrs FDIVv8f16)>; 772def : InstRW<[M4WriteFDIV7], (instrs FDIVv2f32)>; 773def : InstRW<[M4WriteNEONV], (instrs FDIVv4f32)>; 774def : InstRW<[M4WriteNEONW], (instrs FDIVv2f64)>; 775def : InstRW<[M4WriteNMSC1], (instregex "^F(MAX|MIN)(NM)?v")>; 776def : InstRW<[M4WriteNMSC2], (instregex "^F(MAX|MIN)(NM)?Pv")>; 777def : InstRW<[M4WriteNEONZ], (instregex "^F(MAX|MIN)(NM)?Vv")>; 778def : InstRW<[M4WriteFMAC2H], (instregex "^FMULX?v.[fi]16")>; 779def : InstRW<[M4WriteFMAC3], (instregex "^FMULX?v.[fi](32|64)")>; 780def : InstRW<[M4WriteFMAC4H, 781 M4ReadFMACM1], (instregex "^FML[AS]v.[fi]16")>; 782def : InstRW<[M4WriteFMAC4, 783 M4ReadFMACM1], (instregex "^FML[AS]v.[fi](32|64)")>; 784def : InstRW<[M4WriteNALU1H], (instregex "^FNEGv.f16")>; 785def : InstRW<[M4WriteNALU1], (instregex "^FNEGv.f(32|64)")>; 786def : InstRW<[M4WriteFCVT3A], (instregex "^FRINT[AIMNPXZ]v")>; 787def : InstRW<[M4WriteFSQR7H], (instrs FSQRTv4f16)>; 788def : InstRW<[M4WriteNEONXH], (instrs FSQRTv8f16)>; 789def : InstRW<[M4WriteFSQR8], (instrs FSQRTv2f32)>; 790def : InstRW<[M4WriteNEONX], (instrs FSQRTv4f32)>; 791def : InstRW<[M4WriteNEONY], (instrs FSQRTv2f64)>; 792 793// ASIMD miscellaneous instructions. 794def : InstRW<[M4WriteNALU1], (instregex "^RBITv")>; 795def : InstRW<[M4WriteNALU1], (instregex "^(BIF|BIT|BSL)v")>; 796def : InstRW<[M4WriteNALU1], (instregex "^CL[STZ]v")>; 797def : InstRW<[M4WriteNEONB], (instregex "^DUPv.+gpr")>; 798def : InstRW<[M4WriteNSHF1], (instregex "^CPY")>; 799def : InstRW<[M4WriteNSHF1], (instregex "^DUPv.+lane")>; 800def : InstRW<[M4WriteNSHF1], (instregex "^EXTv")>; 801def : InstRW<[M4WriteNSHT4A], (instregex "^XTNv")>; 802def : InstRW<[M4WriteNSHT4A], (instregex "^[SU]?QXTU?Nv")>; 803def : InstRW<[M4WriteNEONB], (instregex "^INSv.+gpr")>; 804def : InstRW<[M4WriteNSHF1], (instregex "^INSv.+lane")>; 805def : InstRW<[M4WriteMOVI], (instregex "^(MOV|MVN)I")>; 806def : InstRW<[M4WriteNALU1H], (instregex "^FMOVv.f16")>; 807def : InstRW<[M4WriteNALU1], (instregex "^FMOVv.f(32|64)")>; 808def : InstRW<[M4WriteFCVT3H], (instregex "^F(RECP|RSQRT)Ev[248]f16")>; 809def : InstRW<[M4WriteFCVT3], (instregex "^F(RECP|RSQRT)Ev[248]f(32|64)")>; 810def : InstRW<[M4WriteFCVT3], (instregex "^U(RECP|RSQRT)Ev[24]i32")>; 811def : InstRW<[M4WriteFMAC4H, 812 M4ReadFMACM1], (instregex "^F(RECP|RSQRT)Sv.f16")>; 813def : InstRW<[M4WriteFMAC4, 814 M4ReadFMACM1], (instregex "^F(RECP|RSQRT)Sv.f(32|64)")>; 815def : InstRW<[M4WriteNSHF1], (instregex "^REV(16|32|64)v")>; 816def : InstRW<[M4WriteNSHFA], (instregex "^TB[LX]v(8|16)i8One")>; 817def : InstRW<[M4WriteNSHFB], (instregex "^TB[LX]v(8|16)i8Two")>; 818def : InstRW<[M4WriteNSHFC], (instregex "^TB[LX]v(8|16)i8Three")>; 819def : InstRW<[M4WriteNSHFD], (instregex "^TB[LX]v(8|16)i8Four")>; 820def : InstRW<[M4WriteNEONP], (instregex "^[SU]MOVv")>; 821def : InstRW<[M4WriteNSHF1], (instregex "^(TRN|UZP|ZIP)[12]v")>; 822 823// ASIMD load instructions. 824def : InstRW<[WriteVLD], (instregex "LD1Onev(8b|4h|2s|1d)$")>; 825def : InstRW<[WriteVLD, 826 M4WriteA1], (instregex "LD1Onev(8b|4h|2s|1d)_POST$")>; 827def : InstRW<[WriteVLD], (instregex "LD1Onev(16b|8h|4s|2d)$")>; 828def : InstRW<[WriteVLD, 829 M4WriteA1], (instregex "LD1Onev(16b|8h|4s|2d)_POST$")>; 830 831def : InstRW<[M4WriteVLDA], (instregex "LD1Twov(8b|4h|2s|1d)$")>; 832def : InstRW<[M4WriteVLDA, 833 M4WriteA1], (instregex "LD1Twov(8b|4h|2s|1d)_POST$")>; 834def : InstRW<[M4WriteVLDA], (instregex "LD1Twov(16b|8h|4s|2d)$")>; 835def : InstRW<[M4WriteVLDA, 836 M4WriteA1], (instregex "LD1Twov(16b|8h|4s|2d)_POST$")>; 837 838def : InstRW<[M4WriteVLDB], (instregex "LD1Threev(8b|4h|2s|1d)$")>; 839def : InstRW<[M4WriteVLDB, 840 M4WriteA1], (instregex "LD1Threev(8b|4h|2s|1d)_POST$")>; 841def : InstRW<[M4WriteVLDB], (instregex "LD1Threev(16b|8h|4s|2d)$")>; 842def : InstRW<[M4WriteVLDB, 843 M4WriteA1], (instregex "LD1Threev(16b|8h|4s|2d)_POST$")>; 844 845def : InstRW<[M4WriteVLDC], (instregex "LD1Fourv(8b|4h|2s|1d)$")>; 846def : InstRW<[M4WriteVLDC, 847 M4WriteA1], (instregex "LD1Fourv(8b|4h|2s|1d)_POST$")>; 848def : InstRW<[M4WriteVLDC], (instregex "LD1Fourv(16b|8h|4s|2d)$")>; 849def : InstRW<[M4WriteVLDC, 850 M4WriteA1], (instregex "LD1Fourv(16b|8h|4s|2d)_POST$")>; 851 852def : InstRW<[M4WriteVLDD], (instregex "LD1i(8|16|32|64)$")>; 853def : InstRW<[M4WriteVLDD, 854 M4WriteA1], (instregex "LD1i(8|16|32|64)_POST$")>; 855 856def : InstRW<[WriteVLD], (instregex "LD1Rv(8b|4h|2s|1d)$")>; 857def : InstRW<[WriteVLD, 858 M4WriteA1], (instregex "LD1Rv(8b|4h|2s|1d)_POST$")>; 859def : InstRW<[WriteVLD], (instregex "LD1Rv(16b|8h|4s|2d)$")>; 860def : InstRW<[WriteVLD, 861 M4WriteA1], (instregex "LD1Rv(16b|8h|4s|2d)_POST$")>; 862 863def : InstRW<[M4WriteVLDF], (instregex "LD2Twov(8b|4h|2s)$")>; 864def : InstRW<[M4WriteVLDF, 865 M4WriteA1], (instregex "LD2Twov(8b|4h|2s)_POST$")>; 866def : InstRW<[M4WriteVLDF], (instregex "LD2Twov(16b|8h|4s|2d)$")>; 867def : InstRW<[M4WriteVLDF, 868 M4WriteA1], (instregex "LD2Twov(16b|8h|4s|2d)_POST$")>; 869 870def : InstRW<[M4WriteVLDG], (instregex "LD2i(8|16|32|64)$")>; 871def : InstRW<[M4WriteVLDG, 872 M4WriteA1], (instregex "LD2i(8|16|32|64)_POST$")>; 873 874def : InstRW<[M4WriteVLDA], (instregex "LD2Rv(8b|4h|2s|1d)$")>; 875def : InstRW<[M4WriteVLDA, 876 M4WriteA1], (instregex "LD2Rv(8b|4h|2s|1d)_POST$")>; 877def : InstRW<[M4WriteVLDA], (instregex "LD2Rv(16b|8h|4s|2d)$")>; 878def : InstRW<[M4WriteVLDA, 879 M4WriteA1], (instregex "LD2Rv(16b|8h|4s|2d)_POST$")>; 880 881def : InstRW<[M4WriteVLDI], (instregex "LD3Threev(8b|4h|2s)$")>; 882def : InstRW<[M4WriteVLDI, 883 M4WriteA1], (instregex "LD3Threev(8b|4h|2s)_POST$")>; 884def : InstRW<[M4WriteVLDI], (instregex "LD3Threev(16b|8h|4s|2d)$")>; 885def : InstRW<[M4WriteVLDI, 886 M4WriteA1], (instregex "LD3Threev(16b|8h|4s|2d)_POST$")>; 887 888def : InstRW<[M4WriteVLDJ], (instregex "LD3i(8|16|32)$")>; 889def : InstRW<[M4WriteVLDJ, 890 M4WriteA1], (instregex "LD3i(8|16|32)_POST$")>; 891def : InstRW<[M4WriteVLDL], (instregex "LD3i64$")>; 892def : InstRW<[M4WriteVLDL, 893 M4WriteA1], (instregex "LD3i64_POST$")>; 894 895def : InstRW<[M4WriteVLDB], (instregex "LD3Rv(8b|4h|2s|1d)$")>; 896def : InstRW<[M4WriteVLDB, 897 M4WriteA1], (instregex "LD3Rv(8b|4h|2s|1d)_POST$")>; 898def : InstRW<[M4WriteVLDB], (instregex "LD3Rv(16b|8h|4s|2d)$")>; 899def : InstRW<[M4WriteVLDB, 900 M4WriteA1], (instregex "LD3Rv(16b|8h|4s|2d)_POST$")>; 901 902def : InstRW<[M4WriteVLDN], (instregex "LD4Fourv(8b|4h|2s)$")>; 903def : InstRW<[M4WriteVLDN, 904 M4WriteA1], (instregex "LD4Fourv(8b|4h|2s)_POST$")>; 905def : InstRW<[M4WriteVLDN], (instregex "LD4Fourv(16b|8h|4s|2d)$")>; 906def : InstRW<[M4WriteVLDN, 907 M4WriteA1], (instregex "LD4Fourv(16b|8h|4s|2d)_POST$")>; 908 909def : InstRW<[M4WriteVLDK], (instregex "LD4i(8|16|32)$")>; 910def : InstRW<[M4WriteVLDK, 911 M4WriteA1], (instregex "LD4i(8|16|32)_POST$")>; 912def : InstRW<[M4WriteVLDM], (instregex "LD4i64$")>; 913def : InstRW<[M4WriteVLDM, 914 M4WriteA1], (instregex "LD4i64_POST$")>; 915 916def : InstRW<[M4WriteVLDC], (instregex "LD4Rv(8b|4h|2s|1d)$")>; 917def : InstRW<[M4WriteVLDC, 918 M4WriteA1], (instregex "LD4Rv(8b|4h|2s|1d)_POST$")>; 919def : InstRW<[M4WriteVLDC], (instregex "LD4Rv(16b|8h|4s|2d)$")>; 920def : InstRW<[M4WriteVLDC, 921 M4WriteA1], (instregex "LD4Rv(16b|8h|4s|2d)_POST$")>; 922 923// ASIMD store instructions. 924def : InstRW<[WriteVST], (instregex "ST1Onev(8b|4h|2s|1d)$")>; 925def : InstRW<[WriteVST, 926 M4WriteA1], (instregex "ST1Onev(8b|4h|2s|1d)_POST$")>; 927def : InstRW<[WriteVST], (instregex "ST1Onev(16b|8h|4s|2d)$")>; 928def : InstRW<[WriteVST, 929 M4WriteA1], (instregex "ST1Onev(16b|8h|4s|2d)_POST$")>; 930 931def : InstRW<[M4WriteVSTA], (instregex "ST1Twov(8b|4h|2s|1d)$")>; 932def : InstRW<[M4WriteVSTA, 933 M4WriteA1], (instregex "ST1Twov(8b|4h|2s|1d)_POST$")>; 934def : InstRW<[M4WriteVSTA], (instregex "ST1Twov(16b|8h|4s|2d)$")>; 935def : InstRW<[M4WriteVSTA, 936 M4WriteA1], (instregex "ST1Twov(16b|8h|4s|2d)_POST$")>; 937 938def : InstRW<[M4WriteVSTB], (instregex "ST1Threev(8b|4h|2s|1d)$")>; 939def : InstRW<[M4WriteVSTB, 940 M4WriteA1], (instregex "ST1Threev(8b|4h|2s|1d)_POST$")>; 941def : InstRW<[M4WriteVSTB], (instregex "ST1Threev(16b|8h|4s|2d)$")>; 942def : InstRW<[M4WriteVSTB, 943 M4WriteA1], (instregex "ST1Threev(16b|8h|4s|2d)_POST$")>; 944 945def : InstRW<[M4WriteVSTC], (instregex "ST1Fourv(8b|4h|2s|1d)$")>; 946def : InstRW<[M4WriteVSTC, 947 M4WriteA1], (instregex "ST1Fourv(8b|4h|2s|1d)_POST$")>; 948def : InstRW<[M4WriteVSTC], (instregex "ST1Fourv(16b|8h|4s|2d)$")>; 949def : InstRW<[M4WriteVSTC, 950 M4WriteA1], (instregex "ST1Fourv(16b|8h|4s|2d)_POST$")>; 951 952def : InstRW<[WriteVST], (instregex "ST1i(8|16|32|64)$")>; 953def : InstRW<[WriteVST, 954 M4WriteA1], (instregex "ST1i(8|16|32|64)_POST$")>; 955 956def : InstRW<[M4WriteVSTD], (instregex "ST2Twov(8b|4h|2s)$")>; 957def : InstRW<[M4WriteVSTD, 958 M4WriteA1], (instregex "ST2Twov(8b|4h|2s)_POST$")>; 959def : InstRW<[M4WriteVSTE], (instregex "ST2Twov(16b|8h|4s|2d)$")>; 960def : InstRW<[M4WriteVSTE, 961 M4WriteA1], (instregex "ST2Twov(16b|8h|4s|2d)_POST$")>; 962 963def : InstRW<[M4WriteVSTD], (instregex "ST2i(8|16|32|64)$")>; 964def : InstRW<[M4WriteVSTD, 965 M4WriteA1], (instregex "ST2i(8|16|32|64)_POST$")>; 966 967def : InstRW<[M4WriteVSTF], (instregex "ST3Threev(8b|4h|2s)$")>; 968def : InstRW<[M4WriteVSTF, 969 M4WriteA1], (instregex "ST3Threev(8b|4h|2s)_POST$")>; 970def : InstRW<[M4WriteVSTG], (instregex "ST3Threev(16b|8h|4s|2d)$")>; 971def : InstRW<[M4WriteVSTG, 972 M4WriteA1], (instregex "ST3Threev(16b|8h|4s|2d)_POST$")>; 973 974def : InstRW<[M4WriteVSTE], (instregex "ST3i(8|16|32|64)$")>; 975def : InstRW<[M4WriteVSTE, 976 M4WriteA1], (instregex "ST3i(8|16|32|64)_POST$")>; 977 978def : InstRW<[M4WriteVSTL], (instregex "ST4Fourv(8b|4h|2s)$")>; 979def : InstRW<[M4WriteVSTL, 980 M4WriteA1], (instregex "ST4Fourv(8b|4h|2s)_POST$")>; 981def : InstRW<[M4WriteVSTI], (instregex "ST4Fourv(16b|8h|4s|2d)$")>; 982def : InstRW<[M4WriteVSTI, 983 M4WriteA1], (instregex "ST4Fourv(16b|8h|4s|2d)_POST$")>; 984 985def : InstRW<[M4WriteVSTE], (instregex "ST4i(8|16|32|64)$")>; 986def : InstRW<[M4WriteVSTE, 987 M4WriteA1], (instregex "ST4i(8|16|32|64)_POST$")>; 988 989// Cryptography instructions. 990def : InstRW<[M4WriteNCRY1], (instregex "^AES[DE]")>; 991def : InstRW<[M4WriteNCRY1, 992 M4ReadAESM1], (instregex "^AESI?MC")>; 993def : InstRW<[M4WriteNCRY1A], (instregex "^PMULv")>; 994def : InstRW<[M4WriteNCRY1A], (instregex "^PMULLv(1|8)i")>; 995def : InstRW<[M4WriteNCRY3A], (instregex "^PMULLv(2|16)i")>; 996def : InstRW<[M4WriteNCRY1A], (instregex "^SHA1([CHMP]|SU[01])")>; 997def : InstRW<[M4WriteNCRY1A], (instrs SHA256SU0rr)>; 998def : InstRW<[M4WriteNCRY5A], (instrs SHA256SU1rrr)>; 999def : InstRW<[M4WriteNCRY5A], (instrs SHA256H2rrr)>; 1000 1001// CRC instructions. 1002def : InstRW<[M4WriteE2], (instregex "^CRC32C?[BHWX]rr$")>; 1003 1004} // SchedModel = ExynosM4Model 1005