AArch64SchedExynosM3.td revision 363496
1//=- AArch64SchedExynosM3.td - Samsung Exynos M3 Sched Defs --*- tablegen -*-=// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file defines the machine model for the Samsung Exynos M3 to support 10// instruction scheduling and other instruction cost heuristics. 11// 12//===----------------------------------------------------------------------===// 13 14//===----------------------------------------------------------------------===// 15// The Exynos-M3 is an advanced superscalar microprocessor with a 6-wide 16// in-order stage for decode and dispatch and a wider issue stage. 17// The execution units and loads and stores are out-of-order. 18 19def ExynosM3Model : SchedMachineModel { 20 let IssueWidth = 6; // Up to 6 uops per cycle. 21 let MicroOpBufferSize = 228; // ROB size. 22 let LoopMicroOpBufferSize = 40; // Based on the instruction queue size. 23 let LoadLatency = 4; // Optimistic load cases. 24 let MispredictPenalty = 16; // Minimum branch misprediction penalty. 25 let CompleteModel = 1; // Use the default model otherwise. 26 27 list<Predicate> UnsupportedFeatures = !listconcat(SVEUnsupported.F, 28 PAUnsupported.F); 29} 30 31//===----------------------------------------------------------------------===// 32// Define each kind of processor resource and number available on the Exynos-M3, 33// which has 12 pipelines, each with its own queue with out-of-order dispatch. 34 35let SchedModel = ExynosM3Model in { 36 37def M3UnitA : ProcResource<2>; // Simple integer 38def M3UnitC : ProcResource<2>; // Simple and complex integer 39def M3UnitD : ProcResource<1>; // Integer division (inside C0, serialized) 40def M3UnitB : ProcResource<2>; // Branch 41def M3UnitL : ProcResource<2>; // Load 42def M3UnitS : ProcResource<1>; // Store 43def M3PipeF0 : ProcResource<1>; // FP #0 44let Super = M3PipeF0 in { 45 def M3UnitFMAC0 : ProcResource<1>; // FP multiplication 46 def M3UnitFADD0 : ProcResource<1>; // Simple FP 47 def M3UnitFCVT0 : ProcResource<1>; // FP conversion 48 def M3UnitFSQR : ProcResource<2>; // FP square root (serialized) 49 def M3UnitNALU0 : ProcResource<1>; // Simple vector 50 def M3UnitNMSC : ProcResource<1>; // FP and vector miscellanea 51 def M3UnitNSHT0 : ProcResource<1>; // Vector shifting 52 def M3UnitNSHF0 : ProcResource<1>; // Vector shuffling 53} 54def M3PipeF1 : ProcResource<1>; // FP #1 55let Super = M3PipeF1 in { 56 def M3UnitFMAC1 : ProcResource<1>; // FP multiplication 57 def M3UnitFADD1 : ProcResource<1>; // Simple FP 58 def M3UnitFDIV0 : ProcResource<2>; // FP division (serialized) 59 def M3UnitFCVT1 : ProcResource<1>; // FP conversion 60 def M3UnitFST0 : ProcResource<1>; // FP store 61 def M3UnitNALU1 : ProcResource<1>; // Simple vector 62 def M3UnitNCRY0 : ProcResource<1>; // Cryptographic 63 def M3UnitNMUL : ProcResource<1>; // Vector multiplication 64 def M3UnitNSHT1 : ProcResource<1>; // Vector shifting 65 def M3UnitNSHF1 : ProcResource<1>; // Vector shuffling 66} 67def M3PipeF2 : ProcResource<1>; // FP #2 68let Super = M3PipeF2 in { 69 def M3UnitFMAC2 : ProcResource<1>; // FP multiplication 70 def M3UnitFADD2 : ProcResource<1>; // Simple FP 71 def M3UnitFDIV1 : ProcResource<2>; // FP division (serialized) 72 def M3UnitFST1 : ProcResource<1>; // FP store 73 def M3UnitNALU2 : ProcResource<1>; // Simple vector 74 def M3UnitNCRY1 : ProcResource<1>; // Cryptographic 75 def M3UnitNSHT2 : ProcResource<1>; // Vector shifting 76 def M3UnitNSHF2 : ProcResource<1>; // Vector shuffling 77} 78 79 80def M3UnitALU : ProcResGroup<[M3UnitA, 81 M3UnitC]>; 82def M3UnitFMAC : ProcResGroup<[M3UnitFMAC0, 83 M3UnitFMAC1, 84 M3UnitFMAC2]>; 85def M3UnitFADD : ProcResGroup<[M3UnitFADD0, 86 M3UnitFADD1, 87 M3UnitFADD2]>; 88def M3UnitFDIV : ProcResGroup<[M3UnitFDIV0, 89 M3UnitFDIV1]>; 90def M3UnitFCVT : ProcResGroup<[M3UnitFCVT0, 91 M3UnitFCVT1]>; 92def M3UnitFST : ProcResGroup<[M3UnitFST0, 93 M3UnitFST1]>; 94def M3UnitNALU : ProcResGroup<[M3UnitNALU0, 95 M3UnitNALU1, 96 M3UnitNALU2]>; 97def M3UnitNCRY : ProcResGroup<[M3UnitNCRY0, 98 M3UnitNCRY1]>; 99def M3UnitNSHT : ProcResGroup<[M3UnitNSHT0, 100 M3UnitNSHT1, 101 M3UnitNSHT2]>; 102def M3UnitNSHF : ProcResGroup<[M3UnitNSHF0, 103 M3UnitNSHF1, 104 M3UnitNSHF2]>; 105 106//===----------------------------------------------------------------------===// 107// Coarse scheduling model. 108 109def M3WriteZ0 : SchedWriteRes<[]> { let Latency = 0; 110 let NumMicroOps = 1; } 111def M3WriteZ1 : SchedWriteRes<[]> { let Latency = 1; 112 let NumMicroOps = 0; } 113 114def M3WriteA1 : SchedWriteRes<[M3UnitALU]> { let Latency = 1; } 115def M3WriteAA : SchedWriteRes<[M3UnitALU]> { let Latency = 2; 116 let ResourceCycles = [2]; } 117def M3WriteAB : SchedWriteRes<[M3UnitALU, 118 M3UnitC]> { let Latency = 1; 119 let NumMicroOps = 2; } 120def M3WriteAC : SchedWriteRes<[M3UnitALU, 121 M3UnitALU, 122 M3UnitC]> { let Latency = 2; 123 let NumMicroOps = 3; } 124def M3WriteAD : SchedWriteRes<[M3UnitALU, 125 M3UnitC]> { let Latency = 2; 126 let NumMicroOps = 2; } 127def M3WriteC1 : SchedWriteRes<[M3UnitC]> { let Latency = 1; } 128def M3WriteC2 : SchedWriteRes<[M3UnitC]> { let Latency = 2; } 129def M3WriteAU : SchedWriteVariant<[SchedVar<IsCopyIdiomPred, [M3WriteZ0]>, 130 SchedVar<ExynosArithPred, [M3WriteA1]>, 131 SchedVar<ExynosLogicPred, [M3WriteA1]>, 132 SchedVar<NoSchedPred, [M3WriteAA]>]>; 133def M3WriteAV : SchedWriteVariant<[SchedVar<IsCopyIdiomPred, [M3WriteZ0]>, 134 SchedVar<ExynosArithPred, [M3WriteA1]>, 135 SchedVar<NoSchedPred, [M3WriteAA]>]>; 136def M3WriteAW : SchedWriteVariant<[SchedVar<IsZeroIdiomPred, [M3WriteZ0]>, 137 SchedVar<ExynosLogicPred, [M3WriteA1]>, 138 SchedVar<NoSchedPred, [M3WriteAA]>]>; 139def M3WriteAX : SchedWriteVariant<[SchedVar<ExynosArithPred, [M3WriteA1]>, 140 SchedVar<ExynosLogicPred, [M3WriteA1]>, 141 SchedVar<NoSchedPred, [M3WriteAA]>]>; 142def M3WriteAY : SchedWriteVariant<[SchedVar<ExynosRotateRightImmPred, [M3WriteA1]>, 143 SchedVar<NoSchedPred, [M3WriteAA]>]>; 144 145def M3WriteB1 : SchedWriteRes<[M3UnitB]> { let Latency = 1; } 146def M3WriteBX : SchedWriteVariant<[SchedVar<ExynosBranchLinkLRPred, [M3WriteAC]>, 147 SchedVar<NoSchedPred, [M3WriteAB]>]>; 148 149def M3WriteL4 : SchedWriteRes<[M3UnitL]> { let Latency = 4; } 150def M3WriteL5 : SchedWriteRes<[M3UnitL]> { let Latency = 5; } 151def M3WriteLA : SchedWriteRes<[M3UnitL, 152 M3UnitL]> { let Latency = 5; 153 let NumMicroOps = 1; } 154def M3WriteLB : SchedWriteRes<[M3UnitA, 155 M3UnitL]> { let Latency = 5; 156 let NumMicroOps = 2; } 157def M3WriteLC : SchedWriteRes<[M3UnitA, 158 M3UnitL, 159 M3UnitL]> { let Latency = 5; 160 let NumMicroOps = 2; } 161def M3WriteLD : SchedWriteRes<[M3UnitA, 162 M3UnitL]> { let Latency = 4; 163 let NumMicroOps = 2; } 164def M3WriteLE : SchedWriteRes<[M3UnitA, 165 M3UnitL]> { let Latency = 6; 166 let NumMicroOps = 2; } 167def M3WriteLH : SchedWriteRes<[]> { let Latency = 5; 168 let NumMicroOps = 0; } 169def M3WriteLX : SchedWriteVariant<[SchedVar<ExynosScaledIdxPred, [M3WriteL5]>, 170 SchedVar<NoSchedPred, [M3WriteL4]>]>; 171def M3WriteLY : SchedWriteVariant<[SchedVar<ExynosScaledIdxPred, [M3WriteLE]>, 172 SchedVar<NoSchedPred, [M3WriteL5]>]>; 173 174def M3WriteS1 : SchedWriteRes<[M3UnitS]> { let Latency = 1; } 175def M3WriteSA : SchedWriteRes<[M3UnitA, 176 M3UnitS, 177 M3UnitFST]> { let Latency = 3; 178 let NumMicroOps = 2; } 179def M3WriteSB : SchedWriteRes<[M3UnitA, 180 M3UnitS]> { let Latency = 2; 181 let NumMicroOps = 2; } 182def M3WriteSC : SchedWriteRes<[M3UnitA, 183 M3UnitS, 184 M3UnitFST]> { let Latency = 1; 185 let NumMicroOps = 2; } 186def M3WriteSY : SchedWriteVariant<[SchedVar<ExynosScaledIdxPred, [M3WriteSA]>, 187 SchedVar<NoSchedPred, [WriteVST]>]>; 188 189def M3ReadAdrBase : SchedReadVariant<[SchedVar<ExynosScaledIdxPred, [ReadDefault]>, 190 SchedVar<NoSchedPred, [ReadDefault]>]>; 191 192// Branch instructions. 193def : SchedAlias<WriteBr, M3WriteZ0>; 194def : SchedAlias<WriteBrReg, M3WriteC1>; 195 196// Arithmetic and logical integer instructions. 197def : SchedAlias<WriteI, M3WriteA1>; 198def : SchedAlias<WriteISReg, M3WriteA1>; 199def : SchedAlias<WriteIEReg, M3WriteA1>; 200def : SchedAlias<WriteIS, M3WriteA1>; 201 202// Move instructions. 203def : SchedAlias<WriteImm, M3WriteA1>; 204 205// Divide and multiply instructions. 206def : WriteRes<WriteID32, [M3UnitC, 207 M3UnitD]> { let Latency = 12; 208 let ResourceCycles = [1, 12]; } 209def : WriteRes<WriteID64, [M3UnitC, 210 M3UnitD]> { let Latency = 21; 211 let ResourceCycles = [1, 21]; } 212def : WriteRes<WriteIM32, [M3UnitC]> { let Latency = 3; } 213def : WriteRes<WriteIM64, [M3UnitC]> { let Latency = 4; 214 let ResourceCycles = [2]; } 215 216// Miscellaneous instructions. 217def : SchedAlias<WriteExtr, M3WriteAY>; 218 219// Addressing modes. 220def : SchedAlias<WriteAdr, M3WriteZ1>; 221def : SchedAlias<ReadAdrBase, M3ReadAdrBase>; 222 223// Load instructions. 224def : SchedAlias<WriteLD, M3WriteL4>; 225def : WriteRes<WriteLDHi, []> { let Latency = 4; 226 let NumMicroOps = 0; } 227def : SchedAlias<WriteLDIdx, M3WriteLB>; 228 229// Store instructions. 230def : SchedAlias<WriteST, M3WriteS1>; 231def : SchedAlias<WriteSTP, M3WriteS1>; 232def : SchedAlias<WriteSTX, M3WriteS1>; 233def : SchedAlias<WriteSTIdx, M3WriteSB>; 234 235// FP data instructions. 236def : WriteRes<WriteF, [M3UnitFADD]> { let Latency = 2; } 237def : WriteRes<WriteFCmp, [M3UnitNMSC]> { let Latency = 2; } 238def : WriteRes<WriteFDiv, [M3UnitFDIV]> { let Latency = 12; 239 let ResourceCycles = [12]; } 240def : WriteRes<WriteFMul, [M3UnitFMAC]> { let Latency = 4; } 241 242// FP miscellaneous instructions. 243def : WriteRes<WriteFCvt, [M3UnitFCVT]> { let Latency = 3; } 244def : WriteRes<WriteFImm, [M3UnitNALU]> { let Latency = 1; } 245def : WriteRes<WriteFCopy, [M3UnitNALU]> { let Latency = 1; } 246 247// FP load instructions. 248def : SchedAlias<WriteVLD, M3WriteL5>; 249 250// FP store instructions. 251def : WriteRes<WriteVST, [M3UnitS, 252 M3UnitFST]> { let Latency = 1; 253 let NumMicroOps = 1; } 254 255// ASIMD FP instructions. 256def : WriteRes<WriteV, [M3UnitNALU]> { let Latency = 3; } 257 258// Other miscellaneous instructions. 259def : WriteRes<WriteAtomic, []> { let Unsupported = 1; } 260def : WriteRes<WriteBarrier, []> { let Latency = 1; } 261def : WriteRes<WriteHint, []> { let Latency = 1; } 262def : WriteRes<WriteSys, []> { let Latency = 1; } 263 264//===----------------------------------------------------------------------===// 265// Generic fast forwarding. 266 267// TODO: Add FP register forwarding rules. 268 269def : ReadAdvance<ReadI, 0>; 270def : ReadAdvance<ReadISReg, 0>; 271def : ReadAdvance<ReadIEReg, 0>; 272def : ReadAdvance<ReadIM, 0>; 273// TODO: The forwarding for 32 bits actually saves 2 cycles. 274def : ReadAdvance<ReadIMA, 3, [WriteIM32, WriteIM64]>; 275def : ReadAdvance<ReadID, 0>; 276def : ReadAdvance<ReadExtrHi, 0>; 277def : ReadAdvance<ReadAdrBase, 0>; 278def : ReadAdvance<ReadVLD, 0>; 279 280//===----------------------------------------------------------------------===// 281// Finer scheduling model. 282 283def M3WriteNEONA : SchedWriteRes<[M3UnitNSHF, 284 M3UnitFADD]> { let Latency = 3; 285 let NumMicroOps = 2; } 286def M3WriteNEONB : SchedWriteRes<[M3UnitNALU, 287 M3UnitFST]> { let Latency = 10; 288 let NumMicroOps = 2; } 289def M3WriteNEOND : SchedWriteRes<[M3UnitNSHF, 290 M3UnitFST]> { let Latency = 6; 291 let NumMicroOps = 2; } 292def M3WriteNEONH : SchedWriteRes<[M3UnitNALU, 293 M3UnitS]> { let Latency = 5; 294 let NumMicroOps = 2; } 295def M3WriteNEONI : SchedWriteRes<[M3UnitNSHF, 296 M3UnitS]> { let Latency = 5; 297 let NumMicroOps = 2; } 298def M3WriteNEONV : SchedWriteRes<[M3UnitFDIV0, 299 M3UnitFDIV1]> { let Latency = 7; 300 let NumMicroOps = 2; 301 let ResourceCycles = [8, 8]; } 302def M3WriteNEONW : SchedWriteRes<[M3UnitFDIV0, 303 M3UnitFDIV1]> { let Latency = 12; 304 let NumMicroOps = 2; 305 let ResourceCycles = [13, 13]; } 306def M3WriteNEONX : SchedWriteRes<[M3UnitFSQR, 307 M3UnitFSQR]> { let Latency = 18; 308 let NumMicroOps = 2; 309 let ResourceCycles = [19, 19]; } 310def M3WriteNEONY : SchedWriteRes<[M3UnitFSQR, 311 M3UnitFSQR]> { let Latency = 25; 312 let NumMicroOps = 2; 313 let ResourceCycles = [26, 26]; } 314def M3WriteNEONZ : SchedWriteRes<[M3UnitNMSC, 315 M3UnitNMSC]> { let Latency = 5; 316 let NumMicroOps = 2; } 317def M3WriteFADD2 : SchedWriteRes<[M3UnitFADD]> { let Latency = 2; } 318def M3WriteFCVT2 : SchedWriteRes<[M3UnitFCVT]> { let Latency = 2; } 319def M3WriteFCVT3 : SchedWriteRes<[M3UnitFCVT]> { let Latency = 3; } 320def M3WriteFCVT3A : SchedWriteRes<[M3UnitFCVT0]> { let Latency = 3; } 321def M3WriteFCVT4A : SchedWriteRes<[M3UnitFCVT0]> { let Latency = 4; } 322def M3WriteFCVT4 : SchedWriteRes<[M3UnitFCVT]> { let Latency = 4; } 323def M3WriteFDIV10 : SchedWriteRes<[M3UnitFDIV]> { let Latency = 7; 324 let ResourceCycles = [8]; } 325def M3WriteFDIV12 : SchedWriteRes<[M3UnitFDIV]> { let Latency = 12; 326 let ResourceCycles = [13]; } 327def M3WriteFMAC3 : SchedWriteRes<[M3UnitFMAC]> { let Latency = 3; } 328def M3WriteFMAC4 : SchedWriteRes<[M3UnitFMAC]> { let Latency = 4; } 329def M3WriteFMAC5 : SchedWriteRes<[M3UnitFMAC]> { let Latency = 5; } 330def M3WriteFSQR17 : SchedWriteRes<[M3UnitFSQR]> { let Latency = 18; 331 let ResourceCycles = [19]; } 332def M3WriteFSQR25 : SchedWriteRes<[M3UnitFSQR]> { let Latency = 25; 333 let ResourceCycles = [26]; } 334def M3WriteNALU1 : SchedWriteRes<[M3UnitNALU]> { let Latency = 1; } 335def M3WriteNCRY1A : SchedWriteRes<[M3UnitNCRY0]> { let Latency = 1; } 336def M3WriteNCRY3A : SchedWriteRes<[M3UnitNCRY0]> { let Latency = 3; } 337def M3WriteNCRY5A : SchedWriteRes<[M3UnitNCRY]> { let Latency = 5; } 338def M3WriteNMSC1 : SchedWriteRes<[M3UnitNMSC]> { let Latency = 1; } 339def M3WriteNMSC2 : SchedWriteRes<[M3UnitNMSC]> { let Latency = 2; } 340def M3WriteNMSC3 : SchedWriteRes<[M3UnitNMSC]> { let Latency = 3; } 341def M3WriteNMUL3 : SchedWriteRes<[M3UnitNMUL]> { let Latency = 3; } 342def M3WriteNSHF1 : SchedWriteRes<[M3UnitNSHF]> { let Latency = 1; } 343def M3WriteNSHF3 : SchedWriteRes<[M3UnitNSHF]> { let Latency = 3; } 344def M3WriteNSHT1 : SchedWriteRes<[M3UnitNSHT]> { let Latency = 1; } 345def M3WriteNSHT2 : SchedWriteRes<[M3UnitNSHT]> { let Latency = 2; } 346def M3WriteNSHT3 : SchedWriteRes<[M3UnitNSHT]> { let Latency = 3; } 347def M3WriteVLDA : SchedWriteRes<[M3UnitL, 348 M3UnitL]> { let Latency = 5; 349 let NumMicroOps = 2; } 350def M3WriteVLDB : SchedWriteRes<[M3UnitL, 351 M3UnitL, 352 M3UnitL]> { let Latency = 6; 353 let NumMicroOps = 3; } 354def M3WriteVLDC : SchedWriteRes<[M3UnitL, 355 M3UnitL, 356 M3UnitL, 357 M3UnitL]> { let Latency = 6; 358 let NumMicroOps = 4; } 359def M3WriteVLDD : SchedWriteRes<[M3UnitL, 360 M3UnitNALU]> { let Latency = 7; 361 let NumMicroOps = 2; 362 let ResourceCycles = [2, 1]; } 363def M3WriteVLDE : SchedWriteRes<[M3UnitL, 364 M3UnitNALU]> { let Latency = 6; 365 let NumMicroOps = 2; 366 let ResourceCycles = [2, 1]; } 367def M3WriteVLDF : SchedWriteRes<[M3UnitL, 368 M3UnitL]> { let Latency = 10; 369 let NumMicroOps = 2; 370 let ResourceCycles = [5, 5]; } 371def M3WriteVLDG : SchedWriteRes<[M3UnitL, 372 M3UnitNALU, 373 M3UnitNALU]> { let Latency = 7; 374 let NumMicroOps = 3; 375 let ResourceCycles = [2, 1, 1]; } 376def M3WriteVLDH : SchedWriteRes<[M3UnitL, 377 M3UnitNALU, 378 M3UnitNALU]> { let Latency = 6; 379 let NumMicroOps = 3; 380 let ResourceCycles = [2, 1, 1]; } 381def M3WriteVLDI : SchedWriteRes<[M3UnitL, 382 M3UnitL, 383 M3UnitL]> { let Latency = 12; 384 let NumMicroOps = 3; 385 let ResourceCycles = [6, 6, 6]; } 386def M3WriteVLDJ : SchedWriteRes<[M3UnitL, 387 M3UnitNALU, 388 M3UnitNALU, 389 M3UnitNALU]> { let Latency = 7; 390 let NumMicroOps = 4; 391 let ResourceCycles = [2, 1, 1, 1]; } 392def M3WriteVLDK : SchedWriteRes<[M3UnitL, 393 M3UnitNALU, 394 M3UnitNALU, 395 M3UnitNALU, 396 M3UnitNALU]> { let Latency = 9; 397 let NumMicroOps = 5; 398 let ResourceCycles = [4, 1, 1, 1, 1]; } 399def M3WriteVLDL : SchedWriteRes<[M3UnitL, 400 M3UnitNALU, 401 M3UnitNALU, 402 M3UnitL, 403 M3UnitNALU]> { let Latency = 6; 404 let NumMicroOps = 5; 405 let ResourceCycles = [6, 1, 1, 6, 1]; } 406def M3WriteVLDM : SchedWriteRes<[M3UnitL, 407 M3UnitNALU, 408 M3UnitNALU, 409 M3UnitL, 410 M3UnitNALU, 411 M3UnitNALU]> { let Latency = 7; 412 let NumMicroOps = 6; 413 let ResourceCycles = [6, 1, 1, 6, 1, 1]; } 414def M3WriteVLDN : SchedWriteRes<[M3UnitL, 415 M3UnitL, 416 M3UnitL, 417 M3UnitL]> { let Latency = 14; 418 let NumMicroOps = 4; 419 let ResourceCycles = [6, 6, 6, 6]; } 420def M3WriteVSTA : WriteSequence<[WriteVST], 2>; 421def M3WriteVSTB : WriteSequence<[WriteVST], 3>; 422def M3WriteVSTC : WriteSequence<[WriteVST], 4>; 423def M3WriteVSTD : SchedWriteRes<[M3UnitS, 424 M3UnitFST, 425 M3UnitS, 426 M3UnitFST]> { let Latency = 7; 427 let NumMicroOps = 4; 428 let ResourceCycles = [1, 3, 1, 3]; } 429def M3WriteVSTE : SchedWriteRes<[M3UnitS, 430 M3UnitFST, 431 M3UnitS, 432 M3UnitFST, 433 M3UnitS, 434 M3UnitFST]> { let Latency = 8; 435 let NumMicroOps = 6; 436 let ResourceCycles = [1, 3, 1, 3, 1, 3]; } 437def M3WriteVSTF : SchedWriteRes<[M3UnitNALU, 438 M3UnitFST, 439 M3UnitFST, 440 M3UnitS, 441 M3UnitFST, 442 M3UnitS, 443 M3UnitFST]> { let Latency = 15; 444 let NumMicroOps = 7; 445 let ResourceCycles = [1, 3, 3, 1, 3, 1, 3]; } 446def M3WriteVSTG : SchedWriteRes<[M3UnitNALU, 447 M3UnitFST, 448 M3UnitFST, 449 M3UnitS, 450 M3UnitFST, 451 M3UnitS, 452 M3UnitFST, 453 M3UnitS, 454 M3UnitFST]> { let Latency = 16; 455 let NumMicroOps = 9; 456 let ResourceCycles = [1, 3, 3, 1, 3, 1, 3, 1, 3]; } 457def M3WriteVSTH : SchedWriteRes<[M3UnitNALU, 458 M3UnitFST, 459 M3UnitFST, 460 M3UnitS, 461 M3UnitFST]> { let Latency = 14; 462 let NumMicroOps = 5; 463 let ResourceCycles = [1, 3, 3, 1, 3]; } 464def M3WriteVSTI : SchedWriteRes<[M3UnitNALU, 465 M3UnitFST, 466 M3UnitFST, 467 M3UnitS, 468 M3UnitFST, 469 M3UnitS, 470 M3UnitFST, 471 M3UnitS, 472 M3UnitFST]> { let Latency = 17; 473 let NumMicroOps = 9; 474 let ResourceCycles = [1, 3, 3, 1, 3, 1, 3, 1, 3]; } 475 476// Special cases. 477def M3WriteAES : SchedWriteRes<[M3UnitNCRY]> { let Latency = 1; } 478def M3WriteCOPY : SchedWriteVariant<[SchedVar<ExynosFPPred, [M3WriteNALU1]>, 479 SchedVar<NoSchedPred, [M3WriteZ0]>]>; 480def M3WriteMOVI : SchedWriteVariant<[SchedVar<IsZeroFPIdiomPred, [M3WriteZ0]>, 481 SchedVar<NoSchedPred, [M3WriteNALU1]>]>; 482 483// Fast forwarding. 484def M3ReadAES : SchedReadAdvance<1, [M3WriteAES]>; 485def M3ReadFMAC : SchedReadAdvance<1, [M3WriteFMAC4, 486 M3WriteFMAC5]>; 487def M3ReadNMUL : SchedReadAdvance<1, [M3WriteNMUL3]>; 488 489// Branch instructions 490def : InstRW<[M3WriteB1], (instrs Bcc)>; 491def : InstRW<[M3WriteA1], (instrs BL)>; 492def : InstRW<[M3WriteBX], (instrs BLR)>; 493def : InstRW<[M3WriteC1], (instregex "^CBN?Z[WX]")>; 494def : InstRW<[M3WriteAD], (instregex "^TBN?Z[WX]")>; 495 496// Arithmetic and logical integer instructions. 497def : InstRW<[M3WriteAX], (instregex "^(ADD|AND|BIC|EON|EOR|ORN|SUB)[WX]rs$")>; 498def : InstRW<[M3WriteAU], (instrs ORRWrs, ORRXrs)>; 499def : InstRW<[M3WriteAX], (instregex "^(ADD|SUB)S?[WX]rx(64)?$")>; 500def : InstRW<[M3WriteAX], (instregex "^(ADD|AND|BIC|SUB)S[WX]rs$")>; 501def : InstRW<[M3WriteAV], (instrs ADDWri, ADDXri)>; 502def : InstRW<[M3WriteAW], (instrs ORRWri, ORRXri)>; 503 504// Move instructions. 505def : InstRW<[M3WriteCOPY], (instrs COPY)>; 506def : InstRW<[M3WriteZ0], (instrs ADR, ADRP)>; 507def : InstRW<[M3WriteZ0], (instregex "^MOV[NZ][WX]i")>; 508 509// Divide and multiply instructions. 510 511// Miscellaneous instructions. 512 513// Load instructions. 514def : InstRW<[M3WriteLD, 515 WriteLDHi, 516 WriteAdr], (instregex "^LDP(SW|W|X)(post|pre)")>; 517def : InstRW<[M3WriteLB, 518 ReadAdrBase], (instregex "^LDR(BB|SBW|SBX|HH|SHW|SHX|SW|W|X)roW")>; 519def : InstRW<[M3WriteLX, 520 ReadAdrBase], (instregex "^LDR(BB|SBW|SBX|HH|SHW|SHX|SW|W|X)roX")>; 521def : InstRW<[M3WriteLB, 522 ReadAdrBase], (instrs PRFMroW)>; 523def : InstRW<[M3WriteLX, 524 ReadAdrBase], (instrs PRFMroX)>; 525 526// Store instructions. 527def : InstRW<[M3WriteSB, 528 ReadAdrBase], (instregex "^STR(BB|HH|W|X)roW")>; 529def : InstRW<[WriteST, 530 ReadAdrBase], (instregex "^STR(BB|HH|W|X)roX")>; 531 532// FP data instructions. 533def : InstRW<[M3WriteNSHF1], (instregex "^FABS[DS]r")>; 534def : InstRW<[M3WriteFADD2], (instregex "^F(ADD|SUB)[DS]rr")>; 535def : InstRW<[M3WriteFDIV10], (instrs FDIVSrr)>; 536def : InstRW<[M3WriteFDIV12], (instrs FDIVDrr)>; 537def : InstRW<[M3WriteNMSC1], (instregex "^F(MAX|MIN).+rr")>; 538def : InstRW<[M3WriteFMAC3], (instregex "^FN?MUL[DS]rr")>; 539def : InstRW<[M3WriteFMAC4, 540 M3ReadFMAC], (instregex "^FN?M(ADD|SUB)[DS]rrr")>; 541def : InstRW<[M3WriteNALU1], (instregex "^FNEG[DS]r")>; 542def : InstRW<[M3WriteFCVT3A], (instregex "^FRINT.+r")>; 543def : InstRW<[M3WriteNEONH], (instregex "^FCSEL[DS]rrr")>; 544def : InstRW<[M3WriteFSQR17], (instrs FSQRTSr)>; 545def : InstRW<[M3WriteFSQR25], (instrs FSQRTDr)>; 546 547// FP miscellaneous instructions. 548def : InstRW<[M3WriteFCVT3], (instregex "^FCVT[DHS][DHS]r")>; 549def : InstRW<[M3WriteFCVT4A], (instregex "^[SU]CVTF[SU][XW][DHS]ri")>; 550def : InstRW<[M3WriteFCVT3A], (instregex "^FCVT[AMNPZ][SU]U[XW][DHS]r")>; 551def : InstRW<[M3WriteFCVT3A], (instregex "^FCVTZ[SU][dhs]")>; 552def : InstRW<[M3WriteNALU1], (instregex "^FMOV[DS][ir]")>; 553def : InstRW<[M3WriteFCVT4], (instregex "^[FU](RECP|RSQRT)Ev1")>; 554def : InstRW<[M3WriteNMSC1], (instregex "^FRECPXv1")>; 555def : InstRW<[M3WriteFMAC4, 556 M3ReadFMAC], (instregex "^F(RECP|RSQRT)S(16|32|64)")>; 557def : InstRW<[M3WriteNALU1], (instregex "^FMOV[WX][DS]r")>; 558def : InstRW<[M3WriteNALU1], (instregex "^FMOV[DS][WX]r")>; 559def : InstRW<[M3WriteNEONI], (instregex "^FMOV(DX|XD)Highr")>; 560 561// FP load instructions. 562def : InstRW<[WriteVLD], (instregex "^LDR[DSQ]l")>; 563def : InstRW<[WriteVLD], (instregex "^LDUR[BDHSQ]i")>; 564def : InstRW<[WriteVLD, 565 WriteAdr], (instregex "^LDR[BDHSQ](post|pre)")>; 566def : InstRW<[WriteVLD], (instregex "^LDR[BDHSQ]ui")>; 567def : InstRW<[M3WriteLE, 568 ReadAdrBase], (instregex "^LDR[BDHS]roW")>; 569def : InstRW<[WriteVLD, 570 ReadAdrBase], (instregex "^LDR[BDHS]roX")>; 571def : InstRW<[M3WriteLY, 572 ReadAdrBase], (instregex "^LDRQro[WX]")>; 573def : InstRW<[WriteVLD, 574 M3WriteLH], (instregex "^LDN?P[DS]i")>; 575def : InstRW<[M3WriteLA, 576 M3WriteLH], (instregex "^LDN?PQi")>; 577def : InstRW<[M3WriteLB, 578 M3WriteLH, 579 WriteAdr], (instregex "^LDP[DS](post|pre)")>; 580def : InstRW<[M3WriteLC, 581 M3WriteLH, 582 WriteAdr], (instregex "^LDPQ(post|pre)")>; 583 584// FP store instructions. 585def : InstRW<[WriteVST], (instregex "^STUR[BDHSQ]i")>; 586def : InstRW<[WriteVST, 587 WriteAdr], (instregex "^STR[BDHSQ](post|pre)")>; 588def : InstRW<[WriteVST], (instregex "^STR[BDHSQ]ui")>; 589def : InstRW<[M3WriteSA, 590 ReadAdrBase], (instregex "^STR[BDHS]roW")>; 591def : InstRW<[M3WriteSA, 592 ReadAdrBase], (instregex "^STRQroW")>; 593def : InstRW<[WriteVST, 594 ReadAdrBase], (instregex "^STR[BDHS]roX")>; 595def : InstRW<[M3WriteSY, 596 ReadAdrBase], (instregex "^STRQroX")>; 597def : InstRW<[WriteVST], (instregex "^STN?P[DSQ]i")>; 598def : InstRW<[WriteVST, 599 WriteAdr], (instregex "^STP[DS](post|pre)")>; 600def : InstRW<[M3WriteSC, 601 WriteAdr], (instregex "^STPQ(post|pre)")>; 602 603// ASIMD instructions. 604def : InstRW<[M3WriteNMSC3], (instregex "^[SU]ABAL?v")>; 605def : InstRW<[M3WriteNMSC1], (instregex "^[SU]ABDL?v")>; 606def : InstRW<[M3WriteNMSC1], (instregex "^((SQ)?ABS|SQNEG)v")>; 607def : InstRW<[M3WriteNALU1], (instregex "^(ADD|NEG|SUB)v")>; 608def : InstRW<[M3WriteNMSC3], (instregex "^[SU]?ADDL?Pv")>; 609def : InstRW<[M3WriteNMSC3], (instregex "^[SU]H(ADD|SUB)v")>; 610def : InstRW<[M3WriteNMSC3], (instregex "^[SU](ADD|SUB)[LW]V?v")>; 611def : InstRW<[M3WriteNMSC3], (instregex "^R?(ADD|SUB)HN2?v")>; 612def : InstRW<[M3WriteNMSC3], (instregex "^[SU]Q(ADD|SUB)v")>; 613def : InstRW<[M3WriteNMSC3], (instregex "^(SU|US)QADDv")>; 614def : InstRW<[M3WriteNMSC3], (instregex "^[SU]RHADDv")>; 615def : InstRW<[M3WriteNMSC1], (instregex "^CM(EQ|GE|GT|HI|HS|LE|LT)v")>; 616def : InstRW<[M3WriteNALU1], (instregex "^CMTSTv")>; 617def : InstRW<[M3WriteNALU1], (instregex "^(AND|BIC|EOR|MVNI|NOT|ORN|ORR)v")>; 618def : InstRW<[M3WriteNMSC1], (instregex "^[SU](MIN|MAX)v")>; 619def : InstRW<[M3WriteNMSC2], (instregex "^[SU](MIN|MAX)Pv")>; 620def : InstRW<[M3WriteNMSC3], (instregex "^[SU](MIN|MAX)Vv")>; 621def : InstRW<[M3WriteNMUL3], (instregex "^(MUL|SQR?DMULH)v")>; 622def : InstRW<[M3WriteNMUL3, 623 M3ReadNMUL], (instregex "^ML[AS]v")>; 624def : InstRW<[M3WriteNMUL3], (instregex "^[SU]ML[AS]Lv")>; 625def : InstRW<[M3WriteNMUL3], (instregex "^SQDML[AS]L")>; 626def : InstRW<[M3WriteNMUL3], (instregex "^(S|U|SQD)MULLv")>; 627def : InstRW<[M3WriteNMSC3], (instregex "^[SU]ADALPv")>; 628def : InstRW<[M3WriteNSHT3], (instregex "^[SU]R?SRAv")>; 629def : InstRW<[M3WriteNSHT1], (instregex "^SHL[dv]")>; 630def : InstRW<[M3WriteNSHT1], (instregex "^[SU]SH[LR][dv]")>; 631def : InstRW<[M3WriteNSHT1], (instregex "^S[RS]I[dv]")>; 632def : InstRW<[M3WriteNSHT2], (instregex "^[SU]?SHLLv")>; 633def : InstRW<[M3WriteNSHT3], (instregex "^(([SU]Q)?R)?SHRU?N[bhsv]")>; 634def : InstRW<[M3WriteNSHT3], (instregex "^[SU]RSH[LR][dv]")>; 635def : InstRW<[M3WriteNSHT3], (instregex "^[SU]QR?SHLU?[bdhsv]")>; 636 637// ASIMD FP instructions. 638def : InstRW<[M3WriteNSHF1], (instregex "^FABSv")>; 639def : InstRW<[M3WriteFADD2], (instregex "^F(ABD|ADD|SUB)v")>; 640def : InstRW<[M3WriteNEONA], (instregex "^FADDP")>; 641def : InstRW<[M3WriteNMSC1], (instregex "^F(AC|CM)(EQ|GE|GT|LE|LT)v[^1]")>; 642def : InstRW<[M3WriteFCVT3], (instregex "^FCVT(L|N|XN)v")>; 643def : InstRW<[M3WriteFCVT2], (instregex "^FCVT[AMNPZ][SU]v")>; 644def : InstRW<[M3WriteFCVT2], (instregex "^[SU]CVTFv")>; 645def : InstRW<[M3WriteFDIV10], (instrs FDIVv2f32)>; 646def : InstRW<[M3WriteNEONV], (instrs FDIVv4f32)>; 647def : InstRW<[M3WriteNEONW], (instrs FDIVv2f64)>; 648def : InstRW<[M3WriteNMSC1], (instregex "^F(MAX|MIN)(NM)?v")>; 649def : InstRW<[M3WriteNMSC2], (instregex "^F(MAX|MIN)(NM)?Pv")>; 650def : InstRW<[M3WriteNEONZ], (instregex "^F(MAX|MIN)(NM)?Vv")>; 651def : InstRW<[M3WriteFMAC3], (instregex "^FMULX?v.[fi]")>; 652def : InstRW<[M3WriteFMAC4, 653 M3ReadFMAC], (instregex "^FML[AS]v.f")>; 654def : InstRW<[M3WriteFMAC5, 655 M3ReadFMAC], (instregex "^FML[AS]v.i")>; 656def : InstRW<[M3WriteNALU1], (instregex "^FNEGv")>; 657def : InstRW<[M3WriteFCVT3A], (instregex "^FRINT[AIMNPXZ]v")>; 658def : InstRW<[M3WriteFSQR17], (instrs FSQRTv2f32)>; 659def : InstRW<[M3WriteNEONX], (instrs FSQRTv4f32)>; 660def : InstRW<[M3WriteNEONY], (instrs FSQRTv2f64)>; 661 662// ASIMD miscellaneous instructions. 663def : InstRW<[M3WriteNALU1], (instregex "^RBITv")>; 664def : InstRW<[M3WriteNALU1], (instregex "^(BIF|BIT|BSL)v")>; 665def : InstRW<[M3WriteNEONB], (instregex "^DUPv.+gpr")>; 666def : InstRW<[M3WriteNSHF1], (instregex "^DUPv.+lane")>; 667def : InstRW<[M3WriteNSHF1], (instregex "^EXTv")>; 668def : InstRW<[M3WriteNSHF1], (instregex "^[SU]?Q?XTU?Nv")>; 669def : InstRW<[M3WriteNSHF1], (instregex "^CPY")>; 670def : InstRW<[M3WriteNSHF1], (instregex "^INSv.+lane")>; 671def : InstRW<[M3WriteMOVI], (instregex "^MOVI")>; 672def : InstRW<[M3WriteNALU1], (instregex "^FMOVv")>; 673def : InstRW<[M3WriteFCVT4], (instregex "^[FU](RECP|RSQRT)Ev[248]")>; 674def : InstRW<[M3WriteFMAC4, 675 M3ReadFMAC], (instregex "^F(RECP|RSQRT)Sv")>; 676def : InstRW<[M3WriteNSHF1], (instregex "^REV(16|32|64)v")>; 677def : InstRW<[M3WriteNSHF1], (instregex "^TB[LX]v")>; 678def : InstRW<[M3WriteNEOND], (instregex "^[SU]MOVv")>; 679def : InstRW<[M3WriteNSHF3], (instregex "^INSv.+gpr")>; 680def : InstRW<[M3WriteNSHF1], (instregex "^(TRN|UZP|ZIP)[12]v")>; 681 682// ASIMD load instructions. 683def : InstRW<[M3WriteL5], (instregex "LD1Onev(8b|4h|2s|1d)$")>; 684def : InstRW<[M3WriteL5, 685 M3WriteA1], (instregex "LD1Onev(8b|4h|2s|1d)_POST")>; 686def : InstRW<[M3WriteL5], (instregex "LD1Onev(16b|8h|4s|2d)$")>; 687def : InstRW<[M3WriteL5, 688 M3WriteA1], (instregex "LD1Onev(16b|8h|4s|2d)_POST")>; 689 690def : InstRW<[M3WriteVLDA], (instregex "LD1Twov(8b|4h|2s|1d)$")>; 691def : InstRW<[M3WriteVLDA, 692 M3WriteA1], (instregex "LD1Twov(8b|4h|2s|1d)_POST")>; 693def : InstRW<[M3WriteVLDA], (instregex "LD1Twov(16b|8h|4s|2d)$")>; 694def : InstRW<[M3WriteVLDA, 695 M3WriteA1], (instregex "LD1Twov(16b|8h|4s|2d)_POST")>; 696 697def : InstRW<[M3WriteVLDB], (instregex "LD1Threev(8b|4h|2s|1d)$")>; 698def : InstRW<[M3WriteVLDB, 699 M3WriteA1], (instregex "LD1Threev(8b|4h|2s|1d)_POST")>; 700def : InstRW<[M3WriteVLDB], (instregex "LD1Threev(16b|8h|4s|2d)$")>; 701def : InstRW<[M3WriteVLDB, 702 M3WriteA1], (instregex "LD1Threev(16b|8h|4s|2d)_POST")>; 703 704def : InstRW<[M3WriteVLDC], (instregex "LD1Fourv(8b|4h|2s|1d)$")>; 705def : InstRW<[M3WriteVLDC, 706 M3WriteA1], (instregex "LD1Fourv(8b|4h|2s|1d)_POST")>; 707def : InstRW<[M3WriteVLDC], (instregex "LD1Fourv(16b|8h|4s|2d)$")>; 708def : InstRW<[M3WriteVLDC, 709 M3WriteA1], (instregex "LD1Fourv(16b|8h|4s|2d)_POST")>; 710 711def : InstRW<[M3WriteVLDD], (instregex "LD1i(8|16|32)$")>; 712def : InstRW<[M3WriteVLDD, 713 M3WriteA1], (instregex "LD1i(8|16|32)_POST")>; 714def : InstRW<[M3WriteVLDE], (instregex "LD1i(64)$")>; 715def : InstRW<[M3WriteVLDE, 716 M3WriteA1], (instregex "LD1i(64)_POST")>; 717 718def : InstRW<[M3WriteL5], (instregex "LD1Rv(8b|4h|2s|1d)$")>; 719def : InstRW<[M3WriteL5, 720 M3WriteA1], (instregex "LD1Rv(8b|4h|2s|1d)_POST")>; 721def : InstRW<[M3WriteL5], (instregex "LD1Rv(16b|8h|4s|2d)$")>; 722def : InstRW<[M3WriteL5, 723 M3WriteA1], (instregex "LD1Rv(16b|8h|4s|2d)_POST")>; 724 725def : InstRW<[M3WriteVLDF], (instregex "LD2Twov(8b|4h|2s)$")>; 726def : InstRW<[M3WriteVLDF, 727 M3WriteA1], (instregex "LD2Twov(8b|4h|2s)_POST")>; 728def : InstRW<[M3WriteVLDF], (instregex "LD2Twov(16b|8h|4s|2d)$")>; 729def : InstRW<[M3WriteVLDF, 730 M3WriteA1], (instregex "LD2Twov(16b|8h|4s|2d)_POST")>; 731 732def : InstRW<[M3WriteVLDG], (instregex "LD2i(8|16|32)$")>; 733def : InstRW<[M3WriteVLDG, 734 M3WriteA1], (instregex "LD2i(8|16|32)_POST")>; 735def : InstRW<[M3WriteVLDH], (instregex "LD2i(64)$")>; 736def : InstRW<[M3WriteVLDH, 737 M3WriteA1], (instregex "LD2i(64)_POST")>; 738 739def : InstRW<[M3WriteVLDA], (instregex "LD2Rv(8b|4h|2s|1d)$")>; 740def : InstRW<[M3WriteVLDA, 741 M3WriteA1], (instregex "LD2Rv(8b|4h|2s|1d)_POST")>; 742def : InstRW<[M3WriteVLDA], (instregex "LD2Rv(16b|8h|4s|2d)$")>; 743def : InstRW<[M3WriteVLDA, 744 M3WriteA1], (instregex "LD2Rv(16b|8h|4s|2d)_POST")>; 745 746def : InstRW<[M3WriteVLDI], (instregex "LD3Threev(8b|4h|2s)$")>; 747def : InstRW<[M3WriteVLDI, 748 M3WriteA1], (instregex "LD3Threev(8b|4h|2s)_POST")>; 749def : InstRW<[M3WriteVLDI], (instregex "LD3Threev(16b|8h|4s|2d)$")>; 750def : InstRW<[M3WriteVLDI, 751 M3WriteA1], (instregex "LD3Threev(16b|8h|4s|2d)_POST")>; 752 753def : InstRW<[M3WriteVLDJ], (instregex "LD3i(8|16|32)$")>; 754def : InstRW<[M3WriteVLDJ, 755 M3WriteA1], (instregex "LD3i(8|16|32)_POST")>; 756def : InstRW<[M3WriteVLDL], (instregex "LD3i(64)$")>; 757def : InstRW<[M3WriteVLDL, 758 M3WriteA1], (instregex "LD3i(64)_POST")>; 759 760def : InstRW<[M3WriteVLDB], (instregex "LD3Rv(8b|4h|2s|1d)$")>; 761def : InstRW<[M3WriteVLDB, 762 M3WriteA1], (instregex "LD3Rv(8b|4h|2s|1d)_POST")>; 763def : InstRW<[M3WriteVLDB], (instregex "LD3Rv(16b|8h|4s|2d)$")>; 764def : InstRW<[M3WriteVLDB, 765 M3WriteA1], (instregex "LD3Rv(16b|8h|4s|2d)_POST")>; 766 767def : InstRW<[M3WriteVLDN], (instregex "LD4Fourv(8b|4h|2s)$")>; 768def : InstRW<[M3WriteVLDN, 769 M3WriteA1], (instregex "LD4Fourv(8b|4h|2s)_POST")>; 770def : InstRW<[M3WriteVLDN], (instregex "LD4Fourv(16b|8h|4s|2d)$")>; 771def : InstRW<[M3WriteVLDN, 772 M3WriteA1], (instregex "LD4Fourv(16b|8h|4s|2d)_POST")>; 773 774def : InstRW<[M3WriteVLDK], (instregex "LD4i(8|16|32)$")>; 775def : InstRW<[M3WriteVLDK, 776 M3WriteA1], (instregex "LD4i(8|16|32)_POST")>; 777def : InstRW<[M3WriteVLDM], (instregex "LD4i(64)$")>; 778def : InstRW<[M3WriteVLDM, 779 M3WriteA1], (instregex "LD4i(64)_POST")>; 780 781def : InstRW<[M3WriteVLDC], (instregex "LD4Rv(8b|4h|2s|1d)$")>; 782def : InstRW<[M3WriteVLDC, 783 M3WriteA1], (instregex "LD4Rv(8b|4h|2s|1d)_POST")>; 784def : InstRW<[M3WriteVLDC], (instregex "LD4Rv(16b|8h|4s|2d)$")>; 785def : InstRW<[M3WriteVLDC, 786 M3WriteA1], (instregex "LD4Rv(16b|8h|4s|2d)_POST")>; 787 788// ASIMD store instructions. 789def : InstRW<[WriteVST], (instregex "ST1Onev(8b|4h|2s|1d)$")>; 790def : InstRW<[WriteVST, 791 WriteAdr], (instregex "ST1Onev(8b|4h|2s|1d)_POST")>; 792def : InstRW<[WriteVST], (instregex "ST1Onev(16b|8h|4s|2d)$")>; 793def : InstRW<[WriteVST, 794 WriteAdr], (instregex "ST1Onev(16b|8h|4s|2d)_POST")>; 795 796def : InstRW<[M3WriteVSTA], (instregex "ST1Twov(8b|4h|2s|1d)$")>; 797def : InstRW<[M3WriteVSTA, 798 WriteAdr], (instregex "ST1Twov(8b|4h|2s|1d)_POST")>; 799def : InstRW<[M3WriteVSTA], (instregex "ST1Twov(16b|8h|4s|2d)$")>; 800def : InstRW<[M3WriteVSTA, 801 WriteAdr], (instregex "ST1Twov(16b|8h|4s|2d)_POST")>; 802 803def : InstRW<[M3WriteVSTB], (instregex "ST1Threev(8b|4h|2s|1d)$")>; 804def : InstRW<[M3WriteVSTB, 805 WriteAdr], (instregex "ST1Threev(8b|4h|2s|1d)_POST")>; 806def : InstRW<[M3WriteVSTB], (instregex "ST1Threev(16b|8h|4s|2d)$")>; 807def : InstRW<[M3WriteVSTB, 808 WriteAdr], (instregex "ST1Threev(16b|8h|4s|2d)_POST")>; 809 810def : InstRW<[M3WriteVSTC], (instregex "ST1Fourv(8b|4h|2s|1d)$")>; 811def : InstRW<[M3WriteVSTC, 812 WriteAdr], (instregex "ST1Fourv(8b|4h|2s|1d)_POST")>; 813def : InstRW<[M3WriteVSTC], (instregex "ST1Fourv(16b|8h|4s|2d)$")>; 814def : InstRW<[M3WriteVSTC, 815 WriteAdr], (instregex "ST1Fourv(16b|8h|4s|2d)_POST")>; 816 817def : InstRW<[M3WriteVSTD], (instregex "ST1i(8|16|32|64)$")>; 818def : InstRW<[M3WriteVSTD, 819 WriteAdr], (instregex "ST1i(8|16|32|64)_POST")>; 820 821def : InstRW<[M3WriteVSTD], (instregex "ST2Twov(8b|4h|2s)$")>; 822def : InstRW<[M3WriteVSTD, 823 WriteAdr], (instregex "ST2Twov(8b|4h|2s)_POST")>; 824def : InstRW<[M3WriteVSTE], (instregex "ST2Twov(16b|8h|4s|2d)$")>; 825def : InstRW<[M3WriteVSTE, 826 WriteAdr], (instregex "ST2Twov(16b|8h|4s|2d)_POST")>; 827 828def : InstRW<[M3WriteVSTD], (instregex "ST2i(8|16|32)$")>; 829def : InstRW<[M3WriteVSTD, 830 WriteAdr], (instregex "ST2i(8|16|32)_POST")>; 831def : InstRW<[M3WriteVSTD], (instregex "ST2i(64)$")>; 832def : InstRW<[M3WriteVSTD, 833 WriteAdr], (instregex "ST2i(64)_POST")>; 834 835def : InstRW<[M3WriteVSTF], (instregex "ST3Threev(8b|4h|2s)$")>; 836def : InstRW<[M3WriteVSTF, 837 WriteAdr], (instregex "ST3Threev(8b|4h|2s)_POST")>; 838def : InstRW<[M3WriteVSTG], (instregex "ST3Threev(16b|8h|4s|2d)$")>; 839def : InstRW<[M3WriteVSTG, 840 WriteAdr], (instregex "ST3Threev(16b|8h|4s|2d)_POST")>; 841 842def : InstRW<[M3WriteVSTH], (instregex "ST3i(8|16|32)$")>; 843def : InstRW<[M3WriteVSTH, 844 WriteAdr], (instregex "ST3i(8|16|32)_POST")>; 845def : InstRW<[M3WriteVSTF], (instregex "ST3i(64)$")>; 846def : InstRW<[M3WriteVSTF, 847 WriteAdr], (instregex "ST3i(64)_POST")>; 848 849def : InstRW<[M3WriteVSTF], (instregex "ST4Fourv(8b|4h|2s)$")>; 850def : InstRW<[M3WriteVSTF, 851 WriteAdr], (instregex "ST4Fourv(8b|4h|2s)_POST")>; 852def : InstRW<[M3WriteVSTI], (instregex "ST4Fourv(16b|8h|4s|2d)$")>; 853def : InstRW<[M3WriteVSTI, 854 WriteAdr], (instregex "ST4Fourv(16b|8h|4s|2d)_POST")>; 855 856def : InstRW<[M3WriteVSTF], (instregex "ST4i(8|16|32|64)$")>; 857def : InstRW<[M3WriteVSTF, 858 WriteAdr], (instregex "ST4i(8|16|32|64)_POST")>; 859 860// Cryptography instructions. 861def : InstRW<[M3WriteAES], (instregex "^AES[DE]")>; 862def : InstRW<[M3WriteAES, 863 M3ReadAES], (instregex "^AESI?MC")>; 864 865def : InstRW<[M3WriteNCRY3A], (instregex "^PMULL?v")>; 866 867def : InstRW<[M3WriteNCRY1A], (instregex "^SHA1([CHMP]|SU[01])")>; 868def : InstRW<[M3WriteNCRY1A], (instregex "^SHA256SU0")>; 869def : InstRW<[M3WriteNCRY5A], (instregex "^SHA256(H2?|SU1)")>; 870 871// CRC instructions. 872def : InstRW<[M3WriteC2], (instregex "^CRC32")>; 873 874} // SchedModel = ExynosM3Model 875