1274955Ssvnmir//=- AArch64SchedA57WriteRes.td - ARM Cortex-A57 Write Res ---*- tablegen -*-=// 2274955Ssvnmir// 3353358Sdim// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4353358Sdim// See https://llvm.org/LICENSE.txt for license information. 5353358Sdim// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6274955Ssvnmir// 7274955Ssvnmir//===----------------------------------------------------------------------===// 8274955Ssvnmir// 9274955Ssvnmir// Contains all of the Cortex-A57 specific SchedWriteRes types. The approach 10274955Ssvnmir// below is to define a generic SchedWriteRes for every combination of 11274955Ssvnmir// latency and microOps. The naming conventions is to use a prefix, one field 12274955Ssvnmir// for latency, and one or more microOp count/type designators. 13274955Ssvnmir// Prefix: A57Write 14274955Ssvnmir// Latency: #cyc 15274955Ssvnmir// MicroOp Count/Types: #(B|I|M|L|S|X|W|V) 16274955Ssvnmir// 17274955Ssvnmir// e.g. A57Write_6cyc_1I_6S_4V means the total latency is 6 and there are 18274955Ssvnmir// 11 micro-ops to be issued down one I pipe, six S pipes and four V pipes. 19274955Ssvnmir// 20274955Ssvnmir//===----------------------------------------------------------------------===// 21274955Ssvnmir 22274955Ssvnmir//===----------------------------------------------------------------------===// 23274955Ssvnmir// Define Generic 1 micro-op types 24274955Ssvnmir 25274955Ssvnmirdef A57Write_5cyc_1L : SchedWriteRes<[A57UnitL]> { let Latency = 5; } 26274955Ssvnmirdef A57Write_5cyc_1M : SchedWriteRes<[A57UnitM]> { let Latency = 5; } 27274955Ssvnmirdef A57Write_5cyc_1V : SchedWriteRes<[A57UnitV]> { let Latency = 5; } 28274955Ssvnmirdef A57Write_5cyc_1W : SchedWriteRes<[A57UnitW]> { let Latency = 5; } 29274955Ssvnmirdef A57Write_10cyc_1V : SchedWriteRes<[A57UnitV]> { let Latency = 10; } 30314564Sdimdef A57Write_17cyc_1W : SchedWriteRes<[A57UnitW]> { let Latency = 17; 31314564Sdim let ResourceCycles = [17]; } 32280031Sdimdef A57Write_19cyc_1M : SchedWriteRes<[A57UnitM]> { let Latency = 19; 33280031Sdim let ResourceCycles = [19]; } 34274955Ssvnmirdef A57Write_1cyc_1B : SchedWriteRes<[A57UnitB]> { let Latency = 1; } 35274955Ssvnmirdef A57Write_1cyc_1I : SchedWriteRes<[A57UnitI]> { let Latency = 1; } 36274955Ssvnmirdef A57Write_1cyc_1S : SchedWriteRes<[A57UnitS]> { let Latency = 1; } 37274955Ssvnmirdef A57Write_2cyc_1M : SchedWriteRes<[A57UnitM]> { let Latency = 2; } 38314564Sdimdef A57Write_32cyc_1W : SchedWriteRes<[A57UnitW]> { let Latency = 32; 39280031Sdim let ResourceCycles = [32]; } 40280031Sdimdef A57Write_35cyc_1M : SchedWriteRes<[A57UnitM]> { let Latency = 35; 41280031Sdim let ResourceCycles = [35]; } 42274955Ssvnmirdef A57Write_3cyc_1M : SchedWriteRes<[A57UnitM]> { let Latency = 3; } 43274955Ssvnmirdef A57Write_3cyc_1V : SchedWriteRes<[A57UnitV]> { let Latency = 3; } 44274955Ssvnmirdef A57Write_3cyc_1W : SchedWriteRes<[A57UnitW]> { let Latency = 3; } 45274955Ssvnmirdef A57Write_3cyc_1X : SchedWriteRes<[A57UnitX]> { let Latency = 3; } 46274955Ssvnmirdef A57Write_4cyc_1L : SchedWriteRes<[A57UnitL]> { let Latency = 4; } 47274955Ssvnmirdef A57Write_4cyc_1X : SchedWriteRes<[A57UnitX]> { let Latency = 4; } 48274955Ssvnmirdef A57Write_9cyc_1V : SchedWriteRes<[A57UnitV]> { let Latency = 9; } 49274955Ssvnmirdef A57Write_6cyc_1M : SchedWriteRes<[A57UnitM]> { let Latency = 6; } 50274955Ssvnmirdef A57Write_6cyc_1V : SchedWriteRes<[A57UnitV]> { let Latency = 6; } 51274955Ssvnmir 52274955Ssvnmir 53274955Ssvnmir//===----------------------------------------------------------------------===// 54274955Ssvnmir// Define Generic 2 micro-op types 55274955Ssvnmir 56314564Sdimdef A57Write_64cyc_2W : SchedWriteRes<[A57UnitW, A57UnitW]> { 57274955Ssvnmir let Latency = 64; 58274955Ssvnmir let NumMicroOps = 2; 59280031Sdim let ResourceCycles = [32, 32]; 60274955Ssvnmir} 61274955Ssvnmirdef A57Write_6cyc_1I_1L : SchedWriteRes<[A57UnitI, 62274955Ssvnmir A57UnitL]> { 63274955Ssvnmir let Latency = 6; 64274955Ssvnmir let NumMicroOps = 2; 65274955Ssvnmir} 66274955Ssvnmirdef A57Write_7cyc_1V_1X : SchedWriteRes<[A57UnitV, 67274955Ssvnmir A57UnitX]> { 68274955Ssvnmir let Latency = 7; 69274955Ssvnmir let NumMicroOps = 2; 70274955Ssvnmir} 71274955Ssvnmirdef A57Write_8cyc_1L_1V : SchedWriteRes<[A57UnitL, 72274955Ssvnmir A57UnitV]> { 73274955Ssvnmir let Latency = 8; 74274955Ssvnmir let NumMicroOps = 2; 75274955Ssvnmir} 76274955Ssvnmirdef A57Write_9cyc_2V : SchedWriteRes<[A57UnitV, A57UnitV]> { 77274955Ssvnmir let Latency = 9; 78274955Ssvnmir let NumMicroOps = 2; 79274955Ssvnmir} 80274955Ssvnmirdef A57Write_8cyc_2X : SchedWriteRes<[A57UnitX, A57UnitX]> { 81274955Ssvnmir let Latency = 8; 82274955Ssvnmir let NumMicroOps = 2; 83274955Ssvnmir} 84274955Ssvnmirdef A57Write_6cyc_2L : SchedWriteRes<[A57UnitL, A57UnitL]> { 85274955Ssvnmir let Latency = 6; 86274955Ssvnmir let NumMicroOps = 2; 87274955Ssvnmir} 88274955Ssvnmirdef A57Write_6cyc_2V : SchedWriteRes<[A57UnitV, A57UnitV]> { 89274955Ssvnmir let Latency = 6; 90274955Ssvnmir let NumMicroOps = 2; 91274955Ssvnmir} 92274955Ssvnmirdef A57Write_6cyc_2W : SchedWriteRes<[A57UnitW, A57UnitW]> { 93274955Ssvnmir let Latency = 6; 94274955Ssvnmir let NumMicroOps = 2; 95274955Ssvnmir} 96274955Ssvnmirdef A57Write_5cyc_1I_1L : SchedWriteRes<[A57UnitI, 97274955Ssvnmir A57UnitL]> { 98274955Ssvnmir let Latency = 5; 99274955Ssvnmir let NumMicroOps = 2; 100274955Ssvnmir} 101274955Ssvnmirdef A57Write_5cyc_2V : SchedWriteRes<[A57UnitV, A57UnitV]> { 102274955Ssvnmir let Latency = 5; 103274955Ssvnmir let NumMicroOps = 2; 104274955Ssvnmir} 105274955Ssvnmirdef A57Write_5cyc_2X : SchedWriteRes<[A57UnitX, A57UnitX]> { 106274955Ssvnmir let Latency = 5; 107274955Ssvnmir let NumMicroOps = 2; 108274955Ssvnmir} 109274955Ssvnmirdef A57Write_10cyc_1L_1V : SchedWriteRes<[A57UnitL, 110274955Ssvnmir A57UnitV]> { 111274955Ssvnmir let Latency = 10; 112274955Ssvnmir let NumMicroOps = 2; 113274955Ssvnmir} 114274955Ssvnmirdef A57Write_10cyc_2V : SchedWriteRes<[A57UnitV, A57UnitV]> { 115274955Ssvnmir let Latency = 10; 116274955Ssvnmir let NumMicroOps = 2; 117274955Ssvnmir} 118274955Ssvnmirdef A57Write_1cyc_1B_1I : SchedWriteRes<[A57UnitB, 119274955Ssvnmir A57UnitI]> { 120274955Ssvnmir let Latency = 1; 121274955Ssvnmir let NumMicroOps = 2; 122274955Ssvnmir} 123274955Ssvnmirdef A57Write_1cyc_1I_1S : SchedWriteRes<[A57UnitI, 124274955Ssvnmir A57UnitS]> { 125274955Ssvnmir let Latency = 1; 126274955Ssvnmir let NumMicroOps = 2; 127274955Ssvnmir} 128274955Ssvnmirdef A57Write_2cyc_1B_1I : SchedWriteRes<[A57UnitB, 129274955Ssvnmir A57UnitI]> { 130274955Ssvnmir let Latency = 2; 131274955Ssvnmir let NumMicroOps = 2; 132274955Ssvnmir} 133274955Ssvnmirdef A57Write_2cyc_2S : SchedWriteRes<[A57UnitS, A57UnitS]> { 134274955Ssvnmir let Latency = 2; 135274955Ssvnmir let NumMicroOps = 2; 136274955Ssvnmir} 137274955Ssvnmirdef A57Write_2cyc_2V : SchedWriteRes<[A57UnitV, A57UnitV]> { 138274955Ssvnmir let Latency = 2; 139274955Ssvnmir let NumMicroOps = 2; 140274955Ssvnmir} 141314564Sdimdef A57Write_34cyc_2W : SchedWriteRes<[A57UnitW, A57UnitW]> { 142314564Sdim let Latency = 34; 143274955Ssvnmir let NumMicroOps = 2; 144314564Sdim let ResourceCycles = [17, 17]; 145274955Ssvnmir} 146274955Ssvnmirdef A57Write_3cyc_1I_1M : SchedWriteRes<[A57UnitI, 147274955Ssvnmir A57UnitM]> { 148274955Ssvnmir let Latency = 3; 149274955Ssvnmir let NumMicroOps = 2; 150274955Ssvnmir} 151274955Ssvnmirdef A57Write_3cyc_1I_1S : SchedWriteRes<[A57UnitI, 152274955Ssvnmir A57UnitS]> { 153274955Ssvnmir let Latency = 3; 154274955Ssvnmir let NumMicroOps = 2; 155274955Ssvnmir} 156274955Ssvnmirdef A57Write_3cyc_1S_1V : SchedWriteRes<[A57UnitS, 157274955Ssvnmir A57UnitV]> { 158274955Ssvnmir let Latency = 3; 159274955Ssvnmir let NumMicroOps = 2; 160274955Ssvnmir} 161280031Sdimdef A57Write_3cyc_2V : SchedWriteRes<[A57UnitV, A57UnitV]> { 162280031Sdim let Latency = 3; 163280031Sdim let NumMicroOps = 2; 164280031Sdim} 165274955Ssvnmirdef A57Write_4cyc_1I_1L : SchedWriteRes<[A57UnitI, 166274955Ssvnmir A57UnitL]> { 167274955Ssvnmir let Latency = 4; 168274955Ssvnmir let NumMicroOps = 2; 169274955Ssvnmir} 170274955Ssvnmirdef A57Write_4cyc_2X : SchedWriteRes<[A57UnitX, A57UnitX]> { 171274955Ssvnmir let Latency = 4; 172274955Ssvnmir let NumMicroOps = 2; 173274955Ssvnmir} 174274955Ssvnmir 175274955Ssvnmir 176274955Ssvnmir//===----------------------------------------------------------------------===// 177274955Ssvnmir// Define Generic 3 micro-op types 178274955Ssvnmir 179274955Ssvnmirdef A57Write_10cyc_3V : SchedWriteRes<[A57UnitV, A57UnitV, A57UnitV]> { 180274955Ssvnmir let Latency = 10; 181274955Ssvnmir let NumMicroOps = 3; 182274955Ssvnmir} 183274955Ssvnmirdef A57Write_2cyc_1I_2S : SchedWriteRes<[A57UnitI, 184274955Ssvnmir A57UnitS, A57UnitS]> { 185274955Ssvnmir let Latency = 2; 186274955Ssvnmir let NumMicroOps = 3; 187274955Ssvnmir} 188274955Ssvnmirdef A57Write_3cyc_1I_1S_1V : SchedWriteRes<[A57UnitI, 189274955Ssvnmir A57UnitS, 190274955Ssvnmir A57UnitV]> { 191274955Ssvnmir let Latency = 3; 192274955Ssvnmir let NumMicroOps = 3; 193274955Ssvnmir} 194274955Ssvnmirdef A57Write_3cyc_1M_2S : SchedWriteRes<[A57UnitM, 195274955Ssvnmir A57UnitS, A57UnitS]> { 196274955Ssvnmir let Latency = 3; 197274955Ssvnmir let NumMicroOps = 3; 198274955Ssvnmir} 199274955Ssvnmirdef A57Write_3cyc_3S : SchedWriteRes<[A57UnitS, A57UnitS, A57UnitS]> { 200274955Ssvnmir let Latency = 3; 201274955Ssvnmir let NumMicroOps = 3; 202274955Ssvnmir} 203274955Ssvnmirdef A57Write_3cyc_2S_1V : SchedWriteRes<[A57UnitS, A57UnitS, 204274955Ssvnmir A57UnitV]> { 205274955Ssvnmir let Latency = 3; 206274955Ssvnmir let NumMicroOps = 3; 207274955Ssvnmir} 208274955Ssvnmirdef A57Write_5cyc_1I_2L : SchedWriteRes<[A57UnitI, 209274955Ssvnmir A57UnitL, A57UnitL]> { 210274955Ssvnmir let Latency = 5; 211274955Ssvnmir let NumMicroOps = 3; 212274955Ssvnmir} 213274955Ssvnmirdef A57Write_6cyc_1I_2L : SchedWriteRes<[A57UnitI, 214274955Ssvnmir A57UnitL, A57UnitL]> { 215274955Ssvnmir let Latency = 6; 216274955Ssvnmir let NumMicroOps = 3; 217274955Ssvnmir} 218274955Ssvnmirdef A57Write_6cyc_3V : SchedWriteRes<[A57UnitV, A57UnitV, A57UnitV]> { 219274955Ssvnmir let Latency = 6; 220274955Ssvnmir let NumMicroOps = 3; 221274955Ssvnmir} 222274955Ssvnmirdef A57Write_7cyc_3L : SchedWriteRes<[A57UnitL, A57UnitL, A57UnitL]> { 223274955Ssvnmir let Latency = 7; 224274955Ssvnmir let NumMicroOps = 3; 225274955Ssvnmir} 226274955Ssvnmirdef A57Write_8cyc_1I_1L_1V : SchedWriteRes<[A57UnitI, 227274955Ssvnmir A57UnitL, 228274955Ssvnmir A57UnitV]> { 229274955Ssvnmir let Latency = 8; 230274955Ssvnmir let NumMicroOps = 3; 231274955Ssvnmir} 232274955Ssvnmirdef A57Write_8cyc_1L_2V : SchedWriteRes<[A57UnitL, 233274955Ssvnmir A57UnitV, A57UnitV]> { 234274955Ssvnmir let Latency = 8; 235274955Ssvnmir let NumMicroOps = 3; 236274955Ssvnmir} 237274955Ssvnmirdef A57Write_8cyc_3V : SchedWriteRes<[A57UnitV, A57UnitV, A57UnitV]> { 238274955Ssvnmir let Latency = 8; 239274955Ssvnmir let NumMicroOps = 3; 240274955Ssvnmir} 241274955Ssvnmirdef A57Write_9cyc_3V : SchedWriteRes<[A57UnitV, A57UnitV, A57UnitV]> { 242274955Ssvnmir let Latency = 9; 243274955Ssvnmir let NumMicroOps = 3; 244274955Ssvnmir} 245274955Ssvnmir 246274955Ssvnmir 247274955Ssvnmir//===----------------------------------------------------------------------===// 248274955Ssvnmir// Define Generic 4 micro-op types 249274955Ssvnmir 250274955Ssvnmirdef A57Write_2cyc_2I_2S : SchedWriteRes<[A57UnitI, A57UnitI, 251274955Ssvnmir A57UnitS, A57UnitS]> { 252274955Ssvnmir let Latency = 2; 253274955Ssvnmir let NumMicroOps = 4; 254274955Ssvnmir} 255274955Ssvnmirdef A57Write_3cyc_2I_2S : SchedWriteRes<[A57UnitI, A57UnitI, 256274955Ssvnmir A57UnitS, A57UnitS]> { 257274955Ssvnmir let Latency = 3; 258274955Ssvnmir let NumMicroOps = 4; 259274955Ssvnmir} 260274955Ssvnmirdef A57Write_3cyc_1I_3S : SchedWriteRes<[A57UnitI, 261274955Ssvnmir A57UnitS, A57UnitS, A57UnitS]> { 262274955Ssvnmir let Latency = 3; 263274955Ssvnmir let NumMicroOps = 4; 264274955Ssvnmir} 265274955Ssvnmirdef A57Write_3cyc_1I_2S_1V : SchedWriteRes<[A57UnitI, 266274955Ssvnmir A57UnitS, A57UnitS, 267274955Ssvnmir A57UnitV]> { 268274955Ssvnmir let Latency = 3; 269274955Ssvnmir let NumMicroOps = 4; 270274955Ssvnmir} 271274955Ssvnmirdef A57Write_4cyc_4S : SchedWriteRes<[A57UnitS, A57UnitS, 272274955Ssvnmir A57UnitS, A57UnitS]> { 273274955Ssvnmir let Latency = 4; 274274955Ssvnmir let NumMicroOps = 4; 275274955Ssvnmir} 276274955Ssvnmirdef A57Write_7cyc_1I_3L : SchedWriteRes<[A57UnitI, 277274955Ssvnmir A57UnitL, A57UnitL, A57UnitL]> { 278274955Ssvnmir let Latency = 7; 279274955Ssvnmir let NumMicroOps = 4; 280274955Ssvnmir} 281274955Ssvnmirdef A57Write_5cyc_2I_2L : SchedWriteRes<[A57UnitI, A57UnitI, 282274955Ssvnmir A57UnitL, A57UnitL]> { 283274955Ssvnmir let Latency = 5; 284274955Ssvnmir let NumMicroOps = 4; 285274955Ssvnmir} 286274955Ssvnmirdef A57Write_8cyc_1I_1L_2V : SchedWriteRes<[A57UnitI, 287274955Ssvnmir A57UnitL, 288274955Ssvnmir A57UnitV, A57UnitV]> { 289274955Ssvnmir let Latency = 8; 290274955Ssvnmir let NumMicroOps = 4; 291274955Ssvnmir} 292274955Ssvnmirdef A57Write_8cyc_4L : SchedWriteRes<[A57UnitL, A57UnitL, 293274955Ssvnmir A57UnitL, A57UnitL]> { 294274955Ssvnmir let Latency = 8; 295274955Ssvnmir let NumMicroOps = 4; 296274955Ssvnmir} 297274955Ssvnmirdef A57Write_9cyc_2L_2V : SchedWriteRes<[A57UnitL, A57UnitL, 298274955Ssvnmir A57UnitV, A57UnitV]> { 299274955Ssvnmir let Latency = 9; 300274955Ssvnmir let NumMicroOps = 4; 301274955Ssvnmir} 302274955Ssvnmirdef A57Write_9cyc_1L_3V : SchedWriteRes<[A57UnitL, 303274955Ssvnmir A57UnitV, A57UnitV, A57UnitV]> { 304274955Ssvnmir let Latency = 9; 305274955Ssvnmir let NumMicroOps = 4; 306274955Ssvnmir} 307280031Sdimdef A57Write_12cyc_4V : SchedWriteRes<[A57UnitV, A57UnitV, 308280031Sdim A57UnitV, A57UnitV]> { 309280031Sdim let Latency = 12; 310280031Sdim let NumMicroOps = 4; 311280031Sdim} 312274955Ssvnmir 313274955Ssvnmir 314274955Ssvnmir//===----------------------------------------------------------------------===// 315274955Ssvnmir// Define Generic 5 micro-op types 316274955Ssvnmir 317274955Ssvnmirdef A57Write_3cyc_3S_2V : SchedWriteRes<[A57UnitS, A57UnitS, A57UnitS, 318274955Ssvnmir A57UnitV, A57UnitV]> { 319274955Ssvnmir let Latency = 3; 320274955Ssvnmir let NumMicroOps = 5; 321274955Ssvnmir} 322274955Ssvnmirdef A57Write_8cyc_1I_4L : SchedWriteRes<[A57UnitI, 323274955Ssvnmir A57UnitL, A57UnitL, 324274955Ssvnmir A57UnitL, A57UnitL]> { 325274955Ssvnmir let Latency = 8; 326274955Ssvnmir let NumMicroOps = 5; 327274955Ssvnmir} 328274955Ssvnmirdef A57Write_4cyc_1I_4S : SchedWriteRes<[A57UnitI, 329274955Ssvnmir A57UnitS, A57UnitS, 330274955Ssvnmir A57UnitS, A57UnitS]> { 331274955Ssvnmir let Latency = 4; 332274955Ssvnmir let NumMicroOps = 5; 333274955Ssvnmir} 334274955Ssvnmirdef A57Write_9cyc_1I_2L_2V : SchedWriteRes<[A57UnitI, 335274955Ssvnmir A57UnitL, A57UnitL, 336274955Ssvnmir A57UnitV, A57UnitV]> { 337274955Ssvnmir let Latency = 9; 338274955Ssvnmir let NumMicroOps = 5; 339274955Ssvnmir} 340274955Ssvnmirdef A57Write_9cyc_1I_1L_3V : SchedWriteRes<[A57UnitI, 341274955Ssvnmir A57UnitL, 342274955Ssvnmir A57UnitV, A57UnitV, A57UnitV]> { 343274955Ssvnmir let Latency = 9; 344274955Ssvnmir let NumMicroOps = 5; 345274955Ssvnmir} 346274955Ssvnmirdef A57Write_9cyc_2L_3V : SchedWriteRes<[A57UnitL, A57UnitL, 347274955Ssvnmir A57UnitV, A57UnitV, A57UnitV]> { 348274955Ssvnmir let Latency = 9; 349274955Ssvnmir let NumMicroOps = 5; 350274955Ssvnmir} 351280031Sdimdef A57Write_9cyc_5V : SchedWriteRes<[A57UnitV, A57UnitV, A57UnitV, 352280031Sdim A57UnitV, A57UnitV]> { 353280031Sdim let Latency = 9; 354280031Sdim let NumMicroOps = 5; 355280031Sdim} 356274955Ssvnmir 357274955Ssvnmir 358274955Ssvnmir//===----------------------------------------------------------------------===// 359274955Ssvnmir// Define Generic 6 micro-op types 360274955Ssvnmir 361274955Ssvnmirdef A57Write_3cyc_1I_3S_2V : SchedWriteRes<[A57UnitI, 362274955Ssvnmir A57UnitS, A57UnitS, A57UnitS, 363274955Ssvnmir A57UnitV, A57UnitV]> { 364274955Ssvnmir let Latency = 3; 365274955Ssvnmir let NumMicroOps = 6; 366274955Ssvnmir} 367274955Ssvnmirdef A57Write_4cyc_2I_4S : SchedWriteRes<[A57UnitI, A57UnitI, 368274955Ssvnmir A57UnitS, A57UnitS, 369274955Ssvnmir A57UnitS, A57UnitS]> { 370274955Ssvnmir let Latency = 4; 371274955Ssvnmir let NumMicroOps = 6; 372274955Ssvnmir} 373274955Ssvnmirdef A57Write_4cyc_4S_2V : SchedWriteRes<[A57UnitS, A57UnitS, 374274955Ssvnmir A57UnitS, A57UnitS, 375274955Ssvnmir A57UnitV, A57UnitV]> { 376274955Ssvnmir let Latency = 4; 377274955Ssvnmir let NumMicroOps = 6; 378274955Ssvnmir} 379274955Ssvnmirdef A57Write_6cyc_6S : SchedWriteRes<[A57UnitS, A57UnitS, A57UnitS, 380274955Ssvnmir A57UnitS, A57UnitS, A57UnitS]> { 381274955Ssvnmir let Latency = 6; 382274955Ssvnmir let NumMicroOps = 6; 383274955Ssvnmir} 384274955Ssvnmirdef A57Write_9cyc_1I_2L_3V : SchedWriteRes<[A57UnitI, 385274955Ssvnmir A57UnitL, A57UnitL, 386274955Ssvnmir A57UnitV, A57UnitV, A57UnitV]> { 387274955Ssvnmir let Latency = 9; 388274955Ssvnmir let NumMicroOps = 6; 389274955Ssvnmir} 390274955Ssvnmirdef A57Write_9cyc_1I_1L_4V : SchedWriteRes<[A57UnitI, 391274955Ssvnmir A57UnitL, 392274955Ssvnmir A57UnitV, A57UnitV, 393274955Ssvnmir A57UnitV, A57UnitV]> { 394274955Ssvnmir let Latency = 9; 395274955Ssvnmir let NumMicroOps = 6; 396274955Ssvnmir} 397274955Ssvnmirdef A57Write_9cyc_2L_4V : SchedWriteRes<[A57UnitL, A57UnitL, 398274955Ssvnmir A57UnitV, A57UnitV, 399274955Ssvnmir A57UnitV, A57UnitV]> { 400274955Ssvnmir let Latency = 9; 401274955Ssvnmir let NumMicroOps = 6; 402274955Ssvnmir} 403274955Ssvnmir 404274955Ssvnmir 405274955Ssvnmir//===----------------------------------------------------------------------===// 406274955Ssvnmir// Define Generic 7 micro-op types 407274955Ssvnmir 408274955Ssvnmirdef A57Write_10cyc_3L_4V : SchedWriteRes<[A57UnitL, A57UnitL, A57UnitL, 409274955Ssvnmir A57UnitV, A57UnitV, 410274955Ssvnmir A57UnitV, A57UnitV]> { 411274955Ssvnmir let Latency = 10; 412274955Ssvnmir let NumMicroOps = 7; 413274955Ssvnmir} 414274955Ssvnmirdef A57Write_4cyc_1I_4S_2V : SchedWriteRes<[A57UnitI, 415274955Ssvnmir A57UnitS, A57UnitS, 416274955Ssvnmir A57UnitS, A57UnitS, 417274955Ssvnmir A57UnitV, A57UnitV]> { 418274955Ssvnmir let Latency = 4; 419274955Ssvnmir let NumMicroOps = 7; 420274955Ssvnmir} 421280031Sdimdef A57Write_6cyc_1I_6S : SchedWriteRes<[A57UnitI, 422274955Ssvnmir A57UnitS, A57UnitS, A57UnitS, 423274955Ssvnmir A57UnitS, A57UnitS, A57UnitS]> { 424274955Ssvnmir let Latency = 6; 425274955Ssvnmir let NumMicroOps = 7; 426274955Ssvnmir} 427274955Ssvnmirdef A57Write_9cyc_1I_2L_4V : SchedWriteRes<[A57UnitI, 428274955Ssvnmir A57UnitL, A57UnitL, 429274955Ssvnmir A57UnitV, A57UnitV, 430274955Ssvnmir A57UnitV, A57UnitV]> { 431274955Ssvnmir let Latency = 9; 432274955Ssvnmir let NumMicroOps = 7; 433274955Ssvnmir} 434280031Sdimdef A57Write_12cyc_7V : SchedWriteRes<[A57UnitV, A57UnitV, A57UnitV, 435280031Sdim A57UnitV, A57UnitV, 436280031Sdim A57UnitV, A57UnitV]> { 437280031Sdim let Latency = 12; 438280031Sdim let NumMicroOps = 7; 439280031Sdim} 440274955Ssvnmir 441274955Ssvnmir 442274955Ssvnmir//===----------------------------------------------------------------------===// 443274955Ssvnmir// Define Generic 8 micro-op types 444274955Ssvnmir 445274955Ssvnmirdef A57Write_10cyc_1I_3L_4V : SchedWriteRes<[A57UnitI, 446274955Ssvnmir A57UnitL, A57UnitL, A57UnitL, 447274955Ssvnmir A57UnitV, A57UnitV, 448274955Ssvnmir A57UnitV, A57UnitV]> { 449274955Ssvnmir let Latency = 10; 450274955Ssvnmir let NumMicroOps = 8; 451274955Ssvnmir} 452274955Ssvnmirdef A57Write_11cyc_4L_4V : SchedWriteRes<[A57UnitL, A57UnitL, 453274955Ssvnmir A57UnitL, A57UnitL, 454274955Ssvnmir A57UnitV, A57UnitV, 455274955Ssvnmir A57UnitV, A57UnitV]> { 456274955Ssvnmir let Latency = 11; 457274955Ssvnmir let NumMicroOps = 8; 458274955Ssvnmir} 459274955Ssvnmirdef A57Write_8cyc_8S : SchedWriteRes<[A57UnitS, A57UnitS, 460274955Ssvnmir A57UnitS, A57UnitS, 461274955Ssvnmir A57UnitS, A57UnitS, 462274955Ssvnmir A57UnitS, A57UnitS]> { 463274955Ssvnmir let Latency = 8; 464274955Ssvnmir let NumMicroOps = 8; 465274955Ssvnmir} 466274955Ssvnmir 467274955Ssvnmir 468274955Ssvnmir//===----------------------------------------------------------------------===// 469274955Ssvnmir// Define Generic 9 micro-op types 470274955Ssvnmir 471280031Sdimdef A57Write_8cyc_1I_8S : SchedWriteRes<[A57UnitI, 472280031Sdim A57UnitS, A57UnitS, 473280031Sdim A57UnitS, A57UnitS, 474280031Sdim A57UnitS, A57UnitS, 475280031Sdim A57UnitS, A57UnitS]> { 476274955Ssvnmir let Latency = 8; 477274955Ssvnmir let NumMicroOps = 9; 478274955Ssvnmir} 479274955Ssvnmirdef A57Write_11cyc_1I_4L_4V : SchedWriteRes<[A57UnitI, 480274955Ssvnmir A57UnitL, A57UnitL, 481274955Ssvnmir A57UnitL, A57UnitL, 482274955Ssvnmir A57UnitV, A57UnitV, 483274955Ssvnmir A57UnitV, A57UnitV]> { 484274955Ssvnmir let Latency = 11; 485274955Ssvnmir let NumMicroOps = 9; 486274955Ssvnmir} 487280031Sdimdef A57Write_15cyc_9V : SchedWriteRes<[A57UnitV, A57UnitV, A57UnitV, 488280031Sdim A57UnitV, A57UnitV, A57UnitV, 489280031Sdim A57UnitV, A57UnitV, A57UnitV]> { 490280031Sdim let Latency = 15; 491280031Sdim let NumMicroOps = 9; 492280031Sdim} 493274955Ssvnmir 494274955Ssvnmir 495274955Ssvnmir//===----------------------------------------------------------------------===// 496274955Ssvnmir// Define Generic 10 micro-op types 497274955Ssvnmir 498274955Ssvnmirdef A57Write_6cyc_6S_4V : SchedWriteRes<[A57UnitS, A57UnitS, A57UnitS, 499274955Ssvnmir A57UnitS, A57UnitS, A57UnitS, 500274955Ssvnmir A57UnitV, A57UnitV, 501274955Ssvnmir A57UnitV, A57UnitV]> { 502274955Ssvnmir let Latency = 6; 503274955Ssvnmir let NumMicroOps = 10; 504274955Ssvnmir} 505274955Ssvnmir 506274955Ssvnmir 507274955Ssvnmir//===----------------------------------------------------------------------===// 508274955Ssvnmir// Define Generic 11 micro-op types 509274955Ssvnmir 510274955Ssvnmirdef A57Write_6cyc_1I_6S_4V : SchedWriteRes<[A57UnitI, 511274955Ssvnmir A57UnitS, A57UnitS, A57UnitS, 512274955Ssvnmir A57UnitS, A57UnitS, A57UnitS, 513274955Ssvnmir A57UnitV, A57UnitV, 514274955Ssvnmir A57UnitV, A57UnitV]> { 515274955Ssvnmir let Latency = 6; 516274955Ssvnmir let NumMicroOps = 11; 517274955Ssvnmir} 518274955Ssvnmir 519274955Ssvnmir 520274955Ssvnmir//===----------------------------------------------------------------------===// 521274955Ssvnmir// Define Generic 12 micro-op types 522274955Ssvnmir 523274955Ssvnmirdef A57Write_8cyc_8S_4V : SchedWriteRes<[A57UnitS, A57UnitS, A57UnitS, A57UnitS, 524274955Ssvnmir A57UnitS, A57UnitS, A57UnitS, A57UnitS, 525274955Ssvnmir A57UnitV, A57UnitV, 526274955Ssvnmir A57UnitV, A57UnitV]> { 527274955Ssvnmir let Latency = 8; 528274955Ssvnmir let NumMicroOps = 12; 529274955Ssvnmir} 530274955Ssvnmir 531274955Ssvnmir//===----------------------------------------------------------------------===// 532274955Ssvnmir// Define Generic 13 micro-op types 533274955Ssvnmir 534274955Ssvnmirdef A57Write_8cyc_1I_8S_4V : SchedWriteRes<[A57UnitI, 535274955Ssvnmir A57UnitS, A57UnitS, A57UnitS, 536274955Ssvnmir A57UnitS, A57UnitS, A57UnitS, 537274955Ssvnmir A57UnitS, A57UnitS, 538274955Ssvnmir A57UnitV, A57UnitV, 539274955Ssvnmir A57UnitV, A57UnitV]> { 540274955Ssvnmir let Latency = 8; 541274955Ssvnmir let NumMicroOps = 13; 542274955Ssvnmir} 543274955Ssvnmir 544