AArch64SchedA57.td revision 363496
1//=- AArch64SchedA57.td - ARM Cortex-A57 Scheduling Defs -----*- tablegen -*-=// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file defines the machine model for ARM Cortex-A57 to support 10// instruction scheduling and other instruction cost heuristics. 11// 12//===----------------------------------------------------------------------===// 13 14//===----------------------------------------------------------------------===// 15// The Cortex-A57 is a traditional superscalar microprocessor with a 16// conservative 3-wide in-order stage for decode and dispatch. Combined with the 17// much wider out-of-order issue stage, this produced a need to carefully 18// schedule micro-ops so that all three decoded each cycle are successfully 19// issued as the reservation station(s) simply don't stay occupied for long. 20// Therefore, IssueWidth is set to the narrower of the two at three, while still 21// modeling the machine as out-of-order. 22 23def CortexA57Model : SchedMachineModel { 24 let IssueWidth = 3; // 3-way decode and dispatch 25 let MicroOpBufferSize = 128; // 128 micro-op re-order buffer 26 let LoadLatency = 4; // Optimistic load latency 27 let MispredictPenalty = 14; // Fetch + Decode/Rename/Dispatch + Branch 28 29 // Enable partial & runtime unrolling. The magic number is chosen based on 30 // experiments and benchmarking data. 31 let LoopMicroOpBufferSize = 16; 32 let CompleteModel = 1; 33 34 list<Predicate> UnsupportedFeatures = !listconcat(SVEUnsupported.F, 35 PAUnsupported.F); 36} 37 38//===----------------------------------------------------------------------===// 39// Define each kind of processor resource and number available on Cortex-A57. 40// Cortex A-57 has 8 pipelines that each has its own 8-entry queue where 41// micro-ops wait for their operands and then issue out-of-order. 42 43def A57UnitB : ProcResource<1>; // Type B micro-ops 44def A57UnitI : ProcResource<2>; // Type I micro-ops 45def A57UnitM : ProcResource<1>; // Type M micro-ops 46def A57UnitL : ProcResource<1>; // Type L micro-ops 47def A57UnitS : ProcResource<1>; // Type S micro-ops 48def A57UnitX : ProcResource<1>; // Type X micro-ops 49def A57UnitW : ProcResource<1>; // Type W micro-ops 50let SchedModel = CortexA57Model in { 51 def A57UnitV : ProcResGroup<[A57UnitX, A57UnitW]>; // Type V micro-ops 52} 53 54let SchedModel = CortexA57Model in { 55 56//===----------------------------------------------------------------------===// 57// Define customized scheduler read/write types specific to the Cortex-A57. 58 59include "AArch64SchedA57WriteRes.td" 60 61//===----------------------------------------------------------------------===// 62// Map the target-defined scheduler read/write resources and latency for 63// Cortex-A57. The Cortex-A57 types are directly associated with resources, so 64// defining the aliases precludes the need for mapping them using WriteRes. The 65// aliases are sufficient for creating a coarse, working model. As the model 66// evolves, InstRWs will be used to override some of these SchedAliases. 67// 68// WARNING: Using SchedAliases is convenient and works well for latency and 69// resource lookup for instructions. However, this creates an entry in 70// AArch64WriteLatencyTable with a WriteResourceID of 0, breaking 71// any SchedReadAdvance since the lookup will fail. 72 73def : SchedAlias<WriteImm, A57Write_1cyc_1I>; 74def : SchedAlias<WriteI, A57Write_1cyc_1I>; 75def : SchedAlias<WriteISReg, A57Write_2cyc_1M>; 76def : SchedAlias<WriteIEReg, A57Write_2cyc_1M>; 77def : SchedAlias<WriteExtr, A57Write_1cyc_1I>; 78def : SchedAlias<WriteIS, A57Write_1cyc_1I>; 79def : SchedAlias<WriteID32, A57Write_19cyc_1M>; 80def : SchedAlias<WriteID64, A57Write_35cyc_1M>; 81def : WriteRes<WriteIM32, [A57UnitM]> { let Latency = 3; } 82def : WriteRes<WriteIM64, [A57UnitM]> { let Latency = 5; } 83def : SchedAlias<WriteBr, A57Write_1cyc_1B>; 84def : SchedAlias<WriteBrReg, A57Write_1cyc_1B>; 85def : SchedAlias<WriteLD, A57Write_4cyc_1L>; 86def : SchedAlias<WriteST, A57Write_1cyc_1S>; 87def : SchedAlias<WriteSTP, A57Write_1cyc_1S>; 88def : SchedAlias<WriteAdr, A57Write_1cyc_1I>; 89def : SchedAlias<WriteLDIdx, A57Write_4cyc_1I_1L>; 90def : SchedAlias<WriteSTIdx, A57Write_1cyc_1I_1S>; 91def : SchedAlias<WriteF, A57Write_3cyc_1V>; 92def : SchedAlias<WriteFCmp, A57Write_3cyc_1V>; 93def : SchedAlias<WriteFCvt, A57Write_5cyc_1V>; 94def : SchedAlias<WriteFCopy, A57Write_5cyc_1L>; 95def : SchedAlias<WriteFImm, A57Write_3cyc_1V>; 96def : SchedAlias<WriteFMul, A57Write_5cyc_1V>; 97def : SchedAlias<WriteFDiv, A57Write_17cyc_1W>; 98def : SchedAlias<WriteV, A57Write_3cyc_1V>; 99def : SchedAlias<WriteVLD, A57Write_5cyc_1L>; 100def : SchedAlias<WriteVST, A57Write_1cyc_1S>; 101 102def : WriteRes<WriteAtomic, []> { let Unsupported = 1; } 103 104def : WriteRes<WriteSys, []> { let Latency = 1; } 105def : WriteRes<WriteBarrier, []> { let Latency = 1; } 106def : WriteRes<WriteHint, []> { let Latency = 1; } 107 108def : WriteRes<WriteLDHi, []> { let Latency = 4; } 109 110// Forwarding logic is only modeled for multiply and accumulate 111def : ReadAdvance<ReadI, 0>; 112def : ReadAdvance<ReadISReg, 0>; 113def : ReadAdvance<ReadIEReg, 0>; 114def : ReadAdvance<ReadIM, 0>; 115def : ReadAdvance<ReadIMA, 2, [WriteIM32, WriteIM64]>; 116def : ReadAdvance<ReadID, 0>; 117def : ReadAdvance<ReadExtrHi, 0>; 118def : ReadAdvance<ReadAdrBase, 0>; 119def : ReadAdvance<ReadVLD, 0>; 120 121 122//===----------------------------------------------------------------------===// 123// Specialize the coarse model by associating instruction groups with the 124// subtarget-defined types. As the modeled is refined, this will override most 125// of the above ShchedAlias mappings. 126 127// Miscellaneous 128// ----------------------------------------------------------------------------- 129 130def : InstRW<[WriteI], (instrs COPY)>; 131 132 133// Branch Instructions 134// ----------------------------------------------------------------------------- 135 136def : InstRW<[A57Write_1cyc_1B_1I], (instrs BL)>; 137def : InstRW<[A57Write_2cyc_1B_1I], (instrs BLR)>; 138 139 140// Shifted Register with Shift == 0 141// ---------------------------------------------------------------------------- 142 143def A57WriteISReg : SchedWriteVariant<[ 144 SchedVar<RegShiftedPred, [WriteISReg]>, 145 SchedVar<NoSchedPred, [WriteI]>]>; 146def : InstRW<[A57WriteISReg], (instregex ".*rs$")>; 147 148 149// Divide and Multiply Instructions 150// ----------------------------------------------------------------------------- 151 152// Multiply high 153def : InstRW<[A57Write_6cyc_1M], (instrs SMULHrr, UMULHrr)>; 154 155 156// Miscellaneous Data-Processing Instructions 157// ----------------------------------------------------------------------------- 158 159def : InstRW<[A57Write_1cyc_1I], (instrs EXTRWrri)>; 160def : InstRW<[A57Write_3cyc_1I_1M], (instrs EXTRXrri)>; 161def : InstRW<[A57Write_2cyc_1M], (instregex "BFM")>; 162 163 164// Cryptography Extensions 165// ----------------------------------------------------------------------------- 166 167def A57ReadAES : SchedReadAdvance<3, [A57Write_3cyc_1W]>; 168def : InstRW<[A57Write_3cyc_1W], (instregex "^AES[DE]")>; 169def : InstRW<[A57Write_3cyc_1W, A57ReadAES], (instregex "^AESI?MC")>; 170def : InstRW<[A57Write_6cyc_2V], (instregex "^SHA1SU0")>; 171def : InstRW<[A57Write_3cyc_1W], (instregex "^SHA1(H|SU1)")>; 172def : InstRW<[A57Write_6cyc_2W], (instregex "^SHA1[CMP]")>; 173def : InstRW<[A57Write_3cyc_1W], (instregex "^SHA256SU0")>; 174def : InstRW<[A57Write_6cyc_2W], (instregex "^SHA256(H|H2|SU1)")>; 175def : InstRW<[A57Write_3cyc_1W], (instregex "^CRC32")>; 176 177 178// Vector Load 179// ----------------------------------------------------------------------------- 180 181def : InstRW<[A57Write_8cyc_1L_1V], (instregex "LD1i(8|16|32)$")>; 182def : InstRW<[A57Write_8cyc_1L_1V, WriteAdr], (instregex "LD1i(8|16|32)_POST$")>; 183def : InstRW<[A57Write_5cyc_1L], (instregex "LD1i(64)$")>; 184def : InstRW<[A57Write_5cyc_1L, WriteAdr], (instregex "LD1i(64)_POST$")>; 185 186def : InstRW<[A57Write_8cyc_1L_1V], (instregex "LD1Rv(8b|4h|2s)$")>; 187def : InstRW<[A57Write_8cyc_1L_1V, WriteAdr], (instregex "LD1Rv(8b|4h|2s)_POST$")>; 188def : InstRW<[A57Write_5cyc_1L], (instregex "LD1Rv(1d)$")>; 189def : InstRW<[A57Write_5cyc_1L, WriteAdr], (instregex "LD1Rv(1d)_POST$")>; 190def : InstRW<[A57Write_8cyc_1L_1V], (instregex "LD1Rv(16b|8h|4s|2d)$")>; 191def : InstRW<[A57Write_8cyc_1L_1V, WriteAdr], (instregex "LD1Rv(16b|8h|4s|2d)_POST$")>; 192 193def : InstRW<[A57Write_5cyc_1L], (instregex "LD1Onev(8b|4h|2s|1d)$")>; 194def : InstRW<[A57Write_5cyc_1L, WriteAdr], (instregex "LD1Onev(8b|4h|2s|1d)_POST$")>; 195def : InstRW<[A57Write_5cyc_1L], (instregex "LD1Onev(16b|8h|4s|2d)$")>; 196def : InstRW<[A57Write_5cyc_1L, WriteAdr], (instregex "LD1Onev(16b|8h|4s|2d)_POST$")>; 197def : InstRW<[A57Write_5cyc_1L], (instregex "LD1Twov(8b|4h|2s|1d)$")>; 198def : InstRW<[A57Write_5cyc_1L, WriteAdr], (instregex "LD1Twov(8b|4h|2s|1d)_POST$")>; 199def : InstRW<[A57Write_6cyc_2L], (instregex "LD1Twov(16b|8h|4s|2d)$")>; 200def : InstRW<[A57Write_6cyc_2L, WriteAdr], (instregex "LD1Twov(16b|8h|4s|2d)_POST$")>; 201def : InstRW<[A57Write_6cyc_2L], (instregex "LD1Threev(8b|4h|2s|1d)$")>; 202def : InstRW<[A57Write_6cyc_2L, WriteAdr], (instregex "LD1Threev(8b|4h|2s|1d)_POST$")>; 203def : InstRW<[A57Write_7cyc_3L], (instregex "LD1Threev(16b|8h|4s|2d)$")>; 204def : InstRW<[A57Write_7cyc_3L, WriteAdr], (instregex "LD1Threev(16b|8h|4s|2d)_POST$")>; 205def : InstRW<[A57Write_6cyc_2L], (instregex "LD1Fourv(8b|4h|2s|1d)$")>; 206def : InstRW<[A57Write_6cyc_2L, WriteAdr], (instregex "LD1Fourv(8b|4h|2s|1d)_POST$")>; 207def : InstRW<[A57Write_8cyc_4L], (instregex "LD1Fourv(16b|8h|4s|2d)$")>; 208def : InstRW<[A57Write_8cyc_4L, WriteAdr], (instregex "LD1Fourv(16b|8h|4s|2d)_POST$")>; 209 210def : InstRW<[A57Write_8cyc_1L_2V], (instregex "LD2i(8|16)$")>; 211def : InstRW<[A57Write_8cyc_1L_2V, WriteAdr], (instregex "LD2i(8|16)_POST$")>; 212def : InstRW<[A57Write_6cyc_2L], (instregex "LD2i(32)$")>; 213def : InstRW<[A57Write_6cyc_2L, WriteAdr], (instregex "LD2i(32)_POST$")>; 214def : InstRW<[A57Write_8cyc_1L_1V], (instregex "LD2i(64)$")>; 215def : InstRW<[A57Write_8cyc_1L_1V, WriteAdr], (instregex "LD2i(64)_POST$")>; 216 217def : InstRW<[A57Write_8cyc_1L_1V], (instregex "LD2Rv(8b|4h|2s)$")>; 218def : InstRW<[A57Write_8cyc_1L_1V, WriteAdr], (instregex "LD2Rv(8b|4h|2s)_POST$")>; 219def : InstRW<[A57Write_5cyc_1L], (instregex "LD2Rv(1d)$")>; 220def : InstRW<[A57Write_5cyc_1L, WriteAdr], (instregex "LD2Rv(1d)_POST$")>; 221def : InstRW<[A57Write_8cyc_1L_2V], (instregex "LD2Rv(16b|8h|4s|2d)$")>; 222def : InstRW<[A57Write_8cyc_1L_2V, WriteAdr], (instregex "LD2Rv(16b|8h|4s|2d)_POST$")>; 223 224def : InstRW<[A57Write_8cyc_1L_1V], (instregex "LD2Twov(8b|4h|2s)$")>; 225def : InstRW<[A57Write_8cyc_1L_1V, WriteAdr], (instregex "LD2Twov(8b|4h|2s)_POST$")>; 226def : InstRW<[A57Write_9cyc_2L_2V], (instregex "LD2Twov(16b|8h|4s)$")>; 227def : InstRW<[A57Write_9cyc_2L_2V, WriteAdr], (instregex "LD2Twov(16b|8h|4s)_POST$")>; 228def : InstRW<[A57Write_6cyc_2L], (instregex "LD2Twov(2d)$")>; 229def : InstRW<[A57Write_6cyc_2L, WriteAdr], (instregex "LD2Twov(2d)_POST$")>; 230 231def : InstRW<[A57Write_9cyc_1L_3V], (instregex "LD3i(8|16)$")>; 232def : InstRW<[A57Write_9cyc_1L_3V, WriteAdr], (instregex "LD3i(8|16)_POST$")>; 233def : InstRW<[A57Write_8cyc_1L_2V], (instregex "LD3i(32)$")>; 234def : InstRW<[A57Write_8cyc_1L_2V, WriteAdr], (instregex "LD3i(32)_POST$")>; 235def : InstRW<[A57Write_6cyc_2L], (instregex "LD3i(64)$")>; 236def : InstRW<[A57Write_6cyc_2L, WriteAdr], (instregex "LD3i(64)_POST$")>; 237 238def : InstRW<[A57Write_8cyc_1L_2V], (instregex "LD3Rv(8b|4h|2s)$")>; 239def : InstRW<[A57Write_8cyc_1L_2V, WriteAdr], (instregex "LD3Rv(8b|4h|2s)_POST$")>; 240def : InstRW<[A57Write_6cyc_2L], (instregex "LD3Rv(1d)$")>; 241def : InstRW<[A57Write_6cyc_2L, WriteAdr], (instregex "LD3Rv(1d)_POST$")>; 242def : InstRW<[A57Write_9cyc_1L_3V], (instregex "LD3Rv(16b|8h|4s)$")>; 243def : InstRW<[A57Write_9cyc_1L_3V, WriteAdr], (instregex "LD3Rv(16b|8h|4s)_POST$")>; 244def : InstRW<[A57Write_9cyc_2L_3V], (instregex "LD3Rv(2d)$")>; 245def : InstRW<[A57Write_9cyc_2L_3V, WriteAdr], (instregex "LD3Rv(2d)_POST$")>; 246 247def : InstRW<[A57Write_9cyc_2L_2V], (instregex "LD3Threev(8b|4h|2s)$")>; 248def : InstRW<[A57Write_9cyc_2L_2V, WriteAdr], (instregex "LD3Threev(8b|4h|2s)_POST$")>; 249def : InstRW<[A57Write_10cyc_3L_4V], (instregex "LD3Threev(16b|8h|4s)$")>; 250def : InstRW<[A57Write_10cyc_3L_4V, WriteAdr], (instregex "LD3Threev(16b|8h|4s)_POST$")>; 251def : InstRW<[A57Write_8cyc_4L], (instregex "LD3Threev(2d)$")>; 252def : InstRW<[A57Write_8cyc_4L, WriteAdr], (instregex "LD3Threev(2d)_POST$")>; 253 254def : InstRW<[A57Write_9cyc_2L_3V], (instregex "LD4i(8|16)$")>; 255def : InstRW<[A57Write_9cyc_2L_3V, WriteAdr], (instregex "LD4i(8|16)_POST$")>; 256def : InstRW<[A57Write_8cyc_1L_2V], (instregex "LD4i(32)$")>; 257def : InstRW<[A57Write_8cyc_1L_2V, WriteAdr], (instregex "LD4i(32)_POST$")>; 258def : InstRW<[A57Write_9cyc_2L_3V], (instregex "LD4i(64)$")>; 259def : InstRW<[A57Write_9cyc_2L_3V, WriteAdr], (instregex "LD4i(64)_POST$")>; 260 261def : InstRW<[A57Write_8cyc_1L_2V], (instregex "LD4Rv(8b|4h|2s)$")>; 262def : InstRW<[A57Write_8cyc_1L_2V, WriteAdr], (instregex "LD4Rv(8b|4h|2s)_POST$")>; 263def : InstRW<[A57Write_6cyc_2L], (instregex "LD4Rv(1d)$")>; 264def : InstRW<[A57Write_6cyc_2L, WriteAdr], (instregex "LD4Rv(1d)_POST$")>; 265def : InstRW<[A57Write_9cyc_2L_3V], (instregex "LD4Rv(16b|8h|4s)$")>; 266def : InstRW<[A57Write_9cyc_2L_3V, WriteAdr], (instregex "LD4Rv(16b|8h|4s)_POST$")>; 267def : InstRW<[A57Write_9cyc_2L_4V], (instregex "LD4Rv(2d)$")>; 268def : InstRW<[A57Write_9cyc_2L_4V, WriteAdr], (instregex "LD4Rv(2d)_POST$")>; 269 270def : InstRW<[A57Write_9cyc_2L_2V], (instregex "LD4Fourv(8b|4h|2s)$")>; 271def : InstRW<[A57Write_9cyc_2L_2V, WriteAdr], (instregex "LD4Fourv(8b|4h|2s)_POST$")>; 272def : InstRW<[A57Write_11cyc_4L_4V], (instregex "LD4Fourv(16b|8h|4s)$")>; 273def : InstRW<[A57Write_11cyc_4L_4V, WriteAdr], (instregex "LD4Fourv(16b|8h|4s)_POST$")>; 274def : InstRW<[A57Write_8cyc_4L], (instregex "LD4Fourv(2d)$")>; 275def : InstRW<[A57Write_8cyc_4L, WriteAdr], (instregex "LD4Fourv(2d)_POST$")>; 276 277// Vector Store 278// ----------------------------------------------------------------------------- 279 280def : InstRW<[A57Write_1cyc_1S], (instregex "ST1i(8|16|32)$")>; 281def : InstRW<[A57Write_1cyc_1S, WriteAdr], (instregex "ST1i(8|16|32)_POST$")>; 282def : InstRW<[A57Write_3cyc_1S_1V], (instregex "ST1i(64)$")>; 283def : InstRW<[A57Write_3cyc_1S_1V, WriteAdr], (instregex "ST1i(64)_POST$")>; 284 285def : InstRW<[A57Write_1cyc_1S], (instregex "ST1Onev(8b|4h|2s|1d)$")>; 286def : InstRW<[A57Write_1cyc_1S, WriteAdr], (instregex "ST1Onev(8b|4h|2s|1d)_POST$")>; 287def : InstRW<[A57Write_2cyc_2S], (instregex "ST1Onev(16b|8h|4s|2d)$")>; 288def : InstRW<[A57Write_2cyc_2S, WriteAdr], (instregex "ST1Onev(16b|8h|4s|2d)_POST$")>; 289def : InstRW<[A57Write_2cyc_2S], (instregex "ST1Twov(8b|4h|2s|1d)$")>; 290def : InstRW<[A57Write_2cyc_2S, WriteAdr], (instregex "ST1Twov(8b|4h|2s|1d)_POST$")>; 291def : InstRW<[A57Write_4cyc_4S], (instregex "ST1Twov(16b|8h|4s|2d)$")>; 292def : InstRW<[A57Write_4cyc_4S, WriteAdr], (instregex "ST1Twov(16b|8h|4s|2d)_POST$")>; 293def : InstRW<[A57Write_3cyc_3S], (instregex "ST1Threev(8b|4h|2s|1d)$")>; 294def : InstRW<[A57Write_3cyc_3S, WriteAdr], (instregex "ST1Threev(8b|4h|2s|1d)_POST$")>; 295def : InstRW<[A57Write_6cyc_6S], (instregex "ST1Threev(16b|8h|4s|2d)$")>; 296def : InstRW<[A57Write_6cyc_6S, WriteAdr], (instregex "ST1Threev(16b|8h|4s|2d)_POST$")>; 297def : InstRW<[A57Write_4cyc_4S], (instregex "ST1Fourv(8b|4h|2s|1d)$")>; 298def : InstRW<[A57Write_4cyc_4S, WriteAdr], (instregex "ST1Fourv(8b|4h|2s|1d)_POST$")>; 299def : InstRW<[A57Write_8cyc_8S], (instregex "ST1Fourv(16b|8h|4s|2d)$")>; 300def : InstRW<[A57Write_8cyc_8S, WriteAdr], (instregex "ST1Fourv(16b|8h|4s|2d)_POST$")>; 301 302def : InstRW<[A57Write_3cyc_1S_1V], (instregex "ST2i(8|16|32)$")>; 303def : InstRW<[A57Write_3cyc_1S_1V, WriteAdr], (instregex "ST2i(8|16|32)_POST$")>; 304def : InstRW<[A57Write_2cyc_2S], (instregex "ST2i(64)$")>; 305def : InstRW<[A57Write_2cyc_2S, WriteAdr], (instregex "ST2i(64)_POST$")>; 306 307def : InstRW<[A57Write_3cyc_2S_1V], (instregex "ST2Twov(8b|4h|2s)$")>; 308def : InstRW<[A57Write_3cyc_2S_1V, WriteAdr], (instregex "ST2Twov(8b|4h|2s)_POST$")>; 309def : InstRW<[A57Write_4cyc_4S_2V], (instregex "ST2Twov(16b|8h|4s)$")>; 310def : InstRW<[A57Write_4cyc_4S_2V, WriteAdr], (instregex "ST2Twov(16b|8h|4s)_POST$")>; 311def : InstRW<[A57Write_4cyc_4S], (instregex "ST2Twov(2d)$")>; 312def : InstRW<[A57Write_4cyc_4S, WriteAdr], (instregex "ST2Twov(2d)_POST$")>; 313 314def : InstRW<[A57Write_3cyc_1S_1V], (instregex "ST3i(8|16)$")>; 315def : InstRW<[A57Write_3cyc_1S_1V, WriteAdr], (instregex "ST3i(8|16)_POST$")>; 316def : InstRW<[A57Write_3cyc_3S], (instregex "ST3i(32)$")>; 317def : InstRW<[A57Write_3cyc_3S, WriteAdr], (instregex "ST3i(32)_POST$")>; 318def : InstRW<[A57Write_3cyc_2S_1V], (instregex "ST3i(64)$")>; 319def : InstRW<[A57Write_3cyc_2S_1V, WriteAdr], (instregex "ST3i(64)_POST$")>; 320 321def : InstRW<[A57Write_3cyc_3S_2V], (instregex "ST3Threev(8b|4h|2s)$")>; 322def : InstRW<[A57Write_3cyc_3S_2V, WriteAdr], (instregex "ST3Threev(8b|4h|2s)_POST$")>; 323def : InstRW<[A57Write_6cyc_6S_4V], (instregex "ST3Threev(16b|8h|4s)$")>; 324def : InstRW<[A57Write_6cyc_6S_4V, WriteAdr], (instregex "ST3Threev(16b|8h|4s)_POST$")>; 325def : InstRW<[A57Write_6cyc_6S], (instregex "ST3Threev(2d)$")>; 326def : InstRW<[A57Write_6cyc_6S, WriteAdr], (instregex "ST3Threev(2d)_POST$")>; 327 328def : InstRW<[A57Write_3cyc_1S_1V], (instregex "ST4i(8|16)$")>; 329def : InstRW<[A57Write_3cyc_1S_1V, WriteAdr], (instregex "ST4i(8|16)_POST$")>; 330def : InstRW<[A57Write_4cyc_4S], (instregex "ST4i(32)$")>; 331def : InstRW<[A57Write_4cyc_4S, WriteAdr], (instregex "ST4i(32)_POST$")>; 332def : InstRW<[A57Write_3cyc_2S_1V], (instregex "ST4i(64)$")>; 333def : InstRW<[A57Write_3cyc_2S_1V, WriteAdr], (instregex "ST4i(64)_POST$")>; 334 335def : InstRW<[A57Write_4cyc_4S_2V], (instregex "ST4Fourv(8b|4h|2s)$")>; 336def : InstRW<[A57Write_4cyc_4S_2V, WriteAdr], (instregex "ST4Fourv(8b|4h|2s)_POST$")>; 337def : InstRW<[A57Write_8cyc_8S_4V], (instregex "ST4Fourv(16b|8h|4s)$")>; 338def : InstRW<[A57Write_8cyc_8S_4V, WriteAdr], (instregex "ST4Fourv(16b|8h|4s)_POST$")>; 339def : InstRW<[A57Write_8cyc_8S], (instregex "ST4Fourv(2d)$")>; 340def : InstRW<[A57Write_8cyc_8S, WriteAdr], (instregex "ST4Fourv(2d)_POST$")>; 341 342// Vector - Integer 343// ----------------------------------------------------------------------------- 344 345// Reference for forms in this group 346// D form - v8i8, v4i16, v2i32 347// Q form - v16i8, v8i16, v4i32 348// D form - v1i8, v1i16, v1i32, v1i64 349// Q form - v16i8, v8i16, v4i32, v2i64 350// D form - v8i8_v8i16, v4i16_v4i32, v2i32_v2i64 351// Q form - v16i8_v8i16, v8i16_v4i32, v4i32_v2i64 352 353// ASIMD absolute diff accum, D-form 354def : InstRW<[A57Write_4cyc_1X], (instregex "^[SU]ABA(v8i8|v4i16|v2i32)$")>; 355// ASIMD absolute diff accum, Q-form 356def : InstRW<[A57Write_5cyc_2X], (instregex "^[SU]ABA(v16i8|v8i16|v4i32)$")>; 357// ASIMD absolute diff accum long 358def : InstRW<[A57Write_4cyc_1X], (instregex "^[SU]ABAL")>; 359 360// ASIMD arith, reduce, 4H/4S 361def : InstRW<[A57Write_4cyc_1X], (instregex "^[SU]?ADDL?V(v8i8|v4i16|v2i32)v$")>; 362// ASIMD arith, reduce, 8B/8H 363def : InstRW<[A57Write_7cyc_1V_1X], (instregex "^[SU]?ADDL?V(v8i16|v4i32)v$")>; 364// ASIMD arith, reduce, 16B 365def : InstRW<[A57Write_8cyc_2X], (instregex "^[SU]?ADDL?Vv16i8v$")>; 366 367// ASIMD max/min, reduce, 4H/4S 368def : InstRW<[A57Write_4cyc_1X], (instregex "^[SU](MIN|MAX)V(v4i16|v4i32)v$")>; 369// ASIMD max/min, reduce, 8B/8H 370def : InstRW<[A57Write_7cyc_1V_1X], (instregex "^[SU](MIN|MAX)V(v8i8|v8i16)v$")>; 371// ASIMD max/min, reduce, 16B 372def : InstRW<[A57Write_8cyc_2X], (instregex "^[SU](MIN|MAX)Vv16i8v$")>; 373 374// ASIMD multiply, D-form 375def : InstRW<[A57Write_5cyc_1W], (instregex "^(P?MUL|SQR?DMULH)(v8i8|v4i16|v2i32|v1i8|v1i16|v1i32|v1i64)(_indexed)?$")>; 376// ASIMD multiply, Q-form 377def : InstRW<[A57Write_6cyc_2W], (instregex "^(P?MUL|SQR?DMULH)(v16i8|v8i16|v4i32)(_indexed)?$")>; 378 379// ASIMD multiply accumulate, D-form 380def : InstRW<[A57Write_5cyc_1W], (instregex "^ML[AS](v8i8|v4i16|v2i32)(_indexed)?$")>; 381// ASIMD multiply accumulate, Q-form 382def : InstRW<[A57Write_6cyc_2W], (instregex "^ML[AS](v16i8|v8i16|v4i32)(_indexed)?$")>; 383 384// ASIMD multiply accumulate long 385// ASIMD multiply accumulate saturating long 386def A57WriteIVMA : SchedWriteRes<[A57UnitW]> { let Latency = 5; } 387def A57ReadIVMA4 : SchedReadAdvance<4, [A57WriteIVMA]>; 388def : InstRW<[A57WriteIVMA, A57ReadIVMA4], (instregex "^(S|U|SQD)ML[AS]L")>; 389 390// ASIMD multiply long 391def : InstRW<[A57Write_5cyc_1W], (instregex "^(S|U|SQD)MULL")>; 392def : InstRW<[A57Write_5cyc_1W], (instregex "^PMULL(v8i8|v16i8)")>; 393def : InstRW<[A57Write_3cyc_1W], (instregex "^PMULL(v1i64|v2i64)")>; 394 395// ASIMD pairwise add and accumulate 396// ASIMD shift accumulate 397def A57WriteIVA : SchedWriteRes<[A57UnitX]> { let Latency = 4; } 398def A57ReadIVA3 : SchedReadAdvance<3, [A57WriteIVA]>; 399def : InstRW<[A57WriteIVA, A57ReadIVA3], (instregex "^[SU]ADALP")>; 400def : InstRW<[A57WriteIVA, A57ReadIVA3], (instregex "^(S|SR|U|UR)SRA")>; 401 402// ASIMD shift by immed, complex 403def : InstRW<[A57Write_4cyc_1X], (instregex "^[SU]?(Q|R){1,2}SHR")>; 404def : InstRW<[A57Write_4cyc_1X], (instregex "^SQSHLU")>; 405 406 407// ASIMD shift by register, basic, Q-form 408def : InstRW<[A57Write_4cyc_2X], (instregex "^[SU]SHL(v16i8|v8i16|v4i32|v2i64)")>; 409 410// ASIMD shift by register, complex, D-form 411def : InstRW<[A57Write_4cyc_1X], (instregex "^[SU][QR]{1,2}SHL(v1i8|v1i16|v1i32|v1i64|v8i8|v4i16|v2i32|b|d|h|s)")>; 412 413// ASIMD shift by register, complex, Q-form 414def : InstRW<[A57Write_5cyc_2X], (instregex "^[SU][QR]{1,2}SHL(v16i8|v8i16|v4i32|v2i64)")>; 415 416 417// Vector - Floating Point 418// ----------------------------------------------------------------------------- 419 420// Reference for forms in this group 421// D form - v2f32 422// Q form - v4f32, v2f64 423// D form - 32, 64 424// D form - v1i32, v1i64 425// D form - v2i32 426// Q form - v4i32, v2i64 427 428// ASIMD FP arith, normal, D-form 429def : InstRW<[A57Write_5cyc_1V], (instregex "^(FABD|FADD|FSUB)(v2f32|32|64|v2i32p)")>; 430// ASIMD FP arith, normal, Q-form 431def : InstRW<[A57Write_5cyc_2V], (instregex "^(FABD|FADD|FSUB)(v4f32|v2f64|v2i64p)")>; 432 433// ASIMD FP arith, pairwise, D-form 434def : InstRW<[A57Write_5cyc_1V], (instregex "^FADDP(v2f32|32|64|v2i32)")>; 435// ASIMD FP arith, pairwise, Q-form 436def : InstRW<[A57Write_9cyc_3V], (instregex "^FADDP(v4f32|v2f64|v2i64)")>; 437 438// ASIMD FP compare, D-form 439def : InstRW<[A57Write_5cyc_1V], (instregex "^(FACGE|FACGT|FCMEQ|FCMGE|FCMGT|FCMLE|FCMLT)(v2f32|32|64|v1i32|v2i32|v1i64)")>; 440// ASIMD FP compare, Q-form 441def : InstRW<[A57Write_5cyc_2V], (instregex "^(FACGE|FACGT|FCMEQ|FCMGE|FCMGT|FCMLE|FCMLT)(v4f32|v2f64|v4i32|v2i64)")>; 442 443// ASIMD FP convert, long and narrow 444def : InstRW<[A57Write_8cyc_3V], (instregex "^FCVT(L|N|XN)v")>; 445// ASIMD FP convert, other, D-form 446def : InstRW<[A57Write_5cyc_1V], (instregex "^[FVSU]CVT([AMNPZ][SU])?(_Int)?(v2f32|v1i32|v2i32|v1i64)")>; 447// ASIMD FP convert, other, Q-form 448def : InstRW<[A57Write_5cyc_2V], (instregex "^[FVSU]CVT([AMNPZ][SU])?(_Int)?(v4f32|v2f64|v4i32|v2i64)")>; 449 450// ASIMD FP divide, D-form, F32 451def : InstRW<[A57Write_17cyc_1W], (instregex "FDIVv2f32")>; 452// ASIMD FP divide, Q-form, F32 453def : InstRW<[A57Write_34cyc_2W], (instregex "FDIVv4f32")>; 454// ASIMD FP divide, Q-form, F64 455def : InstRW<[A57Write_64cyc_2W], (instregex "FDIVv2f64")>; 456 457// Note: These were simply duplicated from ASIMD FDIV because of missing documentation 458// ASIMD FP square root, D-form, F32 459def : InstRW<[A57Write_17cyc_1W], (instregex "FSQRTv2f32")>; 460// ASIMD FP square root, Q-form, F32 461def : InstRW<[A57Write_34cyc_2W], (instregex "FSQRTv4f32")>; 462// ASIMD FP square root, Q-form, F64 463def : InstRW<[A57Write_64cyc_2W], (instregex "FSQRTv2f64")>; 464 465// ASIMD FP max/min, normal, D-form 466def : InstRW<[A57Write_5cyc_1V], (instregex "^(FMAX|FMIN)(NM)?(v2f32)")>; 467// ASIMD FP max/min, normal, Q-form 468def : InstRW<[A57Write_5cyc_2V], (instregex "^(FMAX|FMIN)(NM)?(v4f32|v2f64)")>; 469// ASIMD FP max/min, pairwise, D-form 470def : InstRW<[A57Write_5cyc_1V], (instregex "^(FMAX|FMIN)(NM)?P(v2f32|v2i32)")>; 471// ASIMD FP max/min, pairwise, Q-form 472def : InstRW<[A57Write_9cyc_3V], (instregex "^(FMAX|FMIN)(NM)?P(v4f32|v2f64|v2i64)")>; 473// ASIMD FP max/min, reduce 474def : InstRW<[A57Write_10cyc_3V], (instregex "^(FMAX|FMIN)(NM)?Vv")>; 475 476// ASIMD FP multiply, D-form, FZ 477def : InstRW<[A57Write_5cyc_1V], (instregex "^FMULX?(v2f32|v1i32|v2i32|v1i64|32|64)")>; 478// ASIMD FP multiply, Q-form, FZ 479def : InstRW<[A57Write_5cyc_2V], (instregex "^FMULX?(v4f32|v2f64|v4i32|v2i64)")>; 480 481// ASIMD FP multiply accumulate, D-form, FZ 482// ASIMD FP multiply accumulate, Q-form, FZ 483def A57WriteFPVMAD : SchedWriteRes<[A57UnitV]> { let Latency = 9; } 484def A57WriteFPVMAQ : SchedWriteRes<[A57UnitV, A57UnitV]> { let Latency = 10; } 485def A57ReadFPVMA5 : SchedReadAdvance<5, [A57WriteFPVMAD, A57WriteFPVMAQ]>; 486def : InstRW<[A57WriteFPVMAD, A57ReadFPVMA5], (instregex "^FML[AS](v2f32|v1i32|v2i32|v1i64)")>; 487def : InstRW<[A57WriteFPVMAQ, A57ReadFPVMA5], (instregex "^FML[AS](v4f32|v2f64|v4i32|v2i64)")>; 488 489// ASIMD FP round, D-form 490def : InstRW<[A57Write_5cyc_1V], (instregex "^FRINT[AIMNPXZ](v2f32)")>; 491// ASIMD FP round, Q-form 492def : InstRW<[A57Write_5cyc_2V], (instregex "^FRINT[AIMNPXZ](v4f32|v2f64)")>; 493 494 495// Vector - Miscellaneous 496// ----------------------------------------------------------------------------- 497 498// Reference for forms in this group 499// D form - v8i8, v4i16, v2i32 500// Q form - v16i8, v8i16, v4i32 501// D form - v1i8, v1i16, v1i32, v1i64 502// Q form - v16i8, v8i16, v4i32, v2i64 503 504// ASIMD bitwise insert, Q-form 505def : InstRW<[A57Write_3cyc_2V], (instregex "^(BIF|BIT|BSL)v16i8")>; 506 507// ASIMD duplicate, gen reg, D-form and Q-form 508def : InstRW<[A57Write_8cyc_1L_1V], (instregex "^CPY")>; 509def : InstRW<[A57Write_8cyc_1L_1V], (instregex "^DUPv.+gpr")>; 510 511// ASIMD move, saturating 512def : InstRW<[A57Write_4cyc_1X], (instregex "^[SU]QXTU?N")>; 513 514// ASIMD reciprocal estimate, D-form 515def : InstRW<[A57Write_5cyc_1V], (instregex "^[FU](RECP|RSQRT)(E|X)(v2f32|v1i32|v2i32|v1i64)")>; 516// ASIMD reciprocal estimate, Q-form 517def : InstRW<[A57Write_5cyc_2V], (instregex "^[FU](RECP|RSQRT)(E|X)(v2f64|v4f32|v4i32)")>; 518 519// ASIMD reciprocal step, D-form, FZ 520def : InstRW<[A57Write_9cyc_1V], (instregex "^F(RECP|RSQRT)S(v2f32|v1i32|v2i32|v1i64|32|64)")>; 521// ASIMD reciprocal step, Q-form, FZ 522def : InstRW<[A57Write_9cyc_2V], (instregex "^F(RECP|RSQRT)S(v2f64|v4f32|v4i32)")>; 523 524// ASIMD table lookup, D-form 525def : InstRW<[A57Write_3cyc_1V], (instregex "^TB[LX]v8i8One")>; 526def : InstRW<[A57Write_6cyc_2V], (instregex "^TB[LX]v8i8Two")>; 527def : InstRW<[A57Write_9cyc_3V], (instregex "^TB[LX]v8i8Three")>; 528def : InstRW<[A57Write_12cyc_4V], (instregex "^TB[LX]v8i8Four")>; 529// ASIMD table lookup, Q-form 530def : InstRW<[A57Write_6cyc_3V], (instregex "^TB[LX]v16i8One")>; 531def : InstRW<[A57Write_9cyc_5V], (instregex "^TB[LX]v16i8Two")>; 532def : InstRW<[A57Write_12cyc_7V], (instregex "^TB[LX]v16i8Three")>; 533def : InstRW<[A57Write_15cyc_9V], (instregex "^TB[LX]v16i8Four")>; 534 535// ASIMD transfer, element to gen reg 536def : InstRW<[A57Write_6cyc_1I_1L], (instregex "^[SU]MOVv")>; 537 538// ASIMD transfer, gen reg to element 539def : InstRW<[A57Write_8cyc_1L_1V], (instregex "^INSv")>; 540 541// ASIMD unzip/zip, Q-form 542def : InstRW<[A57Write_6cyc_3V], (instregex "^(UZP|ZIP)(1|2)(v16i8|v8i16|v4i32|v2i64)")>; 543 544 545// Remainder 546// ----------------------------------------------------------------------------- 547 548def : InstRW<[A57Write_5cyc_1V], (instregex "^F(ADD|SUB)[DS]rr")>; 549 550def A57WriteFPMA : SchedWriteRes<[A57UnitV]> { let Latency = 9; } 551def A57ReadFPMA5 : SchedReadAdvance<5, [A57WriteFPMA]>; 552def A57ReadFPM : SchedReadAdvance<0>; 553def : InstRW<[A57WriteFPMA, A57ReadFPM, A57ReadFPM, A57ReadFPMA5], (instregex "^FN?M(ADD|SUB)[DS]rrr")>; 554 555def : InstRW<[A57Write_10cyc_1L_1V], (instregex "^[FSU]CVT[AMNPZ][SU](_Int)?[SU]?[XW]?[DS]?[rds]i?")>; 556def : InstRW<[A57Write_10cyc_1L_1V], (instregex "^[SU]CVTF")>; 557 558def : InstRW<[A57Write_32cyc_1W], (instrs FDIVDrr)>; 559def : InstRW<[A57Write_17cyc_1W], (instrs FDIVSrr)>; 560 561def : InstRW<[A57Write_5cyc_1V], (instregex "^F(MAX|MIN).+rr")>; 562 563def : InstRW<[A57Write_5cyc_1V], (instregex "^FRINT.+r")>; 564 565def : InstRW<[A57Write_32cyc_1W], (instrs FSQRTDr)>; 566def : InstRW<[A57Write_17cyc_1W], (instrs FSQRTSr)>; 567 568def : InstRW<[A57Write_5cyc_1L, WriteLDHi], (instrs LDNPDi)>; 569def : InstRW<[A57Write_6cyc_2L, WriteLDHi], (instrs LDNPQi)>; 570def : InstRW<[A57Write_5cyc_1L, WriteLDHi], (instrs LDNPSi)>; 571def : InstRW<[A57Write_5cyc_1L, WriteLDHi], (instrs LDPDi)>; 572def : InstRW<[A57Write_5cyc_1L, WriteLDHi, WriteAdr], (instrs LDPDpost)>; 573def : InstRW<[A57Write_5cyc_1L, WriteLDHi, WriteAdr], (instrs LDPDpre)>; 574def : InstRW<[A57Write_6cyc_2L, WriteLDHi], (instrs LDPQi)>; 575def : InstRW<[A57Write_6cyc_2L, WriteLDHi, WriteAdr], (instrs LDPQpost)>; 576def : InstRW<[A57Write_6cyc_2L, WriteLDHi, WriteAdr], (instrs LDPQpre)>; 577def : InstRW<[A57Write_5cyc_1I_2L, WriteLDHi], (instrs LDPSWi)>; 578def : InstRW<[A57Write_5cyc_1I_2L, WriteLDHi, WriteAdr], (instrs LDPSWpost)>; 579def : InstRW<[A57Write_5cyc_1I_2L, WriteLDHi, WriteAdr], (instrs LDPSWpre)>; 580def : InstRW<[A57Write_5cyc_1L, WriteLDHi], (instrs LDPSi)>; 581def : InstRW<[A57Write_5cyc_1L, WriteLDHi, WriteAdr], (instrs LDPSpost)>; 582def : InstRW<[A57Write_5cyc_1L, WriteLDHi, WriteAdr], (instrs LDPSpre)>; 583def : InstRW<[A57Write_5cyc_1L, WriteI], (instrs LDRBpost)>; 584def : InstRW<[A57Write_5cyc_1L, WriteAdr], (instrs LDRBpre)>; 585def : InstRW<[A57Write_5cyc_1L, ReadAdrBase], (instrs LDRBroW)>; 586def : InstRW<[A57Write_5cyc_1L, ReadAdrBase], (instrs LDRBroX)>; 587def : InstRW<[A57Write_5cyc_1L], (instrs LDRBui)>; 588def : InstRW<[A57Write_5cyc_1L], (instrs LDRDl)>; 589def : InstRW<[A57Write_5cyc_1L, WriteI], (instrs LDRDpost)>; 590def : InstRW<[A57Write_5cyc_1L, WriteAdr], (instrs LDRDpre)>; 591def : InstRW<[A57Write_5cyc_1L, ReadAdrBase], (instrs LDRDroW)>; 592def : InstRW<[A57Write_5cyc_1L, ReadAdrBase], (instrs LDRDroX)>; 593def : InstRW<[A57Write_5cyc_1L], (instrs LDRDui)>; 594def : InstRW<[A57Write_5cyc_1I_1L, ReadAdrBase], (instrs LDRHHroW)>; 595def : InstRW<[A57Write_5cyc_1I_1L, ReadAdrBase], (instrs LDRHHroX)>; 596def : InstRW<[A57Write_5cyc_1L, WriteI], (instrs LDRHpost)>; 597def : InstRW<[A57Write_5cyc_1L, WriteAdr], (instrs LDRHpre)>; 598def : InstRW<[A57Write_6cyc_1I_1L, ReadAdrBase], (instrs LDRHroW)>; 599def : InstRW<[A57Write_6cyc_1I_1L, ReadAdrBase], (instrs LDRHroX)>; 600def : InstRW<[A57Write_5cyc_1L], (instrs LDRHui)>; 601def : InstRW<[A57Write_5cyc_1L], (instrs LDRQl)>; 602def : InstRW<[A57Write_5cyc_1L, WriteI], (instrs LDRQpost)>; 603def : InstRW<[A57Write_5cyc_1L, WriteAdr], (instrs LDRQpre)>; 604def : InstRW<[A57Write_6cyc_1I_1L, ReadAdrBase], (instrs LDRQroW)>; 605def : InstRW<[A57Write_6cyc_1I_1L, ReadAdrBase], (instrs LDRQroX)>; 606def : InstRW<[A57Write_5cyc_1L], (instrs LDRQui)>; 607def : InstRW<[A57Write_5cyc_1I_1L, ReadAdrBase], (instrs LDRSHWroW)>; 608def : InstRW<[A57Write_5cyc_1I_1L, ReadAdrBase], (instrs LDRSHWroX)>; 609def : InstRW<[A57Write_5cyc_1I_1L, ReadAdrBase], (instrs LDRSHXroW)>; 610def : InstRW<[A57Write_5cyc_1I_1L, ReadAdrBase], (instrs LDRSHXroX)>; 611def : InstRW<[A57Write_5cyc_1L], (instrs LDRSl)>; 612def : InstRW<[A57Write_5cyc_1L, WriteI], (instrs LDRSpost)>; 613def : InstRW<[A57Write_5cyc_1L, WriteAdr], (instrs LDRSpre)>; 614def : InstRW<[A57Write_5cyc_1L, ReadAdrBase], (instrs LDRSroW)>; 615def : InstRW<[A57Write_5cyc_1L, ReadAdrBase], (instrs LDRSroX)>; 616def : InstRW<[A57Write_5cyc_1L], (instrs LDRSui)>; 617def : InstRW<[A57Write_5cyc_1L], (instrs LDURBi)>; 618def : InstRW<[A57Write_5cyc_1L], (instrs LDURDi)>; 619def : InstRW<[A57Write_5cyc_1L], (instrs LDURHi)>; 620def : InstRW<[A57Write_5cyc_1L], (instrs LDURQi)>; 621def : InstRW<[A57Write_5cyc_1L], (instrs LDURSi)>; 622 623def : InstRW<[A57Write_2cyc_2S], (instrs STNPDi)>; 624def : InstRW<[A57Write_4cyc_1I_4S], (instrs STNPQi)>; 625def : InstRW<[A57Write_2cyc_2S], (instrs STNPXi)>; 626def : InstRW<[A57Write_2cyc_2S], (instrs STPDi)>; 627def : InstRW<[WriteAdr, A57Write_2cyc_1I_2S], (instrs STPDpost)>; 628def : InstRW<[WriteAdr, A57Write_2cyc_1I_2S], (instrs STPDpre)>; 629def : InstRW<[A57Write_4cyc_1I_4S], (instrs STPQi)>; 630def : InstRW<[WriteAdr, A57Write_4cyc_1I_4S], (instrs STPQpost)>; 631def : InstRW<[WriteAdr, A57Write_4cyc_2I_4S], (instrs STPQpre)>; 632def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S], (instrs STPSpost)>; 633def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S], (instrs STPSpre)>; 634def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S], (instrs STPWpost)>; 635def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S], (instrs STPWpre)>; 636def : InstRW<[A57Write_2cyc_2S], (instrs STPXi)>; 637def : InstRW<[WriteAdr, A57Write_2cyc_1I_2S], (instrs STPXpost)>; 638def : InstRW<[WriteAdr, A57Write_2cyc_1I_2S], (instrs STPXpre)>; 639def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S, ReadAdrBase], (instrs STRBBpost)>; 640def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S, ReadAdrBase], (instrs STRBBpre)>; 641def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S, ReadAdrBase], (instrs STRBpost)>; 642def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S], (instrs STRBpre)>; 643def : InstRW<[A57Write_3cyc_1I_1S, ReadAdrBase], (instrs STRBroW)>; 644def : InstRW<[A57Write_3cyc_1I_1S, ReadAdrBase], (instrs STRBroX)>; 645def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S, ReadAdrBase], (instrs STRDpost)>; 646def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S], (instrs STRDpre)>; 647def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S, ReadAdrBase], (instrs STRHHpost)>; 648def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S, ReadAdrBase], (instrs STRHHpre)>; 649def : InstRW<[A57Write_3cyc_1I_1S, ReadAdrBase], (instrs STRHHroW)>; 650def : InstRW<[A57Write_3cyc_1I_1S, ReadAdrBase], (instrs STRHHroX)>; 651def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S, ReadAdrBase], (instrs STRHpost)>; 652def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S], (instrs STRHpre)>; 653def : InstRW<[A57Write_3cyc_1I_1S, ReadAdrBase], (instrs STRHroW)>; 654def : InstRW<[A57Write_3cyc_1I_1S, ReadAdrBase], (instrs STRHroX)>; 655def : InstRW<[WriteAdr, A57Write_2cyc_1I_2S, ReadAdrBase], (instrs STRQpost)>; 656def : InstRW<[WriteAdr, A57Write_2cyc_1I_2S], (instrs STRQpre)>; 657def : InstRW<[A57Write_2cyc_1I_2S, ReadAdrBase], (instrs STRQroW)>; 658def : InstRW<[A57Write_2cyc_1I_2S, ReadAdrBase], (instrs STRQroX)>; 659def : InstRW<[A57Write_2cyc_1I_2S], (instrs STRQui)>; 660def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S, ReadAdrBase], (instrs STRSpost)>; 661def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S], (instrs STRSpre)>; 662def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S, ReadAdrBase], (instrs STRWpost)>; 663def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S, ReadAdrBase], (instrs STRWpre)>; 664def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S, ReadAdrBase], (instrs STRXpost)>; 665def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S, ReadAdrBase], (instrs STRXpre)>; 666def : InstRW<[A57Write_2cyc_2S], (instrs STURQi)>; 667 668} // SchedModel = CortexA57Model 669