AArch64SchedA53.td revision 363496 
1//==- AArch64SchedA53.td - Cortex-A53 Scheduling Definitions -*- tablegen -*-=//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file defines the itinerary class data for the ARM Cortex A53 processors.
10//
11//===----------------------------------------------------------------------===//
12
13// ===---------------------------------------------------------------------===//
14// The following definitions describe the simpler per-operand machine model.
15// This works with MachineScheduler. See MCSchedule.h for details.
16
17// Cortex-A53 machine model for scheduling and other instruction cost heuristics.
18def CortexA53Model : SchedMachineModel {
19  let MicroOpBufferSize = 0; // Explicitly set to zero since A53 is in-order.
20  let IssueWidth = 2;        // 2 micro-ops are dispatched per cycle.
21  let LoadLatency = 3;       // Optimistic load latency assuming bypass.
22                             // This is overriden by OperandCycles if the
23                             // Itineraries are queried instead.
24  let MispredictPenalty = 9; // Based on "Cortex-A53 Software Optimisation
25                             // Specification - Instruction Timings"
26                             // v 1.0 Spreadsheet
27  let CompleteModel = 1;
28
29  list<Predicate> UnsupportedFeatures = !listconcat(SVEUnsupported.F,
30                                                    PAUnsupported.F);
31}
32
33
34//===----------------------------------------------------------------------===//
35// Define each kind of processor resource and number available.
36
37// Modeling each pipeline as a ProcResource using the BufferSize = 0 since
38// Cortex-A53 is in-order.
39
40def A53UnitALU    : ProcResource<2> { let BufferSize = 0; } // Int ALU
41def A53UnitMAC    : ProcResource<1> { let BufferSize = 0; } // Int MAC
42def A53UnitDiv    : ProcResource<1> { let BufferSize = 0; } // Int Division
43def A53UnitLdSt   : ProcResource<1> { let BufferSize = 0; } // Load/Store
44def A53UnitB      : ProcResource<1> { let BufferSize = 0; } // Branch
45def A53UnitFPALU  : ProcResource<1> { let BufferSize = 0; } // FP ALU
46def A53UnitFPMDS  : ProcResource<1> { let BufferSize = 0; } // FP Mult/Div/Sqrt
47
48
49//===----------------------------------------------------------------------===//
50// Subtarget-specific SchedWrite types which both map the ProcResources and
51// set the latency.
52
53let SchedModel = CortexA53Model in {
54
55// ALU - Despite having a full latency of 4, most of the ALU instructions can
56//       forward a cycle earlier and then two cycles earlier in the case of a
57//       shift-only instruction. These latencies will be incorrect when the
58//       result cannot be forwarded, but modeling isn't rocket surgery.
59def : WriteRes<WriteImm, [A53UnitALU]> { let Latency = 3; }
60def : WriteRes<WriteI, [A53UnitALU]> { let Latency = 3; }
61def : WriteRes<WriteISReg, [A53UnitALU]> { let Latency = 3; }
62def : WriteRes<WriteIEReg, [A53UnitALU]> { let Latency = 3; }
63def : WriteRes<WriteIS, [A53UnitALU]> { let Latency = 2; }
64def : WriteRes<WriteExtr, [A53UnitALU]> { let Latency = 3; }
65
66// MAC
67def : WriteRes<WriteIM32, [A53UnitMAC]> { let Latency = 4; }
68def : WriteRes<WriteIM64, [A53UnitMAC]> { let Latency = 4; }
69
70// Div
71def : WriteRes<WriteID32, [A53UnitDiv]> { let Latency = 4; }
72def : WriteRes<WriteID64, [A53UnitDiv]> { let Latency = 4; }
73
74// Load
75def : WriteRes<WriteLD, [A53UnitLdSt]> { let Latency = 4; }
76def : WriteRes<WriteLDIdx, [A53UnitLdSt]> { let Latency = 4; }
77def : WriteRes<WriteLDHi, [A53UnitLdSt]> { let Latency = 4; }
78
79// Vector Load - Vector loads take 1-5 cycles to issue. For the WriteVecLd
80//               below, choosing the median of 3 which makes the latency 6.
81//               May model this more carefully in the future. The remaining
82//               A53WriteVLD# types represent the 1-5 cycle issues explicitly.
83def : WriteRes<WriteVLD, [A53UnitLdSt]> { let Latency = 6;
84                                          let ResourceCycles = [3]; }
85def A53WriteVLD1 : SchedWriteRes<[A53UnitLdSt]> { let Latency = 4; }
86def A53WriteVLD2 : SchedWriteRes<[A53UnitLdSt]> { let Latency = 5;
87                                                  let ResourceCycles = [2]; }
88def A53WriteVLD3 : SchedWriteRes<[A53UnitLdSt]> { let Latency = 6;
89                                                  let ResourceCycles = [3]; }
90def A53WriteVLD4 : SchedWriteRes<[A53UnitLdSt]> { let Latency = 7;
91                                                  let ResourceCycles = [4]; }
92def A53WriteVLD5 : SchedWriteRes<[A53UnitLdSt]> { let Latency = 8;
93                                                  let ResourceCycles = [5]; }
94
95// Pre/Post Indexing - Performed as part of address generation which is already
96//                     accounted for in the WriteST* latencies below
97def : WriteRes<WriteAdr, []> { let Latency = 0; }
98
99// Store
100def : WriteRes<WriteST, [A53UnitLdSt]> { let Latency = 4; }
101def : WriteRes<WriteSTP, [A53UnitLdSt]> { let Latency = 4; }
102def : WriteRes<WriteSTIdx, [A53UnitLdSt]> { let Latency = 4; }
103def : WriteRes<WriteSTX, [A53UnitLdSt]> { let Latency = 4; }
104
105// Vector Store - Similar to vector loads, can take 1-3 cycles to issue.
106def : WriteRes<WriteVST, [A53UnitLdSt]> { let Latency = 5;
107                                          let ResourceCycles = [2];}
108def A53WriteVST1 : SchedWriteRes<[A53UnitLdSt]> { let Latency = 4; }
109def A53WriteVST2 : SchedWriteRes<[A53UnitLdSt]> { let Latency = 5;
110                                                  let ResourceCycles = [2]; }
111def A53WriteVST3 : SchedWriteRes<[A53UnitLdSt]> { let Latency = 6;
112                                                  let ResourceCycles = [3]; }
113
114def : WriteRes<WriteAtomic, []> { let Unsupported = 1; }
115
116// Branch
117def : WriteRes<WriteBr, [A53UnitB]>;
118def : WriteRes<WriteBrReg, [A53UnitB]>;
119def : WriteRes<WriteSys, [A53UnitB]>;
120def : WriteRes<WriteBarrier, [A53UnitB]>;
121def : WriteRes<WriteHint, [A53UnitB]>;
122
123// FP ALU
124def : WriteRes<WriteF, [A53UnitFPALU]> { let Latency = 6; }
125def : WriteRes<WriteFCmp, [A53UnitFPALU]> { let Latency = 6; }
126def : WriteRes<WriteFCvt, [A53UnitFPALU]> { let Latency = 6; }
127def : WriteRes<WriteFCopy, [A53UnitFPALU]> { let Latency = 6; }
128def : WriteRes<WriteFImm, [A53UnitFPALU]> { let Latency = 6; }
129def : WriteRes<WriteV, [A53UnitFPALU]> { let Latency = 6; }
130
131// FP Mul, Div, Sqrt
132def : WriteRes<WriteFMul, [A53UnitFPMDS]> { let Latency = 6; }
133def : WriteRes<WriteFDiv, [A53UnitFPMDS]> { let Latency = 33;
134                                            let ResourceCycles = [29]; }
135def A53WriteFMAC : SchedWriteRes<[A53UnitFPMDS]> { let Latency = 10; }
136def A53WriteFDivSP : SchedWriteRes<[A53UnitFPMDS]> { let Latency = 18;
137                                                     let ResourceCycles = [14]; }
138def A53WriteFDivDP : SchedWriteRes<[A53UnitFPMDS]> { let Latency = 33;
139                                                     let ResourceCycles = [29]; }
140def A53WriteFSqrtSP : SchedWriteRes<[A53UnitFPMDS]> { let Latency = 17;
141                                                      let ResourceCycles = [13]; }
142def A53WriteFSqrtDP : SchedWriteRes<[A53UnitFPMDS]> { let Latency = 32;
143                                                      let ResourceCycles = [28]; }
144
145//===----------------------------------------------------------------------===//
146// Subtarget-specific SchedRead types.
147
148// No forwarding for these reads.
149def : ReadAdvance<ReadExtrHi, 0>;
150def : ReadAdvance<ReadAdrBase, 0>;
151def : ReadAdvance<ReadVLD, 0>;
152
153// ALU - Most operands in the ALU pipes are not needed for two cycles. Shiftable
154//       operands are needed one cycle later if and only if they are to be
155//       shifted. Otherwise, they too are needed two cycles later. This same
156//       ReadAdvance applies to Extended registers as well, even though there is
157//       a separate SchedPredicate for them.
158def : ReadAdvance<ReadI, 2, [WriteImm,WriteI,
159                             WriteISReg, WriteIEReg,WriteIS,
160                             WriteID32,WriteID64,
161                             WriteIM32,WriteIM64]>;
162def A53ReadShifted : SchedReadAdvance<1, [WriteImm,WriteI,
163                                          WriteISReg, WriteIEReg,WriteIS,
164                                          WriteID32,WriteID64,
165                                          WriteIM32,WriteIM64]>;
166def A53ReadNotShifted : SchedReadAdvance<2, [WriteImm,WriteI,
167                                             WriteISReg, WriteIEReg,WriteIS,
168                                             WriteID32,WriteID64,
169                                             WriteIM32,WriteIM64]>;
170def A53ReadISReg : SchedReadVariant<[
171	SchedVar<RegShiftedPred, [A53ReadShifted]>,
172	SchedVar<NoSchedPred, [A53ReadNotShifted]>]>;
173def : SchedAlias<ReadISReg, A53ReadISReg>;
174
175def A53ReadIEReg : SchedReadVariant<[
176	SchedVar<RegExtendedPred, [A53ReadShifted]>,
177	SchedVar<NoSchedPred, [A53ReadNotShifted]>]>;
178def : SchedAlias<ReadIEReg, A53ReadIEReg>;
179
180// MAC - Operands are generally needed one cycle later in the MAC pipe.
181//       Accumulator operands are needed two cycles later.
182def : ReadAdvance<ReadIM, 1, [WriteImm,WriteI,
183                              WriteISReg, WriteIEReg,WriteIS,
184                              WriteID32,WriteID64,
185                              WriteIM32,WriteIM64]>;
186def : ReadAdvance<ReadIMA, 2, [WriteImm,WriteI,
187                               WriteISReg, WriteIEReg,WriteIS,
188                               WriteID32,WriteID64,
189                               WriteIM32,WriteIM64]>;
190
191// Div
192def : ReadAdvance<ReadID, 1, [WriteImm,WriteI,
193                              WriteISReg, WriteIEReg,WriteIS,
194                              WriteID32,WriteID64,
195                              WriteIM32,WriteIM64]>;
196
197//===----------------------------------------------------------------------===//
198// Subtarget-specific InstRWs.
199
200//---
201// Miscellaneous
202//---
203def : InstRW<[WriteI], (instrs COPY)>;
204
205//---
206// Vector Loads
207//---
208def : InstRW<[A53WriteVLD1], (instregex "LD1i(8|16|32|64)$")>;
209def : InstRW<[A53WriteVLD1], (instregex "LD1Rv(8b|4h|2s|1d|16b|8h|4s|2d)$")>;
210def : InstRW<[A53WriteVLD1], (instregex "LD1Onev(8b|4h|2s|1d|16b|8h|4s|2d)$")>;
211def : InstRW<[A53WriteVLD2], (instregex "LD1Twov(8b|4h|2s|1d|16b|8h|4s|2d)$")>;
212def : InstRW<[A53WriteVLD3], (instregex "LD1Threev(8b|4h|2s|1d|16b|8h|4s|2d)$")>;
213def : InstRW<[A53WriteVLD4], (instregex "LD1Fourv(8b|4h|2s|1d|16b|8h|4s|2d)$")>;
214def : InstRW<[A53WriteVLD1, WriteAdr], (instregex "LD1i(8|16|32|64)_POST$")>;
215def : InstRW<[A53WriteVLD1, WriteAdr], (instregex "LD1Rv(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;
216def : InstRW<[A53WriteVLD1, WriteAdr], (instregex "LD1Onev(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;
217def : InstRW<[A53WriteVLD2, WriteAdr], (instregex "LD1Twov(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;
218def : InstRW<[A53WriteVLD3, WriteAdr], (instregex "LD1Threev(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;
219def : InstRW<[A53WriteVLD4, WriteAdr], (instregex "LD1Fourv(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;
220
221def : InstRW<[A53WriteVLD1], (instregex "LD2i(8|16|32|64)$")>;
222def : InstRW<[A53WriteVLD1], (instregex "LD2Rv(8b|4h|2s|1d|16b|8h|4s|2d)$")>;
223def : InstRW<[A53WriteVLD2], (instregex "LD2Twov(8b|4h|2s)$")>;
224def : InstRW<[A53WriteVLD4], (instregex "LD2Twov(16b|8h|4s|2d)$")>;
225def : InstRW<[A53WriteVLD1, WriteAdr], (instregex "LD2i(8|16|32|64)_POST$")>;
226def : InstRW<[A53WriteVLD1, WriteAdr], (instregex "LD2Rv(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;
227def : InstRW<[A53WriteVLD2, WriteAdr], (instregex "LD2Twov(8b|4h|2s)_POST$")>;
228def : InstRW<[A53WriteVLD4, WriteAdr], (instregex "LD2Twov(16b|8h|4s|2d)_POST$")>;
229
230def : InstRW<[A53WriteVLD2], (instregex "LD3i(8|16|32|64)$")>;
231def : InstRW<[A53WriteVLD2], (instregex "LD3Rv(8b|4h|2s|1d|16b|8h|4s|2d)$")>;
232def : InstRW<[A53WriteVLD4], (instregex "LD3Threev(8b|4h|2s|1d|16b|8h|4s)$")>;
233def : InstRW<[A53WriteVLD3], (instregex "LD3Threev2d$")>;
234def : InstRW<[A53WriteVLD2, WriteAdr], (instregex "LD3i(8|16|32|64)_POST$")>;
235def : InstRW<[A53WriteVLD2, WriteAdr], (instregex "LD3Rv(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;
236def : InstRW<[A53WriteVLD4, WriteAdr], (instregex "LD3Threev(8b|4h|2s|1d|16b|8h|4s)_POST$")>;
237def : InstRW<[A53WriteVLD3, WriteAdr], (instregex "LD3Threev2d_POST$")>;
238
239def : InstRW<[A53WriteVLD2], (instregex "LD4i(8|16|32|64)$")>;
240def : InstRW<[A53WriteVLD2], (instregex "LD4Rv(8b|4h|2s|1d|16b|8h|4s|2d)$")>;
241def : InstRW<[A53WriteVLD5], (instregex "LD4Fourv(8b|4h|2s|1d|16b|8h|4s)$")>;
242def : InstRW<[A53WriteVLD4], (instregex "LD4Fourv(2d)$")>;
243def : InstRW<[A53WriteVLD2, WriteAdr], (instregex "LD4i(8|16|32|64)_POST$")>;
244def : InstRW<[A53WriteVLD2, WriteAdr], (instregex "LD4Rv(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;
245def : InstRW<[A53WriteVLD5, WriteAdr], (instregex "LD4Fourv(8b|4h|2s|1d|16b|8h|4s)_POST$")>;
246def : InstRW<[A53WriteVLD4, WriteAdr], (instregex "LD4Fourv(2d)_POST$")>;
247
248//---
249// Vector Stores
250//---
251def : InstRW<[A53WriteVST1], (instregex "ST1i(8|16|32|64)$")>;
252def : InstRW<[A53WriteVST1], (instregex "ST1Onev(8b|4h|2s|1d|16b|8h|4s|2d)$")>;
253def : InstRW<[A53WriteVST1], (instregex "ST1Twov(8b|4h|2s|1d|16b|8h|4s|2d)$")>;
254def : InstRW<[A53WriteVST2], (instregex "ST1Threev(8b|4h|2s|1d|16b|8h|4s|2d)$")>;
255def : InstRW<[A53WriteVST2], (instregex "ST1Fourv(8b|4h|2s|1d|16b|8h|4s|2d)$")>;
256def : InstRW<[A53WriteVST1, WriteAdr], (instregex "ST1i(8|16|32|64)_POST$")>;
257def : InstRW<[A53WriteVST1, WriteAdr], (instregex "ST1Onev(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;
258def : InstRW<[A53WriteVST1, WriteAdr], (instregex "ST1Twov(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;
259def : InstRW<[A53WriteVST2, WriteAdr], (instregex "ST1Threev(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;
260def : InstRW<[A53WriteVST2, WriteAdr], (instregex "ST1Fourv(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;
261
262def : InstRW<[A53WriteVST1], (instregex "ST2i(8|16|32|64)$")>;
263def : InstRW<[A53WriteVST1], (instregex "ST2Twov(8b|4h|2s)$")>;
264def : InstRW<[A53WriteVST2], (instregex "ST2Twov(16b|8h|4s|2d)$")>;
265def : InstRW<[A53WriteVST1, WriteAdr], (instregex "ST2i(8|16|32|64)_POST$")>;
266def : InstRW<[A53WriteVST1, WriteAdr], (instregex "ST2Twov(8b|4h|2s)_POST$")>;
267def : InstRW<[A53WriteVST2, WriteAdr], (instregex "ST2Twov(16b|8h|4s|2d)_POST$")>;
268
269def : InstRW<[A53WriteVST2], (instregex "ST3i(8|16|32|64)$")>;
270def : InstRW<[A53WriteVST3], (instregex "ST3Threev(8b|4h|2s|1d|16b|8h|4s)$")>;
271def : InstRW<[A53WriteVST2], (instregex "ST3Threev(2d)$")>;
272def : InstRW<[A53WriteVST2, WriteAdr], (instregex "ST3i(8|16|32|64)_POST$")>;
273def : InstRW<[A53WriteVST3, WriteAdr], (instregex "ST3Threev(8b|4h|2s|1d|16b|8h|4s)_POST$")>;
274def : InstRW<[A53WriteVST2, WriteAdr], (instregex "ST3Threev(2d)_POST$")>;
275
276def : InstRW<[A53WriteVST2], (instregex "ST4i(8|16|32|64)$")>;
277def : InstRW<[A53WriteVST3], (instregex "ST4Fourv(8b|4h|2s|1d|16b|8h|4s)$")>;
278def : InstRW<[A53WriteVST2], (instregex "ST4Fourv(2d)$")>;
279def : InstRW<[A53WriteVST2, WriteAdr], (instregex "ST4i(8|16|32|64)_POST$")>;
280def : InstRW<[A53WriteVST3, WriteAdr], (instregex "ST4Fourv(8b|4h|2s|1d|16b|8h|4s)_POST$")>;
281def : InstRW<[A53WriteVST2, WriteAdr], (instregex "ST4Fourv(2d)_POST$")>;
282
283//---
284// Floating Point MAC, DIV, SQRT
285//---
286def : InstRW<[A53WriteFMAC], (instregex "^FN?M(ADD|SUB).*")>;
287def : InstRW<[A53WriteFMAC], (instregex "^FML(A|S).*")>;
288def : InstRW<[A53WriteFDivSP], (instrs FDIVSrr)>;
289def : InstRW<[A53WriteFDivDP], (instrs FDIVDrr)>;
290def : InstRW<[A53WriteFDivSP], (instregex "^FDIVv.*32$")>;
291def : InstRW<[A53WriteFDivDP], (instregex "^FDIVv.*64$")>;
292def : InstRW<[A53WriteFSqrtSP], (instregex "^.*SQRT.*32$")>;
293def : InstRW<[A53WriteFSqrtDP], (instregex "^.*SQRT.*64$")>;
294
295}
296