Context.cpp revision 353358 
1//===---------------------------- Context.cpp -------------------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8/// \file
9///
10/// This file defines a class for holding ownership of various simulated
11/// hardware units.  A Context also provides a utility routine for constructing
12/// a default out-of-order pipeline with fetch, dispatch, execute, and retire
13/// stages.
14///
15//===----------------------------------------------------------------------===//
16
17#include "llvm/MCA/Context.h"
18#include "llvm/MCA/HardwareUnits/RegisterFile.h"
19#include "llvm/MCA/HardwareUnits/RetireControlUnit.h"
20#include "llvm/MCA/HardwareUnits/Scheduler.h"
21#include "llvm/MCA/Stages/DispatchStage.h"
22#include "llvm/MCA/Stages/EntryStage.h"
23#include "llvm/MCA/Stages/ExecuteStage.h"
24#include "llvm/MCA/Stages/MicroOpQueueStage.h"
25#include "llvm/MCA/Stages/RetireStage.h"
26
27namespace llvm {
28namespace mca {
29
30std::unique_ptr<Pipeline>
31Context::createDefaultPipeline(const PipelineOptions &Opts, InstrBuilder &IB,
32                               SourceMgr &SrcMgr) {
33  const MCSchedModel &SM = STI.getSchedModel();
34
35  // Create the hardware units defining the backend.
36  auto RCU = llvm::make_unique<RetireControlUnit>(SM);
37  auto PRF = llvm::make_unique<RegisterFile>(SM, MRI, Opts.RegisterFileSize);
38  auto LSU = llvm::make_unique<LSUnit>(SM, Opts.LoadQueueSize,
39                                       Opts.StoreQueueSize, Opts.AssumeNoAlias);
40  auto HWS = llvm::make_unique<Scheduler>(SM, *LSU);
41
42  // Create the pipeline stages.
43  auto Fetch = llvm::make_unique<EntryStage>(SrcMgr);
44  auto Dispatch = llvm::make_unique<DispatchStage>(STI, MRI, Opts.DispatchWidth,
45                                                   *RCU, *PRF);
46  auto Execute =
47      llvm::make_unique<ExecuteStage>(*HWS, Opts.EnableBottleneckAnalysis);
48  auto Retire = llvm::make_unique<RetireStage>(*RCU, *PRF);
49
50  // Pass the ownership of all the hardware units to this Context.
51  addHardwareUnit(std::move(RCU));
52  addHardwareUnit(std::move(PRF));
53  addHardwareUnit(std::move(LSU));
54  addHardwareUnit(std::move(HWS));
55
56  // Build the pipeline.
57  auto StagePipeline = llvm::make_unique<Pipeline>();
58  StagePipeline->appendStage(std::move(Fetch));
59  if (Opts.MicroOpQueueSize)
60    StagePipeline->appendStage(llvm::make_unique<MicroOpQueueStage>(
61        Opts.MicroOpQueueSize, Opts.DecodersThroughput));
62  StagePipeline->appendStage(std::move(Dispatch));
63  StagePipeline->appendStage(std::move(Execute));
64  StagePipeline->appendStage(std::move(Retire));
65  return StagePipeline;
66}
67
68} // namespace mca
69} // namespace llvm
70