Disassembler.cpp revision 280031 
1//===-- lib/MC/Disassembler.cpp - Disassembler Public C Interface ---------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9
10#include "Disassembler.h"
11#include "llvm-c/Disassembler.h"
12#include "llvm/MC/MCAsmInfo.h"
13#include "llvm/MC/MCContext.h"
14#include "llvm/MC/MCDisassembler.h"
15#include "llvm/MC/MCInst.h"
16#include "llvm/MC/MCInstPrinter.h"
17#include "llvm/MC/MCInstrInfo.h"
18#include "llvm/MC/MCRegisterInfo.h"
19#include "llvm/MC/MCRelocationInfo.h"
20#include "llvm/MC/MCSubtargetInfo.h"
21#include "llvm/MC/MCSymbolizer.h"
22#include "llvm/Support/ErrorHandling.h"
23#include "llvm/Support/FormattedStream.h"
24#include "llvm/Support/TargetRegistry.h"
25
26using namespace llvm;
27
28// LLVMCreateDisasm() creates a disassembler for the TripleName.  Symbolic
29// disassembly is supported by passing a block of information in the DisInfo
30// parameter and specifying the TagType and callback functions as described in
31// the header llvm-c/Disassembler.h .  The pointer to the block and the
32// functions can all be passed as NULL.  If successful, this returns a
33// disassembler context.  If not, it returns NULL.
34//
35LLVMDisasmContextRef
36LLVMCreateDisasmCPUFeatures(const char *Triple, const char *CPU,
37                            const char *Features, void *DisInfo, int TagType,
38                            LLVMOpInfoCallback GetOpInfo,
39                            LLVMSymbolLookupCallback SymbolLookUp) {
40  // Get the target.
41  std::string Error;
42  const Target *TheTarget = TargetRegistry::lookupTarget(Triple, Error);
43  if (!TheTarget)
44    return nullptr;
45
46  const MCRegisterInfo *MRI = TheTarget->createMCRegInfo(Triple);
47  if (!MRI)
48    return nullptr;
49
50  // Get the assembler info needed to setup the MCContext.
51  const MCAsmInfo *MAI = TheTarget->createMCAsmInfo(*MRI, Triple);
52  if (!MAI)
53    return nullptr;
54
55  const MCInstrInfo *MII = TheTarget->createMCInstrInfo();
56  if (!MII)
57    return nullptr;
58
59  const MCSubtargetInfo *STI = TheTarget->createMCSubtargetInfo(Triple, CPU,
60                                                                Features);
61  if (!STI)
62    return nullptr;
63
64  // Set up the MCContext for creating symbols and MCExpr's.
65  MCContext *Ctx = new MCContext(MAI, MRI, nullptr);
66  if (!Ctx)
67    return nullptr;
68
69  // Set up disassembler.
70  MCDisassembler *DisAsm = TheTarget->createMCDisassembler(*STI, *Ctx);
71  if (!DisAsm)
72    return nullptr;
73
74  std::unique_ptr<MCRelocationInfo> RelInfo(
75      TheTarget->createMCRelocationInfo(Triple, *Ctx));
76  if (!RelInfo)
77    return nullptr;
78
79  std::unique_ptr<MCSymbolizer> Symbolizer(TheTarget->createMCSymbolizer(
80      Triple, GetOpInfo, SymbolLookUp, DisInfo, Ctx, RelInfo.release()));
81  DisAsm->setSymbolizer(std::move(Symbolizer));
82
83  // Set up the instruction printer.
84  int AsmPrinterVariant = MAI->getAssemblerDialect();
85  MCInstPrinter *IP = TheTarget->createMCInstPrinter(AsmPrinterVariant,
86                                                     *MAI, *MII, *MRI, *STI);
87  if (!IP)
88    return nullptr;
89
90  LLVMDisasmContext *DC = new LLVMDisasmContext(Triple, DisInfo, TagType,
91                                                GetOpInfo, SymbolLookUp,
92                                                TheTarget, MAI, MRI,
93                                                STI, MII, Ctx, DisAsm, IP);
94  if (!DC)
95    return nullptr;
96
97  DC->setCPU(CPU);
98  return DC;
99}
100
101LLVMDisasmContextRef LLVMCreateDisasmCPU(const char *Triple, const char *CPU,
102                                         void *DisInfo, int TagType,
103                                         LLVMOpInfoCallback GetOpInfo,
104                                         LLVMSymbolLookupCallback SymbolLookUp){
105  return LLVMCreateDisasmCPUFeatures(Triple, CPU, "", DisInfo, TagType,
106                                     GetOpInfo, SymbolLookUp);
107}
108
109LLVMDisasmContextRef LLVMCreateDisasm(const char *Triple, void *DisInfo,
110                                      int TagType, LLVMOpInfoCallback GetOpInfo,
111                                      LLVMSymbolLookupCallback SymbolLookUp) {
112  return LLVMCreateDisasmCPUFeatures(Triple, "", "", DisInfo, TagType,
113                                     GetOpInfo, SymbolLookUp);
114}
115
116//
117// LLVMDisasmDispose() disposes of the disassembler specified by the context.
118//
119void LLVMDisasmDispose(LLVMDisasmContextRef DCR){
120  LLVMDisasmContext *DC = (LLVMDisasmContext *)DCR;
121  delete DC;
122}
123
124/// \brief Emits the comments that are stored in \p DC comment stream.
125/// Each comment in the comment stream must end with a newline.
126static void emitComments(LLVMDisasmContext *DC,
127                         formatted_raw_ostream &FormattedOS) {
128  // Flush the stream before taking its content.
129  DC->CommentStream.flush();
130  StringRef Comments = DC->CommentsToEmit.str();
131  // Get the default information for printing a comment.
132  const MCAsmInfo *MAI = DC->getAsmInfo();
133  const char *CommentBegin = MAI->getCommentString();
134  unsigned CommentColumn = MAI->getCommentColumn();
135  bool IsFirst = true;
136  while (!Comments.empty()) {
137    if (!IsFirst)
138      FormattedOS << '\n';
139    // Emit a line of comments.
140    FormattedOS.PadToColumn(CommentColumn);
141    size_t Position = Comments.find('\n');
142    FormattedOS << CommentBegin << ' ' << Comments.substr(0, Position);
143    // Move after the newline character.
144    Comments = Comments.substr(Position+1);
145    IsFirst = false;
146  }
147  FormattedOS.flush();
148
149  // Tell the comment stream that the vector changed underneath it.
150  DC->CommentsToEmit.clear();
151  DC->CommentStream.resync();
152}
153
154/// \brief Gets latency information for \p Inst from the itinerary
155/// scheduling model, based on \p DC information.
156/// \return The maximum expected latency over all the operands or -1
157/// if no information is available.
158static int getItineraryLatency(LLVMDisasmContext *DC, const MCInst &Inst) {
159  const int NoInformationAvailable = -1;
160
161  // Check if we have a CPU to get the itinerary information.
162  if (DC->getCPU().empty())
163    return NoInformationAvailable;
164
165  // Get itinerary information.
166  const MCSubtargetInfo *STI = DC->getSubtargetInfo();
167  InstrItineraryData IID = STI->getInstrItineraryForCPU(DC->getCPU());
168  // Get the scheduling class of the requested instruction.
169  const MCInstrDesc& Desc = DC->getInstrInfo()->get(Inst.getOpcode());
170  unsigned SCClass = Desc.getSchedClass();
171
172  int Latency = 0;
173  for (unsigned OpIdx = 0, OpIdxEnd = Inst.getNumOperands(); OpIdx != OpIdxEnd;
174       ++OpIdx)
175    Latency = std::max(Latency, IID.getOperandCycle(SCClass, OpIdx));
176
177  return Latency;
178}
179
180/// \brief Gets latency information for \p Inst, based on \p DC information.
181/// \return The maximum expected latency over all the definitions or -1
182/// if no information is available.
183static int getLatency(LLVMDisasmContext *DC, const MCInst &Inst) {
184  // Try to compute scheduling information.
185  const MCSubtargetInfo *STI = DC->getSubtargetInfo();
186  const MCSchedModel SCModel = STI->getSchedModel();
187  const int NoInformationAvailable = -1;
188
189  // Check if we have a scheduling model for instructions.
190  if (!SCModel.hasInstrSchedModel())
191    // Try to fall back to the itinerary model if the scheduling model doesn't
192    // have a scheduling table.  Note the default does not have a table.
193    return getItineraryLatency(DC, Inst);
194
195  // Get the scheduling class of the requested instruction.
196  const MCInstrDesc& Desc = DC->getInstrInfo()->get(Inst.getOpcode());
197  unsigned SCClass = Desc.getSchedClass();
198  const MCSchedClassDesc *SCDesc = SCModel.getSchedClassDesc(SCClass);
199  // Resolving the variant SchedClass requires an MI to pass to
200  // SubTargetInfo::resolveSchedClass.
201  if (!SCDesc || !SCDesc->isValid() || SCDesc->isVariant())
202    return NoInformationAvailable;
203
204  // Compute output latency.
205  int Latency = 0;
206  for (unsigned DefIdx = 0, DefEnd = SCDesc->NumWriteLatencyEntries;
207       DefIdx != DefEnd; ++DefIdx) {
208    // Lookup the definition's write latency in SubtargetInfo.
209    const MCWriteLatencyEntry *WLEntry = STI->getWriteLatencyEntry(SCDesc,
210                                                                   DefIdx);
211    Latency = std::max(Latency, WLEntry->Cycles);
212  }
213
214  return Latency;
215}
216
217
218/// \brief Emits latency information in DC->CommentStream for \p Inst, based
219/// on the information available in \p DC.
220static void emitLatency(LLVMDisasmContext *DC, const MCInst &Inst) {
221  int Latency = getLatency(DC, Inst);
222
223  // Report only interesting latencies.
224  if (Latency < 2)
225    return;
226
227  DC->CommentStream << "Latency: " << Latency << '\n';
228}
229
230//
231// LLVMDisasmInstruction() disassembles a single instruction using the
232// disassembler context specified in the parameter DC.  The bytes of the
233// instruction are specified in the parameter Bytes, and contains at least
234// BytesSize number of bytes.  The instruction is at the address specified by
235// the PC parameter.  If a valid instruction can be disassembled its string is
236// returned indirectly in OutString which whos size is specified in the
237// parameter OutStringSize.  This function returns the number of bytes in the
238// instruction or zero if there was no valid instruction.  If this function
239// returns zero the caller will have to pick how many bytes they want to step
240// over by printing a .byte, .long etc. to continue.
241//
242size_t LLVMDisasmInstruction(LLVMDisasmContextRef DCR, uint8_t *Bytes,
243                             uint64_t BytesSize, uint64_t PC, char *OutString,
244                             size_t OutStringSize){
245  LLVMDisasmContext *DC = (LLVMDisasmContext *)DCR;
246  // Wrap the pointer to the Bytes, BytesSize and PC in a MemoryObject.
247  ArrayRef<uint8_t> Data(Bytes, BytesSize);
248
249  uint64_t Size;
250  MCInst Inst;
251  const MCDisassembler *DisAsm = DC->getDisAsm();
252  MCInstPrinter *IP = DC->getIP();
253  MCDisassembler::DecodeStatus S;
254  SmallVector<char, 64> InsnStr;
255  raw_svector_ostream Annotations(InsnStr);
256  S = DisAsm->getInstruction(Inst, Size, Data, PC,
257                             /*REMOVE*/ nulls(), Annotations);
258  switch (S) {
259  case MCDisassembler::Fail:
260  case MCDisassembler::SoftFail:
261    // FIXME: Do something different for soft failure modes?
262    return 0;
263
264  case MCDisassembler::Success: {
265    Annotations.flush();
266    StringRef AnnotationsStr = Annotations.str();
267
268    SmallVector<char, 64> InsnStr;
269    raw_svector_ostream OS(InsnStr);
270    formatted_raw_ostream FormattedOS(OS);
271    IP->printInst(&Inst, FormattedOS, AnnotationsStr);
272
273    if (DC->getOptions() & LLVMDisassembler_Option_PrintLatency)
274      emitLatency(DC, Inst);
275
276    emitComments(DC, FormattedOS);
277    OS.flush();
278
279    assert(OutStringSize != 0 && "Output buffer cannot be zero size");
280    size_t OutputSize = std::min(OutStringSize-1, InsnStr.size());
281    std::memcpy(OutString, InsnStr.data(), OutputSize);
282    OutString[OutputSize] = '\0'; // Terminate string.
283
284    return Size;
285  }
286  }
287  llvm_unreachable("Invalid DecodeStatus!");
288}
289
290//
291// LLVMSetDisasmOptions() sets the disassembler's options.  It returns 1 if it
292// can set all the Options and 0 otherwise.
293//
294int LLVMSetDisasmOptions(LLVMDisasmContextRef DCR, uint64_t Options){
295  if (Options & LLVMDisassembler_Option_UseMarkup){
296      LLVMDisasmContext *DC = (LLVMDisasmContext *)DCR;
297      MCInstPrinter *IP = DC->getIP();
298      IP->setUseMarkup(1);
299      DC->addOptions(LLVMDisassembler_Option_UseMarkup);
300      Options &= ~LLVMDisassembler_Option_UseMarkup;
301  }
302  if (Options & LLVMDisassembler_Option_PrintImmHex){
303      LLVMDisasmContext *DC = (LLVMDisasmContext *)DCR;
304      MCInstPrinter *IP = DC->getIP();
305      IP->setPrintImmHex(1);
306      DC->addOptions(LLVMDisassembler_Option_PrintImmHex);
307      Options &= ~LLVMDisassembler_Option_PrintImmHex;
308  }
309  if (Options & LLVMDisassembler_Option_AsmPrinterVariant){
310      LLVMDisasmContext *DC = (LLVMDisasmContext *)DCR;
311      // Try to set up the new instruction printer.
312      const MCAsmInfo *MAI = DC->getAsmInfo();
313      const MCInstrInfo *MII = DC->getInstrInfo();
314      const MCRegisterInfo *MRI = DC->getRegisterInfo();
315      const MCSubtargetInfo *STI = DC->getSubtargetInfo();
316      int AsmPrinterVariant = MAI->getAssemblerDialect();
317      AsmPrinterVariant = AsmPrinterVariant == 0 ? 1 : 0;
318      MCInstPrinter *IP = DC->getTarget()->createMCInstPrinter(
319          AsmPrinterVariant, *MAI, *MII, *MRI, *STI);
320      if (IP) {
321        DC->setIP(IP);
322        DC->addOptions(LLVMDisassembler_Option_AsmPrinterVariant);
323        Options &= ~LLVMDisassembler_Option_AsmPrinterVariant;
324      }
325  }
326  if (Options & LLVMDisassembler_Option_SetInstrComments) {
327    LLVMDisasmContext *DC = (LLVMDisasmContext *)DCR;
328    MCInstPrinter *IP = DC->getIP();
329    IP->setCommentStream(DC->CommentStream);
330    DC->addOptions(LLVMDisassembler_Option_SetInstrComments);
331    Options &= ~LLVMDisassembler_Option_SetInstrComments;
332  }
333  if (Options & LLVMDisassembler_Option_PrintLatency) {
334    LLVMDisasmContext *DC = (LLVMDisasmContext *)DCR;
335    DC->addOptions(LLVMDisassembler_Option_PrintLatency);
336    Options &= ~LLVMDisassembler_Option_PrintLatency;
337  }
338  return (Options == 0);
339}
340