1321369Sdim//===- TargetPassConfig.cpp - Target independent code generation passes ---===// 2303231Sdim// 3353358Sdim// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4353358Sdim// See https://llvm.org/LICENSE.txt for license information. 5353358Sdim// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6303231Sdim// 7303231Sdim//===----------------------------------------------------------------------===// 8303231Sdim// 9303231Sdim// This file defines interfaces to access the target independent code 10303231Sdim// generation passes provided by the LLVM backend. 11303231Sdim// 12303231Sdim//===---------------------------------------------------------------------===// 13303231Sdim 14303231Sdim#include "llvm/CodeGen/TargetPassConfig.h" 15321369Sdim#include "llvm/ADT/DenseMap.h" 16321369Sdim#include "llvm/ADT/SmallVector.h" 17321369Sdim#include "llvm/ADT/StringRef.h" 18303231Sdim#include "llvm/Analysis/BasicAliasAnalysis.h" 19303231Sdim#include "llvm/Analysis/CFLAndersAliasAnalysis.h" 20303231Sdim#include "llvm/Analysis/CFLSteensAliasAnalysis.h" 21303231Sdim#include "llvm/Analysis/CallGraphSCCPass.h" 22303231Sdim#include "llvm/Analysis/ScopedNoAliasAA.h" 23321369Sdim#include "llvm/Analysis/TargetTransformInfo.h" 24303231Sdim#include "llvm/Analysis/TypeBasedAliasAnalysis.h" 25353358Sdim#include "llvm/CodeGen/CSEConfigBase.h" 26303231Sdim#include "llvm/CodeGen/MachineFunctionPass.h" 27321369Sdim#include "llvm/CodeGen/MachinePassRegistry.h" 28321369Sdim#include "llvm/CodeGen/Passes.h" 29303231Sdim#include "llvm/CodeGen/RegAllocRegistry.h" 30303231Sdim#include "llvm/IR/IRPrintingPasses.h" 31303231Sdim#include "llvm/IR/LegacyPassManager.h" 32303231Sdim#include "llvm/IR/Verifier.h" 33360784Sdim#include "llvm/InitializePasses.h" 34303231Sdim#include "llvm/MC/MCAsmInfo.h" 35321369Sdim#include "llvm/MC/MCTargetOptions.h" 36321369Sdim#include "llvm/Pass.h" 37321369Sdim#include "llvm/Support/CodeGen.h" 38321369Sdim#include "llvm/Support/CommandLine.h" 39321369Sdim#include "llvm/Support/Compiler.h" 40303231Sdim#include "llvm/Support/Debug.h" 41303231Sdim#include "llvm/Support/ErrorHandling.h" 42360784Sdim#include "llvm/Support/SaveAndRestore.h" 43321369Sdim#include "llvm/Support/Threading.h" 44303231Sdim#include "llvm/Target/TargetMachine.h" 45303231Sdim#include "llvm/Transforms/Scalar.h" 46341825Sdim#include "llvm/Transforms/Utils.h" 47303231Sdim#include "llvm/Transforms/Utils/SymbolRewriter.h" 48321369Sdim#include <cassert> 49321369Sdim#include <string> 50303231Sdim 51303231Sdimusing namespace llvm; 52303231Sdim 53360784Sdimstatic cl::opt<bool> 54360784Sdim EnableIPRA("enable-ipra", cl::init(false), cl::Hidden, 55360784Sdim cl::desc("Enable interprocedural register allocation " 56360784Sdim "to reduce load/store at procedure calls.")); 57314564Sdimstatic cl::opt<bool> DisablePostRASched("disable-post-ra", cl::Hidden, 58314564Sdim cl::desc("Disable Post Regalloc Scheduler")); 59303231Sdimstatic cl::opt<bool> DisableBranchFold("disable-branch-fold", cl::Hidden, 60303231Sdim cl::desc("Disable branch folding")); 61303231Sdimstatic cl::opt<bool> DisableTailDuplicate("disable-tail-duplicate", cl::Hidden, 62303231Sdim cl::desc("Disable tail duplication")); 63303231Sdimstatic cl::opt<bool> DisableEarlyTailDup("disable-early-taildup", cl::Hidden, 64303231Sdim cl::desc("Disable pre-register allocation tail duplication")); 65303231Sdimstatic cl::opt<bool> DisableBlockPlacement("disable-block-placement", 66303231Sdim cl::Hidden, cl::desc("Disable probability-driven block placement")); 67303231Sdimstatic cl::opt<bool> EnableBlockPlacementStats("enable-block-placement-stats", 68303231Sdim cl::Hidden, cl::desc("Collect probability-driven block placement stats")); 69303231Sdimstatic cl::opt<bool> DisableSSC("disable-ssc", cl::Hidden, 70303231Sdim cl::desc("Disable Stack Slot Coloring")); 71303231Sdimstatic cl::opt<bool> DisableMachineDCE("disable-machine-dce", cl::Hidden, 72303231Sdim cl::desc("Disable Machine Dead Code Elimination")); 73303231Sdimstatic cl::opt<bool> DisableEarlyIfConversion("disable-early-ifcvt", cl::Hidden, 74303231Sdim cl::desc("Disable Early If-conversion")); 75303231Sdimstatic cl::opt<bool> DisableMachineLICM("disable-machine-licm", cl::Hidden, 76303231Sdim cl::desc("Disable Machine LICM")); 77303231Sdimstatic cl::opt<bool> DisableMachineCSE("disable-machine-cse", cl::Hidden, 78303231Sdim cl::desc("Disable Machine Common Subexpression Elimination")); 79303231Sdimstatic cl::opt<cl::boolOrDefault> OptimizeRegAlloc( 80303231Sdim "optimize-regalloc", cl::Hidden, 81303231Sdim cl::desc("Enable optimized register allocation compilation path.")); 82303231Sdimstatic cl::opt<bool> DisablePostRAMachineLICM("disable-postra-machine-licm", 83303231Sdim cl::Hidden, 84303231Sdim cl::desc("Disable Machine LICM")); 85303231Sdimstatic cl::opt<bool> DisableMachineSink("disable-machine-sink", cl::Hidden, 86303231Sdim cl::desc("Disable Machine Sinking")); 87341825Sdimstatic cl::opt<bool> DisablePostRAMachineSink("disable-postra-machine-sink", 88341825Sdim cl::Hidden, 89341825Sdim cl::desc("Disable PostRA Machine Sinking")); 90303231Sdimstatic cl::opt<bool> DisableLSR("disable-lsr", cl::Hidden, 91303231Sdim cl::desc("Disable Loop Strength Reduction Pass")); 92303231Sdimstatic cl::opt<bool> DisableConstantHoisting("disable-constant-hoisting", 93303231Sdim cl::Hidden, cl::desc("Disable ConstantHoisting")); 94303231Sdimstatic cl::opt<bool> DisableCGP("disable-cgp", cl::Hidden, 95303231Sdim cl::desc("Disable Codegen Prepare")); 96303231Sdimstatic cl::opt<bool> DisableCopyProp("disable-copyprop", cl::Hidden, 97303231Sdim cl::desc("Disable Copy Propagation pass")); 98303231Sdimstatic cl::opt<bool> DisablePartialLibcallInlining("disable-partial-libcall-inlining", 99303231Sdim cl::Hidden, cl::desc("Disable Partial Libcall Inlining")); 100303231Sdimstatic cl::opt<bool> EnableImplicitNullChecks( 101303231Sdim "enable-implicit-null-checks", 102303231Sdim cl::desc("Fold null checks into faulting memory operations"), 103327952Sdim cl::init(false), cl::Hidden); 104341825Sdimstatic cl::opt<bool> DisableMergeICmps("disable-mergeicmps", 105341825Sdim cl::desc("Disable MergeICmps Pass"), 106341825Sdim cl::init(false), cl::Hidden); 107303231Sdimstatic cl::opt<bool> PrintLSR("print-lsr-output", cl::Hidden, 108303231Sdim cl::desc("Print LLVM IR produced by the loop-reduce pass")); 109303231Sdimstatic cl::opt<bool> PrintISelInput("print-isel-input", cl::Hidden, 110303231Sdim cl::desc("Print LLVM IR input to isel pass")); 111303231Sdimstatic cl::opt<bool> PrintGCInfo("print-gc", cl::Hidden, 112303231Sdim cl::desc("Dump garbage collector data")); 113344779Sdimstatic cl::opt<cl::boolOrDefault> 114344779Sdim VerifyMachineCode("verify-machineinstrs", cl::Hidden, 115344779Sdim cl::desc("Verify generated machine code"), 116344779Sdim cl::ZeroOrMore); 117341825Sdimenum RunOutliner { AlwaysOutline, NeverOutline, TargetDefault }; 118341825Sdim// Enable or disable the MachineOutliner. 119341825Sdimstatic cl::opt<RunOutliner> EnableMachineOutliner( 120341825Sdim "enable-machine-outliner", cl::desc("Enable the machine outliner"), 121341825Sdim cl::Hidden, cl::ValueOptional, cl::init(TargetDefault), 122341825Sdim cl::values(clEnumValN(AlwaysOutline, "always", 123341825Sdim "Run on all functions guaranteed to be beneficial"), 124341825Sdim clEnumValN(NeverOutline, "never", "Disable all outlining"), 125341825Sdim // Sentinel value for unspecified option. 126341825Sdim clEnumValN(AlwaysOutline, "", ""))); 127321369Sdim// Enable or disable FastISel. Both options are needed, because 128321369Sdim// FastISel is enabled by default with -fast, and we wish to be 129321369Sdim// able to enable or disable fast-isel independently from -O0. 130321369Sdimstatic cl::opt<cl::boolOrDefault> 131321369SdimEnableFastISelOption("fast-isel", cl::Hidden, 132321369Sdim cl::desc("Enable the \"fast\" instruction selector")); 133303231Sdim 134341825Sdimstatic cl::opt<cl::boolOrDefault> EnableGlobalISelOption( 135341825Sdim "global-isel", cl::Hidden, 136341825Sdim cl::desc("Enable the \"global\" instruction selector")); 137321369Sdim 138327952Sdimstatic cl::opt<std::string> PrintMachineInstrs( 139327952Sdim "print-machineinstrs", cl::ValueOptional, cl::desc("Print machine instrs"), 140327952Sdim cl::value_desc("pass-name"), cl::init("option-unspecified"), cl::Hidden); 141303231Sdim 142344779Sdimstatic cl::opt<GlobalISelAbortMode> EnableGlobalISelAbort( 143314564Sdim "global-isel-abort", cl::Hidden, 144314564Sdim cl::desc("Enable abort calls when \"global\" instruction selection " 145344779Sdim "fails to lower/select an instruction"), 146344779Sdim cl::values( 147344779Sdim clEnumValN(GlobalISelAbortMode::Disable, "0", "Disable the abort"), 148344779Sdim clEnumValN(GlobalISelAbortMode::Enable, "1", "Enable the abort"), 149344779Sdim clEnumValN(GlobalISelAbortMode::DisableWithDiag, "2", 150344779Sdim "Disable the abort but emit a diagnostic on failure"))); 151314564Sdim 152303231Sdim// Temporary option to allow experimenting with MachineScheduler as a post-RA 153303231Sdim// scheduler. Targets can "properly" enable this with 154303231Sdim// substitutePass(&PostRASchedulerID, &PostMachineSchedulerID). 155303231Sdim// Targets can return true in targetSchedulesPostRAScheduling() and 156303231Sdim// insert a PostRA scheduling pass wherever it wants. 157360784Sdimstatic cl::opt<bool> MISchedPostRA( 158360784Sdim "misched-postra", cl::Hidden, 159360784Sdim cl::desc( 160360784Sdim "Run MachineScheduler post regalloc (independent of preRA sched)")); 161303231Sdim 162303231Sdim// Experimental option to run live interval analysis early. 163303231Sdimstatic cl::opt<bool> EarlyLiveIntervals("early-live-intervals", cl::Hidden, 164303231Sdim cl::desc("Run live interval analysis earlier in the pipeline")); 165303231Sdim 166303231Sdim// Experimental option to use CFL-AA in codegen 167303231Sdimenum class CFLAAType { None, Steensgaard, Andersen, Both }; 168303231Sdimstatic cl::opt<CFLAAType> UseCFLAA( 169303231Sdim "use-cfl-aa-in-codegen", cl::init(CFLAAType::None), cl::Hidden, 170303231Sdim cl::desc("Enable the new, experimental CFL alias analysis in CodeGen"), 171303231Sdim cl::values(clEnumValN(CFLAAType::None, "none", "Disable CFL-AA"), 172303231Sdim clEnumValN(CFLAAType::Steensgaard, "steens", 173303231Sdim "Enable unification-based CFL-AA"), 174303231Sdim clEnumValN(CFLAAType::Andersen, "anders", 175303231Sdim "Enable inclusion-based CFL-AA"), 176341825Sdim clEnumValN(CFLAAType::Both, "both", 177314564Sdim "Enable both variants of CFL-AA"))); 178303231Sdim 179327952Sdim/// Option names for limiting the codegen pipeline. 180327952Sdim/// Those are used in error reporting and we didn't want 181327952Sdim/// to duplicate their names all over the place. 182360784Sdimstatic const char StartAfterOptName[] = "start-after"; 183360784Sdimstatic const char StartBeforeOptName[] = "start-before"; 184360784Sdimstatic const char StopAfterOptName[] = "stop-after"; 185360784Sdimstatic const char StopBeforeOptName[] = "stop-before"; 186327952Sdim 187327952Sdimstatic cl::opt<std::string> 188327952Sdim StartAfterOpt(StringRef(StartAfterOptName), 189327952Sdim cl::desc("Resume compilation after a specific pass"), 190327952Sdim cl::value_desc("pass-name"), cl::init(""), cl::Hidden); 191327952Sdim 192327952Sdimstatic cl::opt<std::string> 193327952Sdim StartBeforeOpt(StringRef(StartBeforeOptName), 194327952Sdim cl::desc("Resume compilation before a specific pass"), 195327952Sdim cl::value_desc("pass-name"), cl::init(""), cl::Hidden); 196327952Sdim 197327952Sdimstatic cl::opt<std::string> 198327952Sdim StopAfterOpt(StringRef(StopAfterOptName), 199327952Sdim cl::desc("Stop compilation after a specific pass"), 200327952Sdim cl::value_desc("pass-name"), cl::init(""), cl::Hidden); 201327952Sdim 202327952Sdimstatic cl::opt<std::string> 203327952Sdim StopBeforeOpt(StringRef(StopBeforeOptName), 204327952Sdim cl::desc("Stop compilation before a specific pass"), 205327952Sdim cl::value_desc("pass-name"), cl::init(""), cl::Hidden); 206327952Sdim 207303231Sdim/// Allow standard passes to be disabled by command line options. This supports 208303231Sdim/// simple binary flags that either suppress the pass or do nothing. 209303231Sdim/// i.e. -disable-mypass=false has no effect. 210303231Sdim/// These should be converted to boolOrDefault in order to use applyOverride. 211303231Sdimstatic IdentifyingPassPtr applyDisable(IdentifyingPassPtr PassID, 212303231Sdim bool Override) { 213303231Sdim if (Override) 214303231Sdim return IdentifyingPassPtr(); 215303231Sdim return PassID; 216303231Sdim} 217303231Sdim 218303231Sdim/// Allow standard passes to be disabled by the command line, regardless of who 219303231Sdim/// is adding the pass. 220303231Sdim/// 221303231Sdim/// StandardID is the pass identified in the standard pass pipeline and provided 222303231Sdim/// to addPass(). It may be a target-specific ID in the case that the target 223303231Sdim/// directly adds its own pass, but in that case we harmlessly fall through. 224303231Sdim/// 225303231Sdim/// TargetID is the pass that the target has configured to override StandardID. 226303231Sdim/// 227303231Sdim/// StandardID may be a pseudo ID. In that case TargetID is the name of the real 228303231Sdim/// pass to run. This allows multiple options to control a single pass depending 229303231Sdim/// on where in the pipeline that pass is added. 230303231Sdimstatic IdentifyingPassPtr overridePass(AnalysisID StandardID, 231303231Sdim IdentifyingPassPtr TargetID) { 232303231Sdim if (StandardID == &PostRASchedulerID) 233314564Sdim return applyDisable(TargetID, DisablePostRASched); 234303231Sdim 235303231Sdim if (StandardID == &BranchFolderPassID) 236303231Sdim return applyDisable(TargetID, DisableBranchFold); 237303231Sdim 238303231Sdim if (StandardID == &TailDuplicateID) 239303231Sdim return applyDisable(TargetID, DisableTailDuplicate); 240303231Sdim 241341825Sdim if (StandardID == &EarlyTailDuplicateID) 242303231Sdim return applyDisable(TargetID, DisableEarlyTailDup); 243303231Sdim 244303231Sdim if (StandardID == &MachineBlockPlacementID) 245303231Sdim return applyDisable(TargetID, DisableBlockPlacement); 246303231Sdim 247303231Sdim if (StandardID == &StackSlotColoringID) 248303231Sdim return applyDisable(TargetID, DisableSSC); 249303231Sdim 250303231Sdim if (StandardID == &DeadMachineInstructionElimID) 251303231Sdim return applyDisable(TargetID, DisableMachineDCE); 252303231Sdim 253303231Sdim if (StandardID == &EarlyIfConverterID) 254303231Sdim return applyDisable(TargetID, DisableEarlyIfConversion); 255303231Sdim 256341825Sdim if (StandardID == &EarlyMachineLICMID) 257303231Sdim return applyDisable(TargetID, DisableMachineLICM); 258303231Sdim 259303231Sdim if (StandardID == &MachineCSEID) 260303231Sdim return applyDisable(TargetID, DisableMachineCSE); 261303231Sdim 262341825Sdim if (StandardID == &MachineLICMID) 263303231Sdim return applyDisable(TargetID, DisablePostRAMachineLICM); 264303231Sdim 265303231Sdim if (StandardID == &MachineSinkingID) 266303231Sdim return applyDisable(TargetID, DisableMachineSink); 267303231Sdim 268341825Sdim if (StandardID == &PostRAMachineSinkingID) 269341825Sdim return applyDisable(TargetID, DisablePostRAMachineSink); 270341825Sdim 271303231Sdim if (StandardID == &MachineCopyPropagationID) 272303231Sdim return applyDisable(TargetID, DisableCopyProp); 273303231Sdim 274303231Sdim return TargetID; 275303231Sdim} 276303231Sdim 277303231Sdim//===---------------------------------------------------------------------===// 278303231Sdim/// TargetPassConfig 279303231Sdim//===---------------------------------------------------------------------===// 280303231Sdim 281303231SdimINITIALIZE_PASS(TargetPassConfig, "targetpassconfig", 282303231Sdim "Target Pass Configuration", false, false) 283303231Sdimchar TargetPassConfig::ID = 0; 284303231Sdim 285303231Sdimnamespace { 286321369Sdim 287303231Sdimstruct InsertedPass { 288303231Sdim AnalysisID TargetPassID; 289303231Sdim IdentifyingPassPtr InsertedPassID; 290303231Sdim bool VerifyAfter; 291303231Sdim bool PrintAfter; 292303231Sdim 293303231Sdim InsertedPass(AnalysisID TargetPassID, IdentifyingPassPtr InsertedPassID, 294303231Sdim bool VerifyAfter, bool PrintAfter) 295303231Sdim : TargetPassID(TargetPassID), InsertedPassID(InsertedPassID), 296303231Sdim VerifyAfter(VerifyAfter), PrintAfter(PrintAfter) {} 297303231Sdim 298303231Sdim Pass *getInsertedPass() const { 299303231Sdim assert(InsertedPassID.isValid() && "Illegal Pass ID!"); 300303231Sdim if (InsertedPassID.isInstance()) 301303231Sdim return InsertedPassID.getInstance(); 302303231Sdim Pass *NP = Pass::createPass(InsertedPassID.getID()); 303303231Sdim assert(NP && "Pass ID not registered"); 304303231Sdim return NP; 305303231Sdim } 306303231Sdim}; 307303231Sdim 308321369Sdim} // end anonymous namespace 309321369Sdim 310303231Sdimnamespace llvm { 311321369Sdim 312303231Sdimclass PassConfigImpl { 313303231Sdimpublic: 314303231Sdim // List of passes explicitly substituted by this target. Normally this is 315303231Sdim // empty, but it is a convenient way to suppress or replace specific passes 316303231Sdim // that are part of a standard pass pipeline without overridding the entire 317303231Sdim // pipeline. This mechanism allows target options to inherit a standard pass's 318303231Sdim // user interface. For example, a target may disable a standard pass by 319303231Sdim // default by substituting a pass ID of zero, and the user may still enable 320303231Sdim // that standard pass with an explicit command line option. 321303231Sdim DenseMap<AnalysisID,IdentifyingPassPtr> TargetPasses; 322303231Sdim 323303231Sdim /// Store the pairs of <AnalysisID, AnalysisID> of which the second pass 324303231Sdim /// is inserted after each instance of the first one. 325303231Sdim SmallVector<InsertedPass, 4> InsertedPasses; 326303231Sdim}; 327303231Sdim 328321369Sdim} // end namespace llvm 329321369Sdim 330303231Sdim// Out of line virtual method. 331303231SdimTargetPassConfig::~TargetPassConfig() { 332303231Sdim delete Impl; 333303231Sdim} 334303231Sdim 335327952Sdimstatic const PassInfo *getPassInfo(StringRef PassName) { 336327952Sdim if (PassName.empty()) 337327952Sdim return nullptr; 338327952Sdim 339327952Sdim const PassRegistry &PR = *PassRegistry::getPassRegistry(); 340327952Sdim const PassInfo *PI = PR.getPassInfo(PassName); 341327952Sdim if (!PI) 342327952Sdim report_fatal_error(Twine('\"') + Twine(PassName) + 343327952Sdim Twine("\" pass is not registered.")); 344327952Sdim return PI; 345327952Sdim} 346327952Sdim 347327952Sdimstatic AnalysisID getPassIDFromName(StringRef PassName) { 348327952Sdim const PassInfo *PI = getPassInfo(PassName); 349327952Sdim return PI ? PI->getTypeInfo() : nullptr; 350327952Sdim} 351327952Sdim 352344779Sdimstatic std::pair<StringRef, unsigned> 353344779SdimgetPassNameAndInstanceNum(StringRef PassName) { 354344779Sdim StringRef Name, InstanceNumStr; 355344779Sdim std::tie(Name, InstanceNumStr) = PassName.split(','); 356344779Sdim 357344779Sdim unsigned InstanceNum = 0; 358344779Sdim if (!InstanceNumStr.empty() && InstanceNumStr.getAsInteger(10, InstanceNum)) 359344779Sdim report_fatal_error("invalid pass instance specifier " + PassName); 360344779Sdim 361344779Sdim return std::make_pair(Name, InstanceNum); 362344779Sdim} 363344779Sdim 364327952Sdimvoid TargetPassConfig::setStartStopPasses() { 365344779Sdim StringRef StartBeforeName; 366344779Sdim std::tie(StartBeforeName, StartBeforeInstanceNum) = 367344779Sdim getPassNameAndInstanceNum(StartBeforeOpt); 368344779Sdim 369344779Sdim StringRef StartAfterName; 370344779Sdim std::tie(StartAfterName, StartAfterInstanceNum) = 371344779Sdim getPassNameAndInstanceNum(StartAfterOpt); 372344779Sdim 373344779Sdim StringRef StopBeforeName; 374344779Sdim std::tie(StopBeforeName, StopBeforeInstanceNum) 375344779Sdim = getPassNameAndInstanceNum(StopBeforeOpt); 376344779Sdim 377344779Sdim StringRef StopAfterName; 378344779Sdim std::tie(StopAfterName, StopAfterInstanceNum) 379344779Sdim = getPassNameAndInstanceNum(StopAfterOpt); 380344779Sdim 381344779Sdim StartBefore = getPassIDFromName(StartBeforeName); 382344779Sdim StartAfter = getPassIDFromName(StartAfterName); 383344779Sdim StopBefore = getPassIDFromName(StopBeforeName); 384344779Sdim StopAfter = getPassIDFromName(StopAfterName); 385327952Sdim if (StartBefore && StartAfter) 386327952Sdim report_fatal_error(Twine(StartBeforeOptName) + Twine(" and ") + 387327952Sdim Twine(StartAfterOptName) + Twine(" specified!")); 388327952Sdim if (StopBefore && StopAfter) 389327952Sdim report_fatal_error(Twine(StopBeforeOptName) + Twine(" and ") + 390327952Sdim Twine(StopAfterOptName) + Twine(" specified!")); 391327952Sdim Started = (StartAfter == nullptr) && (StartBefore == nullptr); 392327952Sdim} 393327952Sdim 394303231Sdim// Out of line constructor provides default values for pass options and 395303231Sdim// registers all common codegen passes. 396321369SdimTargetPassConfig::TargetPassConfig(LLVMTargetMachine &TM, PassManagerBase &pm) 397321369Sdim : ImmutablePass(ID), PM(&pm), TM(&TM) { 398303231Sdim Impl = new PassConfigImpl(); 399303231Sdim 400303231Sdim // Register all target independent codegen passes to activate their PassIDs, 401303231Sdim // including this pass itself. 402303231Sdim initializeCodeGen(*PassRegistry::getPassRegistry()); 403303231Sdim 404303231Sdim // Also register alias analysis passes required by codegen passes. 405303231Sdim initializeBasicAAWrapperPassPass(*PassRegistry::getPassRegistry()); 406303231Sdim initializeAAResultsWrapperPassPass(*PassRegistry::getPassRegistry()); 407303231Sdim 408303231Sdim if (StringRef(PrintMachineInstrs.getValue()).equals("")) 409321369Sdim TM.Options.PrintMachineCode = true; 410321369Sdim 411327952Sdim if (EnableIPRA.getNumOccurrences()) 412327952Sdim TM.Options.EnableIPRA = EnableIPRA; 413327952Sdim else { 414327952Sdim // If not explicitly specified, use target default. 415353358Sdim TM.Options.EnableIPRA |= TM.useIPRA(); 416327952Sdim } 417327952Sdim 418321369Sdim if (TM.Options.EnableIPRA) 419321369Sdim setRequiresCodeGenSCCOrder(); 420327952Sdim 421344779Sdim if (EnableGlobalISelAbort.getNumOccurrences()) 422344779Sdim TM.Options.GlobalISelAbort = EnableGlobalISelAbort; 423344779Sdim 424327952Sdim setStartStopPasses(); 425303231Sdim} 426303231Sdim 427303231SdimCodeGenOpt::Level TargetPassConfig::getOptLevel() const { 428303231Sdim return TM->getOptLevel(); 429303231Sdim} 430303231Sdim 431303231Sdim/// Insert InsertedPassID pass after TargetPassID. 432303231Sdimvoid TargetPassConfig::insertPass(AnalysisID TargetPassID, 433303231Sdim IdentifyingPassPtr InsertedPassID, 434303231Sdim bool VerifyAfter, bool PrintAfter) { 435303231Sdim assert(((!InsertedPassID.isInstance() && 436303231Sdim TargetPassID != InsertedPassID.getID()) || 437303231Sdim (InsertedPassID.isInstance() && 438303231Sdim TargetPassID != InsertedPassID.getInstance()->getPassID())) && 439303231Sdim "Insert a pass after itself!"); 440303231Sdim Impl->InsertedPasses.emplace_back(TargetPassID, InsertedPassID, VerifyAfter, 441303231Sdim PrintAfter); 442303231Sdim} 443303231Sdim 444303231Sdim/// createPassConfig - Create a pass configuration object to be used by 445303231Sdim/// addPassToEmitX methods for generating a pipeline of CodeGen passes. 446303231Sdim/// 447303231Sdim/// Targets may override this to extend TargetPassConfig. 448303231SdimTargetPassConfig *LLVMTargetMachine::createPassConfig(PassManagerBase &PM) { 449321369Sdim return new TargetPassConfig(*this, PM); 450303231Sdim} 451303231Sdim 452303231SdimTargetPassConfig::TargetPassConfig() 453321369Sdim : ImmutablePass(ID) { 454321369Sdim report_fatal_error("Trying to construct TargetPassConfig without a target " 455321369Sdim "machine. Scheduling a CodeGen pass without a target " 456321369Sdim "triple set?"); 457303231Sdim} 458303231Sdim 459344779Sdimbool TargetPassConfig::willCompleteCodeGenPipeline() { 460344779Sdim return StopBeforeOpt.empty() && StopAfterOpt.empty(); 461327952Sdim} 462327952Sdim 463344779Sdimbool TargetPassConfig::hasLimitedCodeGenPipeline() { 464344779Sdim return !StartBeforeOpt.empty() || !StartAfterOpt.empty() || 465344779Sdim !willCompleteCodeGenPipeline(); 466344779Sdim} 467344779Sdim 468327952Sdimstd::string 469327952SdimTargetPassConfig::getLimitedCodeGenPipelineReason(const char *Separator) const { 470327952Sdim if (!hasLimitedCodeGenPipeline()) 471327952Sdim return std::string(); 472327952Sdim std::string Res; 473327952Sdim static cl::opt<std::string> *PassNames[] = {&StartAfterOpt, &StartBeforeOpt, 474327952Sdim &StopAfterOpt, &StopBeforeOpt}; 475327952Sdim static const char *OptNames[] = {StartAfterOptName, StartBeforeOptName, 476327952Sdim StopAfterOptName, StopBeforeOptName}; 477327952Sdim bool IsFirst = true; 478327952Sdim for (int Idx = 0; Idx < 4; ++Idx) 479327952Sdim if (!PassNames[Idx]->empty()) { 480327952Sdim if (!IsFirst) 481327952Sdim Res += Separator; 482327952Sdim IsFirst = false; 483327952Sdim Res += OptNames[Idx]; 484327952Sdim } 485327952Sdim return Res; 486327952Sdim} 487327952Sdim 488303231Sdim// Helper to verify the analysis is really immutable. 489303231Sdimvoid TargetPassConfig::setOpt(bool &Opt, bool Val) { 490303231Sdim assert(!Initialized && "PassConfig is immutable"); 491303231Sdim Opt = Val; 492303231Sdim} 493303231Sdim 494303231Sdimvoid TargetPassConfig::substitutePass(AnalysisID StandardID, 495303231Sdim IdentifyingPassPtr TargetID) { 496303231Sdim Impl->TargetPasses[StandardID] = TargetID; 497303231Sdim} 498303231Sdim 499303231SdimIdentifyingPassPtr TargetPassConfig::getPassSubstitution(AnalysisID ID) const { 500303231Sdim DenseMap<AnalysisID, IdentifyingPassPtr>::const_iterator 501303231Sdim I = Impl->TargetPasses.find(ID); 502303231Sdim if (I == Impl->TargetPasses.end()) 503303231Sdim return ID; 504303231Sdim return I->second; 505303231Sdim} 506303231Sdim 507303231Sdimbool TargetPassConfig::isPassSubstitutedOrOverridden(AnalysisID ID) const { 508303231Sdim IdentifyingPassPtr TargetID = getPassSubstitution(ID); 509303231Sdim IdentifyingPassPtr FinalPtr = overridePass(ID, TargetID); 510303231Sdim return !FinalPtr.isValid() || FinalPtr.isInstance() || 511303231Sdim FinalPtr.getID() != ID; 512303231Sdim} 513303231Sdim 514303231Sdim/// Add a pass to the PassManager if that pass is supposed to be run. If the 515303231Sdim/// Started/Stopped flags indicate either that the compilation should start at 516303231Sdim/// a later pass or that it should stop after an earlier pass, then do not add 517303231Sdim/// the pass. Finally, compare the current pass against the StartAfter 518303231Sdim/// and StopAfter options and change the Started/Stopped flags accordingly. 519303231Sdimvoid TargetPassConfig::addPass(Pass *P, bool verifyAfter, bool printAfter) { 520303231Sdim assert(!Initialized && "PassConfig is immutable"); 521303231Sdim 522303231Sdim // Cache the Pass ID here in case the pass manager finds this pass is 523303231Sdim // redundant with ones already scheduled / available, and deletes it. 524303231Sdim // Fundamentally, once we add the pass to the manager, we no longer own it 525303231Sdim // and shouldn't reference it. 526303231Sdim AnalysisID PassID = P->getPassID(); 527303231Sdim 528344779Sdim if (StartBefore == PassID && StartBeforeCount++ == StartBeforeInstanceNum) 529303231Sdim Started = true; 530344779Sdim if (StopBefore == PassID && StopBeforeCount++ == StopBeforeInstanceNum) 531314564Sdim Stopped = true; 532303231Sdim if (Started && !Stopped) { 533303231Sdim std::string Banner; 534303231Sdim // Construct banner message before PM->add() as that may delete the pass. 535303231Sdim if (AddingMachinePasses && (printAfter || verifyAfter)) 536303231Sdim Banner = std::string("After ") + std::string(P->getPassName()); 537303231Sdim PM->add(P); 538303231Sdim if (AddingMachinePasses) { 539303231Sdim if (printAfter) 540303231Sdim addPrintPass(Banner); 541303231Sdim if (verifyAfter) 542303231Sdim addVerifyPass(Banner); 543303231Sdim } 544303231Sdim 545303231Sdim // Add the passes after the pass P if there is any. 546303231Sdim for (auto IP : Impl->InsertedPasses) { 547303231Sdim if (IP.TargetPassID == PassID) 548303231Sdim addPass(IP.getInsertedPass(), IP.VerifyAfter, IP.PrintAfter); 549303231Sdim } 550303231Sdim } else { 551303231Sdim delete P; 552303231Sdim } 553344779Sdim 554344779Sdim if (StopAfter == PassID && StopAfterCount++ == StopAfterInstanceNum) 555303231Sdim Stopped = true; 556344779Sdim 557344779Sdim if (StartAfter == PassID && StartAfterCount++ == StartAfterInstanceNum) 558303231Sdim Started = true; 559303231Sdim if (Stopped && !Started) 560303231Sdim report_fatal_error("Cannot stop compilation after pass that is not run"); 561303231Sdim} 562303231Sdim 563303231Sdim/// Add a CodeGen pass at this point in the pipeline after checking for target 564303231Sdim/// and command line overrides. 565303231Sdim/// 566303231Sdim/// addPass cannot return a pointer to the pass instance because is internal the 567303231Sdim/// PassManager and the instance we create here may already be freed. 568303231SdimAnalysisID TargetPassConfig::addPass(AnalysisID PassID, bool verifyAfter, 569303231Sdim bool printAfter) { 570303231Sdim IdentifyingPassPtr TargetID = getPassSubstitution(PassID); 571303231Sdim IdentifyingPassPtr FinalPtr = overridePass(PassID, TargetID); 572303231Sdim if (!FinalPtr.isValid()) 573303231Sdim return nullptr; 574303231Sdim 575303231Sdim Pass *P; 576303231Sdim if (FinalPtr.isInstance()) 577303231Sdim P = FinalPtr.getInstance(); 578303231Sdim else { 579303231Sdim P = Pass::createPass(FinalPtr.getID()); 580303231Sdim if (!P) 581303231Sdim llvm_unreachable("Pass ID not registered"); 582303231Sdim } 583303231Sdim AnalysisID FinalID = P->getPassID(); 584303231Sdim addPass(P, verifyAfter, printAfter); // Ends the lifetime of P. 585303231Sdim 586303231Sdim return FinalID; 587303231Sdim} 588303231Sdim 589303231Sdimvoid TargetPassConfig::printAndVerify(const std::string &Banner) { 590303231Sdim addPrintPass(Banner); 591303231Sdim addVerifyPass(Banner); 592303231Sdim} 593303231Sdim 594303231Sdimvoid TargetPassConfig::addPrintPass(const std::string &Banner) { 595303231Sdim if (TM->shouldPrintMachineCode()) 596303231Sdim PM->add(createMachineFunctionPrinterPass(dbgs(), Banner)); 597303231Sdim} 598303231Sdim 599303231Sdimvoid TargetPassConfig::addVerifyPass(const std::string &Banner) { 600344779Sdim bool Verify = VerifyMachineCode == cl::BOU_TRUE; 601321369Sdim#ifdef EXPENSIVE_CHECKS 602321369Sdim if (VerifyMachineCode == cl::BOU_UNSET) 603321369Sdim Verify = TM->isMachineVerifierClean(); 604321369Sdim#endif 605321369Sdim if (Verify) 606303231Sdim PM->add(createMachineVerifierPass(Banner)); 607303231Sdim} 608303231Sdim 609303231Sdim/// Add common target configurable passes that perform LLVM IR to IR transforms 610303231Sdim/// following machine independent optimization. 611303231Sdimvoid TargetPassConfig::addIRPasses() { 612303231Sdim switch (UseCFLAA) { 613303231Sdim case CFLAAType::Steensgaard: 614303231Sdim addPass(createCFLSteensAAWrapperPass()); 615303231Sdim break; 616303231Sdim case CFLAAType::Andersen: 617303231Sdim addPass(createCFLAndersAAWrapperPass()); 618303231Sdim break; 619303231Sdim case CFLAAType::Both: 620303231Sdim addPass(createCFLAndersAAWrapperPass()); 621303231Sdim addPass(createCFLSteensAAWrapperPass()); 622303231Sdim break; 623303231Sdim default: 624303231Sdim break; 625303231Sdim } 626303231Sdim 627303231Sdim // Basic AliasAnalysis support. 628303231Sdim // Add TypeBasedAliasAnalysis before BasicAliasAnalysis so that 629303231Sdim // BasicAliasAnalysis wins if they disagree. This is intended to help 630303231Sdim // support "obvious" type-punning idioms. 631303231Sdim addPass(createTypeBasedAAWrapperPass()); 632303231Sdim addPass(createScopedNoAliasAAWrapperPass()); 633303231Sdim addPass(createBasicAAWrapperPass()); 634303231Sdim 635303231Sdim // Before running any passes, run the verifier to determine if the input 636303231Sdim // coming from the front-end and/or optimizer is valid. 637303231Sdim if (!DisableVerify) 638303231Sdim addPass(createVerifierPass()); 639303231Sdim 640303231Sdim // Run loop strength reduction before anything else. 641303231Sdim if (getOptLevel() != CodeGenOpt::None && !DisableLSR) { 642303231Sdim addPass(createLoopStrengthReducePass()); 643303231Sdim if (PrintLSR) 644303231Sdim addPass(createPrintFunctionPass(dbgs(), "\n\n*** Code after LSR ***\n")); 645303231Sdim } 646303231Sdim 647327952Sdim if (getOptLevel() != CodeGenOpt::None) { 648327952Sdim // The MergeICmpsPass tries to create memcmp calls by grouping sequences of 649327952Sdim // loads and compares. ExpandMemCmpPass then tries to expand those calls 650327952Sdim // into optimally-sized loads and compares. The transforms are enabled by a 651327952Sdim // target lowering hook. 652341825Sdim if (!DisableMergeICmps) 653353358Sdim addPass(createMergeICmpsLegacyPass()); 654327952Sdim addPass(createExpandMemCmpPass()); 655327952Sdim } 656327952Sdim 657303231Sdim // Run GC lowering passes for builtin collectors 658303231Sdim // TODO: add a pass insertion point here 659303231Sdim addPass(createGCLoweringPass()); 660303231Sdim addPass(createShadowStackGCLoweringPass()); 661360784Sdim addPass(createLowerConstantIntrinsicsPass()); 662303231Sdim 663303231Sdim // Make sure that no unreachable blocks are instruction selected. 664303231Sdim addPass(createUnreachableBlockEliminationPass()); 665303231Sdim 666303231Sdim // Prepare expensive constants for SelectionDAG. 667303231Sdim if (getOptLevel() != CodeGenOpt::None && !DisableConstantHoisting) 668303231Sdim addPass(createConstantHoistingPass()); 669303231Sdim 670303231Sdim if (getOptLevel() != CodeGenOpt::None && !DisablePartialLibcallInlining) 671303231Sdim addPass(createPartiallyInlineLibCallsPass()); 672314564Sdim 673327952Sdim // Instrument function entry and exit, e.g. with calls to mcount(). 674327952Sdim addPass(createPostInlineEntryExitInstrumenterPass()); 675321369Sdim 676321369Sdim // Add scalarization of target's unsupported masked memory intrinsics pass. 677321369Sdim // the unsupported intrinsic will be replaced with a chain of basic blocks, 678321369Sdim // that stores/loads element one-by-one if the appropriate mask bit is set. 679321369Sdim addPass(createScalarizeMaskedMemIntrinPass()); 680321369Sdim 681321369Sdim // Expand reduction intrinsics into shuffle sequences if the target wants to. 682321369Sdim addPass(createExpandReductionsPass()); 683303231Sdim} 684303231Sdim 685303231Sdim/// Turn exception handling constructs into something the code generators can 686303231Sdim/// handle. 687303231Sdimvoid TargetPassConfig::addPassesToHandleExceptions() { 688314564Sdim const MCAsmInfo *MCAI = TM->getMCAsmInfo(); 689314564Sdim assert(MCAI && "No MCAsmInfo"); 690314564Sdim switch (MCAI->getExceptionHandlingType()) { 691303231Sdim case ExceptionHandling::SjLj: 692303231Sdim // SjLj piggy-backs on dwarf for this bit. The cleanups done apply to both 693303231Sdim // Dwarf EH prepare needs to be run after SjLj prepare. Otherwise, 694303231Sdim // catch info can get misplaced when a selector ends up more than one block 695303231Sdim // removed from the parent invoke(s). This could happen when a landing 696303231Sdim // pad is shared by multiple invokes and is also a target of a normal 697303231Sdim // edge from elsewhere. 698303231Sdim addPass(createSjLjEHPreparePass()); 699314564Sdim LLVM_FALLTHROUGH; 700303231Sdim case ExceptionHandling::DwarfCFI: 701303231Sdim case ExceptionHandling::ARM: 702321369Sdim addPass(createDwarfEHPass()); 703303231Sdim break; 704303231Sdim case ExceptionHandling::WinEH: 705303231Sdim // We support using both GCC-style and MSVC-style exceptions on Windows, so 706303231Sdim // add both preparation passes. Each pass will only actually run if it 707303231Sdim // recognizes the personality function. 708321369Sdim addPass(createWinEHPass()); 709321369Sdim addPass(createDwarfEHPass()); 710303231Sdim break; 711341825Sdim case ExceptionHandling::Wasm: 712341825Sdim // Wasm EH uses Windows EH instructions, but it does not need to demote PHIs 713341825Sdim // on catchpads and cleanuppads because it does not outline them into 714341825Sdim // funclets. Catchswitch blocks are not lowered in SelectionDAG, so we 715341825Sdim // should remove PHIs there. 716341825Sdim addPass(createWinEHPass(/*DemoteCatchSwitchPHIOnly=*/false)); 717341825Sdim addPass(createWasmEHPass()); 718341825Sdim break; 719303231Sdim case ExceptionHandling::None: 720303231Sdim addPass(createLowerInvokePass()); 721303231Sdim 722303231Sdim // The lower invoke pass may create unreachable code. Remove it. 723303231Sdim addPass(createUnreachableBlockEliminationPass()); 724303231Sdim break; 725303231Sdim } 726303231Sdim} 727303231Sdim 728303231Sdim/// Add pass to prepare the LLVM IR for code generation. This should be done 729303231Sdim/// before exception handling preparation passes. 730303231Sdimvoid TargetPassConfig::addCodeGenPrepare() { 731303231Sdim if (getOptLevel() != CodeGenOpt::None && !DisableCGP) 732321369Sdim addPass(createCodeGenPreparePass()); 733303231Sdim addPass(createRewriteSymbolsPass()); 734303231Sdim} 735303231Sdim 736303231Sdim/// Add common passes that perform LLVM IR to IR transforms in preparation for 737303231Sdim/// instruction selection. 738303231Sdimvoid TargetPassConfig::addISelPrepare() { 739303231Sdim addPreISel(); 740303231Sdim 741303231Sdim // Force codegen to run according to the callgraph. 742321369Sdim if (requiresCodeGenSCCOrder()) 743303231Sdim addPass(new DummyCGSCCPass); 744303231Sdim 745303231Sdim // Add both the safe stack and the stack protection passes: each of them will 746303231Sdim // only protect functions that have corresponding attributes. 747321369Sdim addPass(createSafeStackPass()); 748321369Sdim addPass(createStackProtectorPass()); 749303231Sdim 750303231Sdim if (PrintISelInput) 751303231Sdim addPass(createPrintFunctionPass( 752303231Sdim dbgs(), "\n\n*** Final LLVM Code input to ISel ***\n")); 753303231Sdim 754303231Sdim // All passes which modify the LLVM IR are now complete; run the verifier 755303231Sdim // to ensure that the IR is valid. 756303231Sdim if (!DisableVerify) 757303231Sdim addPass(createVerifierPass()); 758303231Sdim} 759303231Sdim 760321369Sdimbool TargetPassConfig::addCoreISelPasses() { 761341825Sdim // Enable FastISel with -fast-isel, but allow that to be overridden. 762321369Sdim TM->setO0WantsFastISel(EnableFastISelOption != cl::BOU_FALSE); 763344779Sdim 764344779Sdim // Determine an instruction selector. 765344779Sdim enum class SelectorType { SelectionDAG, FastISel, GlobalISel }; 766344779Sdim SelectorType Selector; 767344779Sdim 768344779Sdim if (EnableFastISelOption == cl::BOU_TRUE) 769344779Sdim Selector = SelectorType::FastISel; 770344779Sdim else if (EnableGlobalISelOption == cl::BOU_TRUE || 771344779Sdim (TM->Options.EnableGlobalISel && 772344779Sdim EnableGlobalISelOption != cl::BOU_FALSE)) 773344779Sdim Selector = SelectorType::GlobalISel; 774344779Sdim else if (TM->getOptLevel() == CodeGenOpt::None && TM->getO0WantsFastISel()) 775344779Sdim Selector = SelectorType::FastISel; 776344779Sdim else 777344779Sdim Selector = SelectorType::SelectionDAG; 778344779Sdim 779344779Sdim // Set consistently TM->Options.EnableFastISel and EnableGlobalISel. 780344779Sdim if (Selector == SelectorType::FastISel) { 781321369Sdim TM->setFastISel(true); 782344779Sdim TM->setGlobalISel(false); 783344779Sdim } else if (Selector == SelectorType::GlobalISel) { 784328753Sdim TM->setFastISel(false); 785344779Sdim TM->setGlobalISel(true); 786344779Sdim } 787328753Sdim 788344779Sdim // Add instruction selector passes. 789344779Sdim if (Selector == SelectorType::GlobalISel) { 790344779Sdim SaveAndRestore<bool> SavedAddingMachinePasses(AddingMachinePasses, true); 791321369Sdim if (addIRTranslator()) 792321369Sdim return true; 793321369Sdim 794321369Sdim addPreLegalizeMachineIR(); 795321369Sdim 796321369Sdim if (addLegalizeMachineIR()) 797321369Sdim return true; 798321369Sdim 799321369Sdim // Before running the register bank selector, ask the target if it 800321369Sdim // wants to run some passes. 801321369Sdim addPreRegBankSelect(); 802321369Sdim 803321369Sdim if (addRegBankSelect()) 804321369Sdim return true; 805321369Sdim 806321369Sdim addPreGlobalInstructionSelect(); 807321369Sdim 808321369Sdim if (addGlobalInstructionSelect()) 809321369Sdim return true; 810321369Sdim 811321369Sdim // Pass to reset the MachineFunction if the ISel failed. 812321369Sdim addPass(createResetMachineFunctionPass( 813321369Sdim reportDiagnosticWhenGlobalISelFallback(), isGlobalISelAbortEnabled())); 814321369Sdim 815321369Sdim // Provide a fallback path when we do not want to abort on 816321369Sdim // not-yet-supported input. 817321369Sdim if (!isGlobalISelAbortEnabled() && addInstSelector()) 818321369Sdim return true; 819321369Sdim 820321369Sdim } else if (addInstSelector()) 821321369Sdim return true; 822321369Sdim 823353358Sdim // Expand pseudo-instructions emitted by ISel. Don't run the verifier before 824353358Sdim // FinalizeISel. 825353358Sdim addPass(&FinalizeISelID); 826353358Sdim 827353358Sdim // Print the instruction selected machine code... 828353358Sdim printAndVerify("After Instruction Selection"); 829353358Sdim 830321369Sdim return false; 831321369Sdim} 832321369Sdim 833321369Sdimbool TargetPassConfig::addISelPasses() { 834341825Sdim if (TM->useEmulatedTLS()) 835321369Sdim addPass(createLowerEmuTLSPass()); 836321369Sdim 837321369Sdim addPass(createPreISelIntrinsicLoweringPass()); 838321369Sdim addPass(createTargetTransformInfoWrapperPass(TM->getTargetIRAnalysis())); 839321369Sdim addIRPasses(); 840321369Sdim addCodeGenPrepare(); 841321369Sdim addPassesToHandleExceptions(); 842321369Sdim addISelPrepare(); 843321369Sdim 844321369Sdim return addCoreISelPasses(); 845321369Sdim} 846321369Sdim 847321369Sdim/// -regalloc=... command line option. 848321369Sdimstatic FunctionPass *useDefaultRegisterAllocator() { return nullptr; } 849321369Sdimstatic cl::opt<RegisterRegAlloc::FunctionPassCtor, false, 850327952Sdim RegisterPassParser<RegisterRegAlloc>> 851327952Sdim RegAlloc("regalloc", cl::Hidden, cl::init(&useDefaultRegisterAllocator), 852327952Sdim cl::desc("Register allocator to use")); 853321369Sdim 854303231Sdim/// Add the complete set of target-independent postISel code generator passes. 855303231Sdim/// 856303231Sdim/// This can be read as the standard order of major LLVM CodeGen stages. Stages 857303231Sdim/// with nontrivial configuration or multiple passes are broken out below in 858303231Sdim/// add%Stage routines. 859303231Sdim/// 860303231Sdim/// Any TargetPassConfig::addXX routine may be overriden by the Target. The 861303231Sdim/// addPre/Post methods with empty header implementations allow injecting 862303231Sdim/// target-specific fixups just before or after major stages. Additionally, 863303231Sdim/// targets have the flexibility to change pass order within a stage by 864303231Sdim/// overriding default implementation of add%Stage routines below. Each 865303231Sdim/// technique has maintainability tradeoffs because alternate pass orders are 866303231Sdim/// not well supported. addPre/Post works better if the target pass is easily 867303231Sdim/// tied to a common pass. But if it has subtle dependencies on multiple passes, 868303231Sdim/// the target should override the stage instead. 869303231Sdim/// 870303231Sdim/// TODO: We could use a single addPre/Post(ID) hook to allow pass injection 871303231Sdim/// before/after any target-independent pass. But it's currently overkill. 872303231Sdimvoid TargetPassConfig::addMachinePasses() { 873303231Sdim AddingMachinePasses = true; 874303231Sdim 875303231Sdim // Insert a machine instr printer pass after the specified pass. 876344779Sdim StringRef PrintMachineInstrsPassName = PrintMachineInstrs.getValue(); 877344779Sdim if (!PrintMachineInstrsPassName.equals("") && 878344779Sdim !PrintMachineInstrsPassName.equals("option-unspecified")) { 879344779Sdim if (const PassInfo *TPI = getPassInfo(PrintMachineInstrsPassName)) { 880344779Sdim const PassRegistry *PR = PassRegistry::getPassRegistry(); 881344779Sdim const PassInfo *IPI = PR->getPassInfo(StringRef("machineinstr-printer")); 882344779Sdim assert(IPI && "failed to get \"machineinstr-printer\" PassInfo!"); 883344779Sdim const char *TID = (const char *)(TPI->getTypeInfo()); 884344779Sdim const char *IID = (const char *)(IPI->getTypeInfo()); 885344779Sdim insertPass(TID, IID); 886344779Sdim } 887303231Sdim } 888303231Sdim 889303231Sdim // Add passes that optimize machine instructions in SSA form. 890303231Sdim if (getOptLevel() != CodeGenOpt::None) { 891303231Sdim addMachineSSAOptimization(); 892303231Sdim } else { 893303231Sdim // If the target requests it, assign local variables to stack slots relative 894303231Sdim // to one another and simplify frame index references where possible. 895303231Sdim addPass(&LocalStackSlotAllocationID, false); 896303231Sdim } 897303231Sdim 898327952Sdim if (TM->Options.EnableIPRA) 899327952Sdim addPass(createRegUsageInfoPropPass()); 900327952Sdim 901303231Sdim // Run pre-ra passes. 902303231Sdim addPreRegAlloc(); 903303231Sdim 904303231Sdim // Run register allocation and passes that are tightly coupled with it, 905303231Sdim // including phi elimination and scheduling. 906303231Sdim if (getOptimizeRegAlloc()) 907353358Sdim addOptimizedRegAlloc(); 908353358Sdim else 909353358Sdim addFastRegAlloc(); 910303231Sdim 911303231Sdim // Run post-ra passes. 912303231Sdim addPostRegAlloc(); 913303231Sdim 914303231Sdim // Insert prolog/epilog code. Eliminate abstract frame index references... 915341825Sdim if (getOptLevel() != CodeGenOpt::None) { 916341825Sdim addPass(&PostRAMachineSinkingID); 917303231Sdim addPass(&ShrinkWrapID); 918341825Sdim } 919303231Sdim 920303231Sdim // Prolog/Epilog inserter needs a TargetMachine to instantiate. But only 921303231Sdim // do so if it hasn't been disabled, substituted, or overridden. 922303231Sdim if (!isPassSubstitutedOrOverridden(&PrologEpilogCodeInserterID)) 923321369Sdim addPass(createPrologEpilogInserterPass()); 924303231Sdim 925303231Sdim /// Add passes that optimize machine instructions after register allocation. 926303231Sdim if (getOptLevel() != CodeGenOpt::None) 927303231Sdim addMachineLateOptimization(); 928303231Sdim 929303231Sdim // Expand pseudo instructions before second scheduling pass. 930303231Sdim addPass(&ExpandPostRAPseudosID); 931303231Sdim 932303231Sdim // Run pre-sched2 passes. 933303231Sdim addPreSched2(); 934303231Sdim 935303231Sdim if (EnableImplicitNullChecks) 936303231Sdim addPass(&ImplicitNullChecksID); 937303231Sdim 938303231Sdim // Second pass scheduler. 939303231Sdim // Let Target optionally insert this pass by itself at some other 940303231Sdim // point. 941303231Sdim if (getOptLevel() != CodeGenOpt::None && 942303231Sdim !TM->targetSchedulesPostRAScheduling()) { 943303231Sdim if (MISchedPostRA) 944303231Sdim addPass(&PostMachineSchedulerID); 945303231Sdim else 946303231Sdim addPass(&PostRASchedulerID); 947303231Sdim } 948303231Sdim 949303231Sdim // GC 950303231Sdim if (addGCPasses()) { 951303231Sdim if (PrintGCInfo) 952303231Sdim addPass(createGCInfoPrinter(dbgs()), false, false); 953303231Sdim } 954303231Sdim 955303231Sdim // Basic block placement. 956303231Sdim if (getOptLevel() != CodeGenOpt::None) 957303231Sdim addBlockPlacement(); 958303231Sdim 959360784Sdim // Insert before XRay Instrumentation. 960360784Sdim addPass(&FEntryInserterID, false); 961360784Sdim 962360784Sdim addPass(&XRayInstrumentationID, false); 963360784Sdim addPass(&PatchableFunctionID, false); 964360784Sdim 965303231Sdim addPreEmitPass(); 966303231Sdim 967303231Sdim if (TM->Options.EnableIPRA) 968303231Sdim // Collect register usage information and produce a register mask of 969303231Sdim // clobbered registers, to be used to optimize call sites. 970303231Sdim addPass(createRegUsageInfoCollector()); 971303231Sdim 972303231Sdim addPass(&FuncletLayoutID, false); 973303231Sdim 974303231Sdim addPass(&StackMapLivenessID, false); 975303231Sdim addPass(&LiveDebugValuesID, false); 976303231Sdim 977341825Sdim if (TM->Options.EnableMachineOutliner && getOptLevel() != CodeGenOpt::None && 978341825Sdim EnableMachineOutliner != NeverOutline) { 979341825Sdim bool RunOnAllFunctions = (EnableMachineOutliner == AlwaysOutline); 980341825Sdim bool AddOutliner = RunOnAllFunctions || 981341825Sdim TM->Options.SupportsDefaultOutlining; 982341825Sdim if (AddOutliner) 983341825Sdim addPass(createMachineOutlinerPass(RunOnAllFunctions)); 984341825Sdim } 985321369Sdim 986328817Sdim // Add passes that directly emit MI after all other MI passes. 987328817Sdim addPreEmitPass2(); 988328817Sdim 989303231Sdim AddingMachinePasses = false; 990303231Sdim} 991303231Sdim 992303231Sdim/// Add passes that optimize machine instructions in SSA form. 993303231Sdimvoid TargetPassConfig::addMachineSSAOptimization() { 994303231Sdim // Pre-ra tail duplication. 995303231Sdim addPass(&EarlyTailDuplicateID); 996303231Sdim 997303231Sdim // Optimize PHIs before DCE: removing dead PHI cycles may make more 998303231Sdim // instructions dead. 999303231Sdim addPass(&OptimizePHIsID, false); 1000303231Sdim 1001303231Sdim // This pass merges large allocas. StackSlotColoring is a different pass 1002303231Sdim // which merges spill slots. 1003303231Sdim addPass(&StackColoringID, false); 1004303231Sdim 1005303231Sdim // If the target requests it, assign local variables to stack slots relative 1006303231Sdim // to one another and simplify frame index references where possible. 1007303231Sdim addPass(&LocalStackSlotAllocationID, false); 1008303231Sdim 1009303231Sdim // With optimization, dead code should already be eliminated. However 1010303231Sdim // there is one known exception: lowered code for arguments that are only 1011303231Sdim // used by tail calls, where the tail calls reuse the incoming stack 1012303231Sdim // arguments directly (see t11 in test/CodeGen/X86/sibcall.ll). 1013303231Sdim addPass(&DeadMachineInstructionElimID); 1014303231Sdim 1015303231Sdim // Allow targets to insert passes that improve instruction level parallelism, 1016303231Sdim // like if-conversion. Such passes will typically need dominator trees and 1017303231Sdim // loop info, just like LICM and CSE below. 1018303231Sdim addILPOpts(); 1019303231Sdim 1020341825Sdim addPass(&EarlyMachineLICMID, false); 1021303231Sdim addPass(&MachineCSEID, false); 1022321369Sdim 1023303231Sdim addPass(&MachineSinkingID); 1024303231Sdim 1025303231Sdim addPass(&PeepholeOptimizerID); 1026303231Sdim // Clean-up the dead code that may have been generated by peephole 1027303231Sdim // rewriting. 1028303231Sdim addPass(&DeadMachineInstructionElimID); 1029303231Sdim} 1030303231Sdim 1031303231Sdim//===---------------------------------------------------------------------===// 1032303231Sdim/// Register Allocation Pass Configuration 1033303231Sdim//===---------------------------------------------------------------------===// 1034303231Sdim 1035303231Sdimbool TargetPassConfig::getOptimizeRegAlloc() const { 1036303231Sdim switch (OptimizeRegAlloc) { 1037303231Sdim case cl::BOU_UNSET: return getOptLevel() != CodeGenOpt::None; 1038303231Sdim case cl::BOU_TRUE: return true; 1039303231Sdim case cl::BOU_FALSE: return false; 1040303231Sdim } 1041303231Sdim llvm_unreachable("Invalid optimize-regalloc state"); 1042303231Sdim} 1043303231Sdim 1044303231Sdim/// A dummy default pass factory indicates whether the register allocator is 1045303231Sdim/// overridden on the command line. 1046321369Sdimstatic llvm::once_flag InitializeDefaultRegisterAllocatorFlag; 1047321369Sdim 1048303231Sdimstatic RegisterRegAlloc 1049303231SdimdefaultRegAlloc("default", 1050303231Sdim "pick register allocator based on -O option", 1051303231Sdim useDefaultRegisterAllocator); 1052303231Sdim 1053303231Sdimstatic void initializeDefaultRegisterAllocatorOnce() { 1054353358Sdim if (!RegisterRegAlloc::getDefault()) 1055303231Sdim RegisterRegAlloc::setDefault(RegAlloc); 1056303231Sdim} 1057303231Sdim 1058303231Sdim/// Instantiate the default register allocator pass for this target for either 1059303231Sdim/// the optimized or unoptimized allocation path. This will be added to the pass 1060303231Sdim/// manager by addFastRegAlloc in the unoptimized case or addOptimizedRegAlloc 1061303231Sdim/// in the optimized case. 1062303231Sdim/// 1063303231Sdim/// A target that uses the standard regalloc pass order for fast or optimized 1064303231Sdim/// allocation may still override this for per-target regalloc 1065303231Sdim/// selection. But -regalloc=... always takes precedence. 1066303231SdimFunctionPass *TargetPassConfig::createTargetRegisterAllocator(bool Optimized) { 1067303231Sdim if (Optimized) 1068303231Sdim return createGreedyRegisterAllocator(); 1069303231Sdim else 1070303231Sdim return createFastRegisterAllocator(); 1071303231Sdim} 1072303231Sdim 1073303231Sdim/// Find and instantiate the register allocation pass requested by this target 1074303231Sdim/// at the current optimization level. Different register allocators are 1075303231Sdim/// defined as separate passes because they may require different analysis. 1076303231Sdim/// 1077303231Sdim/// This helper ensures that the regalloc= option is always available, 1078303231Sdim/// even for targets that override the default allocator. 1079303231Sdim/// 1080303231Sdim/// FIXME: When MachinePassRegistry register pass IDs instead of function ptrs, 1081303231Sdim/// this can be folded into addPass. 1082303231SdimFunctionPass *TargetPassConfig::createRegAllocPass(bool Optimized) { 1083303231Sdim // Initialize the global default. 1084303231Sdim llvm::call_once(InitializeDefaultRegisterAllocatorFlag, 1085303231Sdim initializeDefaultRegisterAllocatorOnce); 1086303231Sdim 1087303231Sdim RegisterRegAlloc::FunctionPassCtor Ctor = RegisterRegAlloc::getDefault(); 1088303231Sdim if (Ctor != useDefaultRegisterAllocator) 1089303231Sdim return Ctor(); 1090303231Sdim 1091303231Sdim // With no -regalloc= override, ask the target for a regalloc pass. 1092303231Sdim return createTargetRegisterAllocator(Optimized); 1093303231Sdim} 1094303231Sdim 1095353358Sdimbool TargetPassConfig::addRegAssignmentFast() { 1096353358Sdim if (RegAlloc != &useDefaultRegisterAllocator && 1097353358Sdim RegAlloc != &createFastRegisterAllocator) 1098353358Sdim report_fatal_error("Must use fast (default) register allocator for unoptimized regalloc."); 1099353358Sdim 1100353358Sdim addPass(createRegAllocPass(false)); 1101353358Sdim return true; 1102353358Sdim} 1103353358Sdim 1104353358Sdimbool TargetPassConfig::addRegAssignmentOptimized() { 1105353358Sdim // Add the selected register allocation pass. 1106353358Sdim addPass(createRegAllocPass(true)); 1107353358Sdim 1108353358Sdim // Allow targets to change the register assignments before rewriting. 1109353358Sdim addPreRewrite(); 1110353358Sdim 1111353358Sdim // Finally rewrite virtual registers. 1112353358Sdim addPass(&VirtRegRewriterID); 1113353358Sdim // Perform stack slot coloring and post-ra machine LICM. 1114353358Sdim // 1115353358Sdim // FIXME: Re-enable coloring with register when it's capable of adding 1116353358Sdim // kill markers. 1117353358Sdim addPass(&StackSlotColoringID); 1118353358Sdim 1119353358Sdim return true; 1120353358Sdim} 1121353358Sdim 1122303231Sdim/// Return true if the default global register allocator is in use and 1123303231Sdim/// has not be overriden on the command line with '-regalloc=...' 1124303231Sdimbool TargetPassConfig::usingDefaultRegAlloc() const { 1125303231Sdim return RegAlloc.getNumOccurrences() == 0; 1126303231Sdim} 1127303231Sdim 1128303231Sdim/// Add the minimum set of target-independent passes that are required for 1129303231Sdim/// register allocation. No coalescing or scheduling. 1130353358Sdimvoid TargetPassConfig::addFastRegAlloc() { 1131303231Sdim addPass(&PHIEliminationID, false); 1132303231Sdim addPass(&TwoAddressInstructionPassID, false); 1133303231Sdim 1134353358Sdim addRegAssignmentFast(); 1135303231Sdim} 1136303231Sdim 1137303231Sdim/// Add standard target-independent passes that are tightly coupled with 1138303231Sdim/// optimized register allocation, including coalescing, machine instruction 1139303231Sdim/// scheduling, and register allocation itself. 1140353358Sdimvoid TargetPassConfig::addOptimizedRegAlloc() { 1141303231Sdim addPass(&DetectDeadLanesID, false); 1142303231Sdim 1143303231Sdim addPass(&ProcessImplicitDefsID, false); 1144303231Sdim 1145303231Sdim // LiveVariables currently requires pure SSA form. 1146303231Sdim // 1147303231Sdim // FIXME: Once TwoAddressInstruction pass no longer uses kill flags, 1148303231Sdim // LiveVariables can be removed completely, and LiveIntervals can be directly 1149303231Sdim // computed. (We still either need to regenerate kill flags after regalloc, or 1150303231Sdim // preferably fix the scavenger to not depend on them). 1151303231Sdim addPass(&LiveVariablesID, false); 1152303231Sdim 1153303231Sdim // Edge splitting is smarter with machine loop info. 1154303231Sdim addPass(&MachineLoopInfoID, false); 1155303231Sdim addPass(&PHIEliminationID, false); 1156303231Sdim 1157303231Sdim // Eventually, we want to run LiveIntervals before PHI elimination. 1158303231Sdim if (EarlyLiveIntervals) 1159303231Sdim addPass(&LiveIntervalsID, false); 1160303231Sdim 1161303231Sdim addPass(&TwoAddressInstructionPassID, false); 1162303231Sdim addPass(&RegisterCoalescerID); 1163303231Sdim 1164303231Sdim // The machine scheduler may accidentally create disconnected components 1165303231Sdim // when moving subregister definitions around, avoid this by splitting them to 1166303231Sdim // separate vregs before. Splitting can also improve reg. allocation quality. 1167303231Sdim addPass(&RenameIndependentSubregsID); 1168303231Sdim 1169303231Sdim // PreRA instruction scheduling. 1170303231Sdim addPass(&MachineSchedulerID); 1171303231Sdim 1172353358Sdim if (addRegAssignmentOptimized()) { 1173353358Sdim // Allow targets to expand pseudo instructions depending on the choice of 1174353358Sdim // registers before MachineCopyPropagation. 1175353358Sdim addPostRewrite(); 1176303231Sdim 1177341825Sdim // Copy propagate to forward register uses and try to eliminate COPYs that 1178341825Sdim // were not coalesced. 1179341825Sdim addPass(&MachineCopyPropagationID); 1180341825Sdim 1181303231Sdim // Run post-ra machine LICM to hoist reloads / remats. 1182303231Sdim // 1183303231Sdim // FIXME: can this move into MachineLateOptimization? 1184341825Sdim addPass(&MachineLICMID); 1185303231Sdim } 1186303231Sdim} 1187303231Sdim 1188303231Sdim//===---------------------------------------------------------------------===// 1189303231Sdim/// Post RegAlloc Pass Configuration 1190303231Sdim//===---------------------------------------------------------------------===// 1191303231Sdim 1192303231Sdim/// Add passes that optimize machine instructions after register allocation. 1193303231Sdimvoid TargetPassConfig::addMachineLateOptimization() { 1194303231Sdim // Branch folding must be run after regalloc and prolog/epilog insertion. 1195303231Sdim addPass(&BranchFolderPassID); 1196303231Sdim 1197303231Sdim // Tail duplication. 1198303231Sdim // Note that duplicating tail just increases code size and degrades 1199303231Sdim // performance for targets that require Structured Control Flow. 1200303231Sdim // In addition it can also make CFG irreducible. Thus we disable it. 1201303231Sdim if (!TM->requiresStructuredCFG()) 1202303231Sdim addPass(&TailDuplicateID); 1203303231Sdim 1204303231Sdim // Copy propagation. 1205303231Sdim addPass(&MachineCopyPropagationID); 1206303231Sdim} 1207303231Sdim 1208303231Sdim/// Add standard GC passes. 1209303231Sdimbool TargetPassConfig::addGCPasses() { 1210303231Sdim addPass(&GCMachineCodeAnalysisID, false); 1211303231Sdim return true; 1212303231Sdim} 1213303231Sdim 1214303231Sdim/// Add standard basic block placement passes. 1215303231Sdimvoid TargetPassConfig::addBlockPlacement() { 1216303231Sdim if (addPass(&MachineBlockPlacementID)) { 1217303231Sdim // Run a separate pass to collect block placement statistics. 1218303231Sdim if (EnableBlockPlacementStats) 1219303231Sdim addPass(&MachineBlockPlacementStatsID); 1220303231Sdim } 1221303231Sdim} 1222314564Sdim 1223314564Sdim//===---------------------------------------------------------------------===// 1224314564Sdim/// GlobalISel Configuration 1225314564Sdim//===---------------------------------------------------------------------===// 1226314564Sdimbool TargetPassConfig::isGlobalISelAbortEnabled() const { 1227344779Sdim return TM->Options.GlobalISelAbort == GlobalISelAbortMode::Enable; 1228314564Sdim} 1229314564Sdim 1230314564Sdimbool TargetPassConfig::reportDiagnosticWhenGlobalISelFallback() const { 1231344779Sdim return TM->Options.GlobalISelAbort == GlobalISelAbortMode::DisableWithDiag; 1232314564Sdim} 1233353358Sdim 1234353358Sdimbool TargetPassConfig::isGISelCSEEnabled() const { 1235353358Sdim return true; 1236353358Sdim} 1237353358Sdim 1238353358Sdimstd::unique_ptr<CSEConfigBase> TargetPassConfig::getCSEConfig() const { 1239360784Sdim return std::make_unique<CSEConfigBase>(); 1240353358Sdim} 1241