SelectionDAGISel.cpp revision 239462
1181624Skmacy//===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===// 2181624Skmacy// 3181624Skmacy// The LLVM Compiler Infrastructure 4181624Skmacy// 5181624Skmacy// This file is distributed under the University of Illinois Open Source 6181624Skmacy// License. See LICENSE.TXT for details. 7181624Skmacy// 8181624Skmacy//===----------------------------------------------------------------------===// 9181624Skmacy// 10181624Skmacy// This implements the SelectionDAGISel class. 11181624Skmacy// 12181624Skmacy//===----------------------------------------------------------------------===// 13181624Skmacy 14181624Skmacy#define DEBUG_TYPE "isel" 15181624Skmacy#include "ScheduleDAGSDNodes.h" 16181624Skmacy#include "SelectionDAGBuilder.h" 17181624Skmacy#include "llvm/Constants.h" 18181624Skmacy#include "llvm/DebugInfo.h" 19181624Skmacy#include "llvm/Function.h" 20181624Skmacy#include "llvm/InlineAsm.h" 21181624Skmacy#include "llvm/Instructions.h" 22181624Skmacy#include "llvm/Intrinsics.h" 23181624Skmacy#include "llvm/IntrinsicInst.h" 24181624Skmacy#include "llvm/LLVMContext.h" 25181624Skmacy#include "llvm/Module.h" 26181624Skmacy#include "llvm/Analysis/AliasAnalysis.h" 27251767Sgibbs#include "llvm/Analysis/BranchProbabilityInfo.h" 28251767Sgibbs#include "llvm/CodeGen/FastISel.h" 29181624Skmacy#include "llvm/CodeGen/FunctionLoweringInfo.h" 30181624Skmacy#include "llvm/CodeGen/GCStrategy.h" 31181624Skmacy#include "llvm/CodeGen/GCMetadata.h" 32183340Skmacy#include "llvm/CodeGen/MachineFrameInfo.h" 33183340Skmacy#include "llvm/CodeGen/MachineFunction.h" 34183340Skmacy#include "llvm/CodeGen/MachineInstrBuilder.h" 35183340Skmacy#include "llvm/CodeGen/MachineModuleInfo.h" 36183340Skmacy#include "llvm/CodeGen/MachineRegisterInfo.h" 37251767Sgibbs#include "llvm/CodeGen/ScheduleHazardRecognizer.h" 38183340Skmacy#include "llvm/CodeGen/SchedulerRegistry.h" 39183340Skmacy#include "llvm/CodeGen/SelectionDAG.h" 40183340Skmacy#include "llvm/CodeGen/SelectionDAGISel.h" 41183340Skmacy#include "llvm/Target/TargetRegisterInfo.h" 42183340Skmacy#include "llvm/Target/TargetIntrinsicInfo.h" 43183340Skmacy#include "llvm/Target/TargetInstrInfo.h" 44183340Skmacy#include "llvm/Target/TargetLibraryInfo.h" 45183340Skmacy#include "llvm/Target/TargetLowering.h" 46183340Skmacy#include "llvm/Target/TargetMachine.h" 47251767Sgibbs#include "llvm/Target/TargetOptions.h" 48183340Skmacy#include "llvm/Transforms/Utils/BasicBlockUtils.h" 49183340Skmacy#include "llvm/Support/Compiler.h" 50183340Skmacy#include "llvm/Support/Debug.h" 51251767Sgibbs#include "llvm/Support/ErrorHandling.h" 52183340Skmacy#include "llvm/Support/Timer.h" 53181624Skmacy#include "llvm/Support/raw_ostream.h" 54251767Sgibbs#include "llvm/ADT/PostOrderIterator.h" 55181624Skmacy#include "llvm/ADT/Statistic.h" 56251767Sgibbs#include <algorithm> 57181624Skmacyusing namespace llvm; 58181624Skmacy 59181624SkmacySTATISTIC(NumFastIselFailures, "Number of instructions fast isel failed on"); 60181624SkmacySTATISTIC(NumFastIselSuccess, "Number of instructions fast isel selected"); 61181624SkmacySTATISTIC(NumFastIselBlocks, "Number of blocks selected entirely by fast isel"); 62181624SkmacySTATISTIC(NumDAGBlocks, "Number of blocks selected using DAG"); 63181624SkmacySTATISTIC(NumDAGIselRetries,"Number of times dag isel has to try another path"); 64181624Skmacy 65181624Skmacy#ifndef NDEBUG 66181624Skmacystatic cl::opt<bool> 67181624SkmacyEnableFastISelVerbose2("fast-isel-verbose2", cl::Hidden, 68251767Sgibbs cl::desc("Enable extra verbose messages in the \"fast\" " 69251767Sgibbs "instruction selector")); 70251767Sgibbs // Terminators 71251767SgibbsSTATISTIC(NumFastIselFailRet,"Fast isel fails on Ret"); 72251767SgibbsSTATISTIC(NumFastIselFailBr,"Fast isel fails on Br"); 73181624SkmacySTATISTIC(NumFastIselFailSwitch,"Fast isel fails on Switch"); 74181624SkmacySTATISTIC(NumFastIselFailIndirectBr,"Fast isel fails on IndirectBr"); 75181624SkmacySTATISTIC(NumFastIselFailInvoke,"Fast isel fails on Invoke"); 76181624SkmacySTATISTIC(NumFastIselFailResume,"Fast isel fails on Resume"); 77181624SkmacySTATISTIC(NumFastIselFailUnreachable,"Fast isel fails on Unreachable"); 78181624Skmacy 79181624Skmacy // Standard binary operators... 80181624SkmacySTATISTIC(NumFastIselFailAdd,"Fast isel fails on Add"); 81181624SkmacySTATISTIC(NumFastIselFailFAdd,"Fast isel fails on FAdd"); 82251767SgibbsSTATISTIC(NumFastIselFailSub,"Fast isel fails on Sub"); 83251767SgibbsSTATISTIC(NumFastIselFailFSub,"Fast isel fails on FSub"); 84181624SkmacySTATISTIC(NumFastIselFailMul,"Fast isel fails on Mul"); 85181624SkmacySTATISTIC(NumFastIselFailFMul,"Fast isel fails on FMul"); 86181624SkmacySTATISTIC(NumFastIselFailUDiv,"Fast isel fails on UDiv"); 87181624SkmacySTATISTIC(NumFastIselFailSDiv,"Fast isel fails on SDiv"); 88181624SkmacySTATISTIC(NumFastIselFailFDiv,"Fast isel fails on FDiv"); 89181624SkmacySTATISTIC(NumFastIselFailURem,"Fast isel fails on URem"); 90251767SgibbsSTATISTIC(NumFastIselFailSRem,"Fast isel fails on SRem"); 91251767SgibbsSTATISTIC(NumFastIselFailFRem,"Fast isel fails on FRem"); 92251767Sgibbs 93251767Sgibbs // Logical operators... 94251767SgibbsSTATISTIC(NumFastIselFailAnd,"Fast isel fails on And"); 95251767SgibbsSTATISTIC(NumFastIselFailOr,"Fast isel fails on Or"); 96251767SgibbsSTATISTIC(NumFastIselFailXor,"Fast isel fails on Xor"); 97251767Sgibbs 98251767Sgibbs // Memory instructions... 99251767SgibbsSTATISTIC(NumFastIselFailAlloca,"Fast isel fails on Alloca"); 100251767SgibbsSTATISTIC(NumFastIselFailLoad,"Fast isel fails on Load"); 101251767SgibbsSTATISTIC(NumFastIselFailStore,"Fast isel fails on Store"); 102181624SkmacySTATISTIC(NumFastIselFailAtomicCmpXchg,"Fast isel fails on AtomicCmpXchg"); 103251767SgibbsSTATISTIC(NumFastIselFailAtomicRMW,"Fast isel fails on AtomicRWM"); 104181624SkmacySTATISTIC(NumFastIselFailFence,"Fast isel fails on Frence"); 105181624SkmacySTATISTIC(NumFastIselFailGetElementPtr,"Fast isel fails on GetElementPtr"); 106181624Skmacy 107181624Skmacy // Convert instructions... 108181624SkmacySTATISTIC(NumFastIselFailTrunc,"Fast isel fails on Trunc"); 109181624SkmacySTATISTIC(NumFastIselFailZExt,"Fast isel fails on ZExt"); 110181624SkmacySTATISTIC(NumFastIselFailSExt,"Fast isel fails on SExt"); 111181624SkmacySTATISTIC(NumFastIselFailFPTrunc,"Fast isel fails on FPTrunc"); 112181624SkmacySTATISTIC(NumFastIselFailFPExt,"Fast isel fails on FPExt"); 113181624SkmacySTATISTIC(NumFastIselFailFPToUI,"Fast isel fails on FPToUI"); 114181624SkmacySTATISTIC(NumFastIselFailFPToSI,"Fast isel fails on FPToSI"); 115181624SkmacySTATISTIC(NumFastIselFailUIToFP,"Fast isel fails on UIToFP"); 116181624SkmacySTATISTIC(NumFastIselFailSIToFP,"Fast isel fails on SIToFP"); 117181624SkmacySTATISTIC(NumFastIselFailIntToPtr,"Fast isel fails on IntToPtr"); 118181624SkmacySTATISTIC(NumFastIselFailPtrToInt,"Fast isel fails on PtrToInt"); 119181624SkmacySTATISTIC(NumFastIselFailBitCast,"Fast isel fails on BitCast"); 120181624Skmacy 121181624Skmacy // Other instructions... 122181624SkmacySTATISTIC(NumFastIselFailICmp,"Fast isel fails on ICmp"); 123181624SkmacySTATISTIC(NumFastIselFailFCmp,"Fast isel fails on FCmp"); 124181624SkmacySTATISTIC(NumFastIselFailPHI,"Fast isel fails on PHI"); 125181624SkmacySTATISTIC(NumFastIselFailSelect,"Fast isel fails on Select"); 126181624SkmacySTATISTIC(NumFastIselFailCall,"Fast isel fails on Call"); 127181624SkmacySTATISTIC(NumFastIselFailShl,"Fast isel fails on Shl"); 128181624SkmacySTATISTIC(NumFastIselFailLShr,"Fast isel fails on LShr"); 129181624SkmacySTATISTIC(NumFastIselFailAShr,"Fast isel fails on AShr"); 130181624SkmacySTATISTIC(NumFastIselFailVAArg,"Fast isel fails on VAArg"); 131181624SkmacySTATISTIC(NumFastIselFailExtractElement,"Fast isel fails on ExtractElement"); 132181624SkmacySTATISTIC(NumFastIselFailInsertElement,"Fast isel fails on InsertElement"); 133181624SkmacySTATISTIC(NumFastIselFailShuffleVector,"Fast isel fails on ShuffleVector"); 134181624SkmacySTATISTIC(NumFastIselFailExtractValue,"Fast isel fails on ExtractValue"); 135181624SkmacySTATISTIC(NumFastIselFailInsertValue,"Fast isel fails on InsertValue"); 136181624SkmacySTATISTIC(NumFastIselFailLandingPad,"Fast isel fails on LandingPad"); 137181624Skmacy#endif 138181624Skmacy 139181624Skmacystatic cl::opt<bool> 140181624SkmacyEnableFastISelVerbose("fast-isel-verbose", cl::Hidden, 141181624Skmacy cl::desc("Enable verbose messages in the \"fast\" " 142181624Skmacy "instruction selector")); 143181624Skmacystatic cl::opt<bool> 144181624SkmacyEnableFastISelAbort("fast-isel-abort", cl::Hidden, 145181624Skmacy cl::desc("Enable abort calls when \"fast\" instruction fails")); 146181624Skmacy 147181624Skmacystatic cl::opt<bool> 148181624SkmacyUseMBPI("use-mbpi", 149181624Skmacy cl::desc("use Machine Branch Probability Info"), 150181624Skmacy cl::init(true), cl::Hidden); 151181624Skmacy 152181624Skmacy#ifndef NDEBUG 153181624Skmacystatic cl::opt<bool> 154181624SkmacyViewDAGCombine1("view-dag-combine1-dags", cl::Hidden, 155181624Skmacy cl::desc("Pop up a window to show dags before the first " 156181624Skmacy "dag combine pass")); 157181624Skmacystatic cl::opt<bool> 158181624SkmacyViewLegalizeTypesDAGs("view-legalize-types-dags", cl::Hidden, 159181624Skmacy cl::desc("Pop up a window to show dags before legalize types")); 160181624Skmacystatic cl::opt<bool> 161181624SkmacyViewLegalizeDAGs("view-legalize-dags", cl::Hidden, 162181624Skmacy cl::desc("Pop up a window to show dags before legalize")); 163181624Skmacystatic cl::opt<bool> 164181624SkmacyViewDAGCombine2("view-dag-combine2-dags", cl::Hidden, 165181624Skmacy cl::desc("Pop up a window to show dags before the second " 166181624Skmacy "dag combine pass")); 167181624Skmacystatic cl::opt<bool> 168181624SkmacyViewDAGCombineLT("view-dag-combine-lt-dags", cl::Hidden, 169181624Skmacy cl::desc("Pop up a window to show dags before the post legalize types" 170251767Sgibbs " dag combine pass")); 171181624Skmacystatic cl::opt<bool> 172181624SkmacyViewISelDAGs("view-isel-dags", cl::Hidden, 173181624Skmacy cl::desc("Pop up a window to show isel dags as they are selected")); 174181624Skmacystatic cl::opt<bool> 175181624SkmacyViewSchedDAGs("view-sched-dags", cl::Hidden, 176181624Skmacy cl::desc("Pop up a window to show sched dags as they are processed")); 177181624Skmacystatic cl::opt<bool> 178181624SkmacyViewSUnitDAGs("view-sunit-dags", cl::Hidden, 179181624Skmacy cl::desc("Pop up a window to show SUnit dags after they are processed")); 180181624Skmacy#else 181181624Skmacystatic const bool ViewDAGCombine1 = false, 182181624Skmacy ViewLegalizeTypesDAGs = false, ViewLegalizeDAGs = false, 183181624Skmacy ViewDAGCombine2 = false, 184181624Skmacy ViewDAGCombineLT = false, 185181624Skmacy ViewISelDAGs = false, ViewSchedDAGs = false, 186181624Skmacy ViewSUnitDAGs = false; 187181624Skmacy#endif 188181624Skmacy 189181624Skmacy//===---------------------------------------------------------------------===// 190181624Skmacy/// 191181624Skmacy/// RegisterScheduler class - Track the registration of instruction schedulers. 192181624Skmacy/// 193181624Skmacy//===---------------------------------------------------------------------===// 194181624SkmacyMachinePassRegistry RegisterScheduler::Registry; 195181624Skmacy 196181624Skmacy//===---------------------------------------------------------------------===// 197181624Skmacy/// 198251767Sgibbs/// ISHeuristic command line option for instruction schedulers. 199251767Sgibbs/// 200251767Sgibbs//===---------------------------------------------------------------------===// 201251767Sgibbsstatic cl::opt<RegisterScheduler::FunctionPassCtor, false, 202251767Sgibbs RegisterPassParser<RegisterScheduler> > 203251767SgibbsISHeuristic("pre-RA-sched", 204251767Sgibbs cl::init(&createDefaultScheduler), 205251767Sgibbs cl::desc("Instruction schedulers available (before register" 206251767Sgibbs " allocation):")); 207251767Sgibbs 208251767Sgibbsstatic RegisterScheduler 209251767SgibbsdefaultListDAGScheduler("default", "Best scheduler for the target", 210251767Sgibbs createDefaultScheduler); 211251767Sgibbs 212251767Sgibbsnamespace llvm { 213251767Sgibbs //===--------------------------------------------------------------------===// 214251767Sgibbs /// createDefaultScheduler - This creates an instruction scheduler appropriate 215251767Sgibbs /// for the target. 216181624Skmacy ScheduleDAGSDNodes* createDefaultScheduler(SelectionDAGISel *IS, 217181624Skmacy CodeGenOpt::Level OptLevel) { 218181624Skmacy const TargetLowering &TLI = IS->getTargetLowering(); 219181624Skmacy 220181624Skmacy if (OptLevel == CodeGenOpt::None || 221181624Skmacy TLI.getSchedulingPreference() == Sched::Source) 222181624Skmacy return createSourceListDAGScheduler(IS, OptLevel); 223181624Skmacy if (TLI.getSchedulingPreference() == Sched::RegPressure) 224181624Skmacy return createBURRListDAGScheduler(IS, OptLevel); 225181624Skmacy if (TLI.getSchedulingPreference() == Sched::Hybrid) 226181624Skmacy return createHybridListDAGScheduler(IS, OptLevel); 227181624Skmacy if (TLI.getSchedulingPreference() == Sched::VLIW) 228181624Skmacy return createVLIWDAGScheduler(IS, OptLevel); 229181624Skmacy assert(TLI.getSchedulingPreference() == Sched::ILP && 230181624Skmacy "Unknown sched type!"); 231181624Skmacy return createILPListDAGScheduler(IS, OptLevel); 232181624Skmacy } 233181624Skmacy} 234181624Skmacy 235181624Skmacy// EmitInstrWithCustomInserter - This method should be implemented by targets 236181624Skmacy// that mark instructions with the 'usesCustomInserter' flag. These 237181624Skmacy// instructions are special in various ways, which require special support to 238// insert. The specified MachineInstr is created but not inserted into any 239// basic blocks, and this method is called to expand it into a sequence of 240// instructions, potentially also creating new basic blocks and control flow. 241// When new basic blocks are inserted and the edges from MBB to its successors 242// are modified, the method should insert pairs of <OldSucc, NewSucc> into the 243// DenseMap. 244MachineBasicBlock * 245TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 246 MachineBasicBlock *MBB) const { 247#ifndef NDEBUG 248 dbgs() << "If a target marks an instruction with " 249 "'usesCustomInserter', it must implement " 250 "TargetLowering::EmitInstrWithCustomInserter!"; 251#endif 252 llvm_unreachable(0); 253} 254 255void TargetLowering::AdjustInstrPostInstrSelection(MachineInstr *MI, 256 SDNode *Node) const { 257 assert(!MI->hasPostISelHook() && 258 "If a target marks an instruction with 'hasPostISelHook', " 259 "it must implement TargetLowering::AdjustInstrPostInstrSelection!"); 260} 261 262//===----------------------------------------------------------------------===// 263// SelectionDAGISel code 264//===----------------------------------------------------------------------===// 265 266SelectionDAGISel::SelectionDAGISel(const TargetMachine &tm, 267 CodeGenOpt::Level OL) : 268 MachineFunctionPass(ID), TM(tm), TLI(*tm.getTargetLowering()), 269 FuncInfo(new FunctionLoweringInfo(TLI)), 270 CurDAG(new SelectionDAG(tm, OL)), 271 SDB(new SelectionDAGBuilder(*CurDAG, *FuncInfo, OL)), 272 GFI(), 273 OptLevel(OL), 274 DAGSize(0) { 275 initializeGCModuleInfoPass(*PassRegistry::getPassRegistry()); 276 initializeAliasAnalysisAnalysisGroup(*PassRegistry::getPassRegistry()); 277 initializeBranchProbabilityInfoPass(*PassRegistry::getPassRegistry()); 278 initializeTargetLibraryInfoPass(*PassRegistry::getPassRegistry()); 279 } 280 281SelectionDAGISel::~SelectionDAGISel() { 282 delete SDB; 283 delete CurDAG; 284 delete FuncInfo; 285} 286 287void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const { 288 AU.addRequired<AliasAnalysis>(); 289 AU.addPreserved<AliasAnalysis>(); 290 AU.addRequired<GCModuleInfo>(); 291 AU.addPreserved<GCModuleInfo>(); 292 AU.addRequired<TargetLibraryInfo>(); 293 if (UseMBPI && OptLevel != CodeGenOpt::None) 294 AU.addRequired<BranchProbabilityInfo>(); 295 MachineFunctionPass::getAnalysisUsage(AU); 296} 297 298/// SplitCriticalSideEffectEdges - Look for critical edges with a PHI value that 299/// may trap on it. In this case we have to split the edge so that the path 300/// through the predecessor block that doesn't go to the phi block doesn't 301/// execute the possibly trapping instruction. 302/// 303/// This is required for correctness, so it must be done at -O0. 304/// 305static void SplitCriticalSideEffectEdges(Function &Fn, Pass *SDISel) { 306 // Loop for blocks with phi nodes. 307 for (Function::iterator BB = Fn.begin(), E = Fn.end(); BB != E; ++BB) { 308 PHINode *PN = dyn_cast<PHINode>(BB->begin()); 309 if (PN == 0) continue; 310 311 ReprocessBlock: 312 // For each block with a PHI node, check to see if any of the input values 313 // are potentially trapping constant expressions. Constant expressions are 314 // the only potentially trapping value that can occur as the argument to a 315 // PHI. 316 for (BasicBlock::iterator I = BB->begin(); (PN = dyn_cast<PHINode>(I)); ++I) 317 for (unsigned i = 0, e = PN->getNumIncomingValues(); i != e; ++i) { 318 ConstantExpr *CE = dyn_cast<ConstantExpr>(PN->getIncomingValue(i)); 319 if (CE == 0 || !CE->canTrap()) continue; 320 321 // The only case we have to worry about is when the edge is critical. 322 // Since this block has a PHI Node, we assume it has multiple input 323 // edges: check to see if the pred has multiple successors. 324 BasicBlock *Pred = PN->getIncomingBlock(i); 325 if (Pred->getTerminator()->getNumSuccessors() == 1) 326 continue; 327 328 // Okay, we have to split this edge. 329 SplitCriticalEdge(Pred->getTerminator(), 330 GetSuccessorNumber(Pred, BB), SDISel, true); 331 goto ReprocessBlock; 332 } 333 } 334} 335 336bool SelectionDAGISel::runOnMachineFunction(MachineFunction &mf) { 337 // Do some sanity-checking on the command-line options. 338 assert((!EnableFastISelVerbose || TM.Options.EnableFastISel) && 339 "-fast-isel-verbose requires -fast-isel"); 340 assert((!EnableFastISelAbort || TM.Options.EnableFastISel) && 341 "-fast-isel-abort requires -fast-isel"); 342 343 const Function &Fn = *mf.getFunction(); 344 const TargetInstrInfo &TII = *TM.getInstrInfo(); 345 const TargetRegisterInfo &TRI = *TM.getRegisterInfo(); 346 347 MF = &mf; 348 RegInfo = &MF->getRegInfo(); 349 AA = &getAnalysis<AliasAnalysis>(); 350 LibInfo = &getAnalysis<TargetLibraryInfo>(); 351 GFI = Fn.hasGC() ? &getAnalysis<GCModuleInfo>().getFunctionInfo(Fn) : 0; 352 353 DEBUG(dbgs() << "\n\n\n=== " << Fn.getName() << "\n"); 354 355 SplitCriticalSideEffectEdges(const_cast<Function&>(Fn), this); 356 357 CurDAG->init(*MF); 358 FuncInfo->set(Fn, *MF); 359 360 if (UseMBPI && OptLevel != CodeGenOpt::None) 361 FuncInfo->BPI = &getAnalysis<BranchProbabilityInfo>(); 362 else 363 FuncInfo->BPI = 0; 364 365 SDB->init(GFI, *AA, LibInfo); 366 367 SelectAllBasicBlocks(Fn); 368 369 // If the first basic block in the function has live ins that need to be 370 // copied into vregs, emit the copies into the top of the block before 371 // emitting the code for the block. 372 MachineBasicBlock *EntryMBB = MF->begin(); 373 RegInfo->EmitLiveInCopies(EntryMBB, TRI, TII); 374 375 DenseMap<unsigned, unsigned> LiveInMap; 376 if (!FuncInfo->ArgDbgValues.empty()) 377 for (MachineRegisterInfo::livein_iterator LI = RegInfo->livein_begin(), 378 E = RegInfo->livein_end(); LI != E; ++LI) 379 if (LI->second) 380 LiveInMap.insert(std::make_pair(LI->first, LI->second)); 381 382 // Insert DBG_VALUE instructions for function arguments to the entry block. 383 for (unsigned i = 0, e = FuncInfo->ArgDbgValues.size(); i != e; ++i) { 384 MachineInstr *MI = FuncInfo->ArgDbgValues[e-i-1]; 385 unsigned Reg = MI->getOperand(0).getReg(); 386 if (TargetRegisterInfo::isPhysicalRegister(Reg)) 387 EntryMBB->insert(EntryMBB->begin(), MI); 388 else { 389 MachineInstr *Def = RegInfo->getVRegDef(Reg); 390 MachineBasicBlock::iterator InsertPos = Def; 391 // FIXME: VR def may not be in entry block. 392 Def->getParent()->insert(llvm::next(InsertPos), MI); 393 } 394 395 // If Reg is live-in then update debug info to track its copy in a vreg. 396 DenseMap<unsigned, unsigned>::iterator LDI = LiveInMap.find(Reg); 397 if (LDI != LiveInMap.end()) { 398 MachineInstr *Def = RegInfo->getVRegDef(LDI->second); 399 MachineBasicBlock::iterator InsertPos = Def; 400 const MDNode *Variable = 401 MI->getOperand(MI->getNumOperands()-1).getMetadata(); 402 unsigned Offset = MI->getOperand(1).getImm(); 403 // Def is never a terminator here, so it is ok to increment InsertPos. 404 BuildMI(*EntryMBB, ++InsertPos, MI->getDebugLoc(), 405 TII.get(TargetOpcode::DBG_VALUE)) 406 .addReg(LDI->second, RegState::Debug) 407 .addImm(Offset).addMetadata(Variable); 408 409 // If this vreg is directly copied into an exported register then 410 // that COPY instructions also need DBG_VALUE, if it is the only 411 // user of LDI->second. 412 MachineInstr *CopyUseMI = NULL; 413 for (MachineRegisterInfo::use_iterator 414 UI = RegInfo->use_begin(LDI->second); 415 MachineInstr *UseMI = UI.skipInstruction();) { 416 if (UseMI->isDebugValue()) continue; 417 if (UseMI->isCopy() && !CopyUseMI && UseMI->getParent() == EntryMBB) { 418 CopyUseMI = UseMI; continue; 419 } 420 // Otherwise this is another use or second copy use. 421 CopyUseMI = NULL; break; 422 } 423 if (CopyUseMI) { 424 MachineInstr *NewMI = 425 BuildMI(*MF, CopyUseMI->getDebugLoc(), 426 TII.get(TargetOpcode::DBG_VALUE)) 427 .addReg(CopyUseMI->getOperand(0).getReg(), RegState::Debug) 428 .addImm(Offset).addMetadata(Variable); 429 MachineBasicBlock::iterator Pos = CopyUseMI; 430 EntryMBB->insertAfter(Pos, NewMI); 431 } 432 } 433 } 434 435 // Determine if there are any calls in this machine function. 436 MachineFrameInfo *MFI = MF->getFrameInfo(); 437 if (!MFI->hasCalls()) { 438 for (MachineFunction::const_iterator 439 I = MF->begin(), E = MF->end(); I != E; ++I) { 440 const MachineBasicBlock *MBB = I; 441 for (MachineBasicBlock::const_iterator 442 II = MBB->begin(), IE = MBB->end(); II != IE; ++II) { 443 const MCInstrDesc &MCID = TM.getInstrInfo()->get(II->getOpcode()); 444 445 if ((MCID.isCall() && !MCID.isReturn()) || 446 II->isStackAligningInlineAsm()) { 447 MFI->setHasCalls(true); 448 goto done; 449 } 450 } 451 } 452 } 453 454 done: 455 // Determine if there is a call to setjmp in the machine function. 456 MF->setExposesReturnsTwice(Fn.callsFunctionThatReturnsTwice()); 457 458 // Replace forward-declared registers with the registers containing 459 // the desired value. 460 MachineRegisterInfo &MRI = MF->getRegInfo(); 461 for (DenseMap<unsigned, unsigned>::iterator 462 I = FuncInfo->RegFixups.begin(), E = FuncInfo->RegFixups.end(); 463 I != E; ++I) { 464 unsigned From = I->first; 465 unsigned To = I->second; 466 // If To is also scheduled to be replaced, find what its ultimate 467 // replacement is. 468 for (;;) { 469 DenseMap<unsigned, unsigned>::iterator J = FuncInfo->RegFixups.find(To); 470 if (J == E) break; 471 To = J->second; 472 } 473 // Replace it. 474 MRI.replaceRegWith(From, To); 475 } 476 477 // Release function-specific state. SDB and CurDAG are already cleared 478 // at this point. 479 FuncInfo->clear(); 480 481 return true; 482} 483 484void SelectionDAGISel::SelectBasicBlock(BasicBlock::const_iterator Begin, 485 BasicBlock::const_iterator End, 486 bool &HadTailCall) { 487 // Lower all of the non-terminator instructions. If a call is emitted 488 // as a tail call, cease emitting nodes for this block. Terminators 489 // are handled below. 490 for (BasicBlock::const_iterator I = Begin; I != End && !SDB->HasTailCall; ++I) 491 SDB->visit(*I); 492 493 // Make sure the root of the DAG is up-to-date. 494 CurDAG->setRoot(SDB->getControlRoot()); 495 HadTailCall = SDB->HasTailCall; 496 SDB->clear(); 497 498 // Final step, emit the lowered DAG as machine code. 499 CodeGenAndEmitDAG(); 500} 501 502void SelectionDAGISel::ComputeLiveOutVRegInfo() { 503 SmallPtrSet<SDNode*, 128> VisitedNodes; 504 SmallVector<SDNode*, 128> Worklist; 505 506 Worklist.push_back(CurDAG->getRoot().getNode()); 507 508 APInt KnownZero; 509 APInt KnownOne; 510 511 do { 512 SDNode *N = Worklist.pop_back_val(); 513 514 // If we've already seen this node, ignore it. 515 if (!VisitedNodes.insert(N)) 516 continue; 517 518 // Otherwise, add all chain operands to the worklist. 519 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 520 if (N->getOperand(i).getValueType() == MVT::Other) 521 Worklist.push_back(N->getOperand(i).getNode()); 522 523 // If this is a CopyToReg with a vreg dest, process it. 524 if (N->getOpcode() != ISD::CopyToReg) 525 continue; 526 527 unsigned DestReg = cast<RegisterSDNode>(N->getOperand(1))->getReg(); 528 if (!TargetRegisterInfo::isVirtualRegister(DestReg)) 529 continue; 530 531 // Ignore non-scalar or non-integer values. 532 SDValue Src = N->getOperand(2); 533 EVT SrcVT = Src.getValueType(); 534 if (!SrcVT.isInteger() || SrcVT.isVector()) 535 continue; 536 537 unsigned NumSignBits = CurDAG->ComputeNumSignBits(Src); 538 CurDAG->ComputeMaskedBits(Src, KnownZero, KnownOne); 539 FuncInfo->AddLiveOutRegInfo(DestReg, NumSignBits, KnownZero, KnownOne); 540 } while (!Worklist.empty()); 541} 542 543void SelectionDAGISel::CodeGenAndEmitDAG() { 544 std::string GroupName; 545 if (TimePassesIsEnabled) 546 GroupName = "Instruction Selection and Scheduling"; 547 std::string BlockName; 548 int BlockNumber = -1; 549 (void)BlockNumber; 550#ifdef NDEBUG 551 if (ViewDAGCombine1 || ViewLegalizeTypesDAGs || ViewLegalizeDAGs || 552 ViewDAGCombine2 || ViewDAGCombineLT || ViewISelDAGs || ViewSchedDAGs || 553 ViewSUnitDAGs) 554#endif 555 { 556 BlockNumber = FuncInfo->MBB->getNumber(); 557 BlockName = MF->getFunction()->getName().str() + ":" + 558 FuncInfo->MBB->getBasicBlock()->getName().str(); 559 } 560 DEBUG(dbgs() << "Initial selection DAG: BB#" << BlockNumber 561 << " '" << BlockName << "'\n"; CurDAG->dump()); 562 563 if (ViewDAGCombine1) CurDAG->viewGraph("dag-combine1 input for " + BlockName); 564 565 // Run the DAG combiner in pre-legalize mode. 566 { 567 NamedRegionTimer T("DAG Combining 1", GroupName, TimePassesIsEnabled); 568 CurDAG->Combine(BeforeLegalizeTypes, *AA, OptLevel); 569 } 570 571 DEBUG(dbgs() << "Optimized lowered selection DAG: BB#" << BlockNumber 572 << " '" << BlockName << "'\n"; CurDAG->dump()); 573 574 // Second step, hack on the DAG until it only uses operations and types that 575 // the target supports. 576 if (ViewLegalizeTypesDAGs) CurDAG->viewGraph("legalize-types input for " + 577 BlockName); 578 579 bool Changed; 580 { 581 NamedRegionTimer T("Type Legalization", GroupName, TimePassesIsEnabled); 582 Changed = CurDAG->LegalizeTypes(); 583 } 584 585 DEBUG(dbgs() << "Type-legalized selection DAG: BB#" << BlockNumber 586 << " '" << BlockName << "'\n"; CurDAG->dump()); 587 588 if (Changed) { 589 if (ViewDAGCombineLT) 590 CurDAG->viewGraph("dag-combine-lt input for " + BlockName); 591 592 // Run the DAG combiner in post-type-legalize mode. 593 { 594 NamedRegionTimer T("DAG Combining after legalize types", GroupName, 595 TimePassesIsEnabled); 596 CurDAG->Combine(AfterLegalizeTypes, *AA, OptLevel); 597 } 598 599 DEBUG(dbgs() << "Optimized type-legalized selection DAG: BB#" << BlockNumber 600 << " '" << BlockName << "'\n"; CurDAG->dump()); 601 } 602 603 { 604 NamedRegionTimer T("Vector Legalization", GroupName, TimePassesIsEnabled); 605 Changed = CurDAG->LegalizeVectors(); 606 } 607 608 if (Changed) { 609 { 610 NamedRegionTimer T("Type Legalization 2", GroupName, TimePassesIsEnabled); 611 CurDAG->LegalizeTypes(); 612 } 613 614 if (ViewDAGCombineLT) 615 CurDAG->viewGraph("dag-combine-lv input for " + BlockName); 616 617 // Run the DAG combiner in post-type-legalize mode. 618 { 619 NamedRegionTimer T("DAG Combining after legalize vectors", GroupName, 620 TimePassesIsEnabled); 621 CurDAG->Combine(AfterLegalizeVectorOps, *AA, OptLevel); 622 } 623 624 DEBUG(dbgs() << "Optimized vector-legalized selection DAG: BB#" 625 << BlockNumber << " '" << BlockName << "'\n"; CurDAG->dump()); 626 } 627 628 if (ViewLegalizeDAGs) CurDAG->viewGraph("legalize input for " + BlockName); 629 630 { 631 NamedRegionTimer T("DAG Legalization", GroupName, TimePassesIsEnabled); 632 CurDAG->Legalize(); 633 } 634 635 DEBUG(dbgs() << "Legalized selection DAG: BB#" << BlockNumber 636 << " '" << BlockName << "'\n"; CurDAG->dump()); 637 638 if (ViewDAGCombine2) CurDAG->viewGraph("dag-combine2 input for " + BlockName); 639 640 // Run the DAG combiner in post-legalize mode. 641 { 642 NamedRegionTimer T("DAG Combining 2", GroupName, TimePassesIsEnabled); 643 CurDAG->Combine(AfterLegalizeDAG, *AA, OptLevel); 644 } 645 646 DEBUG(dbgs() << "Optimized legalized selection DAG: BB#" << BlockNumber 647 << " '" << BlockName << "'\n"; CurDAG->dump()); 648 649 if (OptLevel != CodeGenOpt::None) 650 ComputeLiveOutVRegInfo(); 651 652 if (ViewISelDAGs) CurDAG->viewGraph("isel input for " + BlockName); 653 654 // Third, instruction select all of the operations to machine code, adding the 655 // code to the MachineBasicBlock. 656 { 657 NamedRegionTimer T("Instruction Selection", GroupName, TimePassesIsEnabled); 658 DoInstructionSelection(); 659 } 660 661 DEBUG(dbgs() << "Selected selection DAG: BB#" << BlockNumber 662 << " '" << BlockName << "'\n"; CurDAG->dump()); 663 664 if (ViewSchedDAGs) CurDAG->viewGraph("scheduler input for " + BlockName); 665 666 // Schedule machine code. 667 ScheduleDAGSDNodes *Scheduler = CreateScheduler(); 668 { 669 NamedRegionTimer T("Instruction Scheduling", GroupName, 670 TimePassesIsEnabled); 671 Scheduler->Run(CurDAG, FuncInfo->MBB); 672 } 673 674 if (ViewSUnitDAGs) Scheduler->viewGraph(); 675 676 // Emit machine code to BB. This can change 'BB' to the last block being 677 // inserted into. 678 MachineBasicBlock *FirstMBB = FuncInfo->MBB, *LastMBB; 679 { 680 NamedRegionTimer T("Instruction Creation", GroupName, TimePassesIsEnabled); 681 682 // FuncInfo->InsertPt is passed by reference and set to the end of the 683 // scheduled instructions. 684 LastMBB = FuncInfo->MBB = Scheduler->EmitSchedule(FuncInfo->InsertPt); 685 } 686 687 // If the block was split, make sure we update any references that are used to 688 // update PHI nodes later on. 689 if (FirstMBB != LastMBB) 690 SDB->UpdateSplitBlock(FirstMBB, LastMBB); 691 692 // Free the scheduler state. 693 { 694 NamedRegionTimer T("Instruction Scheduling Cleanup", GroupName, 695 TimePassesIsEnabled); 696 delete Scheduler; 697 } 698 699 // Free the SelectionDAG state, now that we're finished with it. 700 CurDAG->clear(); 701} 702 703namespace { 704/// ISelUpdater - helper class to handle updates of the instruction selection 705/// graph. 706class ISelUpdater : public SelectionDAG::DAGUpdateListener { 707 SelectionDAG::allnodes_iterator &ISelPosition; 708public: 709 ISelUpdater(SelectionDAG &DAG, SelectionDAG::allnodes_iterator &isp) 710 : SelectionDAG::DAGUpdateListener(DAG), ISelPosition(isp) {} 711 712 /// NodeDeleted - Handle nodes deleted from the graph. If the node being 713 /// deleted is the current ISelPosition node, update ISelPosition. 714 /// 715 virtual void NodeDeleted(SDNode *N, SDNode *E) { 716 if (ISelPosition == SelectionDAG::allnodes_iterator(N)) 717 ++ISelPosition; 718 } 719}; 720} // end anonymous namespace 721 722void SelectionDAGISel::DoInstructionSelection() { 723 DEBUG(errs() << "===== Instruction selection begins: BB#" 724 << FuncInfo->MBB->getNumber() 725 << " '" << FuncInfo->MBB->getName() << "'\n"); 726 727 PreprocessISelDAG(); 728 729 // Select target instructions for the DAG. 730 { 731 // Number all nodes with a topological order and set DAGSize. 732 DAGSize = CurDAG->AssignTopologicalOrder(); 733 734 // Create a dummy node (which is not added to allnodes), that adds 735 // a reference to the root node, preventing it from being deleted, 736 // and tracking any changes of the root. 737 HandleSDNode Dummy(CurDAG->getRoot()); 738 SelectionDAG::allnodes_iterator ISelPosition (CurDAG->getRoot().getNode()); 739 ++ISelPosition; 740 741 // Make sure that ISelPosition gets properly updated when nodes are deleted 742 // in calls made from this function. 743 ISelUpdater ISU(*CurDAG, ISelPosition); 744 745 // The AllNodes list is now topological-sorted. Visit the 746 // nodes by starting at the end of the list (the root of the 747 // graph) and preceding back toward the beginning (the entry 748 // node). 749 while (ISelPosition != CurDAG->allnodes_begin()) { 750 SDNode *Node = --ISelPosition; 751 // Skip dead nodes. DAGCombiner is expected to eliminate all dead nodes, 752 // but there are currently some corner cases that it misses. Also, this 753 // makes it theoretically possible to disable the DAGCombiner. 754 if (Node->use_empty()) 755 continue; 756 757 SDNode *ResNode = Select(Node); 758 759 // FIXME: This is pretty gross. 'Select' should be changed to not return 760 // anything at all and this code should be nuked with a tactical strike. 761 762 // If node should not be replaced, continue with the next one. 763 if (ResNode == Node || Node->getOpcode() == ISD::DELETED_NODE) 764 continue; 765 // Replace node. 766 if (ResNode) 767 ReplaceUses(Node, ResNode); 768 769 // If after the replacement this node is not used any more, 770 // remove this dead node. 771 if (Node->use_empty()) // Don't delete EntryToken, etc. 772 CurDAG->RemoveDeadNode(Node); 773 } 774 775 CurDAG->setRoot(Dummy.getValue()); 776 } 777 778 DEBUG(errs() << "===== Instruction selection ends:\n"); 779 780 PostprocessISelDAG(); 781} 782 783/// PrepareEHLandingPad - Emit an EH_LABEL, set up live-in registers, and 784/// do other setup for EH landing-pad blocks. 785void SelectionDAGISel::PrepareEHLandingPad() { 786 MachineBasicBlock *MBB = FuncInfo->MBB; 787 788 // Add a label to mark the beginning of the landing pad. Deletion of the 789 // landing pad can thus be detected via the MachineModuleInfo. 790 MCSymbol *Label = MF->getMMI().addLandingPad(MBB); 791 792 // Assign the call site to the landing pad's begin label. 793 MF->getMMI().setCallSiteLandingPad(Label, SDB->LPadToCallSiteMap[MBB]); 794 795 const MCInstrDesc &II = TM.getInstrInfo()->get(TargetOpcode::EH_LABEL); 796 BuildMI(*MBB, FuncInfo->InsertPt, SDB->getCurDebugLoc(), II) 797 .addSym(Label); 798 799 // Mark exception register as live in. 800 unsigned Reg = TLI.getExceptionPointerRegister(); 801 if (Reg) MBB->addLiveIn(Reg); 802 803 // Mark exception selector register as live in. 804 Reg = TLI.getExceptionSelectorRegister(); 805 if (Reg) MBB->addLiveIn(Reg); 806} 807 808/// TryToFoldFastISelLoad - We're checking to see if we can fold the specified 809/// load into the specified FoldInst. Note that we could have a sequence where 810/// multiple LLVM IR instructions are folded into the same machineinstr. For 811/// example we could have: 812/// A: x = load i32 *P 813/// B: y = icmp A, 42 814/// C: br y, ... 815/// 816/// In this scenario, LI is "A", and FoldInst is "C". We know about "B" (and 817/// any other folded instructions) because it is between A and C. 818/// 819/// If we succeed in folding the load into the operation, return true. 820/// 821bool SelectionDAGISel::TryToFoldFastISelLoad(const LoadInst *LI, 822 const Instruction *FoldInst, 823 FastISel *FastIS) { 824 // We know that the load has a single use, but don't know what it is. If it 825 // isn't one of the folded instructions, then we can't succeed here. Handle 826 // this by scanning the single-use users of the load until we get to FoldInst. 827 unsigned MaxUsers = 6; // Don't scan down huge single-use chains of instrs. 828 829 const Instruction *TheUser = LI->use_back(); 830 while (TheUser != FoldInst && // Scan up until we find FoldInst. 831 // Stay in the right block. 832 TheUser->getParent() == FoldInst->getParent() && 833 --MaxUsers) { // Don't scan too far. 834 // If there are multiple or no uses of this instruction, then bail out. 835 if (!TheUser->hasOneUse()) 836 return false; 837 838 TheUser = TheUser->use_back(); 839 } 840 841 // If we didn't find the fold instruction, then we failed to collapse the 842 // sequence. 843 if (TheUser != FoldInst) 844 return false; 845 846 // Don't try to fold volatile loads. Target has to deal with alignment 847 // constraints. 848 if (LI->isVolatile()) return false; 849 850 // Figure out which vreg this is going into. If there is no assigned vreg yet 851 // then there actually was no reference to it. Perhaps the load is referenced 852 // by a dead instruction. 853 unsigned LoadReg = FastIS->getRegForValue(LI); 854 if (LoadReg == 0) 855 return false; 856 857 // Check to see what the uses of this vreg are. If it has no uses, or more 858 // than one use (at the machine instr level) then we can't fold it. 859 MachineRegisterInfo::reg_iterator RI = RegInfo->reg_begin(LoadReg); 860 if (RI == RegInfo->reg_end()) 861 return false; 862 863 // See if there is exactly one use of the vreg. If there are multiple uses, 864 // then the instruction got lowered to multiple machine instructions or the 865 // use of the loaded value ended up being multiple operands of the result, in 866 // either case, we can't fold this. 867 MachineRegisterInfo::reg_iterator PostRI = RI; ++PostRI; 868 if (PostRI != RegInfo->reg_end()) 869 return false; 870 871 assert(RI.getOperand().isUse() && 872 "The only use of the vreg must be a use, we haven't emitted the def!"); 873 874 MachineInstr *User = &*RI; 875 876 // Set the insertion point properly. Folding the load can cause generation of 877 // other random instructions (like sign extends) for addressing modes, make 878 // sure they get inserted in a logical place before the new instruction. 879 FuncInfo->InsertPt = User; 880 FuncInfo->MBB = User->getParent(); 881 882 // Ask the target to try folding the load. 883 return FastIS->TryToFoldLoad(User, RI.getOperandNo(), LI); 884} 885 886/// isFoldedOrDeadInstruction - Return true if the specified instruction is 887/// side-effect free and is either dead or folded into a generated instruction. 888/// Return false if it needs to be emitted. 889static bool isFoldedOrDeadInstruction(const Instruction *I, 890 FunctionLoweringInfo *FuncInfo) { 891 return !I->mayWriteToMemory() && // Side-effecting instructions aren't folded. 892 !isa<TerminatorInst>(I) && // Terminators aren't folded. 893 !isa<DbgInfoIntrinsic>(I) && // Debug instructions aren't folded. 894 !isa<LandingPadInst>(I) && // Landingpad instructions aren't folded. 895 !FuncInfo->isExportedInst(I); // Exported instrs must be computed. 896} 897 898#ifndef NDEBUG 899// Collect per Instruction statistics for fast-isel misses. Only those 900// instructions that cause the bail are accounted for. It does not account for 901// instructions higher in the block. Thus, summing the per instructions stats 902// will not add up to what is reported by NumFastIselFailures. 903static void collectFailStats(const Instruction *I) { 904 switch (I->getOpcode()) { 905 default: assert (0 && "<Invalid operator> "); 906 907 // Terminators 908 case Instruction::Ret: NumFastIselFailRet++; return; 909 case Instruction::Br: NumFastIselFailBr++; return; 910 case Instruction::Switch: NumFastIselFailSwitch++; return; 911 case Instruction::IndirectBr: NumFastIselFailIndirectBr++; return; 912 case Instruction::Invoke: NumFastIselFailInvoke++; return; 913 case Instruction::Resume: NumFastIselFailResume++; return; 914 case Instruction::Unreachable: NumFastIselFailUnreachable++; return; 915 916 // Standard binary operators... 917 case Instruction::Add: NumFastIselFailAdd++; return; 918 case Instruction::FAdd: NumFastIselFailFAdd++; return; 919 case Instruction::Sub: NumFastIselFailSub++; return; 920 case Instruction::FSub: NumFastIselFailFSub++; return; 921 case Instruction::Mul: NumFastIselFailMul++; return; 922 case Instruction::FMul: NumFastIselFailFMul++; return; 923 case Instruction::UDiv: NumFastIselFailUDiv++; return; 924 case Instruction::SDiv: NumFastIselFailSDiv++; return; 925 case Instruction::FDiv: NumFastIselFailFDiv++; return; 926 case Instruction::URem: NumFastIselFailURem++; return; 927 case Instruction::SRem: NumFastIselFailSRem++; return; 928 case Instruction::FRem: NumFastIselFailFRem++; return; 929 930 // Logical operators... 931 case Instruction::And: NumFastIselFailAnd++; return; 932 case Instruction::Or: NumFastIselFailOr++; return; 933 case Instruction::Xor: NumFastIselFailXor++; return; 934 935 // Memory instructions... 936 case Instruction::Alloca: NumFastIselFailAlloca++; return; 937 case Instruction::Load: NumFastIselFailLoad++; return; 938 case Instruction::Store: NumFastIselFailStore++; return; 939 case Instruction::AtomicCmpXchg: NumFastIselFailAtomicCmpXchg++; return; 940 case Instruction::AtomicRMW: NumFastIselFailAtomicRMW++; return; 941 case Instruction::Fence: NumFastIselFailFence++; return; 942 case Instruction::GetElementPtr: NumFastIselFailGetElementPtr++; return; 943 944 // Convert instructions... 945 case Instruction::Trunc: NumFastIselFailTrunc++; return; 946 case Instruction::ZExt: NumFastIselFailZExt++; return; 947 case Instruction::SExt: NumFastIselFailSExt++; return; 948 case Instruction::FPTrunc: NumFastIselFailFPTrunc++; return; 949 case Instruction::FPExt: NumFastIselFailFPExt++; return; 950 case Instruction::FPToUI: NumFastIselFailFPToUI++; return; 951 case Instruction::FPToSI: NumFastIselFailFPToSI++; return; 952 case Instruction::UIToFP: NumFastIselFailUIToFP++; return; 953 case Instruction::SIToFP: NumFastIselFailSIToFP++; return; 954 case Instruction::IntToPtr: NumFastIselFailIntToPtr++; return; 955 case Instruction::PtrToInt: NumFastIselFailPtrToInt++; return; 956 case Instruction::BitCast: NumFastIselFailBitCast++; return; 957 958 // Other instructions... 959 case Instruction::ICmp: NumFastIselFailICmp++; return; 960 case Instruction::FCmp: NumFastIselFailFCmp++; return; 961 case Instruction::PHI: NumFastIselFailPHI++; return; 962 case Instruction::Select: NumFastIselFailSelect++; return; 963 case Instruction::Call: NumFastIselFailCall++; return; 964 case Instruction::Shl: NumFastIselFailShl++; return; 965 case Instruction::LShr: NumFastIselFailLShr++; return; 966 case Instruction::AShr: NumFastIselFailAShr++; return; 967 case Instruction::VAArg: NumFastIselFailVAArg++; return; 968 case Instruction::ExtractElement: NumFastIselFailExtractElement++; return; 969 case Instruction::InsertElement: NumFastIselFailInsertElement++; return; 970 case Instruction::ShuffleVector: NumFastIselFailShuffleVector++; return; 971 case Instruction::ExtractValue: NumFastIselFailExtractValue++; return; 972 case Instruction::InsertValue: NumFastIselFailInsertValue++; return; 973 case Instruction::LandingPad: NumFastIselFailLandingPad++; return; 974 } 975} 976#endif 977 978void SelectionDAGISel::SelectAllBasicBlocks(const Function &Fn) { 979 // Initialize the Fast-ISel state, if needed. 980 FastISel *FastIS = 0; 981 if (TM.Options.EnableFastISel) 982 FastIS = TLI.createFastISel(*FuncInfo, LibInfo); 983 984 // Iterate over all basic blocks in the function. 985 ReversePostOrderTraversal<const Function*> RPOT(&Fn); 986 for (ReversePostOrderTraversal<const Function*>::rpo_iterator 987 I = RPOT.begin(), E = RPOT.end(); I != E; ++I) { 988 const BasicBlock *LLVMBB = *I; 989 990 if (OptLevel != CodeGenOpt::None) { 991 bool AllPredsVisited = true; 992 for (const_pred_iterator PI = pred_begin(LLVMBB), PE = pred_end(LLVMBB); 993 PI != PE; ++PI) { 994 if (!FuncInfo->VisitedBBs.count(*PI)) { 995 AllPredsVisited = false; 996 break; 997 } 998 } 999 1000 if (AllPredsVisited) { 1001 for (BasicBlock::const_iterator I = LLVMBB->begin(); 1002 isa<PHINode>(I); ++I) 1003 FuncInfo->ComputePHILiveOutRegInfo(cast<PHINode>(I)); 1004 } else { 1005 for (BasicBlock::const_iterator I = LLVMBB->begin(); 1006 isa<PHINode>(I); ++I) 1007 FuncInfo->InvalidatePHILiveOutRegInfo(cast<PHINode>(I)); 1008 } 1009 1010 FuncInfo->VisitedBBs.insert(LLVMBB); 1011 } 1012 1013 FuncInfo->MBB = FuncInfo->MBBMap[LLVMBB]; 1014 FuncInfo->InsertPt = FuncInfo->MBB->getFirstNonPHI(); 1015 1016 BasicBlock::const_iterator const Begin = LLVMBB->getFirstNonPHI(); 1017 BasicBlock::const_iterator const End = LLVMBB->end(); 1018 BasicBlock::const_iterator BI = End; 1019 1020 FuncInfo->InsertPt = FuncInfo->MBB->getFirstNonPHI(); 1021 1022 // Setup an EH landing-pad block. 1023 if (FuncInfo->MBB->isLandingPad()) 1024 PrepareEHLandingPad(); 1025 1026 // Lower any arguments needed in this block if this is the entry block. 1027 if (LLVMBB == &Fn.getEntryBlock()) 1028 LowerArguments(LLVMBB); 1029 1030 // Before doing SelectionDAG ISel, see if FastISel has been requested. 1031 if (FastIS) { 1032 FastIS->startNewBlock(); 1033 1034 // Emit code for any incoming arguments. This must happen before 1035 // beginning FastISel on the entry block. 1036 if (LLVMBB == &Fn.getEntryBlock()) { 1037 CurDAG->setRoot(SDB->getControlRoot()); 1038 SDB->clear(); 1039 CodeGenAndEmitDAG(); 1040 1041 // If we inserted any instructions at the beginning, make a note of 1042 // where they are, so we can be sure to emit subsequent instructions 1043 // after them. 1044 if (FuncInfo->InsertPt != FuncInfo->MBB->begin()) 1045 FastIS->setLastLocalValue(llvm::prior(FuncInfo->InsertPt)); 1046 else 1047 FastIS->setLastLocalValue(0); 1048 } 1049 1050 unsigned NumFastIselRemaining = std::distance(Begin, End); 1051 // Do FastISel on as many instructions as possible. 1052 for (; BI != Begin; --BI) { 1053 const Instruction *Inst = llvm::prior(BI); 1054 1055 // If we no longer require this instruction, skip it. 1056 if (isFoldedOrDeadInstruction(Inst, FuncInfo)) { 1057 --NumFastIselRemaining; 1058 continue; 1059 } 1060 1061 // Bottom-up: reset the insert pos at the top, after any local-value 1062 // instructions. 1063 FastIS->recomputeInsertPt(); 1064 1065 // Try to select the instruction with FastISel. 1066 if (FastIS->SelectInstruction(Inst)) { 1067 --NumFastIselRemaining; 1068 ++NumFastIselSuccess; 1069 // If fast isel succeeded, skip over all the folded instructions, and 1070 // then see if there is a load right before the selected instructions. 1071 // Try to fold the load if so. 1072 const Instruction *BeforeInst = Inst; 1073 while (BeforeInst != Begin) { 1074 BeforeInst = llvm::prior(BasicBlock::const_iterator(BeforeInst)); 1075 if (!isFoldedOrDeadInstruction(BeforeInst, FuncInfo)) 1076 break; 1077 } 1078 if (BeforeInst != Inst && isa<LoadInst>(BeforeInst) && 1079 BeforeInst->hasOneUse() && 1080 TryToFoldFastISelLoad(cast<LoadInst>(BeforeInst), Inst, FastIS)) { 1081 // If we succeeded, don't re-select the load. 1082 BI = llvm::next(BasicBlock::const_iterator(BeforeInst)); 1083 --NumFastIselRemaining; 1084 ++NumFastIselSuccess; 1085 } 1086 continue; 1087 } 1088 1089#ifndef NDEBUG 1090 if (EnableFastISelVerbose2) 1091 collectFailStats(Inst); 1092#endif 1093 1094 // Then handle certain instructions as single-LLVM-Instruction blocks. 1095 if (isa<CallInst>(Inst)) { 1096 1097 if (EnableFastISelVerbose || EnableFastISelAbort) { 1098 dbgs() << "FastISel missed call: "; 1099 Inst->dump(); 1100 } 1101 1102 if (!Inst->getType()->isVoidTy() && !Inst->use_empty()) { 1103 unsigned &R = FuncInfo->ValueMap[Inst]; 1104 if (!R) 1105 R = FuncInfo->CreateRegs(Inst->getType()); 1106 } 1107 1108 bool HadTailCall = false; 1109 SelectBasicBlock(Inst, BI, HadTailCall); 1110 1111 // Recompute NumFastIselRemaining as Selection DAG instruction 1112 // selection may have handled the call, input args, etc. 1113 unsigned RemainingNow = std::distance(Begin, BI); 1114 NumFastIselFailures += NumFastIselRemaining - RemainingNow; 1115 1116 // If the call was emitted as a tail call, we're done with the block. 1117 if (HadTailCall) { 1118 --BI; 1119 break; 1120 } 1121 1122 NumFastIselRemaining = RemainingNow; 1123 continue; 1124 } 1125 1126 if (isa<TerminatorInst>(Inst) && !isa<BranchInst>(Inst)) { 1127 // Don't abort, and use a different message for terminator misses. 1128 NumFastIselFailures += NumFastIselRemaining; 1129 if (EnableFastISelVerbose || EnableFastISelAbort) { 1130 dbgs() << "FastISel missed terminator: "; 1131 Inst->dump(); 1132 } 1133 } else { 1134 NumFastIselFailures += NumFastIselRemaining; 1135 if (EnableFastISelVerbose || EnableFastISelAbort) { 1136 dbgs() << "FastISel miss: "; 1137 Inst->dump(); 1138 } 1139 if (EnableFastISelAbort) 1140 // The "fast" selector couldn't handle something and bailed. 1141 // For the purpose of debugging, just abort. 1142 llvm_unreachable("FastISel didn't select the entire block"); 1143 } 1144 break; 1145 } 1146 1147 FastIS->recomputeInsertPt(); 1148 } 1149 1150 if (Begin != BI) 1151 ++NumDAGBlocks; 1152 else 1153 ++NumFastIselBlocks; 1154 1155 if (Begin != BI) { 1156 // Run SelectionDAG instruction selection on the remainder of the block 1157 // not handled by FastISel. If FastISel is not run, this is the entire 1158 // block. 1159 bool HadTailCall; 1160 SelectBasicBlock(Begin, BI, HadTailCall); 1161 } 1162 1163 FinishBasicBlock(); 1164 FuncInfo->PHINodesToUpdate.clear(); 1165 } 1166 1167 delete FastIS; 1168 SDB->clearDanglingDebugInfo(); 1169} 1170 1171void 1172SelectionDAGISel::FinishBasicBlock() { 1173 1174 DEBUG(dbgs() << "Total amount of phi nodes to update: " 1175 << FuncInfo->PHINodesToUpdate.size() << "\n"; 1176 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) 1177 dbgs() << "Node " << i << " : (" 1178 << FuncInfo->PHINodesToUpdate[i].first 1179 << ", " << FuncInfo->PHINodesToUpdate[i].second << ")\n"); 1180 1181 // Next, now that we know what the last MBB the LLVM BB expanded is, update 1182 // PHI nodes in successors. 1183 if (SDB->SwitchCases.empty() && 1184 SDB->JTCases.empty() && 1185 SDB->BitTestCases.empty()) { 1186 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) { 1187 MachineInstr *PHI = FuncInfo->PHINodesToUpdate[i].first; 1188 assert(PHI->isPHI() && 1189 "This is not a machine PHI node that we are updating!"); 1190 if (!FuncInfo->MBB->isSuccessor(PHI->getParent())) 1191 continue; 1192 PHI->addOperand( 1193 MachineOperand::CreateReg(FuncInfo->PHINodesToUpdate[i].second, false)); 1194 PHI->addOperand(MachineOperand::CreateMBB(FuncInfo->MBB)); 1195 } 1196 return; 1197 } 1198 1199 for (unsigned i = 0, e = SDB->BitTestCases.size(); i != e; ++i) { 1200 // Lower header first, if it wasn't already lowered 1201 if (!SDB->BitTestCases[i].Emitted) { 1202 // Set the current basic block to the mbb we wish to insert the code into 1203 FuncInfo->MBB = SDB->BitTestCases[i].Parent; 1204 FuncInfo->InsertPt = FuncInfo->MBB->end(); 1205 // Emit the code 1206 SDB->visitBitTestHeader(SDB->BitTestCases[i], FuncInfo->MBB); 1207 CurDAG->setRoot(SDB->getRoot()); 1208 SDB->clear(); 1209 CodeGenAndEmitDAG(); 1210 } 1211 1212 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); j != ej; ++j) { 1213 // Set the current basic block to the mbb we wish to insert the code into 1214 FuncInfo->MBB = SDB->BitTestCases[i].Cases[j].ThisBB; 1215 FuncInfo->InsertPt = FuncInfo->MBB->end(); 1216 // Emit the code 1217 if (j+1 != ej) 1218 SDB->visitBitTestCase(SDB->BitTestCases[i], 1219 SDB->BitTestCases[i].Cases[j+1].ThisBB, 1220 SDB->BitTestCases[i].Reg, 1221 SDB->BitTestCases[i].Cases[j], 1222 FuncInfo->MBB); 1223 else 1224 SDB->visitBitTestCase(SDB->BitTestCases[i], 1225 SDB->BitTestCases[i].Default, 1226 SDB->BitTestCases[i].Reg, 1227 SDB->BitTestCases[i].Cases[j], 1228 FuncInfo->MBB); 1229 1230 1231 CurDAG->setRoot(SDB->getRoot()); 1232 SDB->clear(); 1233 CodeGenAndEmitDAG(); 1234 } 1235 1236 // Update PHI Nodes 1237 for (unsigned pi = 0, pe = FuncInfo->PHINodesToUpdate.size(); 1238 pi != pe; ++pi) { 1239 MachineInstr *PHI = FuncInfo->PHINodesToUpdate[pi].first; 1240 MachineBasicBlock *PHIBB = PHI->getParent(); 1241 assert(PHI->isPHI() && 1242 "This is not a machine PHI node that we are updating!"); 1243 // This is "default" BB. We have two jumps to it. From "header" BB and 1244 // from last "case" BB. 1245 if (PHIBB == SDB->BitTestCases[i].Default) { 1246 PHI->addOperand(MachineOperand:: 1247 CreateReg(FuncInfo->PHINodesToUpdate[pi].second, 1248 false)); 1249 PHI->addOperand(MachineOperand::CreateMBB(SDB->BitTestCases[i].Parent)); 1250 PHI->addOperand(MachineOperand:: 1251 CreateReg(FuncInfo->PHINodesToUpdate[pi].second, 1252 false)); 1253 PHI->addOperand(MachineOperand::CreateMBB(SDB->BitTestCases[i].Cases. 1254 back().ThisBB)); 1255 } 1256 // One of "cases" BB. 1257 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); 1258 j != ej; ++j) { 1259 MachineBasicBlock* cBB = SDB->BitTestCases[i].Cases[j].ThisBB; 1260 if (cBB->isSuccessor(PHIBB)) { 1261 PHI->addOperand(MachineOperand:: 1262 CreateReg(FuncInfo->PHINodesToUpdate[pi].second, 1263 false)); 1264 PHI->addOperand(MachineOperand::CreateMBB(cBB)); 1265 } 1266 } 1267 } 1268 } 1269 SDB->BitTestCases.clear(); 1270 1271 // If the JumpTable record is filled in, then we need to emit a jump table. 1272 // Updating the PHI nodes is tricky in this case, since we need to determine 1273 // whether the PHI is a successor of the range check MBB or the jump table MBB 1274 for (unsigned i = 0, e = SDB->JTCases.size(); i != e; ++i) { 1275 // Lower header first, if it wasn't already lowered 1276 if (!SDB->JTCases[i].first.Emitted) { 1277 // Set the current basic block to the mbb we wish to insert the code into 1278 FuncInfo->MBB = SDB->JTCases[i].first.HeaderBB; 1279 FuncInfo->InsertPt = FuncInfo->MBB->end(); 1280 // Emit the code 1281 SDB->visitJumpTableHeader(SDB->JTCases[i].second, SDB->JTCases[i].first, 1282 FuncInfo->MBB); 1283 CurDAG->setRoot(SDB->getRoot()); 1284 SDB->clear(); 1285 CodeGenAndEmitDAG(); 1286 } 1287 1288 // Set the current basic block to the mbb we wish to insert the code into 1289 FuncInfo->MBB = SDB->JTCases[i].second.MBB; 1290 FuncInfo->InsertPt = FuncInfo->MBB->end(); 1291 // Emit the code 1292 SDB->visitJumpTable(SDB->JTCases[i].second); 1293 CurDAG->setRoot(SDB->getRoot()); 1294 SDB->clear(); 1295 CodeGenAndEmitDAG(); 1296 1297 // Update PHI Nodes 1298 for (unsigned pi = 0, pe = FuncInfo->PHINodesToUpdate.size(); 1299 pi != pe; ++pi) { 1300 MachineInstr *PHI = FuncInfo->PHINodesToUpdate[pi].first; 1301 MachineBasicBlock *PHIBB = PHI->getParent(); 1302 assert(PHI->isPHI() && 1303 "This is not a machine PHI node that we are updating!"); 1304 // "default" BB. We can go there only from header BB. 1305 if (PHIBB == SDB->JTCases[i].second.Default) { 1306 PHI->addOperand 1307 (MachineOperand::CreateReg(FuncInfo->PHINodesToUpdate[pi].second, 1308 false)); 1309 PHI->addOperand 1310 (MachineOperand::CreateMBB(SDB->JTCases[i].first.HeaderBB)); 1311 } 1312 // JT BB. Just iterate over successors here 1313 if (FuncInfo->MBB->isSuccessor(PHIBB)) { 1314 PHI->addOperand 1315 (MachineOperand::CreateReg(FuncInfo->PHINodesToUpdate[pi].second, 1316 false)); 1317 PHI->addOperand(MachineOperand::CreateMBB(FuncInfo->MBB)); 1318 } 1319 } 1320 } 1321 SDB->JTCases.clear(); 1322 1323 // If the switch block involved a branch to one of the actual successors, we 1324 // need to update PHI nodes in that block. 1325 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) { 1326 MachineInstr *PHI = FuncInfo->PHINodesToUpdate[i].first; 1327 assert(PHI->isPHI() && 1328 "This is not a machine PHI node that we are updating!"); 1329 if (FuncInfo->MBB->isSuccessor(PHI->getParent())) { 1330 PHI->addOperand( 1331 MachineOperand::CreateReg(FuncInfo->PHINodesToUpdate[i].second, false)); 1332 PHI->addOperand(MachineOperand::CreateMBB(FuncInfo->MBB)); 1333 } 1334 } 1335 1336 // If we generated any switch lowering information, build and codegen any 1337 // additional DAGs necessary. 1338 for (unsigned i = 0, e = SDB->SwitchCases.size(); i != e; ++i) { 1339 // Set the current basic block to the mbb we wish to insert the code into 1340 FuncInfo->MBB = SDB->SwitchCases[i].ThisBB; 1341 FuncInfo->InsertPt = FuncInfo->MBB->end(); 1342 1343 // Determine the unique successors. 1344 SmallVector<MachineBasicBlock *, 2> Succs; 1345 Succs.push_back(SDB->SwitchCases[i].TrueBB); 1346 if (SDB->SwitchCases[i].TrueBB != SDB->SwitchCases[i].FalseBB) 1347 Succs.push_back(SDB->SwitchCases[i].FalseBB); 1348 1349 // Emit the code. Note that this could result in FuncInfo->MBB being split. 1350 SDB->visitSwitchCase(SDB->SwitchCases[i], FuncInfo->MBB); 1351 CurDAG->setRoot(SDB->getRoot()); 1352 SDB->clear(); 1353 CodeGenAndEmitDAG(); 1354 1355 // Remember the last block, now that any splitting is done, for use in 1356 // populating PHI nodes in successors. 1357 MachineBasicBlock *ThisBB = FuncInfo->MBB; 1358 1359 // Handle any PHI nodes in successors of this chunk, as if we were coming 1360 // from the original BB before switch expansion. Note that PHI nodes can 1361 // occur multiple times in PHINodesToUpdate. We have to be very careful to 1362 // handle them the right number of times. 1363 for (unsigned i = 0, e = Succs.size(); i != e; ++i) { 1364 FuncInfo->MBB = Succs[i]; 1365 FuncInfo->InsertPt = FuncInfo->MBB->end(); 1366 // FuncInfo->MBB may have been removed from the CFG if a branch was 1367 // constant folded. 1368 if (ThisBB->isSuccessor(FuncInfo->MBB)) { 1369 for (MachineBasicBlock::iterator Phi = FuncInfo->MBB->begin(); 1370 Phi != FuncInfo->MBB->end() && Phi->isPHI(); 1371 ++Phi) { 1372 // This value for this PHI node is recorded in PHINodesToUpdate. 1373 for (unsigned pn = 0; ; ++pn) { 1374 assert(pn != FuncInfo->PHINodesToUpdate.size() && 1375 "Didn't find PHI entry!"); 1376 if (FuncInfo->PHINodesToUpdate[pn].first == Phi) { 1377 Phi->addOperand(MachineOperand:: 1378 CreateReg(FuncInfo->PHINodesToUpdate[pn].second, 1379 false)); 1380 Phi->addOperand(MachineOperand::CreateMBB(ThisBB)); 1381 break; 1382 } 1383 } 1384 } 1385 } 1386 } 1387 } 1388 SDB->SwitchCases.clear(); 1389} 1390 1391 1392/// Create the scheduler. If a specific scheduler was specified 1393/// via the SchedulerRegistry, use it, otherwise select the 1394/// one preferred by the target. 1395/// 1396ScheduleDAGSDNodes *SelectionDAGISel::CreateScheduler() { 1397 RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault(); 1398 1399 if (!Ctor) { 1400 Ctor = ISHeuristic; 1401 RegisterScheduler::setDefault(Ctor); 1402 } 1403 1404 return Ctor(this, OptLevel); 1405} 1406 1407//===----------------------------------------------------------------------===// 1408// Helper functions used by the generated instruction selector. 1409//===----------------------------------------------------------------------===// 1410// Calls to these methods are generated by tblgen. 1411 1412/// CheckAndMask - The isel is trying to match something like (and X, 255). If 1413/// the dag combiner simplified the 255, we still want to match. RHS is the 1414/// actual value in the DAG on the RHS of an AND, and DesiredMaskS is the value 1415/// specified in the .td file (e.g. 255). 1416bool SelectionDAGISel::CheckAndMask(SDValue LHS, ConstantSDNode *RHS, 1417 int64_t DesiredMaskS) const { 1418 const APInt &ActualMask = RHS->getAPIntValue(); 1419 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS); 1420 1421 // If the actual mask exactly matches, success! 1422 if (ActualMask == DesiredMask) 1423 return true; 1424 1425 // If the actual AND mask is allowing unallowed bits, this doesn't match. 1426 if (ActualMask.intersects(~DesiredMask)) 1427 return false; 1428 1429 // Otherwise, the DAG Combiner may have proven that the value coming in is 1430 // either already zero or is not demanded. Check for known zero input bits. 1431 APInt NeededMask = DesiredMask & ~ActualMask; 1432 if (CurDAG->MaskedValueIsZero(LHS, NeededMask)) 1433 return true; 1434 1435 // TODO: check to see if missing bits are just not demanded. 1436 1437 // Otherwise, this pattern doesn't match. 1438 return false; 1439} 1440 1441/// CheckOrMask - The isel is trying to match something like (or X, 255). If 1442/// the dag combiner simplified the 255, we still want to match. RHS is the 1443/// actual value in the DAG on the RHS of an OR, and DesiredMaskS is the value 1444/// specified in the .td file (e.g. 255). 1445bool SelectionDAGISel::CheckOrMask(SDValue LHS, ConstantSDNode *RHS, 1446 int64_t DesiredMaskS) const { 1447 const APInt &ActualMask = RHS->getAPIntValue(); 1448 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS); 1449 1450 // If the actual mask exactly matches, success! 1451 if (ActualMask == DesiredMask) 1452 return true; 1453 1454 // If the actual AND mask is allowing unallowed bits, this doesn't match. 1455 if (ActualMask.intersects(~DesiredMask)) 1456 return false; 1457 1458 // Otherwise, the DAG Combiner may have proven that the value coming in is 1459 // either already zero or is not demanded. Check for known zero input bits. 1460 APInt NeededMask = DesiredMask & ~ActualMask; 1461 1462 APInt KnownZero, KnownOne; 1463 CurDAG->ComputeMaskedBits(LHS, KnownZero, KnownOne); 1464 1465 // If all the missing bits in the or are already known to be set, match! 1466 if ((NeededMask & KnownOne) == NeededMask) 1467 return true; 1468 1469 // TODO: check to see if missing bits are just not demanded. 1470 1471 // Otherwise, this pattern doesn't match. 1472 return false; 1473} 1474 1475 1476/// SelectInlineAsmMemoryOperands - Calls to this are automatically generated 1477/// by tblgen. Others should not call it. 1478void SelectionDAGISel:: 1479SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops) { 1480 std::vector<SDValue> InOps; 1481 std::swap(InOps, Ops); 1482 1483 Ops.push_back(InOps[InlineAsm::Op_InputChain]); // 0 1484 Ops.push_back(InOps[InlineAsm::Op_AsmString]); // 1 1485 Ops.push_back(InOps[InlineAsm::Op_MDNode]); // 2, !srcloc 1486 Ops.push_back(InOps[InlineAsm::Op_ExtraInfo]); // 3 (SideEffect, AlignStack) 1487 1488 unsigned i = InlineAsm::Op_FirstOperand, e = InOps.size(); 1489 if (InOps[e-1].getValueType() == MVT::Glue) 1490 --e; // Don't process a glue operand if it is here. 1491 1492 while (i != e) { 1493 unsigned Flags = cast<ConstantSDNode>(InOps[i])->getZExtValue(); 1494 if (!InlineAsm::isMemKind(Flags)) { 1495 // Just skip over this operand, copying the operands verbatim. 1496 Ops.insert(Ops.end(), InOps.begin()+i, 1497 InOps.begin()+i+InlineAsm::getNumOperandRegisters(Flags) + 1); 1498 i += InlineAsm::getNumOperandRegisters(Flags) + 1; 1499 } else { 1500 assert(InlineAsm::getNumOperandRegisters(Flags) == 1 && 1501 "Memory operand with multiple values?"); 1502 // Otherwise, this is a memory operand. Ask the target to select it. 1503 std::vector<SDValue> SelOps; 1504 if (SelectInlineAsmMemoryOperand(InOps[i+1], 'm', SelOps)) 1505 report_fatal_error("Could not match memory address. Inline asm" 1506 " failure!"); 1507 1508 // Add this to the output node. 1509 unsigned NewFlags = 1510 InlineAsm::getFlagWord(InlineAsm::Kind_Mem, SelOps.size()); 1511 Ops.push_back(CurDAG->getTargetConstant(NewFlags, MVT::i32)); 1512 Ops.insert(Ops.end(), SelOps.begin(), SelOps.end()); 1513 i += 2; 1514 } 1515 } 1516 1517 // Add the glue input back if present. 1518 if (e != InOps.size()) 1519 Ops.push_back(InOps.back()); 1520} 1521 1522/// findGlueUse - Return use of MVT::Glue value produced by the specified 1523/// SDNode. 1524/// 1525static SDNode *findGlueUse(SDNode *N) { 1526 unsigned FlagResNo = N->getNumValues()-1; 1527 for (SDNode::use_iterator I = N->use_begin(), E = N->use_end(); I != E; ++I) { 1528 SDUse &Use = I.getUse(); 1529 if (Use.getResNo() == FlagResNo) 1530 return Use.getUser(); 1531 } 1532 return NULL; 1533} 1534 1535/// findNonImmUse - Return true if "Use" is a non-immediate use of "Def". 1536/// This function recursively traverses up the operand chain, ignoring 1537/// certain nodes. 1538static bool findNonImmUse(SDNode *Use, SDNode* Def, SDNode *ImmedUse, 1539 SDNode *Root, SmallPtrSet<SDNode*, 16> &Visited, 1540 bool IgnoreChains) { 1541 // The NodeID's are given uniques ID's where a node ID is guaranteed to be 1542 // greater than all of its (recursive) operands. If we scan to a point where 1543 // 'use' is smaller than the node we're scanning for, then we know we will 1544 // never find it. 1545 // 1546 // The Use may be -1 (unassigned) if it is a newly allocated node. This can 1547 // happen because we scan down to newly selected nodes in the case of glue 1548 // uses. 1549 if ((Use->getNodeId() < Def->getNodeId() && Use->getNodeId() != -1)) 1550 return false; 1551 1552 // Don't revisit nodes if we already scanned it and didn't fail, we know we 1553 // won't fail if we scan it again. 1554 if (!Visited.insert(Use)) 1555 return false; 1556 1557 for (unsigned i = 0, e = Use->getNumOperands(); i != e; ++i) { 1558 // Ignore chain uses, they are validated by HandleMergeInputChains. 1559 if (Use->getOperand(i).getValueType() == MVT::Other && IgnoreChains) 1560 continue; 1561 1562 SDNode *N = Use->getOperand(i).getNode(); 1563 if (N == Def) { 1564 if (Use == ImmedUse || Use == Root) 1565 continue; // We are not looking for immediate use. 1566 assert(N != Root); 1567 return true; 1568 } 1569 1570 // Traverse up the operand chain. 1571 if (findNonImmUse(N, Def, ImmedUse, Root, Visited, IgnoreChains)) 1572 return true; 1573 } 1574 return false; 1575} 1576 1577/// IsProfitableToFold - Returns true if it's profitable to fold the specific 1578/// operand node N of U during instruction selection that starts at Root. 1579bool SelectionDAGISel::IsProfitableToFold(SDValue N, SDNode *U, 1580 SDNode *Root) const { 1581 if (OptLevel == CodeGenOpt::None) return false; 1582 return N.hasOneUse(); 1583} 1584 1585/// IsLegalToFold - Returns true if the specific operand node N of 1586/// U can be folded during instruction selection that starts at Root. 1587bool SelectionDAGISel::IsLegalToFold(SDValue N, SDNode *U, SDNode *Root, 1588 CodeGenOpt::Level OptLevel, 1589 bool IgnoreChains) { 1590 if (OptLevel == CodeGenOpt::None) return false; 1591 1592 // If Root use can somehow reach N through a path that that doesn't contain 1593 // U then folding N would create a cycle. e.g. In the following 1594 // diagram, Root can reach N through X. If N is folded into into Root, then 1595 // X is both a predecessor and a successor of U. 1596 // 1597 // [N*] // 1598 // ^ ^ // 1599 // / \ // 1600 // [U*] [X]? // 1601 // ^ ^ // 1602 // \ / // 1603 // \ / // 1604 // [Root*] // 1605 // 1606 // * indicates nodes to be folded together. 1607 // 1608 // If Root produces glue, then it gets (even more) interesting. Since it 1609 // will be "glued" together with its glue use in the scheduler, we need to 1610 // check if it might reach N. 1611 // 1612 // [N*] // 1613 // ^ ^ // 1614 // / \ // 1615 // [U*] [X]? // 1616 // ^ ^ // 1617 // \ \ // 1618 // \ | // 1619 // [Root*] | // 1620 // ^ | // 1621 // f | // 1622 // | / // 1623 // [Y] / // 1624 // ^ / // 1625 // f / // 1626 // | / // 1627 // [GU] // 1628 // 1629 // If GU (glue use) indirectly reaches N (the load), and Root folds N 1630 // (call it Fold), then X is a predecessor of GU and a successor of 1631 // Fold. But since Fold and GU are glued together, this will create 1632 // a cycle in the scheduling graph. 1633 1634 // If the node has glue, walk down the graph to the "lowest" node in the 1635 // glueged set. 1636 EVT VT = Root->getValueType(Root->getNumValues()-1); 1637 while (VT == MVT::Glue) { 1638 SDNode *GU = findGlueUse(Root); 1639 if (GU == NULL) 1640 break; 1641 Root = GU; 1642 VT = Root->getValueType(Root->getNumValues()-1); 1643 1644 // If our query node has a glue result with a use, we've walked up it. If 1645 // the user (which has already been selected) has a chain or indirectly uses 1646 // the chain, our WalkChainUsers predicate will not consider it. Because of 1647 // this, we cannot ignore chains in this predicate. 1648 IgnoreChains = false; 1649 } 1650 1651 1652 SmallPtrSet<SDNode*, 16> Visited; 1653 return !findNonImmUse(Root, N.getNode(), U, Root, Visited, IgnoreChains); 1654} 1655 1656SDNode *SelectionDAGISel::Select_INLINEASM(SDNode *N) { 1657 std::vector<SDValue> Ops(N->op_begin(), N->op_end()); 1658 SelectInlineAsmMemoryOperands(Ops); 1659 1660 std::vector<EVT> VTs; 1661 VTs.push_back(MVT::Other); 1662 VTs.push_back(MVT::Glue); 1663 SDValue New = CurDAG->getNode(ISD::INLINEASM, N->getDebugLoc(), 1664 VTs, &Ops[0], Ops.size()); 1665 New->setNodeId(-1); 1666 return New.getNode(); 1667} 1668 1669SDNode *SelectionDAGISel::Select_UNDEF(SDNode *N) { 1670 return CurDAG->SelectNodeTo(N, TargetOpcode::IMPLICIT_DEF,N->getValueType(0)); 1671} 1672 1673/// GetVBR - decode a vbr encoding whose top bit is set. 1674LLVM_ATTRIBUTE_ALWAYS_INLINE static uint64_t 1675GetVBR(uint64_t Val, const unsigned char *MatcherTable, unsigned &Idx) { 1676 assert(Val >= 128 && "Not a VBR"); 1677 Val &= 127; // Remove first vbr bit. 1678 1679 unsigned Shift = 7; 1680 uint64_t NextBits; 1681 do { 1682 NextBits = MatcherTable[Idx++]; 1683 Val |= (NextBits&127) << Shift; 1684 Shift += 7; 1685 } while (NextBits & 128); 1686 1687 return Val; 1688} 1689 1690 1691/// UpdateChainsAndGlue - When a match is complete, this method updates uses of 1692/// interior glue and chain results to use the new glue and chain results. 1693void SelectionDAGISel:: 1694UpdateChainsAndGlue(SDNode *NodeToMatch, SDValue InputChain, 1695 const SmallVectorImpl<SDNode*> &ChainNodesMatched, 1696 SDValue InputGlue, 1697 const SmallVectorImpl<SDNode*> &GlueResultNodesMatched, 1698 bool isMorphNodeTo) { 1699 SmallVector<SDNode*, 4> NowDeadNodes; 1700 1701 // Now that all the normal results are replaced, we replace the chain and 1702 // glue results if present. 1703 if (!ChainNodesMatched.empty()) { 1704 assert(InputChain.getNode() != 0 && 1705 "Matched input chains but didn't produce a chain"); 1706 // Loop over all of the nodes we matched that produced a chain result. 1707 // Replace all the chain results with the final chain we ended up with. 1708 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) { 1709 SDNode *ChainNode = ChainNodesMatched[i]; 1710 1711 // If this node was already deleted, don't look at it. 1712 if (ChainNode->getOpcode() == ISD::DELETED_NODE) 1713 continue; 1714 1715 // Don't replace the results of the root node if we're doing a 1716 // MorphNodeTo. 1717 if (ChainNode == NodeToMatch && isMorphNodeTo) 1718 continue; 1719 1720 SDValue ChainVal = SDValue(ChainNode, ChainNode->getNumValues()-1); 1721 if (ChainVal.getValueType() == MVT::Glue) 1722 ChainVal = ChainVal.getValue(ChainVal->getNumValues()-2); 1723 assert(ChainVal.getValueType() == MVT::Other && "Not a chain?"); 1724 CurDAG->ReplaceAllUsesOfValueWith(ChainVal, InputChain); 1725 1726 // If the node became dead and we haven't already seen it, delete it. 1727 if (ChainNode->use_empty() && 1728 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), ChainNode)) 1729 NowDeadNodes.push_back(ChainNode); 1730 } 1731 } 1732 1733 // If the result produces glue, update any glue results in the matched 1734 // pattern with the glue result. 1735 if (InputGlue.getNode() != 0) { 1736 // Handle any interior nodes explicitly marked. 1737 for (unsigned i = 0, e = GlueResultNodesMatched.size(); i != e; ++i) { 1738 SDNode *FRN = GlueResultNodesMatched[i]; 1739 1740 // If this node was already deleted, don't look at it. 1741 if (FRN->getOpcode() == ISD::DELETED_NODE) 1742 continue; 1743 1744 assert(FRN->getValueType(FRN->getNumValues()-1) == MVT::Glue && 1745 "Doesn't have a glue result"); 1746 CurDAG->ReplaceAllUsesOfValueWith(SDValue(FRN, FRN->getNumValues()-1), 1747 InputGlue); 1748 1749 // If the node became dead and we haven't already seen it, delete it. 1750 if (FRN->use_empty() && 1751 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), FRN)) 1752 NowDeadNodes.push_back(FRN); 1753 } 1754 } 1755 1756 if (!NowDeadNodes.empty()) 1757 CurDAG->RemoveDeadNodes(NowDeadNodes); 1758 1759 DEBUG(errs() << "ISEL: Match complete!\n"); 1760} 1761 1762enum ChainResult { 1763 CR_Simple, 1764 CR_InducesCycle, 1765 CR_LeadsToInteriorNode 1766}; 1767 1768/// WalkChainUsers - Walk down the users of the specified chained node that is 1769/// part of the pattern we're matching, looking at all of the users we find. 1770/// This determines whether something is an interior node, whether we have a 1771/// non-pattern node in between two pattern nodes (which prevent folding because 1772/// it would induce a cycle) and whether we have a TokenFactor node sandwiched 1773/// between pattern nodes (in which case the TF becomes part of the pattern). 1774/// 1775/// The walk we do here is guaranteed to be small because we quickly get down to 1776/// already selected nodes "below" us. 1777static ChainResult 1778WalkChainUsers(const SDNode *ChainedNode, 1779 SmallVectorImpl<SDNode*> &ChainedNodesInPattern, 1780 SmallVectorImpl<SDNode*> &InteriorChainedNodes) { 1781 ChainResult Result = CR_Simple; 1782 1783 for (SDNode::use_iterator UI = ChainedNode->use_begin(), 1784 E = ChainedNode->use_end(); UI != E; ++UI) { 1785 // Make sure the use is of the chain, not some other value we produce. 1786 if (UI.getUse().getValueType() != MVT::Other) continue; 1787 1788 SDNode *User = *UI; 1789 1790 // If we see an already-selected machine node, then we've gone beyond the 1791 // pattern that we're selecting down into the already selected chunk of the 1792 // DAG. 1793 if (User->isMachineOpcode() || 1794 User->getOpcode() == ISD::HANDLENODE) // Root of the graph. 1795 continue; 1796 1797 if (User->getOpcode() == ISD::CopyToReg || 1798 User->getOpcode() == ISD::CopyFromReg || 1799 User->getOpcode() == ISD::INLINEASM || 1800 User->getOpcode() == ISD::EH_LABEL) { 1801 // If their node ID got reset to -1 then they've already been selected. 1802 // Treat them like a MachineOpcode. 1803 if (User->getNodeId() == -1) 1804 continue; 1805 } 1806 1807 // If we have a TokenFactor, we handle it specially. 1808 if (User->getOpcode() != ISD::TokenFactor) { 1809 // If the node isn't a token factor and isn't part of our pattern, then it 1810 // must be a random chained node in between two nodes we're selecting. 1811 // This happens when we have something like: 1812 // x = load ptr 1813 // call 1814 // y = x+4 1815 // store y -> ptr 1816 // Because we structurally match the load/store as a read/modify/write, 1817 // but the call is chained between them. We cannot fold in this case 1818 // because it would induce a cycle in the graph. 1819 if (!std::count(ChainedNodesInPattern.begin(), 1820 ChainedNodesInPattern.end(), User)) 1821 return CR_InducesCycle; 1822 1823 // Otherwise we found a node that is part of our pattern. For example in: 1824 // x = load ptr 1825 // y = x+4 1826 // store y -> ptr 1827 // This would happen when we're scanning down from the load and see the 1828 // store as a user. Record that there is a use of ChainedNode that is 1829 // part of the pattern and keep scanning uses. 1830 Result = CR_LeadsToInteriorNode; 1831 InteriorChainedNodes.push_back(User); 1832 continue; 1833 } 1834 1835 // If we found a TokenFactor, there are two cases to consider: first if the 1836 // TokenFactor is just hanging "below" the pattern we're matching (i.e. no 1837 // uses of the TF are in our pattern) we just want to ignore it. Second, 1838 // the TokenFactor can be sandwiched in between two chained nodes, like so: 1839 // [Load chain] 1840 // ^ 1841 // | 1842 // [Load] 1843 // ^ ^ 1844 // | \ DAG's like cheese 1845 // / \ do you? 1846 // / | 1847 // [TokenFactor] [Op] 1848 // ^ ^ 1849 // | | 1850 // \ / 1851 // \ / 1852 // [Store] 1853 // 1854 // In this case, the TokenFactor becomes part of our match and we rewrite it 1855 // as a new TokenFactor. 1856 // 1857 // To distinguish these two cases, do a recursive walk down the uses. 1858 switch (WalkChainUsers(User, ChainedNodesInPattern, InteriorChainedNodes)) { 1859 case CR_Simple: 1860 // If the uses of the TokenFactor are just already-selected nodes, ignore 1861 // it, it is "below" our pattern. 1862 continue; 1863 case CR_InducesCycle: 1864 // If the uses of the TokenFactor lead to nodes that are not part of our 1865 // pattern that are not selected, folding would turn this into a cycle, 1866 // bail out now. 1867 return CR_InducesCycle; 1868 case CR_LeadsToInteriorNode: 1869 break; // Otherwise, keep processing. 1870 } 1871 1872 // Okay, we know we're in the interesting interior case. The TokenFactor 1873 // is now going to be considered part of the pattern so that we rewrite its 1874 // uses (it may have uses that are not part of the pattern) with the 1875 // ultimate chain result of the generated code. We will also add its chain 1876 // inputs as inputs to the ultimate TokenFactor we create. 1877 Result = CR_LeadsToInteriorNode; 1878 ChainedNodesInPattern.push_back(User); 1879 InteriorChainedNodes.push_back(User); 1880 continue; 1881 } 1882 1883 return Result; 1884} 1885 1886/// HandleMergeInputChains - This implements the OPC_EmitMergeInputChains 1887/// operation for when the pattern matched at least one node with a chains. The 1888/// input vector contains a list of all of the chained nodes that we match. We 1889/// must determine if this is a valid thing to cover (i.e. matching it won't 1890/// induce cycles in the DAG) and if so, creating a TokenFactor node. that will 1891/// be used as the input node chain for the generated nodes. 1892static SDValue 1893HandleMergeInputChains(SmallVectorImpl<SDNode*> &ChainNodesMatched, 1894 SelectionDAG *CurDAG) { 1895 // Walk all of the chained nodes we've matched, recursively scanning down the 1896 // users of the chain result. This adds any TokenFactor nodes that are caught 1897 // in between chained nodes to the chained and interior nodes list. 1898 SmallVector<SDNode*, 3> InteriorChainedNodes; 1899 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) { 1900 if (WalkChainUsers(ChainNodesMatched[i], ChainNodesMatched, 1901 InteriorChainedNodes) == CR_InducesCycle) 1902 return SDValue(); // Would induce a cycle. 1903 } 1904 1905 // Okay, we have walked all the matched nodes and collected TokenFactor nodes 1906 // that we are interested in. Form our input TokenFactor node. 1907 SmallVector<SDValue, 3> InputChains; 1908 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) { 1909 // Add the input chain of this node to the InputChains list (which will be 1910 // the operands of the generated TokenFactor) if it's not an interior node. 1911 SDNode *N = ChainNodesMatched[i]; 1912 if (N->getOpcode() != ISD::TokenFactor) { 1913 if (std::count(InteriorChainedNodes.begin(),InteriorChainedNodes.end(),N)) 1914 continue; 1915 1916 // Otherwise, add the input chain. 1917 SDValue InChain = ChainNodesMatched[i]->getOperand(0); 1918 assert(InChain.getValueType() == MVT::Other && "Not a chain"); 1919 InputChains.push_back(InChain); 1920 continue; 1921 } 1922 1923 // If we have a token factor, we want to add all inputs of the token factor 1924 // that are not part of the pattern we're matching. 1925 for (unsigned op = 0, e = N->getNumOperands(); op != e; ++op) { 1926 if (!std::count(ChainNodesMatched.begin(), ChainNodesMatched.end(), 1927 N->getOperand(op).getNode())) 1928 InputChains.push_back(N->getOperand(op)); 1929 } 1930 } 1931 1932 SDValue Res; 1933 if (InputChains.size() == 1) 1934 return InputChains[0]; 1935 return CurDAG->getNode(ISD::TokenFactor, ChainNodesMatched[0]->getDebugLoc(), 1936 MVT::Other, &InputChains[0], InputChains.size()); 1937} 1938 1939/// MorphNode - Handle morphing a node in place for the selector. 1940SDNode *SelectionDAGISel:: 1941MorphNode(SDNode *Node, unsigned TargetOpc, SDVTList VTList, 1942 const SDValue *Ops, unsigned NumOps, unsigned EmitNodeInfo) { 1943 // It is possible we're using MorphNodeTo to replace a node with no 1944 // normal results with one that has a normal result (or we could be 1945 // adding a chain) and the input could have glue and chains as well. 1946 // In this case we need to shift the operands down. 1947 // FIXME: This is a horrible hack and broken in obscure cases, no worse 1948 // than the old isel though. 1949 int OldGlueResultNo = -1, OldChainResultNo = -1; 1950 1951 unsigned NTMNumResults = Node->getNumValues(); 1952 if (Node->getValueType(NTMNumResults-1) == MVT::Glue) { 1953 OldGlueResultNo = NTMNumResults-1; 1954 if (NTMNumResults != 1 && 1955 Node->getValueType(NTMNumResults-2) == MVT::Other) 1956 OldChainResultNo = NTMNumResults-2; 1957 } else if (Node->getValueType(NTMNumResults-1) == MVT::Other) 1958 OldChainResultNo = NTMNumResults-1; 1959 1960 // Call the underlying SelectionDAG routine to do the transmogrification. Note 1961 // that this deletes operands of the old node that become dead. 1962 SDNode *Res = CurDAG->MorphNodeTo(Node, ~TargetOpc, VTList, Ops, NumOps); 1963 1964 // MorphNodeTo can operate in two ways: if an existing node with the 1965 // specified operands exists, it can just return it. Otherwise, it 1966 // updates the node in place to have the requested operands. 1967 if (Res == Node) { 1968 // If we updated the node in place, reset the node ID. To the isel, 1969 // this should be just like a newly allocated machine node. 1970 Res->setNodeId(-1); 1971 } 1972 1973 unsigned ResNumResults = Res->getNumValues(); 1974 // Move the glue if needed. 1975 if ((EmitNodeInfo & OPFL_GlueOutput) && OldGlueResultNo != -1 && 1976 (unsigned)OldGlueResultNo != ResNumResults-1) 1977 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldGlueResultNo), 1978 SDValue(Res, ResNumResults-1)); 1979 1980 if ((EmitNodeInfo & OPFL_GlueOutput) != 0) 1981 --ResNumResults; 1982 1983 // Move the chain reference if needed. 1984 if ((EmitNodeInfo & OPFL_Chain) && OldChainResultNo != -1 && 1985 (unsigned)OldChainResultNo != ResNumResults-1) 1986 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldChainResultNo), 1987 SDValue(Res, ResNumResults-1)); 1988 1989 // Otherwise, no replacement happened because the node already exists. Replace 1990 // Uses of the old node with the new one. 1991 if (Res != Node) 1992 CurDAG->ReplaceAllUsesWith(Node, Res); 1993 1994 return Res; 1995} 1996 1997/// CheckPatternPredicate - Implements OP_CheckPatternPredicate. 1998LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 1999CheckSame(const unsigned char *MatcherTable, unsigned &MatcherIndex, 2000 SDValue N, 2001 const SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes) { 2002 // Accept if it is exactly the same as a previously recorded node. 2003 unsigned RecNo = MatcherTable[MatcherIndex++]; 2004 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2005 return N == RecordedNodes[RecNo].first; 2006} 2007 2008/// CheckPatternPredicate - Implements OP_CheckPatternPredicate. 2009LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 2010CheckPatternPredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex, 2011 const SelectionDAGISel &SDISel) { 2012 return SDISel.CheckPatternPredicate(MatcherTable[MatcherIndex++]); 2013} 2014 2015/// CheckNodePredicate - Implements OP_CheckNodePredicate. 2016LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 2017CheckNodePredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex, 2018 const SelectionDAGISel &SDISel, SDNode *N) { 2019 return SDISel.CheckNodePredicate(N, MatcherTable[MatcherIndex++]); 2020} 2021 2022LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 2023CheckOpcode(const unsigned char *MatcherTable, unsigned &MatcherIndex, 2024 SDNode *N) { 2025 uint16_t Opc = MatcherTable[MatcherIndex++]; 2026 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8; 2027 return N->getOpcode() == Opc; 2028} 2029 2030LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 2031CheckType(const unsigned char *MatcherTable, unsigned &MatcherIndex, 2032 SDValue N, const TargetLowering &TLI) { 2033 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2034 if (N.getValueType() == VT) return true; 2035 2036 // Handle the case when VT is iPTR. 2037 return VT == MVT::iPTR && N.getValueType() == TLI.getPointerTy(); 2038} 2039 2040LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 2041CheckChildType(const unsigned char *MatcherTable, unsigned &MatcherIndex, 2042 SDValue N, const TargetLowering &TLI, 2043 unsigned ChildNo) { 2044 if (ChildNo >= N.getNumOperands()) 2045 return false; // Match fails if out of range child #. 2046 return ::CheckType(MatcherTable, MatcherIndex, N.getOperand(ChildNo), TLI); 2047} 2048 2049 2050LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 2051CheckCondCode(const unsigned char *MatcherTable, unsigned &MatcherIndex, 2052 SDValue N) { 2053 return cast<CondCodeSDNode>(N)->get() == 2054 (ISD::CondCode)MatcherTable[MatcherIndex++]; 2055} 2056 2057LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 2058CheckValueType(const unsigned char *MatcherTable, unsigned &MatcherIndex, 2059 SDValue N, const TargetLowering &TLI) { 2060 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2061 if (cast<VTSDNode>(N)->getVT() == VT) 2062 return true; 2063 2064 // Handle the case when VT is iPTR. 2065 return VT == MVT::iPTR && cast<VTSDNode>(N)->getVT() == TLI.getPointerTy(); 2066} 2067 2068LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 2069CheckInteger(const unsigned char *MatcherTable, unsigned &MatcherIndex, 2070 SDValue N) { 2071 int64_t Val = MatcherTable[MatcherIndex++]; 2072 if (Val & 128) 2073 Val = GetVBR(Val, MatcherTable, MatcherIndex); 2074 2075 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N); 2076 return C != 0 && C->getSExtValue() == Val; 2077} 2078 2079LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 2080CheckAndImm(const unsigned char *MatcherTable, unsigned &MatcherIndex, 2081 SDValue N, const SelectionDAGISel &SDISel) { 2082 int64_t Val = MatcherTable[MatcherIndex++]; 2083 if (Val & 128) 2084 Val = GetVBR(Val, MatcherTable, MatcherIndex); 2085 2086 if (N->getOpcode() != ISD::AND) return false; 2087 2088 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1)); 2089 return C != 0 && SDISel.CheckAndMask(N.getOperand(0), C, Val); 2090} 2091 2092LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 2093CheckOrImm(const unsigned char *MatcherTable, unsigned &MatcherIndex, 2094 SDValue N, const SelectionDAGISel &SDISel) { 2095 int64_t Val = MatcherTable[MatcherIndex++]; 2096 if (Val & 128) 2097 Val = GetVBR(Val, MatcherTable, MatcherIndex); 2098 2099 if (N->getOpcode() != ISD::OR) return false; 2100 2101 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1)); 2102 return C != 0 && SDISel.CheckOrMask(N.getOperand(0), C, Val); 2103} 2104 2105/// IsPredicateKnownToFail - If we know how and can do so without pushing a 2106/// scope, evaluate the current node. If the current predicate is known to 2107/// fail, set Result=true and return anything. If the current predicate is 2108/// known to pass, set Result=false and return the MatcherIndex to continue 2109/// with. If the current predicate is unknown, set Result=false and return the 2110/// MatcherIndex to continue with. 2111static unsigned IsPredicateKnownToFail(const unsigned char *Table, 2112 unsigned Index, SDValue N, 2113 bool &Result, 2114 const SelectionDAGISel &SDISel, 2115 SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes) { 2116 switch (Table[Index++]) { 2117 default: 2118 Result = false; 2119 return Index-1; // Could not evaluate this predicate. 2120 case SelectionDAGISel::OPC_CheckSame: 2121 Result = !::CheckSame(Table, Index, N, RecordedNodes); 2122 return Index; 2123 case SelectionDAGISel::OPC_CheckPatternPredicate: 2124 Result = !::CheckPatternPredicate(Table, Index, SDISel); 2125 return Index; 2126 case SelectionDAGISel::OPC_CheckPredicate: 2127 Result = !::CheckNodePredicate(Table, Index, SDISel, N.getNode()); 2128 return Index; 2129 case SelectionDAGISel::OPC_CheckOpcode: 2130 Result = !::CheckOpcode(Table, Index, N.getNode()); 2131 return Index; 2132 case SelectionDAGISel::OPC_CheckType: 2133 Result = !::CheckType(Table, Index, N, SDISel.TLI); 2134 return Index; 2135 case SelectionDAGISel::OPC_CheckChild0Type: 2136 case SelectionDAGISel::OPC_CheckChild1Type: 2137 case SelectionDAGISel::OPC_CheckChild2Type: 2138 case SelectionDAGISel::OPC_CheckChild3Type: 2139 case SelectionDAGISel::OPC_CheckChild4Type: 2140 case SelectionDAGISel::OPC_CheckChild5Type: 2141 case SelectionDAGISel::OPC_CheckChild6Type: 2142 case SelectionDAGISel::OPC_CheckChild7Type: 2143 Result = !::CheckChildType(Table, Index, N, SDISel.TLI, 2144 Table[Index-1] - SelectionDAGISel::OPC_CheckChild0Type); 2145 return Index; 2146 case SelectionDAGISel::OPC_CheckCondCode: 2147 Result = !::CheckCondCode(Table, Index, N); 2148 return Index; 2149 case SelectionDAGISel::OPC_CheckValueType: 2150 Result = !::CheckValueType(Table, Index, N, SDISel.TLI); 2151 return Index; 2152 case SelectionDAGISel::OPC_CheckInteger: 2153 Result = !::CheckInteger(Table, Index, N); 2154 return Index; 2155 case SelectionDAGISel::OPC_CheckAndImm: 2156 Result = !::CheckAndImm(Table, Index, N, SDISel); 2157 return Index; 2158 case SelectionDAGISel::OPC_CheckOrImm: 2159 Result = !::CheckOrImm(Table, Index, N, SDISel); 2160 return Index; 2161 } 2162} 2163 2164namespace { 2165 2166struct MatchScope { 2167 /// FailIndex - If this match fails, this is the index to continue with. 2168 unsigned FailIndex; 2169 2170 /// NodeStack - The node stack when the scope was formed. 2171 SmallVector<SDValue, 4> NodeStack; 2172 2173 /// NumRecordedNodes - The number of recorded nodes when the scope was formed. 2174 unsigned NumRecordedNodes; 2175 2176 /// NumMatchedMemRefs - The number of matched memref entries. 2177 unsigned NumMatchedMemRefs; 2178 2179 /// InputChain/InputGlue - The current chain/glue 2180 SDValue InputChain, InputGlue; 2181 2182 /// HasChainNodesMatched - True if the ChainNodesMatched list is non-empty. 2183 bool HasChainNodesMatched, HasGlueResultNodesMatched; 2184}; 2185 2186} 2187 2188SDNode *SelectionDAGISel:: 2189SelectCodeCommon(SDNode *NodeToMatch, const unsigned char *MatcherTable, 2190 unsigned TableSize) { 2191 // FIXME: Should these even be selected? Handle these cases in the caller? 2192 switch (NodeToMatch->getOpcode()) { 2193 default: 2194 break; 2195 case ISD::EntryToken: // These nodes remain the same. 2196 case ISD::BasicBlock: 2197 case ISD::Register: 2198 case ISD::RegisterMask: 2199 //case ISD::VALUETYPE: 2200 //case ISD::CONDCODE: 2201 case ISD::HANDLENODE: 2202 case ISD::MDNODE_SDNODE: 2203 case ISD::TargetConstant: 2204 case ISD::TargetConstantFP: 2205 case ISD::TargetConstantPool: 2206 case ISD::TargetFrameIndex: 2207 case ISD::TargetExternalSymbol: 2208 case ISD::TargetBlockAddress: 2209 case ISD::TargetJumpTable: 2210 case ISD::TargetGlobalTLSAddress: 2211 case ISD::TargetGlobalAddress: 2212 case ISD::TokenFactor: 2213 case ISD::CopyFromReg: 2214 case ISD::CopyToReg: 2215 case ISD::EH_LABEL: 2216 NodeToMatch->setNodeId(-1); // Mark selected. 2217 return 0; 2218 case ISD::AssertSext: 2219 case ISD::AssertZext: 2220 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, 0), 2221 NodeToMatch->getOperand(0)); 2222 return 0; 2223 case ISD::INLINEASM: return Select_INLINEASM(NodeToMatch); 2224 case ISD::UNDEF: return Select_UNDEF(NodeToMatch); 2225 } 2226 2227 assert(!NodeToMatch->isMachineOpcode() && "Node already selected!"); 2228 2229 // Set up the node stack with NodeToMatch as the only node on the stack. 2230 SmallVector<SDValue, 8> NodeStack; 2231 SDValue N = SDValue(NodeToMatch, 0); 2232 NodeStack.push_back(N); 2233 2234 // MatchScopes - Scopes used when matching, if a match failure happens, this 2235 // indicates where to continue checking. 2236 SmallVector<MatchScope, 8> MatchScopes; 2237 2238 // RecordedNodes - This is the set of nodes that have been recorded by the 2239 // state machine. The second value is the parent of the node, or null if the 2240 // root is recorded. 2241 SmallVector<std::pair<SDValue, SDNode*>, 8> RecordedNodes; 2242 2243 // MatchedMemRefs - This is the set of MemRef's we've seen in the input 2244 // pattern. 2245 SmallVector<MachineMemOperand*, 2> MatchedMemRefs; 2246 2247 // These are the current input chain and glue for use when generating nodes. 2248 // Various Emit operations change these. For example, emitting a copytoreg 2249 // uses and updates these. 2250 SDValue InputChain, InputGlue; 2251 2252 // ChainNodesMatched - If a pattern matches nodes that have input/output 2253 // chains, the OPC_EmitMergeInputChains operation is emitted which indicates 2254 // which ones they are. The result is captured into this list so that we can 2255 // update the chain results when the pattern is complete. 2256 SmallVector<SDNode*, 3> ChainNodesMatched; 2257 SmallVector<SDNode*, 3> GlueResultNodesMatched; 2258 2259 DEBUG(errs() << "ISEL: Starting pattern match on root node: "; 2260 NodeToMatch->dump(CurDAG); 2261 errs() << '\n'); 2262 2263 // Determine where to start the interpreter. Normally we start at opcode #0, 2264 // but if the state machine starts with an OPC_SwitchOpcode, then we 2265 // accelerate the first lookup (which is guaranteed to be hot) with the 2266 // OpcodeOffset table. 2267 unsigned MatcherIndex = 0; 2268 2269 if (!OpcodeOffset.empty()) { 2270 // Already computed the OpcodeOffset table, just index into it. 2271 if (N.getOpcode() < OpcodeOffset.size()) 2272 MatcherIndex = OpcodeOffset[N.getOpcode()]; 2273 DEBUG(errs() << " Initial Opcode index to " << MatcherIndex << "\n"); 2274 2275 } else if (MatcherTable[0] == OPC_SwitchOpcode) { 2276 // Otherwise, the table isn't computed, but the state machine does start 2277 // with an OPC_SwitchOpcode instruction. Populate the table now, since this 2278 // is the first time we're selecting an instruction. 2279 unsigned Idx = 1; 2280 while (1) { 2281 // Get the size of this case. 2282 unsigned CaseSize = MatcherTable[Idx++]; 2283 if (CaseSize & 128) 2284 CaseSize = GetVBR(CaseSize, MatcherTable, Idx); 2285 if (CaseSize == 0) break; 2286 2287 // Get the opcode, add the index to the table. 2288 uint16_t Opc = MatcherTable[Idx++]; 2289 Opc |= (unsigned short)MatcherTable[Idx++] << 8; 2290 if (Opc >= OpcodeOffset.size()) 2291 OpcodeOffset.resize((Opc+1)*2); 2292 OpcodeOffset[Opc] = Idx; 2293 Idx += CaseSize; 2294 } 2295 2296 // Okay, do the lookup for the first opcode. 2297 if (N.getOpcode() < OpcodeOffset.size()) 2298 MatcherIndex = OpcodeOffset[N.getOpcode()]; 2299 } 2300 2301 while (1) { 2302 assert(MatcherIndex < TableSize && "Invalid index"); 2303#ifndef NDEBUG 2304 unsigned CurrentOpcodeIndex = MatcherIndex; 2305#endif 2306 BuiltinOpcodes Opcode = (BuiltinOpcodes)MatcherTable[MatcherIndex++]; 2307 switch (Opcode) { 2308 case OPC_Scope: { 2309 // Okay, the semantics of this operation are that we should push a scope 2310 // then evaluate the first child. However, pushing a scope only to have 2311 // the first check fail (which then pops it) is inefficient. If we can 2312 // determine immediately that the first check (or first several) will 2313 // immediately fail, don't even bother pushing a scope for them. 2314 unsigned FailIndex; 2315 2316 while (1) { 2317 unsigned NumToSkip = MatcherTable[MatcherIndex++]; 2318 if (NumToSkip & 128) 2319 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex); 2320 // Found the end of the scope with no match. 2321 if (NumToSkip == 0) { 2322 FailIndex = 0; 2323 break; 2324 } 2325 2326 FailIndex = MatcherIndex+NumToSkip; 2327 2328 unsigned MatcherIndexOfPredicate = MatcherIndex; 2329 (void)MatcherIndexOfPredicate; // silence warning. 2330 2331 // If we can't evaluate this predicate without pushing a scope (e.g. if 2332 // it is a 'MoveParent') or if the predicate succeeds on this node, we 2333 // push the scope and evaluate the full predicate chain. 2334 bool Result; 2335 MatcherIndex = IsPredicateKnownToFail(MatcherTable, MatcherIndex, N, 2336 Result, *this, RecordedNodes); 2337 if (!Result) 2338 break; 2339 2340 DEBUG(errs() << " Skipped scope entry (due to false predicate) at " 2341 << "index " << MatcherIndexOfPredicate 2342 << ", continuing at " << FailIndex << "\n"); 2343 ++NumDAGIselRetries; 2344 2345 // Otherwise, we know that this case of the Scope is guaranteed to fail, 2346 // move to the next case. 2347 MatcherIndex = FailIndex; 2348 } 2349 2350 // If the whole scope failed to match, bail. 2351 if (FailIndex == 0) break; 2352 2353 // Push a MatchScope which indicates where to go if the first child fails 2354 // to match. 2355 MatchScope NewEntry; 2356 NewEntry.FailIndex = FailIndex; 2357 NewEntry.NodeStack.append(NodeStack.begin(), NodeStack.end()); 2358 NewEntry.NumRecordedNodes = RecordedNodes.size(); 2359 NewEntry.NumMatchedMemRefs = MatchedMemRefs.size(); 2360 NewEntry.InputChain = InputChain; 2361 NewEntry.InputGlue = InputGlue; 2362 NewEntry.HasChainNodesMatched = !ChainNodesMatched.empty(); 2363 NewEntry.HasGlueResultNodesMatched = !GlueResultNodesMatched.empty(); 2364 MatchScopes.push_back(NewEntry); 2365 continue; 2366 } 2367 case OPC_RecordNode: { 2368 // Remember this node, it may end up being an operand in the pattern. 2369 SDNode *Parent = 0; 2370 if (NodeStack.size() > 1) 2371 Parent = NodeStack[NodeStack.size()-2].getNode(); 2372 RecordedNodes.push_back(std::make_pair(N, Parent)); 2373 continue; 2374 } 2375 2376 case OPC_RecordChild0: case OPC_RecordChild1: 2377 case OPC_RecordChild2: case OPC_RecordChild3: 2378 case OPC_RecordChild4: case OPC_RecordChild5: 2379 case OPC_RecordChild6: case OPC_RecordChild7: { 2380 unsigned ChildNo = Opcode-OPC_RecordChild0; 2381 if (ChildNo >= N.getNumOperands()) 2382 break; // Match fails if out of range child #. 2383 2384 RecordedNodes.push_back(std::make_pair(N->getOperand(ChildNo), 2385 N.getNode())); 2386 continue; 2387 } 2388 case OPC_RecordMemRef: 2389 MatchedMemRefs.push_back(cast<MemSDNode>(N)->getMemOperand()); 2390 continue; 2391 2392 case OPC_CaptureGlueInput: 2393 // If the current node has an input glue, capture it in InputGlue. 2394 if (N->getNumOperands() != 0 && 2395 N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Glue) 2396 InputGlue = N->getOperand(N->getNumOperands()-1); 2397 continue; 2398 2399 case OPC_MoveChild: { 2400 unsigned ChildNo = MatcherTable[MatcherIndex++]; 2401 if (ChildNo >= N.getNumOperands()) 2402 break; // Match fails if out of range child #. 2403 N = N.getOperand(ChildNo); 2404 NodeStack.push_back(N); 2405 continue; 2406 } 2407 2408 case OPC_MoveParent: 2409 // Pop the current node off the NodeStack. 2410 NodeStack.pop_back(); 2411 assert(!NodeStack.empty() && "Node stack imbalance!"); 2412 N = NodeStack.back(); 2413 continue; 2414 2415 case OPC_CheckSame: 2416 if (!::CheckSame(MatcherTable, MatcherIndex, N, RecordedNodes)) break; 2417 continue; 2418 case OPC_CheckPatternPredicate: 2419 if (!::CheckPatternPredicate(MatcherTable, MatcherIndex, *this)) break; 2420 continue; 2421 case OPC_CheckPredicate: 2422 if (!::CheckNodePredicate(MatcherTable, MatcherIndex, *this, 2423 N.getNode())) 2424 break; 2425 continue; 2426 case OPC_CheckComplexPat: { 2427 unsigned CPNum = MatcherTable[MatcherIndex++]; 2428 unsigned RecNo = MatcherTable[MatcherIndex++]; 2429 assert(RecNo < RecordedNodes.size() && "Invalid CheckComplexPat"); 2430 if (!CheckComplexPattern(NodeToMatch, RecordedNodes[RecNo].second, 2431 RecordedNodes[RecNo].first, CPNum, 2432 RecordedNodes)) 2433 break; 2434 continue; 2435 } 2436 case OPC_CheckOpcode: 2437 if (!::CheckOpcode(MatcherTable, MatcherIndex, N.getNode())) break; 2438 continue; 2439 2440 case OPC_CheckType: 2441 if (!::CheckType(MatcherTable, MatcherIndex, N, TLI)) break; 2442 continue; 2443 2444 case OPC_SwitchOpcode: { 2445 unsigned CurNodeOpcode = N.getOpcode(); 2446 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart; 2447 unsigned CaseSize; 2448 while (1) { 2449 // Get the size of this case. 2450 CaseSize = MatcherTable[MatcherIndex++]; 2451 if (CaseSize & 128) 2452 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex); 2453 if (CaseSize == 0) break; 2454 2455 uint16_t Opc = MatcherTable[MatcherIndex++]; 2456 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8; 2457 2458 // If the opcode matches, then we will execute this case. 2459 if (CurNodeOpcode == Opc) 2460 break; 2461 2462 // Otherwise, skip over this case. 2463 MatcherIndex += CaseSize; 2464 } 2465 2466 // If no cases matched, bail out. 2467 if (CaseSize == 0) break; 2468 2469 // Otherwise, execute the case we found. 2470 DEBUG(errs() << " OpcodeSwitch from " << SwitchStart 2471 << " to " << MatcherIndex << "\n"); 2472 continue; 2473 } 2474 2475 case OPC_SwitchType: { 2476 MVT CurNodeVT = N.getValueType().getSimpleVT(); 2477 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart; 2478 unsigned CaseSize; 2479 while (1) { 2480 // Get the size of this case. 2481 CaseSize = MatcherTable[MatcherIndex++]; 2482 if (CaseSize & 128) 2483 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex); 2484 if (CaseSize == 0) break; 2485 2486 MVT CaseVT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2487 if (CaseVT == MVT::iPTR) 2488 CaseVT = TLI.getPointerTy(); 2489 2490 // If the VT matches, then we will execute this case. 2491 if (CurNodeVT == CaseVT) 2492 break; 2493 2494 // Otherwise, skip over this case. 2495 MatcherIndex += CaseSize; 2496 } 2497 2498 // If no cases matched, bail out. 2499 if (CaseSize == 0) break; 2500 2501 // Otherwise, execute the case we found. 2502 DEBUG(errs() << " TypeSwitch[" << EVT(CurNodeVT).getEVTString() 2503 << "] from " << SwitchStart << " to " << MatcherIndex<<'\n'); 2504 continue; 2505 } 2506 case OPC_CheckChild0Type: case OPC_CheckChild1Type: 2507 case OPC_CheckChild2Type: case OPC_CheckChild3Type: 2508 case OPC_CheckChild4Type: case OPC_CheckChild5Type: 2509 case OPC_CheckChild6Type: case OPC_CheckChild7Type: 2510 if (!::CheckChildType(MatcherTable, MatcherIndex, N, TLI, 2511 Opcode-OPC_CheckChild0Type)) 2512 break; 2513 continue; 2514 case OPC_CheckCondCode: 2515 if (!::CheckCondCode(MatcherTable, MatcherIndex, N)) break; 2516 continue; 2517 case OPC_CheckValueType: 2518 if (!::CheckValueType(MatcherTable, MatcherIndex, N, TLI)) break; 2519 continue; 2520 case OPC_CheckInteger: 2521 if (!::CheckInteger(MatcherTable, MatcherIndex, N)) break; 2522 continue; 2523 case OPC_CheckAndImm: 2524 if (!::CheckAndImm(MatcherTable, MatcherIndex, N, *this)) break; 2525 continue; 2526 case OPC_CheckOrImm: 2527 if (!::CheckOrImm(MatcherTable, MatcherIndex, N, *this)) break; 2528 continue; 2529 2530 case OPC_CheckFoldableChainNode: { 2531 assert(NodeStack.size() != 1 && "No parent node"); 2532 // Verify that all intermediate nodes between the root and this one have 2533 // a single use. 2534 bool HasMultipleUses = false; 2535 for (unsigned i = 1, e = NodeStack.size()-1; i != e; ++i) 2536 if (!NodeStack[i].hasOneUse()) { 2537 HasMultipleUses = true; 2538 break; 2539 } 2540 if (HasMultipleUses) break; 2541 2542 // Check to see that the target thinks this is profitable to fold and that 2543 // we can fold it without inducing cycles in the graph. 2544 if (!IsProfitableToFold(N, NodeStack[NodeStack.size()-2].getNode(), 2545 NodeToMatch) || 2546 !IsLegalToFold(N, NodeStack[NodeStack.size()-2].getNode(), 2547 NodeToMatch, OptLevel, 2548 true/*We validate our own chains*/)) 2549 break; 2550 2551 continue; 2552 } 2553 case OPC_EmitInteger: { 2554 MVT::SimpleValueType VT = 2555 (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2556 int64_t Val = MatcherTable[MatcherIndex++]; 2557 if (Val & 128) 2558 Val = GetVBR(Val, MatcherTable, MatcherIndex); 2559 RecordedNodes.push_back(std::pair<SDValue, SDNode*>( 2560 CurDAG->getTargetConstant(Val, VT), (SDNode*)0)); 2561 continue; 2562 } 2563 case OPC_EmitRegister: { 2564 MVT::SimpleValueType VT = 2565 (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2566 unsigned RegNo = MatcherTable[MatcherIndex++]; 2567 RecordedNodes.push_back(std::pair<SDValue, SDNode*>( 2568 CurDAG->getRegister(RegNo, VT), (SDNode*)0)); 2569 continue; 2570 } 2571 case OPC_EmitRegister2: { 2572 // For targets w/ more than 256 register names, the register enum 2573 // values are stored in two bytes in the matcher table (just like 2574 // opcodes). 2575 MVT::SimpleValueType VT = 2576 (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2577 unsigned RegNo = MatcherTable[MatcherIndex++]; 2578 RegNo |= MatcherTable[MatcherIndex++] << 8; 2579 RecordedNodes.push_back(std::pair<SDValue, SDNode*>( 2580 CurDAG->getRegister(RegNo, VT), (SDNode*)0)); 2581 continue; 2582 } 2583 2584 case OPC_EmitConvertToTarget: { 2585 // Convert from IMM/FPIMM to target version. 2586 unsigned RecNo = MatcherTable[MatcherIndex++]; 2587 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2588 SDValue Imm = RecordedNodes[RecNo].first; 2589 2590 if (Imm->getOpcode() == ISD::Constant) { 2591 int64_t Val = cast<ConstantSDNode>(Imm)->getZExtValue(); 2592 Imm = CurDAG->getTargetConstant(Val, Imm.getValueType()); 2593 } else if (Imm->getOpcode() == ISD::ConstantFP) { 2594 const ConstantFP *Val=cast<ConstantFPSDNode>(Imm)->getConstantFPValue(); 2595 Imm = CurDAG->getTargetConstantFP(*Val, Imm.getValueType()); 2596 } 2597 2598 RecordedNodes.push_back(std::make_pair(Imm, RecordedNodes[RecNo].second)); 2599 continue; 2600 } 2601 2602 case OPC_EmitMergeInputChains1_0: // OPC_EmitMergeInputChains, 1, 0 2603 case OPC_EmitMergeInputChains1_1: { // OPC_EmitMergeInputChains, 1, 1 2604 // These are space-optimized forms of OPC_EmitMergeInputChains. 2605 assert(InputChain.getNode() == 0 && 2606 "EmitMergeInputChains should be the first chain producing node"); 2607 assert(ChainNodesMatched.empty() && 2608 "Should only have one EmitMergeInputChains per match"); 2609 2610 // Read all of the chained nodes. 2611 unsigned RecNo = Opcode == OPC_EmitMergeInputChains1_1; 2612 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2613 ChainNodesMatched.push_back(RecordedNodes[RecNo].first.getNode()); 2614 2615 // FIXME: What if other value results of the node have uses not matched 2616 // by this pattern? 2617 if (ChainNodesMatched.back() != NodeToMatch && 2618 !RecordedNodes[RecNo].first.hasOneUse()) { 2619 ChainNodesMatched.clear(); 2620 break; 2621 } 2622 2623 // Merge the input chains if they are not intra-pattern references. 2624 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG); 2625 2626 if (InputChain.getNode() == 0) 2627 break; // Failed to merge. 2628 continue; 2629 } 2630 2631 case OPC_EmitMergeInputChains: { 2632 assert(InputChain.getNode() == 0 && 2633 "EmitMergeInputChains should be the first chain producing node"); 2634 // This node gets a list of nodes we matched in the input that have 2635 // chains. We want to token factor all of the input chains to these nodes 2636 // together. However, if any of the input chains is actually one of the 2637 // nodes matched in this pattern, then we have an intra-match reference. 2638 // Ignore these because the newly token factored chain should not refer to 2639 // the old nodes. 2640 unsigned NumChains = MatcherTable[MatcherIndex++]; 2641 assert(NumChains != 0 && "Can't TF zero chains"); 2642 2643 assert(ChainNodesMatched.empty() && 2644 "Should only have one EmitMergeInputChains per match"); 2645 2646 // Read all of the chained nodes. 2647 for (unsigned i = 0; i != NumChains; ++i) { 2648 unsigned RecNo = MatcherTable[MatcherIndex++]; 2649 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2650 ChainNodesMatched.push_back(RecordedNodes[RecNo].first.getNode()); 2651 2652 // FIXME: What if other value results of the node have uses not matched 2653 // by this pattern? 2654 if (ChainNodesMatched.back() != NodeToMatch && 2655 !RecordedNodes[RecNo].first.hasOneUse()) { 2656 ChainNodesMatched.clear(); 2657 break; 2658 } 2659 } 2660 2661 // If the inner loop broke out, the match fails. 2662 if (ChainNodesMatched.empty()) 2663 break; 2664 2665 // Merge the input chains if they are not intra-pattern references. 2666 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG); 2667 2668 if (InputChain.getNode() == 0) 2669 break; // Failed to merge. 2670 2671 continue; 2672 } 2673 2674 case OPC_EmitCopyToReg: { 2675 unsigned RecNo = MatcherTable[MatcherIndex++]; 2676 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2677 unsigned DestPhysReg = MatcherTable[MatcherIndex++]; 2678 2679 if (InputChain.getNode() == 0) 2680 InputChain = CurDAG->getEntryNode(); 2681 2682 InputChain = CurDAG->getCopyToReg(InputChain, NodeToMatch->getDebugLoc(), 2683 DestPhysReg, RecordedNodes[RecNo].first, 2684 InputGlue); 2685 2686 InputGlue = InputChain.getValue(1); 2687 continue; 2688 } 2689 2690 case OPC_EmitNodeXForm: { 2691 unsigned XFormNo = MatcherTable[MatcherIndex++]; 2692 unsigned RecNo = MatcherTable[MatcherIndex++]; 2693 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2694 SDValue Res = RunSDNodeXForm(RecordedNodes[RecNo].first, XFormNo); 2695 RecordedNodes.push_back(std::pair<SDValue,SDNode*>(Res, (SDNode*) 0)); 2696 continue; 2697 } 2698 2699 case OPC_EmitNode: 2700 case OPC_MorphNodeTo: { 2701 uint16_t TargetOpc = MatcherTable[MatcherIndex++]; 2702 TargetOpc |= (unsigned short)MatcherTable[MatcherIndex++] << 8; 2703 unsigned EmitNodeInfo = MatcherTable[MatcherIndex++]; 2704 // Get the result VT list. 2705 unsigned NumVTs = MatcherTable[MatcherIndex++]; 2706 SmallVector<EVT, 4> VTs; 2707 for (unsigned i = 0; i != NumVTs; ++i) { 2708 MVT::SimpleValueType VT = 2709 (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2710 if (VT == MVT::iPTR) VT = TLI.getPointerTy().SimpleTy; 2711 VTs.push_back(VT); 2712 } 2713 2714 if (EmitNodeInfo & OPFL_Chain) 2715 VTs.push_back(MVT::Other); 2716 if (EmitNodeInfo & OPFL_GlueOutput) 2717 VTs.push_back(MVT::Glue); 2718 2719 // This is hot code, so optimize the two most common cases of 1 and 2 2720 // results. 2721 SDVTList VTList; 2722 if (VTs.size() == 1) 2723 VTList = CurDAG->getVTList(VTs[0]); 2724 else if (VTs.size() == 2) 2725 VTList = CurDAG->getVTList(VTs[0], VTs[1]); 2726 else 2727 VTList = CurDAG->getVTList(VTs.data(), VTs.size()); 2728 2729 // Get the operand list. 2730 unsigned NumOps = MatcherTable[MatcherIndex++]; 2731 SmallVector<SDValue, 8> Ops; 2732 for (unsigned i = 0; i != NumOps; ++i) { 2733 unsigned RecNo = MatcherTable[MatcherIndex++]; 2734 if (RecNo & 128) 2735 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex); 2736 2737 assert(RecNo < RecordedNodes.size() && "Invalid EmitNode"); 2738 Ops.push_back(RecordedNodes[RecNo].first); 2739 } 2740 2741 // If there are variadic operands to add, handle them now. 2742 if (EmitNodeInfo & OPFL_VariadicInfo) { 2743 // Determine the start index to copy from. 2744 unsigned FirstOpToCopy = getNumFixedFromVariadicInfo(EmitNodeInfo); 2745 FirstOpToCopy += (EmitNodeInfo & OPFL_Chain) ? 1 : 0; 2746 assert(NodeToMatch->getNumOperands() >= FirstOpToCopy && 2747 "Invalid variadic node"); 2748 // Copy all of the variadic operands, not including a potential glue 2749 // input. 2750 for (unsigned i = FirstOpToCopy, e = NodeToMatch->getNumOperands(); 2751 i != e; ++i) { 2752 SDValue V = NodeToMatch->getOperand(i); 2753 if (V.getValueType() == MVT::Glue) break; 2754 Ops.push_back(V); 2755 } 2756 } 2757 2758 // If this has chain/glue inputs, add them. 2759 if (EmitNodeInfo & OPFL_Chain) 2760 Ops.push_back(InputChain); 2761 if ((EmitNodeInfo & OPFL_GlueInput) && InputGlue.getNode() != 0) 2762 Ops.push_back(InputGlue); 2763 2764 // Create the node. 2765 SDNode *Res = 0; 2766 if (Opcode != OPC_MorphNodeTo) { 2767 // If this is a normal EmitNode command, just create the new node and 2768 // add the results to the RecordedNodes list. 2769 Res = CurDAG->getMachineNode(TargetOpc, NodeToMatch->getDebugLoc(), 2770 VTList, Ops.data(), Ops.size()); 2771 2772 // Add all the non-glue/non-chain results to the RecordedNodes list. 2773 for (unsigned i = 0, e = VTs.size(); i != e; ++i) { 2774 if (VTs[i] == MVT::Other || VTs[i] == MVT::Glue) break; 2775 RecordedNodes.push_back(std::pair<SDValue,SDNode*>(SDValue(Res, i), 2776 (SDNode*) 0)); 2777 } 2778 2779 } else if (NodeToMatch->getOpcode() != ISD::DELETED_NODE) { 2780 Res = MorphNode(NodeToMatch, TargetOpc, VTList, Ops.data(), Ops.size(), 2781 EmitNodeInfo); 2782 } else { 2783 // NodeToMatch was eliminated by CSE when the target changed the DAG. 2784 // We will visit the equivalent node later. 2785 DEBUG(dbgs() << "Node was eliminated by CSE\n"); 2786 return 0; 2787 } 2788 2789 // If the node had chain/glue results, update our notion of the current 2790 // chain and glue. 2791 if (EmitNodeInfo & OPFL_GlueOutput) { 2792 InputGlue = SDValue(Res, VTs.size()-1); 2793 if (EmitNodeInfo & OPFL_Chain) 2794 InputChain = SDValue(Res, VTs.size()-2); 2795 } else if (EmitNodeInfo & OPFL_Chain) 2796 InputChain = SDValue(Res, VTs.size()-1); 2797 2798 // If the OPFL_MemRefs glue is set on this node, slap all of the 2799 // accumulated memrefs onto it. 2800 // 2801 // FIXME: This is vastly incorrect for patterns with multiple outputs 2802 // instructions that access memory and for ComplexPatterns that match 2803 // loads. 2804 if (EmitNodeInfo & OPFL_MemRefs) { 2805 // Only attach load or store memory operands if the generated 2806 // instruction may load or store. 2807 const MCInstrDesc &MCID = TM.getInstrInfo()->get(TargetOpc); 2808 bool mayLoad = MCID.mayLoad(); 2809 bool mayStore = MCID.mayStore(); 2810 2811 unsigned NumMemRefs = 0; 2812 for (SmallVector<MachineMemOperand*, 2>::const_iterator I = 2813 MatchedMemRefs.begin(), E = MatchedMemRefs.end(); I != E; ++I) { 2814 if ((*I)->isLoad()) { 2815 if (mayLoad) 2816 ++NumMemRefs; 2817 } else if ((*I)->isStore()) { 2818 if (mayStore) 2819 ++NumMemRefs; 2820 } else { 2821 ++NumMemRefs; 2822 } 2823 } 2824 2825 MachineSDNode::mmo_iterator MemRefs = 2826 MF->allocateMemRefsArray(NumMemRefs); 2827 2828 MachineSDNode::mmo_iterator MemRefsPos = MemRefs; 2829 for (SmallVector<MachineMemOperand*, 2>::const_iterator I = 2830 MatchedMemRefs.begin(), E = MatchedMemRefs.end(); I != E; ++I) { 2831 if ((*I)->isLoad()) { 2832 if (mayLoad) 2833 *MemRefsPos++ = *I; 2834 } else if ((*I)->isStore()) { 2835 if (mayStore) 2836 *MemRefsPos++ = *I; 2837 } else { 2838 *MemRefsPos++ = *I; 2839 } 2840 } 2841 2842 cast<MachineSDNode>(Res) 2843 ->setMemRefs(MemRefs, MemRefs + NumMemRefs); 2844 } 2845 2846 DEBUG(errs() << " " 2847 << (Opcode == OPC_MorphNodeTo ? "Morphed" : "Created") 2848 << " node: "; Res->dump(CurDAG); errs() << "\n"); 2849 2850 // If this was a MorphNodeTo then we're completely done! 2851 if (Opcode == OPC_MorphNodeTo) { 2852 // Update chain and glue uses. 2853 UpdateChainsAndGlue(NodeToMatch, InputChain, ChainNodesMatched, 2854 InputGlue, GlueResultNodesMatched, true); 2855 return Res; 2856 } 2857 2858 continue; 2859 } 2860 2861 case OPC_MarkGlueResults: { 2862 unsigned NumNodes = MatcherTable[MatcherIndex++]; 2863 2864 // Read and remember all the glue-result nodes. 2865 for (unsigned i = 0; i != NumNodes; ++i) { 2866 unsigned RecNo = MatcherTable[MatcherIndex++]; 2867 if (RecNo & 128) 2868 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex); 2869 2870 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2871 GlueResultNodesMatched.push_back(RecordedNodes[RecNo].first.getNode()); 2872 } 2873 continue; 2874 } 2875 2876 case OPC_CompleteMatch: { 2877 // The match has been completed, and any new nodes (if any) have been 2878 // created. Patch up references to the matched dag to use the newly 2879 // created nodes. 2880 unsigned NumResults = MatcherTable[MatcherIndex++]; 2881 2882 for (unsigned i = 0; i != NumResults; ++i) { 2883 unsigned ResSlot = MatcherTable[MatcherIndex++]; 2884 if (ResSlot & 128) 2885 ResSlot = GetVBR(ResSlot, MatcherTable, MatcherIndex); 2886 2887 assert(ResSlot < RecordedNodes.size() && "Invalid CheckSame"); 2888 SDValue Res = RecordedNodes[ResSlot].first; 2889 2890 assert(i < NodeToMatch->getNumValues() && 2891 NodeToMatch->getValueType(i) != MVT::Other && 2892 NodeToMatch->getValueType(i) != MVT::Glue && 2893 "Invalid number of results to complete!"); 2894 assert((NodeToMatch->getValueType(i) == Res.getValueType() || 2895 NodeToMatch->getValueType(i) == MVT::iPTR || 2896 Res.getValueType() == MVT::iPTR || 2897 NodeToMatch->getValueType(i).getSizeInBits() == 2898 Res.getValueType().getSizeInBits()) && 2899 "invalid replacement"); 2900 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, i), Res); 2901 } 2902 2903 // If the root node defines glue, add it to the glue nodes to update list. 2904 if (NodeToMatch->getValueType(NodeToMatch->getNumValues()-1) == MVT::Glue) 2905 GlueResultNodesMatched.push_back(NodeToMatch); 2906 2907 // Update chain and glue uses. 2908 UpdateChainsAndGlue(NodeToMatch, InputChain, ChainNodesMatched, 2909 InputGlue, GlueResultNodesMatched, false); 2910 2911 assert(NodeToMatch->use_empty() && 2912 "Didn't replace all uses of the node?"); 2913 2914 // FIXME: We just return here, which interacts correctly with SelectRoot 2915 // above. We should fix this to not return an SDNode* anymore. 2916 return 0; 2917 } 2918 } 2919 2920 // If the code reached this point, then the match failed. See if there is 2921 // another child to try in the current 'Scope', otherwise pop it until we 2922 // find a case to check. 2923 DEBUG(errs() << " Match failed at index " << CurrentOpcodeIndex << "\n"); 2924 ++NumDAGIselRetries; 2925 while (1) { 2926 if (MatchScopes.empty()) { 2927 CannotYetSelect(NodeToMatch); 2928 return 0; 2929 } 2930 2931 // Restore the interpreter state back to the point where the scope was 2932 // formed. 2933 MatchScope &LastScope = MatchScopes.back(); 2934 RecordedNodes.resize(LastScope.NumRecordedNodes); 2935 NodeStack.clear(); 2936 NodeStack.append(LastScope.NodeStack.begin(), LastScope.NodeStack.end()); 2937 N = NodeStack.back(); 2938 2939 if (LastScope.NumMatchedMemRefs != MatchedMemRefs.size()) 2940 MatchedMemRefs.resize(LastScope.NumMatchedMemRefs); 2941 MatcherIndex = LastScope.FailIndex; 2942 2943 DEBUG(errs() << " Continuing at " << MatcherIndex << "\n"); 2944 2945 InputChain = LastScope.InputChain; 2946 InputGlue = LastScope.InputGlue; 2947 if (!LastScope.HasChainNodesMatched) 2948 ChainNodesMatched.clear(); 2949 if (!LastScope.HasGlueResultNodesMatched) 2950 GlueResultNodesMatched.clear(); 2951 2952 // Check to see what the offset is at the new MatcherIndex. If it is zero 2953 // we have reached the end of this scope, otherwise we have another child 2954 // in the current scope to try. 2955 unsigned NumToSkip = MatcherTable[MatcherIndex++]; 2956 if (NumToSkip & 128) 2957 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex); 2958 2959 // If we have another child in this scope to match, update FailIndex and 2960 // try it. 2961 if (NumToSkip != 0) { 2962 LastScope.FailIndex = MatcherIndex+NumToSkip; 2963 break; 2964 } 2965 2966 // End of this scope, pop it and try the next child in the containing 2967 // scope. 2968 MatchScopes.pop_back(); 2969 } 2970 } 2971} 2972 2973 2974 2975void SelectionDAGISel::CannotYetSelect(SDNode *N) { 2976 std::string msg; 2977 raw_string_ostream Msg(msg); 2978 Msg << "Cannot select: "; 2979 2980 if (N->getOpcode() != ISD::INTRINSIC_W_CHAIN && 2981 N->getOpcode() != ISD::INTRINSIC_WO_CHAIN && 2982 N->getOpcode() != ISD::INTRINSIC_VOID) { 2983 N->printrFull(Msg, CurDAG); 2984 Msg << "\nIn function: " << MF->getFunction()->getName(); 2985 } else { 2986 bool HasInputChain = N->getOperand(0).getValueType() == MVT::Other; 2987 unsigned iid = 2988 cast<ConstantSDNode>(N->getOperand(HasInputChain))->getZExtValue(); 2989 if (iid < Intrinsic::num_intrinsics) 2990 Msg << "intrinsic %" << Intrinsic::getName((Intrinsic::ID)iid); 2991 else if (const TargetIntrinsicInfo *TII = TM.getIntrinsicInfo()) 2992 Msg << "target intrinsic %" << TII->getName(iid); 2993 else 2994 Msg << "unknown intrinsic #" << iid; 2995 } 2996 report_fatal_error(Msg.str()); 2997} 2998 2999char SelectionDAGISel::ID = 0; 3000