SelectionDAGISel.cpp revision 208599
1//===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This implements the SelectionDAGISel class. 11// 12//===----------------------------------------------------------------------===// 13 14#define DEBUG_TYPE "isel" 15#include "ScheduleDAGSDNodes.h" 16#include "SelectionDAGBuilder.h" 17#include "FunctionLoweringInfo.h" 18#include "llvm/CodeGen/SelectionDAGISel.h" 19#include "llvm/Analysis/AliasAnalysis.h" 20#include "llvm/Analysis/DebugInfo.h" 21#include "llvm/Constants.h" 22#include "llvm/Function.h" 23#include "llvm/InlineAsm.h" 24#include "llvm/Instructions.h" 25#include "llvm/Intrinsics.h" 26#include "llvm/IntrinsicInst.h" 27#include "llvm/LLVMContext.h" 28#include "llvm/Module.h" 29#include "llvm/CodeGen/FastISel.h" 30#include "llvm/CodeGen/GCStrategy.h" 31#include "llvm/CodeGen/GCMetadata.h" 32#include "llvm/CodeGen/MachineFrameInfo.h" 33#include "llvm/CodeGen/MachineFunction.h" 34#include "llvm/CodeGen/MachineInstrBuilder.h" 35#include "llvm/CodeGen/MachineModuleInfo.h" 36#include "llvm/CodeGen/MachineRegisterInfo.h" 37#include "llvm/CodeGen/ScheduleHazardRecognizer.h" 38#include "llvm/CodeGen/SchedulerRegistry.h" 39#include "llvm/CodeGen/SelectionDAG.h" 40#include "llvm/Target/TargetRegisterInfo.h" 41#include "llvm/Target/TargetIntrinsicInfo.h" 42#include "llvm/Target/TargetInstrInfo.h" 43#include "llvm/Target/TargetLowering.h" 44#include "llvm/Target/TargetMachine.h" 45#include "llvm/Target/TargetOptions.h" 46#include "llvm/Support/Compiler.h" 47#include "llvm/Support/Debug.h" 48#include "llvm/Support/ErrorHandling.h" 49#include "llvm/Support/Timer.h" 50#include "llvm/Support/raw_ostream.h" 51#include "llvm/ADT/Statistic.h" 52#include <algorithm> 53using namespace llvm; 54 55STATISTIC(NumFastIselFailures, "Number of instructions fast isel failed on"); 56STATISTIC(NumDAGIselRetries,"Number of times dag isel has to try another path"); 57 58static cl::opt<bool> 59EnableFastISelVerbose("fast-isel-verbose", cl::Hidden, 60 cl::desc("Enable verbose messages in the \"fast\" " 61 "instruction selector")); 62static cl::opt<bool> 63EnableFastISelAbort("fast-isel-abort", cl::Hidden, 64 cl::desc("Enable abort calls when \"fast\" instruction fails")); 65 66#ifndef NDEBUG 67static cl::opt<bool> 68ViewDAGCombine1("view-dag-combine1-dags", cl::Hidden, 69 cl::desc("Pop up a window to show dags before the first " 70 "dag combine pass")); 71static cl::opt<bool> 72ViewLegalizeTypesDAGs("view-legalize-types-dags", cl::Hidden, 73 cl::desc("Pop up a window to show dags before legalize types")); 74static cl::opt<bool> 75ViewLegalizeDAGs("view-legalize-dags", cl::Hidden, 76 cl::desc("Pop up a window to show dags before legalize")); 77static cl::opt<bool> 78ViewDAGCombine2("view-dag-combine2-dags", cl::Hidden, 79 cl::desc("Pop up a window to show dags before the second " 80 "dag combine pass")); 81static cl::opt<bool> 82ViewDAGCombineLT("view-dag-combine-lt-dags", cl::Hidden, 83 cl::desc("Pop up a window to show dags before the post legalize types" 84 " dag combine pass")); 85static cl::opt<bool> 86ViewISelDAGs("view-isel-dags", cl::Hidden, 87 cl::desc("Pop up a window to show isel dags as they are selected")); 88static cl::opt<bool> 89ViewSchedDAGs("view-sched-dags", cl::Hidden, 90 cl::desc("Pop up a window to show sched dags as they are processed")); 91static cl::opt<bool> 92ViewSUnitDAGs("view-sunit-dags", cl::Hidden, 93 cl::desc("Pop up a window to show SUnit dags after they are processed")); 94#else 95static const bool ViewDAGCombine1 = false, 96 ViewLegalizeTypesDAGs = false, ViewLegalizeDAGs = false, 97 ViewDAGCombine2 = false, 98 ViewDAGCombineLT = false, 99 ViewISelDAGs = false, ViewSchedDAGs = false, 100 ViewSUnitDAGs = false; 101#endif 102 103//===---------------------------------------------------------------------===// 104/// 105/// RegisterScheduler class - Track the registration of instruction schedulers. 106/// 107//===---------------------------------------------------------------------===// 108MachinePassRegistry RegisterScheduler::Registry; 109 110//===---------------------------------------------------------------------===// 111/// 112/// ISHeuristic command line option for instruction schedulers. 113/// 114//===---------------------------------------------------------------------===// 115static cl::opt<RegisterScheduler::FunctionPassCtor, false, 116 RegisterPassParser<RegisterScheduler> > 117ISHeuristic("pre-RA-sched", 118 cl::init(&createDefaultScheduler), 119 cl::desc("Instruction schedulers available (before register" 120 " allocation):")); 121 122static RegisterScheduler 123defaultListDAGScheduler("default", "Best scheduler for the target", 124 createDefaultScheduler); 125 126namespace llvm { 127 //===--------------------------------------------------------------------===// 128 /// createDefaultScheduler - This creates an instruction scheduler appropriate 129 /// for the target. 130 ScheduleDAGSDNodes* createDefaultScheduler(SelectionDAGISel *IS, 131 CodeGenOpt::Level OptLevel) { 132 const TargetLowering &TLI = IS->getTargetLowering(); 133 134 if (OptLevel == CodeGenOpt::None) 135 return createFastDAGScheduler(IS, OptLevel); 136 if (TLI.getSchedulingPreference() == Sched::Latency) 137 return createTDListDAGScheduler(IS, OptLevel); 138 if (TLI.getSchedulingPreference() == Sched::RegPressure) 139 return createBURRListDAGScheduler(IS, OptLevel); 140 assert(TLI.getSchedulingPreference() == Sched::Hybrid && 141 "Unknown sched type!"); 142 return createHybridListDAGScheduler(IS, OptLevel); 143 } 144} 145 146// EmitInstrWithCustomInserter - This method should be implemented by targets 147// that mark instructions with the 'usesCustomInserter' flag. These 148// instructions are special in various ways, which require special support to 149// insert. The specified MachineInstr is created but not inserted into any 150// basic blocks, and this method is called to expand it into a sequence of 151// instructions, potentially also creating new basic blocks and control flow. 152// When new basic blocks are inserted and the edges from MBB to its successors 153// are modified, the method should insert pairs of <OldSucc, NewSucc> into the 154// DenseMap. 155MachineBasicBlock * 156TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 157 MachineBasicBlock *MBB) const { 158#ifndef NDEBUG 159 dbgs() << "If a target marks an instruction with " 160 "'usesCustomInserter', it must implement " 161 "TargetLowering::EmitInstrWithCustomInserter!"; 162#endif 163 llvm_unreachable(0); 164 return 0; 165} 166 167//===----------------------------------------------------------------------===// 168// SelectionDAGISel code 169//===----------------------------------------------------------------------===// 170 171SelectionDAGISel::SelectionDAGISel(const TargetMachine &tm, CodeGenOpt::Level OL) : 172 MachineFunctionPass(&ID), TM(tm), TLI(*tm.getTargetLowering()), 173 FuncInfo(new FunctionLoweringInfo(TLI)), 174 CurDAG(new SelectionDAG(tm, *FuncInfo)), 175 SDB(new SelectionDAGBuilder(*CurDAG, *FuncInfo, OL)), 176 GFI(), 177 OptLevel(OL), 178 DAGSize(0) 179{} 180 181SelectionDAGISel::~SelectionDAGISel() { 182 delete SDB; 183 delete CurDAG; 184 delete FuncInfo; 185} 186 187void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const { 188 AU.addRequired<AliasAnalysis>(); 189 AU.addPreserved<AliasAnalysis>(); 190 AU.addRequired<GCModuleInfo>(); 191 AU.addPreserved<GCModuleInfo>(); 192 MachineFunctionPass::getAnalysisUsage(AU); 193} 194 195/// FunctionCallsSetJmp - Return true if the function has a call to setjmp or 196/// other function that gcc recognizes as "returning twice". This is used to 197/// limit code-gen optimizations on the machine function. 198/// 199/// FIXME: Remove after <rdar://problem/8031714> is fixed. 200static bool FunctionCallsSetJmp(const Function *F) { 201 const Module *M = F->getParent(); 202 static const char *ReturnsTwiceFns[] = { 203 "setjmp", 204 "sigsetjmp", 205 "setjmp_syscall", 206 "savectx", 207 "qsetjmp", 208 "vfork", 209 "getcontext" 210 }; 211#define NUM_RETURNS_TWICE_FNS sizeof(ReturnsTwiceFns) / sizeof(const char *) 212 213 for (unsigned I = 0; I < NUM_RETURNS_TWICE_FNS; ++I) 214 if (const Function *Callee = M->getFunction(ReturnsTwiceFns[I])) { 215 if (!Callee->use_empty()) 216 for (Value::const_use_iterator 217 I = Callee->use_begin(), E = Callee->use_end(); 218 I != E; ++I) 219 if (const CallInst *CI = dyn_cast<CallInst>(I)) 220 if (CI->getParent()->getParent() == F) 221 return true; 222 } 223 224 return false; 225#undef NUM_RETURNS_TWICE_FNS 226} 227 228bool SelectionDAGISel::runOnMachineFunction(MachineFunction &mf) { 229 // Do some sanity-checking on the command-line options. 230 assert((!EnableFastISelVerbose || EnableFastISel) && 231 "-fast-isel-verbose requires -fast-isel"); 232 assert((!EnableFastISelAbort || EnableFastISel) && 233 "-fast-isel-abort requires -fast-isel"); 234 235 const Function &Fn = *mf.getFunction(); 236 const TargetInstrInfo &TII = *TM.getInstrInfo(); 237 const TargetRegisterInfo &TRI = *TM.getRegisterInfo(); 238 239 MF = &mf; 240 RegInfo = &MF->getRegInfo(); 241 AA = &getAnalysis<AliasAnalysis>(); 242 GFI = Fn.hasGC() ? &getAnalysis<GCModuleInfo>().getFunctionInfo(Fn) : 0; 243 244 DEBUG(dbgs() << "\n\n\n=== " << Fn.getName() << "\n"); 245 246 CurDAG->init(*MF); 247 FuncInfo->set(Fn, *MF, EnableFastISel); 248 SDB->init(GFI, *AA); 249 250 SelectAllBasicBlocks(Fn); 251 252 // If the first basic block in the function has live ins that need to be 253 // copied into vregs, emit the copies into the top of the block before 254 // emitting the code for the block. 255 MachineBasicBlock *EntryMBB = MF->begin(); 256 RegInfo->EmitLiveInCopies(EntryMBB, TRI, TII); 257 258 DenseMap<unsigned, unsigned> LiveInMap; 259 if (!FuncInfo->ArgDbgValues.empty()) 260 for (MachineRegisterInfo::livein_iterator LI = RegInfo->livein_begin(), 261 E = RegInfo->livein_end(); LI != E; ++LI) 262 if (LI->second) 263 LiveInMap.insert(std::make_pair(LI->first, LI->second)); 264 265 // Insert DBG_VALUE instructions for function arguments to the entry block. 266 for (unsigned i = 0, e = FuncInfo->ArgDbgValues.size(); i != e; ++i) { 267 MachineInstr *MI = FuncInfo->ArgDbgValues[e-i-1]; 268 unsigned Reg = MI->getOperand(0).getReg(); 269 if (TargetRegisterInfo::isPhysicalRegister(Reg)) 270 EntryMBB->insert(EntryMBB->begin(), MI); 271 else { 272 MachineInstr *Def = RegInfo->getVRegDef(Reg); 273 MachineBasicBlock::iterator InsertPos = Def; 274 // FIXME: VR def may not be in entry block. 275 Def->getParent()->insert(llvm::next(InsertPos), MI); 276 } 277 278 // If Reg is live-in then update debug info to track its copy in a vreg. 279 DenseMap<unsigned, unsigned>::iterator LDI = LiveInMap.find(Reg); 280 if (LDI != LiveInMap.end()) { 281 MachineInstr *Def = RegInfo->getVRegDef(LDI->second); 282 MachineBasicBlock::iterator InsertPos = Def; 283 const MDNode *Variable = 284 MI->getOperand(MI->getNumOperands()-1).getMetadata(); 285 unsigned Offset = MI->getOperand(1).getImm(); 286 // Def is never a terminator here, so it is ok to increment InsertPos. 287 BuildMI(*EntryMBB, ++InsertPos, MI->getDebugLoc(), 288 TII.get(TargetOpcode::DBG_VALUE)) 289 .addReg(LDI->second, RegState::Debug) 290 .addImm(Offset).addMetadata(Variable); 291 } 292 } 293 294 // Determine if there are any calls in this machine function. 295 MachineFrameInfo *MFI = MF->getFrameInfo(); 296 if (!MFI->hasCalls()) { 297 for (MachineFunction::const_iterator 298 I = MF->begin(), E = MF->end(); I != E; ++I) { 299 const MachineBasicBlock *MBB = I; 300 for (MachineBasicBlock::const_iterator 301 II = MBB->begin(), IE = MBB->end(); II != IE; ++II) { 302 const TargetInstrDesc &TID = TM.getInstrInfo()->get(II->getOpcode()); 303 if (II->isInlineAsm() || (TID.isCall() && !TID.isReturn())) { 304 MFI->setHasCalls(true); 305 goto done; 306 } 307 } 308 } 309 done:; 310 } 311 312 // Determine if there is a call to setjmp in the machine function. 313 MF->setCallsSetJmp(FunctionCallsSetJmp(&Fn)); 314 315 // Release function-specific state. SDB and CurDAG are already cleared 316 // at this point. 317 FuncInfo->clear(); 318 319 return true; 320} 321 322MachineBasicBlock * 323SelectionDAGISel::SelectBasicBlock(MachineBasicBlock *BB, 324 const BasicBlock *LLVMBB, 325 BasicBlock::const_iterator Begin, 326 BasicBlock::const_iterator End, 327 bool &HadTailCall) { 328 // Lower all of the non-terminator instructions. If a call is emitted 329 // as a tail call, cease emitting nodes for this block. Terminators 330 // are handled below. 331 for (BasicBlock::const_iterator I = Begin; I != End && !SDB->HasTailCall; ++I) 332 SDB->visit(*I); 333 334 // Make sure the root of the DAG is up-to-date. 335 CurDAG->setRoot(SDB->getControlRoot()); 336 HadTailCall = SDB->HasTailCall; 337 SDB->clear(); 338 339 // Final step, emit the lowered DAG as machine code. 340 return CodeGenAndEmitDAG(BB); 341} 342 343namespace { 344/// WorkListRemover - This class is a DAGUpdateListener that removes any deleted 345/// nodes from the worklist. 346class SDOPsWorkListRemover : public SelectionDAG::DAGUpdateListener { 347 SmallVector<SDNode*, 128> &Worklist; 348 SmallPtrSet<SDNode*, 128> &InWorklist; 349public: 350 SDOPsWorkListRemover(SmallVector<SDNode*, 128> &wl, 351 SmallPtrSet<SDNode*, 128> &inwl) 352 : Worklist(wl), InWorklist(inwl) {} 353 354 void RemoveFromWorklist(SDNode *N) { 355 if (!InWorklist.erase(N)) return; 356 357 SmallVector<SDNode*, 128>::iterator I = 358 std::find(Worklist.begin(), Worklist.end(), N); 359 assert(I != Worklist.end() && "Not in worklist"); 360 361 *I = Worklist.back(); 362 Worklist.pop_back(); 363 } 364 365 virtual void NodeDeleted(SDNode *N, SDNode *E) { 366 RemoveFromWorklist(N); 367 } 368 369 virtual void NodeUpdated(SDNode *N) { 370 // Ignore updates. 371 } 372}; 373} 374 375/// TrivialTruncElim - Eliminate some trivial nops that can result from 376/// ShrinkDemandedOps: (trunc (ext n)) -> n. 377static bool TrivialTruncElim(SDValue Op, 378 TargetLowering::TargetLoweringOpt &TLO) { 379 SDValue N0 = Op.getOperand(0); 380 EVT VT = Op.getValueType(); 381 if ((N0.getOpcode() == ISD::ZERO_EXTEND || 382 N0.getOpcode() == ISD::SIGN_EXTEND || 383 N0.getOpcode() == ISD::ANY_EXTEND) && 384 N0.getOperand(0).getValueType() == VT) { 385 return TLO.CombineTo(Op, N0.getOperand(0)); 386 } 387 return false; 388} 389 390/// ShrinkDemandedOps - A late transformation pass that shrink expressions 391/// using TargetLowering::TargetLoweringOpt::ShrinkDemandedOp. It converts 392/// x+y to (VT)((SmallVT)x+(SmallVT)y) if the casts are free. 393void SelectionDAGISel::ShrinkDemandedOps() { 394 SmallVector<SDNode*, 128> Worklist; 395 SmallPtrSet<SDNode*, 128> InWorklist; 396 397 // Add all the dag nodes to the worklist. 398 Worklist.reserve(CurDAG->allnodes_size()); 399 for (SelectionDAG::allnodes_iterator I = CurDAG->allnodes_begin(), 400 E = CurDAG->allnodes_end(); I != E; ++I) { 401 Worklist.push_back(I); 402 InWorklist.insert(I); 403 } 404 405 TargetLowering::TargetLoweringOpt TLO(*CurDAG, true, true, true); 406 while (!Worklist.empty()) { 407 SDNode *N = Worklist.pop_back_val(); 408 InWorklist.erase(N); 409 410 if (N->use_empty() && N != CurDAG->getRoot().getNode()) { 411 // Deleting this node may make its operands dead, add them to the worklist 412 // if they aren't already there. 413 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 414 if (InWorklist.insert(N->getOperand(i).getNode())) 415 Worklist.push_back(N->getOperand(i).getNode()); 416 417 CurDAG->DeleteNode(N); 418 continue; 419 } 420 421 // Run ShrinkDemandedOp on scalar binary operations. 422 if (N->getNumValues() != 1 || 423 !N->getValueType(0).isSimple() || !N->getValueType(0).isInteger()) 424 continue; 425 426 unsigned BitWidth = N->getValueType(0).getScalarType().getSizeInBits(); 427 APInt Demanded = APInt::getAllOnesValue(BitWidth); 428 APInt KnownZero, KnownOne; 429 if (!TLI.SimplifyDemandedBits(SDValue(N, 0), Demanded, 430 KnownZero, KnownOne, TLO) && 431 (N->getOpcode() != ISD::TRUNCATE || 432 !TrivialTruncElim(SDValue(N, 0), TLO))) 433 continue; 434 435 // Revisit the node. 436 assert(!InWorklist.count(N) && "Already in worklist"); 437 Worklist.push_back(N); 438 InWorklist.insert(N); 439 440 // Replace the old value with the new one. 441 DEBUG(errs() << "\nShrinkDemandedOps replacing "; 442 TLO.Old.getNode()->dump(CurDAG); 443 errs() << "\nWith: "; 444 TLO.New.getNode()->dump(CurDAG); 445 errs() << '\n'); 446 447 if (InWorklist.insert(TLO.New.getNode())) 448 Worklist.push_back(TLO.New.getNode()); 449 450 SDOPsWorkListRemover DeadNodes(Worklist, InWorklist); 451 CurDAG->ReplaceAllUsesOfValueWith(TLO.Old, TLO.New, &DeadNodes); 452 453 if (!TLO.Old.getNode()->use_empty()) continue; 454 455 for (unsigned i = 0, e = TLO.Old.getNode()->getNumOperands(); 456 i != e; ++i) { 457 SDNode *OpNode = TLO.Old.getNode()->getOperand(i).getNode(); 458 if (OpNode->hasOneUse()) { 459 // Add OpNode to the end of the list to revisit. 460 DeadNodes.RemoveFromWorklist(OpNode); 461 Worklist.push_back(OpNode); 462 InWorklist.insert(OpNode); 463 } 464 } 465 466 DeadNodes.RemoveFromWorklist(TLO.Old.getNode()); 467 CurDAG->DeleteNode(TLO.Old.getNode()); 468 } 469} 470 471void SelectionDAGISel::ComputeLiveOutVRegInfo() { 472 SmallPtrSet<SDNode*, 128> VisitedNodes; 473 SmallVector<SDNode*, 128> Worklist; 474 475 Worklist.push_back(CurDAG->getRoot().getNode()); 476 477 APInt Mask; 478 APInt KnownZero; 479 APInt KnownOne; 480 481 do { 482 SDNode *N = Worklist.pop_back_val(); 483 484 // If we've already seen this node, ignore it. 485 if (!VisitedNodes.insert(N)) 486 continue; 487 488 // Otherwise, add all chain operands to the worklist. 489 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 490 if (N->getOperand(i).getValueType() == MVT::Other) 491 Worklist.push_back(N->getOperand(i).getNode()); 492 493 // If this is a CopyToReg with a vreg dest, process it. 494 if (N->getOpcode() != ISD::CopyToReg) 495 continue; 496 497 unsigned DestReg = cast<RegisterSDNode>(N->getOperand(1))->getReg(); 498 if (!TargetRegisterInfo::isVirtualRegister(DestReg)) 499 continue; 500 501 // Ignore non-scalar or non-integer values. 502 SDValue Src = N->getOperand(2); 503 EVT SrcVT = Src.getValueType(); 504 if (!SrcVT.isInteger() || SrcVT.isVector()) 505 continue; 506 507 unsigned NumSignBits = CurDAG->ComputeNumSignBits(Src); 508 Mask = APInt::getAllOnesValue(SrcVT.getSizeInBits()); 509 CurDAG->ComputeMaskedBits(Src, Mask, KnownZero, KnownOne); 510 511 // Only install this information if it tells us something. 512 if (NumSignBits != 1 || KnownZero != 0 || KnownOne != 0) { 513 DestReg -= TargetRegisterInfo::FirstVirtualRegister; 514 if (DestReg >= FuncInfo->LiveOutRegInfo.size()) 515 FuncInfo->LiveOutRegInfo.resize(DestReg+1); 516 FunctionLoweringInfo::LiveOutInfo &LOI = 517 FuncInfo->LiveOutRegInfo[DestReg]; 518 LOI.NumSignBits = NumSignBits; 519 LOI.KnownOne = KnownOne; 520 LOI.KnownZero = KnownZero; 521 } 522 } while (!Worklist.empty()); 523} 524 525MachineBasicBlock *SelectionDAGISel::CodeGenAndEmitDAG(MachineBasicBlock *BB) { 526 std::string GroupName; 527 if (TimePassesIsEnabled) 528 GroupName = "Instruction Selection and Scheduling"; 529 std::string BlockName; 530 if (ViewDAGCombine1 || ViewLegalizeTypesDAGs || ViewLegalizeDAGs || 531 ViewDAGCombine2 || ViewDAGCombineLT || ViewISelDAGs || ViewSchedDAGs || 532 ViewSUnitDAGs) 533 BlockName = MF->getFunction()->getNameStr() + ":" + 534 BB->getBasicBlock()->getNameStr(); 535 536 DEBUG(dbgs() << "Initial selection DAG:\n"); 537 DEBUG(CurDAG->dump()); 538 539 if (ViewDAGCombine1) CurDAG->viewGraph("dag-combine1 input for " + BlockName); 540 541 // Run the DAG combiner in pre-legalize mode. 542 if (TimePassesIsEnabled) { 543 NamedRegionTimer T("DAG Combining 1", GroupName); 544 CurDAG->Combine(Unrestricted, *AA, OptLevel); 545 } else { 546 CurDAG->Combine(Unrestricted, *AA, OptLevel); 547 } 548 549 DEBUG(dbgs() << "Optimized lowered selection DAG:\n"); 550 DEBUG(CurDAG->dump()); 551 552 // Second step, hack on the DAG until it only uses operations and types that 553 // the target supports. 554 if (ViewLegalizeTypesDAGs) CurDAG->viewGraph("legalize-types input for " + 555 BlockName); 556 557 bool Changed; 558 if (TimePassesIsEnabled) { 559 NamedRegionTimer T("Type Legalization", GroupName); 560 Changed = CurDAG->LegalizeTypes(); 561 } else { 562 Changed = CurDAG->LegalizeTypes(); 563 } 564 565 DEBUG(dbgs() << "Type-legalized selection DAG:\n"); 566 DEBUG(CurDAG->dump()); 567 568 if (Changed) { 569 if (ViewDAGCombineLT) 570 CurDAG->viewGraph("dag-combine-lt input for " + BlockName); 571 572 // Run the DAG combiner in post-type-legalize mode. 573 if (TimePassesIsEnabled) { 574 NamedRegionTimer T("DAG Combining after legalize types", GroupName); 575 CurDAG->Combine(NoIllegalTypes, *AA, OptLevel); 576 } else { 577 CurDAG->Combine(NoIllegalTypes, *AA, OptLevel); 578 } 579 580 DEBUG(dbgs() << "Optimized type-legalized selection DAG:\n"); 581 DEBUG(CurDAG->dump()); 582 } 583 584 if (TimePassesIsEnabled) { 585 NamedRegionTimer T("Vector Legalization", GroupName); 586 Changed = CurDAG->LegalizeVectors(); 587 } else { 588 Changed = CurDAG->LegalizeVectors(); 589 } 590 591 if (Changed) { 592 if (TimePassesIsEnabled) { 593 NamedRegionTimer T("Type Legalization 2", GroupName); 594 CurDAG->LegalizeTypes(); 595 } else { 596 CurDAG->LegalizeTypes(); 597 } 598 599 if (ViewDAGCombineLT) 600 CurDAG->viewGraph("dag-combine-lv input for " + BlockName); 601 602 // Run the DAG combiner in post-type-legalize mode. 603 if (TimePassesIsEnabled) { 604 NamedRegionTimer T("DAG Combining after legalize vectors", GroupName); 605 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel); 606 } else { 607 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel); 608 } 609 610 DEBUG(dbgs() << "Optimized vector-legalized selection DAG:\n"); 611 DEBUG(CurDAG->dump()); 612 } 613 614 if (ViewLegalizeDAGs) CurDAG->viewGraph("legalize input for " + BlockName); 615 616 if (TimePassesIsEnabled) { 617 NamedRegionTimer T("DAG Legalization", GroupName); 618 CurDAG->Legalize(OptLevel); 619 } else { 620 CurDAG->Legalize(OptLevel); 621 } 622 623 DEBUG(dbgs() << "Legalized selection DAG:\n"); 624 DEBUG(CurDAG->dump()); 625 626 if (ViewDAGCombine2) CurDAG->viewGraph("dag-combine2 input for " + BlockName); 627 628 // Run the DAG combiner in post-legalize mode. 629 if (TimePassesIsEnabled) { 630 NamedRegionTimer T("DAG Combining 2", GroupName); 631 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel); 632 } else { 633 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel); 634 } 635 636 DEBUG(dbgs() << "Optimized legalized selection DAG:\n"); 637 DEBUG(CurDAG->dump()); 638 639 if (OptLevel != CodeGenOpt::None) { 640 ShrinkDemandedOps(); 641 ComputeLiveOutVRegInfo(); 642 } 643 644 if (ViewISelDAGs) CurDAG->viewGraph("isel input for " + BlockName); 645 646 // Third, instruction select all of the operations to machine code, adding the 647 // code to the MachineBasicBlock. 648 if (TimePassesIsEnabled) { 649 NamedRegionTimer T("Instruction Selection", GroupName); 650 DoInstructionSelection(); 651 } else { 652 DoInstructionSelection(); 653 } 654 655 DEBUG(dbgs() << "Selected selection DAG:\n"); 656 DEBUG(CurDAG->dump()); 657 658 if (ViewSchedDAGs) CurDAG->viewGraph("scheduler input for " + BlockName); 659 660 // Schedule machine code. 661 ScheduleDAGSDNodes *Scheduler = CreateScheduler(); 662 if (TimePassesIsEnabled) { 663 NamedRegionTimer T("Instruction Scheduling", GroupName); 664 Scheduler->Run(CurDAG, BB, BB->end()); 665 } else { 666 Scheduler->Run(CurDAG, BB, BB->end()); 667 } 668 669 if (ViewSUnitDAGs) Scheduler->viewGraph(); 670 671 // Emit machine code to BB. This can change 'BB' to the last block being 672 // inserted into. 673 if (TimePassesIsEnabled) { 674 NamedRegionTimer T("Instruction Creation", GroupName); 675 BB = Scheduler->EmitSchedule(); 676 } else { 677 BB = Scheduler->EmitSchedule(); 678 } 679 680 // Free the scheduler state. 681 if (TimePassesIsEnabled) { 682 NamedRegionTimer T("Instruction Scheduling Cleanup", GroupName); 683 delete Scheduler; 684 } else { 685 delete Scheduler; 686 } 687 688 // Free the SelectionDAG state, now that we're finished with it. 689 CurDAG->clear(); 690 691 return BB; 692} 693 694void SelectionDAGISel::DoInstructionSelection() { 695 DEBUG(errs() << "===== Instruction selection begins:\n"); 696 697 PreprocessISelDAG(); 698 699 // Select target instructions for the DAG. 700 { 701 // Number all nodes with a topological order and set DAGSize. 702 DAGSize = CurDAG->AssignTopologicalOrder(); 703 704 // Create a dummy node (which is not added to allnodes), that adds 705 // a reference to the root node, preventing it from being deleted, 706 // and tracking any changes of the root. 707 HandleSDNode Dummy(CurDAG->getRoot()); 708 ISelPosition = SelectionDAG::allnodes_iterator(CurDAG->getRoot().getNode()); 709 ++ISelPosition; 710 711 // The AllNodes list is now topological-sorted. Visit the 712 // nodes by starting at the end of the list (the root of the 713 // graph) and preceding back toward the beginning (the entry 714 // node). 715 while (ISelPosition != CurDAG->allnodes_begin()) { 716 SDNode *Node = --ISelPosition; 717 // Skip dead nodes. DAGCombiner is expected to eliminate all dead nodes, 718 // but there are currently some corner cases that it misses. Also, this 719 // makes it theoretically possible to disable the DAGCombiner. 720 if (Node->use_empty()) 721 continue; 722 723 SDNode *ResNode = Select(Node); 724 725 // FIXME: This is pretty gross. 'Select' should be changed to not return 726 // anything at all and this code should be nuked with a tactical strike. 727 728 // If node should not be replaced, continue with the next one. 729 if (ResNode == Node || Node->getOpcode() == ISD::DELETED_NODE) 730 continue; 731 // Replace node. 732 if (ResNode) 733 ReplaceUses(Node, ResNode); 734 735 // If after the replacement this node is not used any more, 736 // remove this dead node. 737 if (Node->use_empty()) { // Don't delete EntryToken, etc. 738 ISelUpdater ISU(ISelPosition); 739 CurDAG->RemoveDeadNode(Node, &ISU); 740 } 741 } 742 743 CurDAG->setRoot(Dummy.getValue()); 744 } 745 746 DEBUG(errs() << "===== Instruction selection ends:\n"); 747 748 PostprocessISelDAG(); 749} 750 751/// PrepareEHLandingPad - Emit an EH_LABEL, set up live-in registers, and 752/// do other setup for EH landing-pad blocks. 753void SelectionDAGISel::PrepareEHLandingPad(MachineBasicBlock *BB) { 754 // Add a label to mark the beginning of the landing pad. Deletion of the 755 // landing pad can thus be detected via the MachineModuleInfo. 756 MCSymbol *Label = MF->getMMI().addLandingPad(BB); 757 758 const TargetInstrDesc &II = TM.getInstrInfo()->get(TargetOpcode::EH_LABEL); 759 BuildMI(BB, SDB->getCurDebugLoc(), II).addSym(Label); 760 761 // Mark exception register as live in. 762 unsigned Reg = TLI.getExceptionAddressRegister(); 763 if (Reg) BB->addLiveIn(Reg); 764 765 // Mark exception selector register as live in. 766 Reg = TLI.getExceptionSelectorRegister(); 767 if (Reg) BB->addLiveIn(Reg); 768 769 // FIXME: Hack around an exception handling flaw (PR1508): the personality 770 // function and list of typeids logically belong to the invoke (or, if you 771 // like, the basic block containing the invoke), and need to be associated 772 // with it in the dwarf exception handling tables. Currently however the 773 // information is provided by an intrinsic (eh.selector) that can be moved 774 // to unexpected places by the optimizers: if the unwind edge is critical, 775 // then breaking it can result in the intrinsics being in the successor of 776 // the landing pad, not the landing pad itself. This results 777 // in exceptions not being caught because no typeids are associated with 778 // the invoke. This may not be the only way things can go wrong, but it 779 // is the only way we try to work around for the moment. 780 const BasicBlock *LLVMBB = BB->getBasicBlock(); 781 const BranchInst *Br = dyn_cast<BranchInst>(LLVMBB->getTerminator()); 782 783 if (Br && Br->isUnconditional()) { // Critical edge? 784 BasicBlock::const_iterator I, E; 785 for (I = LLVMBB->begin(), E = --LLVMBB->end(); I != E; ++I) 786 if (isa<EHSelectorInst>(I)) 787 break; 788 789 if (I == E) 790 // No catch info found - try to extract some from the successor. 791 CopyCatchInfo(Br->getSuccessor(0), LLVMBB, &MF->getMMI(), *FuncInfo); 792 } 793} 794 795void SelectionDAGISel::SelectAllBasicBlocks(const Function &Fn) { 796 // Initialize the Fast-ISel state, if needed. 797 FastISel *FastIS = 0; 798 if (EnableFastISel) 799 FastIS = TLI.createFastISel(*MF, FuncInfo->ValueMap, FuncInfo->MBBMap, 800 FuncInfo->StaticAllocaMap, 801 FuncInfo->PHINodesToUpdate 802#ifndef NDEBUG 803 , FuncInfo->CatchInfoLost 804#endif 805 ); 806 807 // Iterate over all basic blocks in the function. 808 for (Function::const_iterator I = Fn.begin(), E = Fn.end(); I != E; ++I) { 809 const BasicBlock *LLVMBB = &*I; 810 MachineBasicBlock *BB = FuncInfo->MBBMap[LLVMBB]; 811 812 BasicBlock::const_iterator const Begin = LLVMBB->getFirstNonPHI(); 813 BasicBlock::const_iterator const End = LLVMBB->end(); 814 BasicBlock::const_iterator BI = Begin; 815 816 // Lower any arguments needed in this block if this is the entry block. 817 if (LLVMBB == &Fn.getEntryBlock()) 818 LowerArguments(LLVMBB); 819 820 // Setup an EH landing-pad block. 821 if (BB->isLandingPad()) 822 PrepareEHLandingPad(BB); 823 824 // Before doing SelectionDAG ISel, see if FastISel has been requested. 825 if (FastIS) { 826 // Emit code for any incoming arguments. This must happen before 827 // beginning FastISel on the entry block. 828 if (LLVMBB == &Fn.getEntryBlock()) { 829 CurDAG->setRoot(SDB->getControlRoot()); 830 SDB->clear(); 831 BB = CodeGenAndEmitDAG(BB); 832 } 833 FastIS->startNewBlock(BB); 834 // Do FastISel on as many instructions as possible. 835 for (; BI != End; ++BI) { 836 // Try to select the instruction with FastISel. 837 if (FastIS->SelectInstruction(BI)) 838 continue; 839 840 // Then handle certain instructions as single-LLVM-Instruction blocks. 841 if (isa<CallInst>(BI)) { 842 ++NumFastIselFailures; 843 if (EnableFastISelVerbose || EnableFastISelAbort) { 844 dbgs() << "FastISel missed call: "; 845 BI->dump(); 846 } 847 848 if (!BI->getType()->isVoidTy() && !BI->use_empty()) { 849 unsigned &R = FuncInfo->ValueMap[BI]; 850 if (!R) 851 R = FuncInfo->CreateRegForValue(BI); 852 } 853 854 bool HadTailCall = false; 855 BB = SelectBasicBlock(BB, LLVMBB, BI, llvm::next(BI), HadTailCall); 856 857 // If the call was emitted as a tail call, we're done with the block. 858 if (HadTailCall) { 859 BI = End; 860 break; 861 } 862 863 // If the instruction was codegen'd with multiple blocks, 864 // inform the FastISel object where to resume inserting. 865 FastIS->setCurrentBlock(BB); 866 continue; 867 } 868 869 // Otherwise, give up on FastISel for the rest of the block. 870 // For now, be a little lenient about non-branch terminators. 871 if (!isa<TerminatorInst>(BI) || isa<BranchInst>(BI)) { 872 ++NumFastIselFailures; 873 if (EnableFastISelVerbose || EnableFastISelAbort) { 874 dbgs() << "FastISel miss: "; 875 BI->dump(); 876 } 877 if (EnableFastISelAbort) 878 // The "fast" selector couldn't handle something and bailed. 879 // For the purpose of debugging, just abort. 880 llvm_unreachable("FastISel didn't select the entire block"); 881 } 882 break; 883 } 884 } 885 886 // Run SelectionDAG instruction selection on the remainder of the block 887 // not handled by FastISel. If FastISel is not run, this is the entire 888 // block. 889 if (BI != End) { 890 bool HadTailCall; 891 BB = SelectBasicBlock(BB, LLVMBB, BI, End, HadTailCall); 892 } 893 894 FinishBasicBlock(BB); 895 FuncInfo->PHINodesToUpdate.clear(); 896 } 897 898 delete FastIS; 899} 900 901void 902SelectionDAGISel::FinishBasicBlock(MachineBasicBlock *BB) { 903 904 DEBUG(dbgs() << "Total amount of phi nodes to update: " 905 << FuncInfo->PHINodesToUpdate.size() << "\n"); 906 DEBUG(for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) 907 dbgs() << "Node " << i << " : (" 908 << FuncInfo->PHINodesToUpdate[i].first 909 << ", " << FuncInfo->PHINodesToUpdate[i].second << ")\n"); 910 911 // Next, now that we know what the last MBB the LLVM BB expanded is, update 912 // PHI nodes in successors. 913 if (SDB->SwitchCases.empty() && 914 SDB->JTCases.empty() && 915 SDB->BitTestCases.empty()) { 916 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) { 917 MachineInstr *PHI = FuncInfo->PHINodesToUpdate[i].first; 918 assert(PHI->isPHI() && 919 "This is not a machine PHI node that we are updating!"); 920 if (!BB->isSuccessor(PHI->getParent())) 921 continue; 922 PHI->addOperand( 923 MachineOperand::CreateReg(FuncInfo->PHINodesToUpdate[i].second, false)); 924 PHI->addOperand(MachineOperand::CreateMBB(BB)); 925 } 926 return; 927 } 928 929 for (unsigned i = 0, e = SDB->BitTestCases.size(); i != e; ++i) { 930 // Lower header first, if it wasn't already lowered 931 if (!SDB->BitTestCases[i].Emitted) { 932 // Set the current basic block to the mbb we wish to insert the code into 933 BB = SDB->BitTestCases[i].Parent; 934 // Emit the code 935 SDB->visitBitTestHeader(SDB->BitTestCases[i], BB); 936 CurDAG->setRoot(SDB->getRoot()); 937 SDB->clear(); 938 BB = CodeGenAndEmitDAG(BB); 939 } 940 941 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); j != ej; ++j) { 942 // Set the current basic block to the mbb we wish to insert the code into 943 BB = SDB->BitTestCases[i].Cases[j].ThisBB; 944 // Emit the code 945 if (j+1 != ej) 946 SDB->visitBitTestCase(SDB->BitTestCases[i].Cases[j+1].ThisBB, 947 SDB->BitTestCases[i].Reg, 948 SDB->BitTestCases[i].Cases[j], 949 BB); 950 else 951 SDB->visitBitTestCase(SDB->BitTestCases[i].Default, 952 SDB->BitTestCases[i].Reg, 953 SDB->BitTestCases[i].Cases[j], 954 BB); 955 956 957 CurDAG->setRoot(SDB->getRoot()); 958 SDB->clear(); 959 BB = CodeGenAndEmitDAG(BB); 960 } 961 962 // Update PHI Nodes 963 for (unsigned pi = 0, pe = FuncInfo->PHINodesToUpdate.size(); 964 pi != pe; ++pi) { 965 MachineInstr *PHI = FuncInfo->PHINodesToUpdate[pi].first; 966 MachineBasicBlock *PHIBB = PHI->getParent(); 967 assert(PHI->isPHI() && 968 "This is not a machine PHI node that we are updating!"); 969 // This is "default" BB. We have two jumps to it. From "header" BB and 970 // from last "case" BB. 971 if (PHIBB == SDB->BitTestCases[i].Default) { 972 PHI->addOperand(MachineOperand:: 973 CreateReg(FuncInfo->PHINodesToUpdate[pi].second, 974 false)); 975 PHI->addOperand(MachineOperand::CreateMBB(SDB->BitTestCases[i].Parent)); 976 PHI->addOperand(MachineOperand:: 977 CreateReg(FuncInfo->PHINodesToUpdate[pi].second, 978 false)); 979 PHI->addOperand(MachineOperand::CreateMBB(SDB->BitTestCases[i].Cases. 980 back().ThisBB)); 981 } 982 // One of "cases" BB. 983 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); 984 j != ej; ++j) { 985 MachineBasicBlock* cBB = SDB->BitTestCases[i].Cases[j].ThisBB; 986 if (cBB->isSuccessor(PHIBB)) { 987 PHI->addOperand(MachineOperand:: 988 CreateReg(FuncInfo->PHINodesToUpdate[pi].second, 989 false)); 990 PHI->addOperand(MachineOperand::CreateMBB(cBB)); 991 } 992 } 993 } 994 } 995 SDB->BitTestCases.clear(); 996 997 // If the JumpTable record is filled in, then we need to emit a jump table. 998 // Updating the PHI nodes is tricky in this case, since we need to determine 999 // whether the PHI is a successor of the range check MBB or the jump table MBB 1000 for (unsigned i = 0, e = SDB->JTCases.size(); i != e; ++i) { 1001 // Lower header first, if it wasn't already lowered 1002 if (!SDB->JTCases[i].first.Emitted) { 1003 // Set the current basic block to the mbb we wish to insert the code into 1004 BB = SDB->JTCases[i].first.HeaderBB; 1005 // Emit the code 1006 SDB->visitJumpTableHeader(SDB->JTCases[i].second, SDB->JTCases[i].first, 1007 BB); 1008 CurDAG->setRoot(SDB->getRoot()); 1009 SDB->clear(); 1010 BB = CodeGenAndEmitDAG(BB); 1011 } 1012 1013 // Set the current basic block to the mbb we wish to insert the code into 1014 BB = SDB->JTCases[i].second.MBB; 1015 // Emit the code 1016 SDB->visitJumpTable(SDB->JTCases[i].second); 1017 CurDAG->setRoot(SDB->getRoot()); 1018 SDB->clear(); 1019 BB = CodeGenAndEmitDAG(BB); 1020 1021 // Update PHI Nodes 1022 for (unsigned pi = 0, pe = FuncInfo->PHINodesToUpdate.size(); 1023 pi != pe; ++pi) { 1024 MachineInstr *PHI = FuncInfo->PHINodesToUpdate[pi].first; 1025 MachineBasicBlock *PHIBB = PHI->getParent(); 1026 assert(PHI->isPHI() && 1027 "This is not a machine PHI node that we are updating!"); 1028 // "default" BB. We can go there only from header BB. 1029 if (PHIBB == SDB->JTCases[i].second.Default) { 1030 PHI->addOperand 1031 (MachineOperand::CreateReg(FuncInfo->PHINodesToUpdate[pi].second, 1032 false)); 1033 PHI->addOperand 1034 (MachineOperand::CreateMBB(SDB->JTCases[i].first.HeaderBB)); 1035 } 1036 // JT BB. Just iterate over successors here 1037 if (BB->isSuccessor(PHIBB)) { 1038 PHI->addOperand 1039 (MachineOperand::CreateReg(FuncInfo->PHINodesToUpdate[pi].second, 1040 false)); 1041 PHI->addOperand(MachineOperand::CreateMBB(BB)); 1042 } 1043 } 1044 } 1045 SDB->JTCases.clear(); 1046 1047 // If the switch block involved a branch to one of the actual successors, we 1048 // need to update PHI nodes in that block. 1049 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) { 1050 MachineInstr *PHI = FuncInfo->PHINodesToUpdate[i].first; 1051 assert(PHI->isPHI() && 1052 "This is not a machine PHI node that we are updating!"); 1053 if (BB->isSuccessor(PHI->getParent())) { 1054 PHI->addOperand( 1055 MachineOperand::CreateReg(FuncInfo->PHINodesToUpdate[i].second, false)); 1056 PHI->addOperand(MachineOperand::CreateMBB(BB)); 1057 } 1058 } 1059 1060 // If we generated any switch lowering information, build and codegen any 1061 // additional DAGs necessary. 1062 for (unsigned i = 0, e = SDB->SwitchCases.size(); i != e; ++i) { 1063 // Set the current basic block to the mbb we wish to insert the code into 1064 MachineBasicBlock *ThisBB = BB = SDB->SwitchCases[i].ThisBB; 1065 1066 // Determine the unique successors. 1067 SmallVector<MachineBasicBlock *, 2> Succs; 1068 Succs.push_back(SDB->SwitchCases[i].TrueBB); 1069 if (SDB->SwitchCases[i].TrueBB != SDB->SwitchCases[i].FalseBB) 1070 Succs.push_back(SDB->SwitchCases[i].FalseBB); 1071 1072 // Emit the code. Note that this could result in ThisBB being split, so 1073 // we need to check for updates. 1074 SDB->visitSwitchCase(SDB->SwitchCases[i], BB); 1075 CurDAG->setRoot(SDB->getRoot()); 1076 SDB->clear(); 1077 ThisBB = CodeGenAndEmitDAG(BB); 1078 1079 // Handle any PHI nodes in successors of this chunk, as if we were coming 1080 // from the original BB before switch expansion. Note that PHI nodes can 1081 // occur multiple times in PHINodesToUpdate. We have to be very careful to 1082 // handle them the right number of times. 1083 for (unsigned i = 0, e = Succs.size(); i != e; ++i) { 1084 BB = Succs[i]; 1085 // BB may have been removed from the CFG if a branch was constant folded. 1086 if (ThisBB->isSuccessor(BB)) { 1087 for (MachineBasicBlock::iterator Phi = BB->begin(); 1088 Phi != BB->end() && Phi->isPHI(); 1089 ++Phi) { 1090 // This value for this PHI node is recorded in PHINodesToUpdate. 1091 for (unsigned pn = 0; ; ++pn) { 1092 assert(pn != FuncInfo->PHINodesToUpdate.size() && 1093 "Didn't find PHI entry!"); 1094 if (FuncInfo->PHINodesToUpdate[pn].first == Phi) { 1095 Phi->addOperand(MachineOperand:: 1096 CreateReg(FuncInfo->PHINodesToUpdate[pn].second, 1097 false)); 1098 Phi->addOperand(MachineOperand::CreateMBB(ThisBB)); 1099 break; 1100 } 1101 } 1102 } 1103 } 1104 } 1105 } 1106 SDB->SwitchCases.clear(); 1107} 1108 1109 1110/// Create the scheduler. If a specific scheduler was specified 1111/// via the SchedulerRegistry, use it, otherwise select the 1112/// one preferred by the target. 1113/// 1114ScheduleDAGSDNodes *SelectionDAGISel::CreateScheduler() { 1115 RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault(); 1116 1117 if (!Ctor) { 1118 Ctor = ISHeuristic; 1119 RegisterScheduler::setDefault(Ctor); 1120 } 1121 1122 return Ctor(this, OptLevel); 1123} 1124 1125ScheduleHazardRecognizer *SelectionDAGISel::CreateTargetHazardRecognizer() { 1126 return new ScheduleHazardRecognizer(); 1127} 1128 1129//===----------------------------------------------------------------------===// 1130// Helper functions used by the generated instruction selector. 1131//===----------------------------------------------------------------------===// 1132// Calls to these methods are generated by tblgen. 1133 1134/// CheckAndMask - The isel is trying to match something like (and X, 255). If 1135/// the dag combiner simplified the 255, we still want to match. RHS is the 1136/// actual value in the DAG on the RHS of an AND, and DesiredMaskS is the value 1137/// specified in the .td file (e.g. 255). 1138bool SelectionDAGISel::CheckAndMask(SDValue LHS, ConstantSDNode *RHS, 1139 int64_t DesiredMaskS) const { 1140 const APInt &ActualMask = RHS->getAPIntValue(); 1141 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS); 1142 1143 // If the actual mask exactly matches, success! 1144 if (ActualMask == DesiredMask) 1145 return true; 1146 1147 // If the actual AND mask is allowing unallowed bits, this doesn't match. 1148 if (ActualMask.intersects(~DesiredMask)) 1149 return false; 1150 1151 // Otherwise, the DAG Combiner may have proven that the value coming in is 1152 // either already zero or is not demanded. Check for known zero input bits. 1153 APInt NeededMask = DesiredMask & ~ActualMask; 1154 if (CurDAG->MaskedValueIsZero(LHS, NeededMask)) 1155 return true; 1156 1157 // TODO: check to see if missing bits are just not demanded. 1158 1159 // Otherwise, this pattern doesn't match. 1160 return false; 1161} 1162 1163/// CheckOrMask - The isel is trying to match something like (or X, 255). If 1164/// the dag combiner simplified the 255, we still want to match. RHS is the 1165/// actual value in the DAG on the RHS of an OR, and DesiredMaskS is the value 1166/// specified in the .td file (e.g. 255). 1167bool SelectionDAGISel::CheckOrMask(SDValue LHS, ConstantSDNode *RHS, 1168 int64_t DesiredMaskS) const { 1169 const APInt &ActualMask = RHS->getAPIntValue(); 1170 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS); 1171 1172 // If the actual mask exactly matches, success! 1173 if (ActualMask == DesiredMask) 1174 return true; 1175 1176 // If the actual AND mask is allowing unallowed bits, this doesn't match. 1177 if (ActualMask.intersects(~DesiredMask)) 1178 return false; 1179 1180 // Otherwise, the DAG Combiner may have proven that the value coming in is 1181 // either already zero or is not demanded. Check for known zero input bits. 1182 APInt NeededMask = DesiredMask & ~ActualMask; 1183 1184 APInt KnownZero, KnownOne; 1185 CurDAG->ComputeMaskedBits(LHS, NeededMask, KnownZero, KnownOne); 1186 1187 // If all the missing bits in the or are already known to be set, match! 1188 if ((NeededMask & KnownOne) == NeededMask) 1189 return true; 1190 1191 // TODO: check to see if missing bits are just not demanded. 1192 1193 // Otherwise, this pattern doesn't match. 1194 return false; 1195} 1196 1197 1198/// SelectInlineAsmMemoryOperands - Calls to this are automatically generated 1199/// by tblgen. Others should not call it. 1200void SelectionDAGISel:: 1201SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops) { 1202 std::vector<SDValue> InOps; 1203 std::swap(InOps, Ops); 1204 1205 Ops.push_back(InOps[InlineAsm::Op_InputChain]); // 0 1206 Ops.push_back(InOps[InlineAsm::Op_AsmString]); // 1 1207 Ops.push_back(InOps[InlineAsm::Op_MDNode]); // 2, !srcloc 1208 1209 unsigned i = InlineAsm::Op_FirstOperand, e = InOps.size(); 1210 if (InOps[e-1].getValueType() == MVT::Flag) 1211 --e; // Don't process a flag operand if it is here. 1212 1213 while (i != e) { 1214 unsigned Flags = cast<ConstantSDNode>(InOps[i])->getZExtValue(); 1215 if (!InlineAsm::isMemKind(Flags)) { 1216 // Just skip over this operand, copying the operands verbatim. 1217 Ops.insert(Ops.end(), InOps.begin()+i, 1218 InOps.begin()+i+InlineAsm::getNumOperandRegisters(Flags) + 1); 1219 i += InlineAsm::getNumOperandRegisters(Flags) + 1; 1220 } else { 1221 assert(InlineAsm::getNumOperandRegisters(Flags) == 1 && 1222 "Memory operand with multiple values?"); 1223 // Otherwise, this is a memory operand. Ask the target to select it. 1224 std::vector<SDValue> SelOps; 1225 if (SelectInlineAsmMemoryOperand(InOps[i+1], 'm', SelOps)) 1226 report_fatal_error("Could not match memory address. Inline asm" 1227 " failure!"); 1228 1229 // Add this to the output node. 1230 unsigned NewFlags = 1231 InlineAsm::getFlagWord(InlineAsm::Kind_Mem, SelOps.size()); 1232 Ops.push_back(CurDAG->getTargetConstant(NewFlags, MVT::i32)); 1233 Ops.insert(Ops.end(), SelOps.begin(), SelOps.end()); 1234 i += 2; 1235 } 1236 } 1237 1238 // Add the flag input back if present. 1239 if (e != InOps.size()) 1240 Ops.push_back(InOps.back()); 1241} 1242 1243/// findFlagUse - Return use of EVT::Flag value produced by the specified 1244/// SDNode. 1245/// 1246static SDNode *findFlagUse(SDNode *N) { 1247 unsigned FlagResNo = N->getNumValues()-1; 1248 for (SDNode::use_iterator I = N->use_begin(), E = N->use_end(); I != E; ++I) { 1249 SDUse &Use = I.getUse(); 1250 if (Use.getResNo() == FlagResNo) 1251 return Use.getUser(); 1252 } 1253 return NULL; 1254} 1255 1256/// findNonImmUse - Return true if "Use" is a non-immediate use of "Def". 1257/// This function recursively traverses up the operand chain, ignoring 1258/// certain nodes. 1259static bool findNonImmUse(SDNode *Use, SDNode* Def, SDNode *ImmedUse, 1260 SDNode *Root, SmallPtrSet<SDNode*, 16> &Visited, 1261 bool IgnoreChains) { 1262 // The NodeID's are given uniques ID's where a node ID is guaranteed to be 1263 // greater than all of its (recursive) operands. If we scan to a point where 1264 // 'use' is smaller than the node we're scanning for, then we know we will 1265 // never find it. 1266 // 1267 // The Use may be -1 (unassigned) if it is a newly allocated node. This can 1268 // happen because we scan down to newly selected nodes in the case of flag 1269 // uses. 1270 if ((Use->getNodeId() < Def->getNodeId() && Use->getNodeId() != -1)) 1271 return false; 1272 1273 // Don't revisit nodes if we already scanned it and didn't fail, we know we 1274 // won't fail if we scan it again. 1275 if (!Visited.insert(Use)) 1276 return false; 1277 1278 for (unsigned i = 0, e = Use->getNumOperands(); i != e; ++i) { 1279 // Ignore chain uses, they are validated by HandleMergeInputChains. 1280 if (Use->getOperand(i).getValueType() == MVT::Other && IgnoreChains) 1281 continue; 1282 1283 SDNode *N = Use->getOperand(i).getNode(); 1284 if (N == Def) { 1285 if (Use == ImmedUse || Use == Root) 1286 continue; // We are not looking for immediate use. 1287 assert(N != Root); 1288 return true; 1289 } 1290 1291 // Traverse up the operand chain. 1292 if (findNonImmUse(N, Def, ImmedUse, Root, Visited, IgnoreChains)) 1293 return true; 1294 } 1295 return false; 1296} 1297 1298/// IsProfitableToFold - Returns true if it's profitable to fold the specific 1299/// operand node N of U during instruction selection that starts at Root. 1300bool SelectionDAGISel::IsProfitableToFold(SDValue N, SDNode *U, 1301 SDNode *Root) const { 1302 if (OptLevel == CodeGenOpt::None) return false; 1303 return N.hasOneUse(); 1304} 1305 1306/// IsLegalToFold - Returns true if the specific operand node N of 1307/// U can be folded during instruction selection that starts at Root. 1308bool SelectionDAGISel::IsLegalToFold(SDValue N, SDNode *U, SDNode *Root, 1309 CodeGenOpt::Level OptLevel, 1310 bool IgnoreChains) { 1311 if (OptLevel == CodeGenOpt::None) return false; 1312 1313 // If Root use can somehow reach N through a path that that doesn't contain 1314 // U then folding N would create a cycle. e.g. In the following 1315 // diagram, Root can reach N through X. If N is folded into into Root, then 1316 // X is both a predecessor and a successor of U. 1317 // 1318 // [N*] // 1319 // ^ ^ // 1320 // / \ // 1321 // [U*] [X]? // 1322 // ^ ^ // 1323 // \ / // 1324 // \ / // 1325 // [Root*] // 1326 // 1327 // * indicates nodes to be folded together. 1328 // 1329 // If Root produces a flag, then it gets (even more) interesting. Since it 1330 // will be "glued" together with its flag use in the scheduler, we need to 1331 // check if it might reach N. 1332 // 1333 // [N*] // 1334 // ^ ^ // 1335 // / \ // 1336 // [U*] [X]? // 1337 // ^ ^ // 1338 // \ \ // 1339 // \ | // 1340 // [Root*] | // 1341 // ^ | // 1342 // f | // 1343 // | / // 1344 // [Y] / // 1345 // ^ / // 1346 // f / // 1347 // | / // 1348 // [FU] // 1349 // 1350 // If FU (flag use) indirectly reaches N (the load), and Root folds N 1351 // (call it Fold), then X is a predecessor of FU and a successor of 1352 // Fold. But since Fold and FU are flagged together, this will create 1353 // a cycle in the scheduling graph. 1354 1355 // If the node has flags, walk down the graph to the "lowest" node in the 1356 // flagged set. 1357 EVT VT = Root->getValueType(Root->getNumValues()-1); 1358 while (VT == MVT::Flag) { 1359 SDNode *FU = findFlagUse(Root); 1360 if (FU == NULL) 1361 break; 1362 Root = FU; 1363 VT = Root->getValueType(Root->getNumValues()-1); 1364 1365 // If our query node has a flag result with a use, we've walked up it. If 1366 // the user (which has already been selected) has a chain or indirectly uses 1367 // the chain, our WalkChainUsers predicate will not consider it. Because of 1368 // this, we cannot ignore chains in this predicate. 1369 IgnoreChains = false; 1370 } 1371 1372 1373 SmallPtrSet<SDNode*, 16> Visited; 1374 return !findNonImmUse(Root, N.getNode(), U, Root, Visited, IgnoreChains); 1375} 1376 1377SDNode *SelectionDAGISel::Select_INLINEASM(SDNode *N) { 1378 std::vector<SDValue> Ops(N->op_begin(), N->op_end()); 1379 SelectInlineAsmMemoryOperands(Ops); 1380 1381 std::vector<EVT> VTs; 1382 VTs.push_back(MVT::Other); 1383 VTs.push_back(MVT::Flag); 1384 SDValue New = CurDAG->getNode(ISD::INLINEASM, N->getDebugLoc(), 1385 VTs, &Ops[0], Ops.size()); 1386 New->setNodeId(-1); 1387 return New.getNode(); 1388} 1389 1390SDNode *SelectionDAGISel::Select_UNDEF(SDNode *N) { 1391 return CurDAG->SelectNodeTo(N, TargetOpcode::IMPLICIT_DEF,N->getValueType(0)); 1392} 1393 1394/// GetVBR - decode a vbr encoding whose top bit is set. 1395ALWAYS_INLINE static uint64_t 1396GetVBR(uint64_t Val, const unsigned char *MatcherTable, unsigned &Idx) { 1397 assert(Val >= 128 && "Not a VBR"); 1398 Val &= 127; // Remove first vbr bit. 1399 1400 unsigned Shift = 7; 1401 uint64_t NextBits; 1402 do { 1403 NextBits = MatcherTable[Idx++]; 1404 Val |= (NextBits&127) << Shift; 1405 Shift += 7; 1406 } while (NextBits & 128); 1407 1408 return Val; 1409} 1410 1411 1412/// UpdateChainsAndFlags - When a match is complete, this method updates uses of 1413/// interior flag and chain results to use the new flag and chain results. 1414void SelectionDAGISel:: 1415UpdateChainsAndFlags(SDNode *NodeToMatch, SDValue InputChain, 1416 const SmallVectorImpl<SDNode*> &ChainNodesMatched, 1417 SDValue InputFlag, 1418 const SmallVectorImpl<SDNode*> &FlagResultNodesMatched, 1419 bool isMorphNodeTo) { 1420 SmallVector<SDNode*, 4> NowDeadNodes; 1421 1422 ISelUpdater ISU(ISelPosition); 1423 1424 // Now that all the normal results are replaced, we replace the chain and 1425 // flag results if present. 1426 if (!ChainNodesMatched.empty()) { 1427 assert(InputChain.getNode() != 0 && 1428 "Matched input chains but didn't produce a chain"); 1429 // Loop over all of the nodes we matched that produced a chain result. 1430 // Replace all the chain results with the final chain we ended up with. 1431 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) { 1432 SDNode *ChainNode = ChainNodesMatched[i]; 1433 1434 // If this node was already deleted, don't look at it. 1435 if (ChainNode->getOpcode() == ISD::DELETED_NODE) 1436 continue; 1437 1438 // Don't replace the results of the root node if we're doing a 1439 // MorphNodeTo. 1440 if (ChainNode == NodeToMatch && isMorphNodeTo) 1441 continue; 1442 1443 SDValue ChainVal = SDValue(ChainNode, ChainNode->getNumValues()-1); 1444 if (ChainVal.getValueType() == MVT::Flag) 1445 ChainVal = ChainVal.getValue(ChainVal->getNumValues()-2); 1446 assert(ChainVal.getValueType() == MVT::Other && "Not a chain?"); 1447 CurDAG->ReplaceAllUsesOfValueWith(ChainVal, InputChain, &ISU); 1448 1449 // If the node became dead and we haven't already seen it, delete it. 1450 if (ChainNode->use_empty() && 1451 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), ChainNode)) 1452 NowDeadNodes.push_back(ChainNode); 1453 } 1454 } 1455 1456 // If the result produces a flag, update any flag results in the matched 1457 // pattern with the flag result. 1458 if (InputFlag.getNode() != 0) { 1459 // Handle any interior nodes explicitly marked. 1460 for (unsigned i = 0, e = FlagResultNodesMatched.size(); i != e; ++i) { 1461 SDNode *FRN = FlagResultNodesMatched[i]; 1462 1463 // If this node was already deleted, don't look at it. 1464 if (FRN->getOpcode() == ISD::DELETED_NODE) 1465 continue; 1466 1467 assert(FRN->getValueType(FRN->getNumValues()-1) == MVT::Flag && 1468 "Doesn't have a flag result"); 1469 CurDAG->ReplaceAllUsesOfValueWith(SDValue(FRN, FRN->getNumValues()-1), 1470 InputFlag, &ISU); 1471 1472 // If the node became dead and we haven't already seen it, delete it. 1473 if (FRN->use_empty() && 1474 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), FRN)) 1475 NowDeadNodes.push_back(FRN); 1476 } 1477 } 1478 1479 if (!NowDeadNodes.empty()) 1480 CurDAG->RemoveDeadNodes(NowDeadNodes, &ISU); 1481 1482 DEBUG(errs() << "ISEL: Match complete!\n"); 1483} 1484 1485enum ChainResult { 1486 CR_Simple, 1487 CR_InducesCycle, 1488 CR_LeadsToInteriorNode 1489}; 1490 1491/// WalkChainUsers - Walk down the users of the specified chained node that is 1492/// part of the pattern we're matching, looking at all of the users we find. 1493/// This determines whether something is an interior node, whether we have a 1494/// non-pattern node in between two pattern nodes (which prevent folding because 1495/// it would induce a cycle) and whether we have a TokenFactor node sandwiched 1496/// between pattern nodes (in which case the TF becomes part of the pattern). 1497/// 1498/// The walk we do here is guaranteed to be small because we quickly get down to 1499/// already selected nodes "below" us. 1500static ChainResult 1501WalkChainUsers(SDNode *ChainedNode, 1502 SmallVectorImpl<SDNode*> &ChainedNodesInPattern, 1503 SmallVectorImpl<SDNode*> &InteriorChainedNodes) { 1504 ChainResult Result = CR_Simple; 1505 1506 for (SDNode::use_iterator UI = ChainedNode->use_begin(), 1507 E = ChainedNode->use_end(); UI != E; ++UI) { 1508 // Make sure the use is of the chain, not some other value we produce. 1509 if (UI.getUse().getValueType() != MVT::Other) continue; 1510 1511 SDNode *User = *UI; 1512 1513 // If we see an already-selected machine node, then we've gone beyond the 1514 // pattern that we're selecting down into the already selected chunk of the 1515 // DAG. 1516 if (User->isMachineOpcode() || 1517 User->getOpcode() == ISD::HANDLENODE) // Root of the graph. 1518 continue; 1519 1520 if (User->getOpcode() == ISD::CopyToReg || 1521 User->getOpcode() == ISD::CopyFromReg || 1522 User->getOpcode() == ISD::INLINEASM || 1523 User->getOpcode() == ISD::EH_LABEL) { 1524 // If their node ID got reset to -1 then they've already been selected. 1525 // Treat them like a MachineOpcode. 1526 if (User->getNodeId() == -1) 1527 continue; 1528 } 1529 1530 // If we have a TokenFactor, we handle it specially. 1531 if (User->getOpcode() != ISD::TokenFactor) { 1532 // If the node isn't a token factor and isn't part of our pattern, then it 1533 // must be a random chained node in between two nodes we're selecting. 1534 // This happens when we have something like: 1535 // x = load ptr 1536 // call 1537 // y = x+4 1538 // store y -> ptr 1539 // Because we structurally match the load/store as a read/modify/write, 1540 // but the call is chained between them. We cannot fold in this case 1541 // because it would induce a cycle in the graph. 1542 if (!std::count(ChainedNodesInPattern.begin(), 1543 ChainedNodesInPattern.end(), User)) 1544 return CR_InducesCycle; 1545 1546 // Otherwise we found a node that is part of our pattern. For example in: 1547 // x = load ptr 1548 // y = x+4 1549 // store y -> ptr 1550 // This would happen when we're scanning down from the load and see the 1551 // store as a user. Record that there is a use of ChainedNode that is 1552 // part of the pattern and keep scanning uses. 1553 Result = CR_LeadsToInteriorNode; 1554 InteriorChainedNodes.push_back(User); 1555 continue; 1556 } 1557 1558 // If we found a TokenFactor, there are two cases to consider: first if the 1559 // TokenFactor is just hanging "below" the pattern we're matching (i.e. no 1560 // uses of the TF are in our pattern) we just want to ignore it. Second, 1561 // the TokenFactor can be sandwiched in between two chained nodes, like so: 1562 // [Load chain] 1563 // ^ 1564 // | 1565 // [Load] 1566 // ^ ^ 1567 // | \ DAG's like cheese 1568 // / \ do you? 1569 // / | 1570 // [TokenFactor] [Op] 1571 // ^ ^ 1572 // | | 1573 // \ / 1574 // \ / 1575 // [Store] 1576 // 1577 // In this case, the TokenFactor becomes part of our match and we rewrite it 1578 // as a new TokenFactor. 1579 // 1580 // To distinguish these two cases, do a recursive walk down the uses. 1581 switch (WalkChainUsers(User, ChainedNodesInPattern, InteriorChainedNodes)) { 1582 case CR_Simple: 1583 // If the uses of the TokenFactor are just already-selected nodes, ignore 1584 // it, it is "below" our pattern. 1585 continue; 1586 case CR_InducesCycle: 1587 // If the uses of the TokenFactor lead to nodes that are not part of our 1588 // pattern that are not selected, folding would turn this into a cycle, 1589 // bail out now. 1590 return CR_InducesCycle; 1591 case CR_LeadsToInteriorNode: 1592 break; // Otherwise, keep processing. 1593 } 1594 1595 // Okay, we know we're in the interesting interior case. The TokenFactor 1596 // is now going to be considered part of the pattern so that we rewrite its 1597 // uses (it may have uses that are not part of the pattern) with the 1598 // ultimate chain result of the generated code. We will also add its chain 1599 // inputs as inputs to the ultimate TokenFactor we create. 1600 Result = CR_LeadsToInteriorNode; 1601 ChainedNodesInPattern.push_back(User); 1602 InteriorChainedNodes.push_back(User); 1603 continue; 1604 } 1605 1606 return Result; 1607} 1608 1609/// HandleMergeInputChains - This implements the OPC_EmitMergeInputChains 1610/// operation for when the pattern matched at least one node with a chains. The 1611/// input vector contains a list of all of the chained nodes that we match. We 1612/// must determine if this is a valid thing to cover (i.e. matching it won't 1613/// induce cycles in the DAG) and if so, creating a TokenFactor node. that will 1614/// be used as the input node chain for the generated nodes. 1615static SDValue 1616HandleMergeInputChains(SmallVectorImpl<SDNode*> &ChainNodesMatched, 1617 SelectionDAG *CurDAG) { 1618 // Walk all of the chained nodes we've matched, recursively scanning down the 1619 // users of the chain result. This adds any TokenFactor nodes that are caught 1620 // in between chained nodes to the chained and interior nodes list. 1621 SmallVector<SDNode*, 3> InteriorChainedNodes; 1622 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) { 1623 if (WalkChainUsers(ChainNodesMatched[i], ChainNodesMatched, 1624 InteriorChainedNodes) == CR_InducesCycle) 1625 return SDValue(); // Would induce a cycle. 1626 } 1627 1628 // Okay, we have walked all the matched nodes and collected TokenFactor nodes 1629 // that we are interested in. Form our input TokenFactor node. 1630 SmallVector<SDValue, 3> InputChains; 1631 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) { 1632 // Add the input chain of this node to the InputChains list (which will be 1633 // the operands of the generated TokenFactor) if it's not an interior node. 1634 SDNode *N = ChainNodesMatched[i]; 1635 if (N->getOpcode() != ISD::TokenFactor) { 1636 if (std::count(InteriorChainedNodes.begin(),InteriorChainedNodes.end(),N)) 1637 continue; 1638 1639 // Otherwise, add the input chain. 1640 SDValue InChain = ChainNodesMatched[i]->getOperand(0); 1641 assert(InChain.getValueType() == MVT::Other && "Not a chain"); 1642 InputChains.push_back(InChain); 1643 continue; 1644 } 1645 1646 // If we have a token factor, we want to add all inputs of the token factor 1647 // that are not part of the pattern we're matching. 1648 for (unsigned op = 0, e = N->getNumOperands(); op != e; ++op) { 1649 if (!std::count(ChainNodesMatched.begin(), ChainNodesMatched.end(), 1650 N->getOperand(op).getNode())) 1651 InputChains.push_back(N->getOperand(op)); 1652 } 1653 } 1654 1655 SDValue Res; 1656 if (InputChains.size() == 1) 1657 return InputChains[0]; 1658 return CurDAG->getNode(ISD::TokenFactor, ChainNodesMatched[0]->getDebugLoc(), 1659 MVT::Other, &InputChains[0], InputChains.size()); 1660} 1661 1662/// MorphNode - Handle morphing a node in place for the selector. 1663SDNode *SelectionDAGISel:: 1664MorphNode(SDNode *Node, unsigned TargetOpc, SDVTList VTList, 1665 const SDValue *Ops, unsigned NumOps, unsigned EmitNodeInfo) { 1666 // It is possible we're using MorphNodeTo to replace a node with no 1667 // normal results with one that has a normal result (or we could be 1668 // adding a chain) and the input could have flags and chains as well. 1669 // In this case we need to shift the operands down. 1670 // FIXME: This is a horrible hack and broken in obscure cases, no worse 1671 // than the old isel though. 1672 int OldFlagResultNo = -1, OldChainResultNo = -1; 1673 1674 unsigned NTMNumResults = Node->getNumValues(); 1675 if (Node->getValueType(NTMNumResults-1) == MVT::Flag) { 1676 OldFlagResultNo = NTMNumResults-1; 1677 if (NTMNumResults != 1 && 1678 Node->getValueType(NTMNumResults-2) == MVT::Other) 1679 OldChainResultNo = NTMNumResults-2; 1680 } else if (Node->getValueType(NTMNumResults-1) == MVT::Other) 1681 OldChainResultNo = NTMNumResults-1; 1682 1683 // Call the underlying SelectionDAG routine to do the transmogrification. Note 1684 // that this deletes operands of the old node that become dead. 1685 SDNode *Res = CurDAG->MorphNodeTo(Node, ~TargetOpc, VTList, Ops, NumOps); 1686 1687 // MorphNodeTo can operate in two ways: if an existing node with the 1688 // specified operands exists, it can just return it. Otherwise, it 1689 // updates the node in place to have the requested operands. 1690 if (Res == Node) { 1691 // If we updated the node in place, reset the node ID. To the isel, 1692 // this should be just like a newly allocated machine node. 1693 Res->setNodeId(-1); 1694 } 1695 1696 unsigned ResNumResults = Res->getNumValues(); 1697 // Move the flag if needed. 1698 if ((EmitNodeInfo & OPFL_FlagOutput) && OldFlagResultNo != -1 && 1699 (unsigned)OldFlagResultNo != ResNumResults-1) 1700 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldFlagResultNo), 1701 SDValue(Res, ResNumResults-1)); 1702 1703 if ((EmitNodeInfo & OPFL_FlagOutput) != 0) 1704 --ResNumResults; 1705 1706 // Move the chain reference if needed. 1707 if ((EmitNodeInfo & OPFL_Chain) && OldChainResultNo != -1 && 1708 (unsigned)OldChainResultNo != ResNumResults-1) 1709 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldChainResultNo), 1710 SDValue(Res, ResNumResults-1)); 1711 1712 // Otherwise, no replacement happened because the node already exists. Replace 1713 // Uses of the old node with the new one. 1714 if (Res != Node) 1715 CurDAG->ReplaceAllUsesWith(Node, Res); 1716 1717 return Res; 1718} 1719 1720/// CheckPatternPredicate - Implements OP_CheckPatternPredicate. 1721ALWAYS_INLINE static bool 1722CheckSame(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1723 SDValue N, const SmallVectorImpl<SDValue> &RecordedNodes) { 1724 // Accept if it is exactly the same as a previously recorded node. 1725 unsigned RecNo = MatcherTable[MatcherIndex++]; 1726 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 1727 return N == RecordedNodes[RecNo]; 1728} 1729 1730/// CheckPatternPredicate - Implements OP_CheckPatternPredicate. 1731ALWAYS_INLINE static bool 1732CheckPatternPredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1733 SelectionDAGISel &SDISel) { 1734 return SDISel.CheckPatternPredicate(MatcherTable[MatcherIndex++]); 1735} 1736 1737/// CheckNodePredicate - Implements OP_CheckNodePredicate. 1738ALWAYS_INLINE static bool 1739CheckNodePredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1740 SelectionDAGISel &SDISel, SDNode *N) { 1741 return SDISel.CheckNodePredicate(N, MatcherTable[MatcherIndex++]); 1742} 1743 1744ALWAYS_INLINE static bool 1745CheckOpcode(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1746 SDNode *N) { 1747 uint16_t Opc = MatcherTable[MatcherIndex++]; 1748 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8; 1749 return N->getOpcode() == Opc; 1750} 1751 1752ALWAYS_INLINE static bool 1753CheckType(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1754 SDValue N, const TargetLowering &TLI) { 1755 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 1756 if (N.getValueType() == VT) return true; 1757 1758 // Handle the case when VT is iPTR. 1759 return VT == MVT::iPTR && N.getValueType() == TLI.getPointerTy(); 1760} 1761 1762ALWAYS_INLINE static bool 1763CheckChildType(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1764 SDValue N, const TargetLowering &TLI, 1765 unsigned ChildNo) { 1766 if (ChildNo >= N.getNumOperands()) 1767 return false; // Match fails if out of range child #. 1768 return ::CheckType(MatcherTable, MatcherIndex, N.getOperand(ChildNo), TLI); 1769} 1770 1771 1772ALWAYS_INLINE static bool 1773CheckCondCode(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1774 SDValue N) { 1775 return cast<CondCodeSDNode>(N)->get() == 1776 (ISD::CondCode)MatcherTable[MatcherIndex++]; 1777} 1778 1779ALWAYS_INLINE static bool 1780CheckValueType(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1781 SDValue N, const TargetLowering &TLI) { 1782 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 1783 if (cast<VTSDNode>(N)->getVT() == VT) 1784 return true; 1785 1786 // Handle the case when VT is iPTR. 1787 return VT == MVT::iPTR && cast<VTSDNode>(N)->getVT() == TLI.getPointerTy(); 1788} 1789 1790ALWAYS_INLINE static bool 1791CheckInteger(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1792 SDValue N) { 1793 int64_t Val = MatcherTable[MatcherIndex++]; 1794 if (Val & 128) 1795 Val = GetVBR(Val, MatcherTable, MatcherIndex); 1796 1797 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N); 1798 return C != 0 && C->getSExtValue() == Val; 1799} 1800 1801ALWAYS_INLINE static bool 1802CheckAndImm(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1803 SDValue N, SelectionDAGISel &SDISel) { 1804 int64_t Val = MatcherTable[MatcherIndex++]; 1805 if (Val & 128) 1806 Val = GetVBR(Val, MatcherTable, MatcherIndex); 1807 1808 if (N->getOpcode() != ISD::AND) return false; 1809 1810 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1)); 1811 return C != 0 && SDISel.CheckAndMask(N.getOperand(0), C, Val); 1812} 1813 1814ALWAYS_INLINE static bool 1815CheckOrImm(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1816 SDValue N, SelectionDAGISel &SDISel) { 1817 int64_t Val = MatcherTable[MatcherIndex++]; 1818 if (Val & 128) 1819 Val = GetVBR(Val, MatcherTable, MatcherIndex); 1820 1821 if (N->getOpcode() != ISD::OR) return false; 1822 1823 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1)); 1824 return C != 0 && SDISel.CheckOrMask(N.getOperand(0), C, Val); 1825} 1826 1827/// IsPredicateKnownToFail - If we know how and can do so without pushing a 1828/// scope, evaluate the current node. If the current predicate is known to 1829/// fail, set Result=true and return anything. If the current predicate is 1830/// known to pass, set Result=false and return the MatcherIndex to continue 1831/// with. If the current predicate is unknown, set Result=false and return the 1832/// MatcherIndex to continue with. 1833static unsigned IsPredicateKnownToFail(const unsigned char *Table, 1834 unsigned Index, SDValue N, 1835 bool &Result, SelectionDAGISel &SDISel, 1836 SmallVectorImpl<SDValue> &RecordedNodes){ 1837 switch (Table[Index++]) { 1838 default: 1839 Result = false; 1840 return Index-1; // Could not evaluate this predicate. 1841 case SelectionDAGISel::OPC_CheckSame: 1842 Result = !::CheckSame(Table, Index, N, RecordedNodes); 1843 return Index; 1844 case SelectionDAGISel::OPC_CheckPatternPredicate: 1845 Result = !::CheckPatternPredicate(Table, Index, SDISel); 1846 return Index; 1847 case SelectionDAGISel::OPC_CheckPredicate: 1848 Result = !::CheckNodePredicate(Table, Index, SDISel, N.getNode()); 1849 return Index; 1850 case SelectionDAGISel::OPC_CheckOpcode: 1851 Result = !::CheckOpcode(Table, Index, N.getNode()); 1852 return Index; 1853 case SelectionDAGISel::OPC_CheckType: 1854 Result = !::CheckType(Table, Index, N, SDISel.TLI); 1855 return Index; 1856 case SelectionDAGISel::OPC_CheckChild0Type: 1857 case SelectionDAGISel::OPC_CheckChild1Type: 1858 case SelectionDAGISel::OPC_CheckChild2Type: 1859 case SelectionDAGISel::OPC_CheckChild3Type: 1860 case SelectionDAGISel::OPC_CheckChild4Type: 1861 case SelectionDAGISel::OPC_CheckChild5Type: 1862 case SelectionDAGISel::OPC_CheckChild6Type: 1863 case SelectionDAGISel::OPC_CheckChild7Type: 1864 Result = !::CheckChildType(Table, Index, N, SDISel.TLI, 1865 Table[Index-1] - SelectionDAGISel::OPC_CheckChild0Type); 1866 return Index; 1867 case SelectionDAGISel::OPC_CheckCondCode: 1868 Result = !::CheckCondCode(Table, Index, N); 1869 return Index; 1870 case SelectionDAGISel::OPC_CheckValueType: 1871 Result = !::CheckValueType(Table, Index, N, SDISel.TLI); 1872 return Index; 1873 case SelectionDAGISel::OPC_CheckInteger: 1874 Result = !::CheckInteger(Table, Index, N); 1875 return Index; 1876 case SelectionDAGISel::OPC_CheckAndImm: 1877 Result = !::CheckAndImm(Table, Index, N, SDISel); 1878 return Index; 1879 case SelectionDAGISel::OPC_CheckOrImm: 1880 Result = !::CheckOrImm(Table, Index, N, SDISel); 1881 return Index; 1882 } 1883} 1884 1885namespace { 1886 1887struct MatchScope { 1888 /// FailIndex - If this match fails, this is the index to continue with. 1889 unsigned FailIndex; 1890 1891 /// NodeStack - The node stack when the scope was formed. 1892 SmallVector<SDValue, 4> NodeStack; 1893 1894 /// NumRecordedNodes - The number of recorded nodes when the scope was formed. 1895 unsigned NumRecordedNodes; 1896 1897 /// NumMatchedMemRefs - The number of matched memref entries. 1898 unsigned NumMatchedMemRefs; 1899 1900 /// InputChain/InputFlag - The current chain/flag 1901 SDValue InputChain, InputFlag; 1902 1903 /// HasChainNodesMatched - True if the ChainNodesMatched list is non-empty. 1904 bool HasChainNodesMatched, HasFlagResultNodesMatched; 1905}; 1906 1907} 1908 1909SDNode *SelectionDAGISel:: 1910SelectCodeCommon(SDNode *NodeToMatch, const unsigned char *MatcherTable, 1911 unsigned TableSize) { 1912 // FIXME: Should these even be selected? Handle these cases in the caller? 1913 switch (NodeToMatch->getOpcode()) { 1914 default: 1915 break; 1916 case ISD::EntryToken: // These nodes remain the same. 1917 case ISD::BasicBlock: 1918 case ISD::Register: 1919 //case ISD::VALUETYPE: 1920 //case ISD::CONDCODE: 1921 case ISD::HANDLENODE: 1922 case ISD::MDNODE_SDNODE: 1923 case ISD::TargetConstant: 1924 case ISD::TargetConstantFP: 1925 case ISD::TargetConstantPool: 1926 case ISD::TargetFrameIndex: 1927 case ISD::TargetExternalSymbol: 1928 case ISD::TargetBlockAddress: 1929 case ISD::TargetJumpTable: 1930 case ISD::TargetGlobalTLSAddress: 1931 case ISD::TargetGlobalAddress: 1932 case ISD::TokenFactor: 1933 case ISD::CopyFromReg: 1934 case ISD::CopyToReg: 1935 case ISD::EH_LABEL: 1936 NodeToMatch->setNodeId(-1); // Mark selected. 1937 return 0; 1938 case ISD::AssertSext: 1939 case ISD::AssertZext: 1940 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, 0), 1941 NodeToMatch->getOperand(0)); 1942 return 0; 1943 case ISD::INLINEASM: return Select_INLINEASM(NodeToMatch); 1944 case ISD::UNDEF: return Select_UNDEF(NodeToMatch); 1945 } 1946 1947 assert(!NodeToMatch->isMachineOpcode() && "Node already selected!"); 1948 1949 // Set up the node stack with NodeToMatch as the only node on the stack. 1950 SmallVector<SDValue, 8> NodeStack; 1951 SDValue N = SDValue(NodeToMatch, 0); 1952 NodeStack.push_back(N); 1953 1954 // MatchScopes - Scopes used when matching, if a match failure happens, this 1955 // indicates where to continue checking. 1956 SmallVector<MatchScope, 8> MatchScopes; 1957 1958 // RecordedNodes - This is the set of nodes that have been recorded by the 1959 // state machine. 1960 SmallVector<SDValue, 8> RecordedNodes; 1961 1962 // MatchedMemRefs - This is the set of MemRef's we've seen in the input 1963 // pattern. 1964 SmallVector<MachineMemOperand*, 2> MatchedMemRefs; 1965 1966 // These are the current input chain and flag for use when generating nodes. 1967 // Various Emit operations change these. For example, emitting a copytoreg 1968 // uses and updates these. 1969 SDValue InputChain, InputFlag; 1970 1971 // ChainNodesMatched - If a pattern matches nodes that have input/output 1972 // chains, the OPC_EmitMergeInputChains operation is emitted which indicates 1973 // which ones they are. The result is captured into this list so that we can 1974 // update the chain results when the pattern is complete. 1975 SmallVector<SDNode*, 3> ChainNodesMatched; 1976 SmallVector<SDNode*, 3> FlagResultNodesMatched; 1977 1978 DEBUG(errs() << "ISEL: Starting pattern match on root node: "; 1979 NodeToMatch->dump(CurDAG); 1980 errs() << '\n'); 1981 1982 // Determine where to start the interpreter. Normally we start at opcode #0, 1983 // but if the state machine starts with an OPC_SwitchOpcode, then we 1984 // accelerate the first lookup (which is guaranteed to be hot) with the 1985 // OpcodeOffset table. 1986 unsigned MatcherIndex = 0; 1987 1988 if (!OpcodeOffset.empty()) { 1989 // Already computed the OpcodeOffset table, just index into it. 1990 if (N.getOpcode() < OpcodeOffset.size()) 1991 MatcherIndex = OpcodeOffset[N.getOpcode()]; 1992 DEBUG(errs() << " Initial Opcode index to " << MatcherIndex << "\n"); 1993 1994 } else if (MatcherTable[0] == OPC_SwitchOpcode) { 1995 // Otherwise, the table isn't computed, but the state machine does start 1996 // with an OPC_SwitchOpcode instruction. Populate the table now, since this 1997 // is the first time we're selecting an instruction. 1998 unsigned Idx = 1; 1999 while (1) { 2000 // Get the size of this case. 2001 unsigned CaseSize = MatcherTable[Idx++]; 2002 if (CaseSize & 128) 2003 CaseSize = GetVBR(CaseSize, MatcherTable, Idx); 2004 if (CaseSize == 0) break; 2005 2006 // Get the opcode, add the index to the table. 2007 uint16_t Opc = MatcherTable[Idx++]; 2008 Opc |= (unsigned short)MatcherTable[Idx++] << 8; 2009 if (Opc >= OpcodeOffset.size()) 2010 OpcodeOffset.resize((Opc+1)*2); 2011 OpcodeOffset[Opc] = Idx; 2012 Idx += CaseSize; 2013 } 2014 2015 // Okay, do the lookup for the first opcode. 2016 if (N.getOpcode() < OpcodeOffset.size()) 2017 MatcherIndex = OpcodeOffset[N.getOpcode()]; 2018 } 2019 2020 while (1) { 2021 assert(MatcherIndex < TableSize && "Invalid index"); 2022#ifndef NDEBUG 2023 unsigned CurrentOpcodeIndex = MatcherIndex; 2024#endif 2025 BuiltinOpcodes Opcode = (BuiltinOpcodes)MatcherTable[MatcherIndex++]; 2026 switch (Opcode) { 2027 case OPC_Scope: { 2028 // Okay, the semantics of this operation are that we should push a scope 2029 // then evaluate the first child. However, pushing a scope only to have 2030 // the first check fail (which then pops it) is inefficient. If we can 2031 // determine immediately that the first check (or first several) will 2032 // immediately fail, don't even bother pushing a scope for them. 2033 unsigned FailIndex; 2034 2035 while (1) { 2036 unsigned NumToSkip = MatcherTable[MatcherIndex++]; 2037 if (NumToSkip & 128) 2038 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex); 2039 // Found the end of the scope with no match. 2040 if (NumToSkip == 0) { 2041 FailIndex = 0; 2042 break; 2043 } 2044 2045 FailIndex = MatcherIndex+NumToSkip; 2046 2047 unsigned MatcherIndexOfPredicate = MatcherIndex; 2048 (void)MatcherIndexOfPredicate; // silence warning. 2049 2050 // If we can't evaluate this predicate without pushing a scope (e.g. if 2051 // it is a 'MoveParent') or if the predicate succeeds on this node, we 2052 // push the scope and evaluate the full predicate chain. 2053 bool Result; 2054 MatcherIndex = IsPredicateKnownToFail(MatcherTable, MatcherIndex, N, 2055 Result, *this, RecordedNodes); 2056 if (!Result) 2057 break; 2058 2059 DEBUG(errs() << " Skipped scope entry (due to false predicate) at " 2060 << "index " << MatcherIndexOfPredicate 2061 << ", continuing at " << FailIndex << "\n"); 2062 ++NumDAGIselRetries; 2063 2064 // Otherwise, we know that this case of the Scope is guaranteed to fail, 2065 // move to the next case. 2066 MatcherIndex = FailIndex; 2067 } 2068 2069 // If the whole scope failed to match, bail. 2070 if (FailIndex == 0) break; 2071 2072 // Push a MatchScope which indicates where to go if the first child fails 2073 // to match. 2074 MatchScope NewEntry; 2075 NewEntry.FailIndex = FailIndex; 2076 NewEntry.NodeStack.append(NodeStack.begin(), NodeStack.end()); 2077 NewEntry.NumRecordedNodes = RecordedNodes.size(); 2078 NewEntry.NumMatchedMemRefs = MatchedMemRefs.size(); 2079 NewEntry.InputChain = InputChain; 2080 NewEntry.InputFlag = InputFlag; 2081 NewEntry.HasChainNodesMatched = !ChainNodesMatched.empty(); 2082 NewEntry.HasFlagResultNodesMatched = !FlagResultNodesMatched.empty(); 2083 MatchScopes.push_back(NewEntry); 2084 continue; 2085 } 2086 case OPC_RecordNode: 2087 // Remember this node, it may end up being an operand in the pattern. 2088 RecordedNodes.push_back(N); 2089 continue; 2090 2091 case OPC_RecordChild0: case OPC_RecordChild1: 2092 case OPC_RecordChild2: case OPC_RecordChild3: 2093 case OPC_RecordChild4: case OPC_RecordChild5: 2094 case OPC_RecordChild6: case OPC_RecordChild7: { 2095 unsigned ChildNo = Opcode-OPC_RecordChild0; 2096 if (ChildNo >= N.getNumOperands()) 2097 break; // Match fails if out of range child #. 2098 2099 RecordedNodes.push_back(N->getOperand(ChildNo)); 2100 continue; 2101 } 2102 case OPC_RecordMemRef: 2103 MatchedMemRefs.push_back(cast<MemSDNode>(N)->getMemOperand()); 2104 continue; 2105 2106 case OPC_CaptureFlagInput: 2107 // If the current node has an input flag, capture it in InputFlag. 2108 if (N->getNumOperands() != 0 && 2109 N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Flag) 2110 InputFlag = N->getOperand(N->getNumOperands()-1); 2111 continue; 2112 2113 case OPC_MoveChild: { 2114 unsigned ChildNo = MatcherTable[MatcherIndex++]; 2115 if (ChildNo >= N.getNumOperands()) 2116 break; // Match fails if out of range child #. 2117 N = N.getOperand(ChildNo); 2118 NodeStack.push_back(N); 2119 continue; 2120 } 2121 2122 case OPC_MoveParent: 2123 // Pop the current node off the NodeStack. 2124 NodeStack.pop_back(); 2125 assert(!NodeStack.empty() && "Node stack imbalance!"); 2126 N = NodeStack.back(); 2127 continue; 2128 2129 case OPC_CheckSame: 2130 if (!::CheckSame(MatcherTable, MatcherIndex, N, RecordedNodes)) break; 2131 continue; 2132 case OPC_CheckPatternPredicate: 2133 if (!::CheckPatternPredicate(MatcherTable, MatcherIndex, *this)) break; 2134 continue; 2135 case OPC_CheckPredicate: 2136 if (!::CheckNodePredicate(MatcherTable, MatcherIndex, *this, 2137 N.getNode())) 2138 break; 2139 continue; 2140 case OPC_CheckComplexPat: { 2141 unsigned CPNum = MatcherTable[MatcherIndex++]; 2142 unsigned RecNo = MatcherTable[MatcherIndex++]; 2143 assert(RecNo < RecordedNodes.size() && "Invalid CheckComplexPat"); 2144 if (!CheckComplexPattern(NodeToMatch, RecordedNodes[RecNo], CPNum, 2145 RecordedNodes)) 2146 break; 2147 continue; 2148 } 2149 case OPC_CheckOpcode: 2150 if (!::CheckOpcode(MatcherTable, MatcherIndex, N.getNode())) break; 2151 continue; 2152 2153 case OPC_CheckType: 2154 if (!::CheckType(MatcherTable, MatcherIndex, N, TLI)) break; 2155 continue; 2156 2157 case OPC_SwitchOpcode: { 2158 unsigned CurNodeOpcode = N.getOpcode(); 2159 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart; 2160 unsigned CaseSize; 2161 while (1) { 2162 // Get the size of this case. 2163 CaseSize = MatcherTable[MatcherIndex++]; 2164 if (CaseSize & 128) 2165 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex); 2166 if (CaseSize == 0) break; 2167 2168 uint16_t Opc = MatcherTable[MatcherIndex++]; 2169 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8; 2170 2171 // If the opcode matches, then we will execute this case. 2172 if (CurNodeOpcode == Opc) 2173 break; 2174 2175 // Otherwise, skip over this case. 2176 MatcherIndex += CaseSize; 2177 } 2178 2179 // If no cases matched, bail out. 2180 if (CaseSize == 0) break; 2181 2182 // Otherwise, execute the case we found. 2183 DEBUG(errs() << " OpcodeSwitch from " << SwitchStart 2184 << " to " << MatcherIndex << "\n"); 2185 continue; 2186 } 2187 2188 case OPC_SwitchType: { 2189 MVT::SimpleValueType CurNodeVT = N.getValueType().getSimpleVT().SimpleTy; 2190 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart; 2191 unsigned CaseSize; 2192 while (1) { 2193 // Get the size of this case. 2194 CaseSize = MatcherTable[MatcherIndex++]; 2195 if (CaseSize & 128) 2196 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex); 2197 if (CaseSize == 0) break; 2198 2199 MVT::SimpleValueType CaseVT = 2200 (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2201 if (CaseVT == MVT::iPTR) 2202 CaseVT = TLI.getPointerTy().SimpleTy; 2203 2204 // If the VT matches, then we will execute this case. 2205 if (CurNodeVT == CaseVT) 2206 break; 2207 2208 // Otherwise, skip over this case. 2209 MatcherIndex += CaseSize; 2210 } 2211 2212 // If no cases matched, bail out. 2213 if (CaseSize == 0) break; 2214 2215 // Otherwise, execute the case we found. 2216 DEBUG(errs() << " TypeSwitch[" << EVT(CurNodeVT).getEVTString() 2217 << "] from " << SwitchStart << " to " << MatcherIndex<<'\n'); 2218 continue; 2219 } 2220 case OPC_CheckChild0Type: case OPC_CheckChild1Type: 2221 case OPC_CheckChild2Type: case OPC_CheckChild3Type: 2222 case OPC_CheckChild4Type: case OPC_CheckChild5Type: 2223 case OPC_CheckChild6Type: case OPC_CheckChild7Type: 2224 if (!::CheckChildType(MatcherTable, MatcherIndex, N, TLI, 2225 Opcode-OPC_CheckChild0Type)) 2226 break; 2227 continue; 2228 case OPC_CheckCondCode: 2229 if (!::CheckCondCode(MatcherTable, MatcherIndex, N)) break; 2230 continue; 2231 case OPC_CheckValueType: 2232 if (!::CheckValueType(MatcherTable, MatcherIndex, N, TLI)) break; 2233 continue; 2234 case OPC_CheckInteger: 2235 if (!::CheckInteger(MatcherTable, MatcherIndex, N)) break; 2236 continue; 2237 case OPC_CheckAndImm: 2238 if (!::CheckAndImm(MatcherTable, MatcherIndex, N, *this)) break; 2239 continue; 2240 case OPC_CheckOrImm: 2241 if (!::CheckOrImm(MatcherTable, MatcherIndex, N, *this)) break; 2242 continue; 2243 2244 case OPC_CheckFoldableChainNode: { 2245 assert(NodeStack.size() != 1 && "No parent node"); 2246 // Verify that all intermediate nodes between the root and this one have 2247 // a single use. 2248 bool HasMultipleUses = false; 2249 for (unsigned i = 1, e = NodeStack.size()-1; i != e; ++i) 2250 if (!NodeStack[i].hasOneUse()) { 2251 HasMultipleUses = true; 2252 break; 2253 } 2254 if (HasMultipleUses) break; 2255 2256 // Check to see that the target thinks this is profitable to fold and that 2257 // we can fold it without inducing cycles in the graph. 2258 if (!IsProfitableToFold(N, NodeStack[NodeStack.size()-2].getNode(), 2259 NodeToMatch) || 2260 !IsLegalToFold(N, NodeStack[NodeStack.size()-2].getNode(), 2261 NodeToMatch, OptLevel, 2262 true/*We validate our own chains*/)) 2263 break; 2264 2265 continue; 2266 } 2267 case OPC_EmitInteger: { 2268 MVT::SimpleValueType VT = 2269 (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2270 int64_t Val = MatcherTable[MatcherIndex++]; 2271 if (Val & 128) 2272 Val = GetVBR(Val, MatcherTable, MatcherIndex); 2273 RecordedNodes.push_back(CurDAG->getTargetConstant(Val, VT)); 2274 continue; 2275 } 2276 case OPC_EmitRegister: { 2277 MVT::SimpleValueType VT = 2278 (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2279 unsigned RegNo = MatcherTable[MatcherIndex++]; 2280 RecordedNodes.push_back(CurDAG->getRegister(RegNo, VT)); 2281 continue; 2282 } 2283 2284 case OPC_EmitConvertToTarget: { 2285 // Convert from IMM/FPIMM to target version. 2286 unsigned RecNo = MatcherTable[MatcherIndex++]; 2287 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2288 SDValue Imm = RecordedNodes[RecNo]; 2289 2290 if (Imm->getOpcode() == ISD::Constant) { 2291 int64_t Val = cast<ConstantSDNode>(Imm)->getZExtValue(); 2292 Imm = CurDAG->getTargetConstant(Val, Imm.getValueType()); 2293 } else if (Imm->getOpcode() == ISD::ConstantFP) { 2294 const ConstantFP *Val=cast<ConstantFPSDNode>(Imm)->getConstantFPValue(); 2295 Imm = CurDAG->getTargetConstantFP(*Val, Imm.getValueType()); 2296 } 2297 2298 RecordedNodes.push_back(Imm); 2299 continue; 2300 } 2301 2302 case OPC_EmitMergeInputChains1_0: // OPC_EmitMergeInputChains, 1, 0 2303 case OPC_EmitMergeInputChains1_1: { // OPC_EmitMergeInputChains, 1, 1 2304 // These are space-optimized forms of OPC_EmitMergeInputChains. 2305 assert(InputChain.getNode() == 0 && 2306 "EmitMergeInputChains should be the first chain producing node"); 2307 assert(ChainNodesMatched.empty() && 2308 "Should only have one EmitMergeInputChains per match"); 2309 2310 // Read all of the chained nodes. 2311 unsigned RecNo = Opcode == OPC_EmitMergeInputChains1_1; 2312 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2313 ChainNodesMatched.push_back(RecordedNodes[RecNo].getNode()); 2314 2315 // FIXME: What if other value results of the node have uses not matched 2316 // by this pattern? 2317 if (ChainNodesMatched.back() != NodeToMatch && 2318 !RecordedNodes[RecNo].hasOneUse()) { 2319 ChainNodesMatched.clear(); 2320 break; 2321 } 2322 2323 // Merge the input chains if they are not intra-pattern references. 2324 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG); 2325 2326 if (InputChain.getNode() == 0) 2327 break; // Failed to merge. 2328 continue; 2329 } 2330 2331 case OPC_EmitMergeInputChains: { 2332 assert(InputChain.getNode() == 0 && 2333 "EmitMergeInputChains should be the first chain producing node"); 2334 // This node gets a list of nodes we matched in the input that have 2335 // chains. We want to token factor all of the input chains to these nodes 2336 // together. However, if any of the input chains is actually one of the 2337 // nodes matched in this pattern, then we have an intra-match reference. 2338 // Ignore these because the newly token factored chain should not refer to 2339 // the old nodes. 2340 unsigned NumChains = MatcherTable[MatcherIndex++]; 2341 assert(NumChains != 0 && "Can't TF zero chains"); 2342 2343 assert(ChainNodesMatched.empty() && 2344 "Should only have one EmitMergeInputChains per match"); 2345 2346 // Read all of the chained nodes. 2347 for (unsigned i = 0; i != NumChains; ++i) { 2348 unsigned RecNo = MatcherTable[MatcherIndex++]; 2349 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2350 ChainNodesMatched.push_back(RecordedNodes[RecNo].getNode()); 2351 2352 // FIXME: What if other value results of the node have uses not matched 2353 // by this pattern? 2354 if (ChainNodesMatched.back() != NodeToMatch && 2355 !RecordedNodes[RecNo].hasOneUse()) { 2356 ChainNodesMatched.clear(); 2357 break; 2358 } 2359 } 2360 2361 // If the inner loop broke out, the match fails. 2362 if (ChainNodesMatched.empty()) 2363 break; 2364 2365 // Merge the input chains if they are not intra-pattern references. 2366 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG); 2367 2368 if (InputChain.getNode() == 0) 2369 break; // Failed to merge. 2370 2371 continue; 2372 } 2373 2374 case OPC_EmitCopyToReg: { 2375 unsigned RecNo = MatcherTable[MatcherIndex++]; 2376 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2377 unsigned DestPhysReg = MatcherTable[MatcherIndex++]; 2378 2379 if (InputChain.getNode() == 0) 2380 InputChain = CurDAG->getEntryNode(); 2381 2382 InputChain = CurDAG->getCopyToReg(InputChain, NodeToMatch->getDebugLoc(), 2383 DestPhysReg, RecordedNodes[RecNo], 2384 InputFlag); 2385 2386 InputFlag = InputChain.getValue(1); 2387 continue; 2388 } 2389 2390 case OPC_EmitNodeXForm: { 2391 unsigned XFormNo = MatcherTable[MatcherIndex++]; 2392 unsigned RecNo = MatcherTable[MatcherIndex++]; 2393 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2394 RecordedNodes.push_back(RunSDNodeXForm(RecordedNodes[RecNo], XFormNo)); 2395 continue; 2396 } 2397 2398 case OPC_EmitNode: 2399 case OPC_MorphNodeTo: { 2400 uint16_t TargetOpc = MatcherTable[MatcherIndex++]; 2401 TargetOpc |= (unsigned short)MatcherTable[MatcherIndex++] << 8; 2402 unsigned EmitNodeInfo = MatcherTable[MatcherIndex++]; 2403 // Get the result VT list. 2404 unsigned NumVTs = MatcherTable[MatcherIndex++]; 2405 SmallVector<EVT, 4> VTs; 2406 for (unsigned i = 0; i != NumVTs; ++i) { 2407 MVT::SimpleValueType VT = 2408 (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2409 if (VT == MVT::iPTR) VT = TLI.getPointerTy().SimpleTy; 2410 VTs.push_back(VT); 2411 } 2412 2413 if (EmitNodeInfo & OPFL_Chain) 2414 VTs.push_back(MVT::Other); 2415 if (EmitNodeInfo & OPFL_FlagOutput) 2416 VTs.push_back(MVT::Flag); 2417 2418 // This is hot code, so optimize the two most common cases of 1 and 2 2419 // results. 2420 SDVTList VTList; 2421 if (VTs.size() == 1) 2422 VTList = CurDAG->getVTList(VTs[0]); 2423 else if (VTs.size() == 2) 2424 VTList = CurDAG->getVTList(VTs[0], VTs[1]); 2425 else 2426 VTList = CurDAG->getVTList(VTs.data(), VTs.size()); 2427 2428 // Get the operand list. 2429 unsigned NumOps = MatcherTable[MatcherIndex++]; 2430 SmallVector<SDValue, 8> Ops; 2431 for (unsigned i = 0; i != NumOps; ++i) { 2432 unsigned RecNo = MatcherTable[MatcherIndex++]; 2433 if (RecNo & 128) 2434 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex); 2435 2436 assert(RecNo < RecordedNodes.size() && "Invalid EmitNode"); 2437 Ops.push_back(RecordedNodes[RecNo]); 2438 } 2439 2440 // If there are variadic operands to add, handle them now. 2441 if (EmitNodeInfo & OPFL_VariadicInfo) { 2442 // Determine the start index to copy from. 2443 unsigned FirstOpToCopy = getNumFixedFromVariadicInfo(EmitNodeInfo); 2444 FirstOpToCopy += (EmitNodeInfo & OPFL_Chain) ? 1 : 0; 2445 assert(NodeToMatch->getNumOperands() >= FirstOpToCopy && 2446 "Invalid variadic node"); 2447 // Copy all of the variadic operands, not including a potential flag 2448 // input. 2449 for (unsigned i = FirstOpToCopy, e = NodeToMatch->getNumOperands(); 2450 i != e; ++i) { 2451 SDValue V = NodeToMatch->getOperand(i); 2452 if (V.getValueType() == MVT::Flag) break; 2453 Ops.push_back(V); 2454 } 2455 } 2456 2457 // If this has chain/flag inputs, add them. 2458 if (EmitNodeInfo & OPFL_Chain) 2459 Ops.push_back(InputChain); 2460 if ((EmitNodeInfo & OPFL_FlagInput) && InputFlag.getNode() != 0) 2461 Ops.push_back(InputFlag); 2462 2463 // Create the node. 2464 SDNode *Res = 0; 2465 if (Opcode != OPC_MorphNodeTo) { 2466 // If this is a normal EmitNode command, just create the new node and 2467 // add the results to the RecordedNodes list. 2468 Res = CurDAG->getMachineNode(TargetOpc, NodeToMatch->getDebugLoc(), 2469 VTList, Ops.data(), Ops.size()); 2470 2471 // Add all the non-flag/non-chain results to the RecordedNodes list. 2472 for (unsigned i = 0, e = VTs.size(); i != e; ++i) { 2473 if (VTs[i] == MVT::Other || VTs[i] == MVT::Flag) break; 2474 RecordedNodes.push_back(SDValue(Res, i)); 2475 } 2476 2477 } else { 2478 Res = MorphNode(NodeToMatch, TargetOpc, VTList, Ops.data(), Ops.size(), 2479 EmitNodeInfo); 2480 } 2481 2482 // If the node had chain/flag results, update our notion of the current 2483 // chain and flag. 2484 if (EmitNodeInfo & OPFL_FlagOutput) { 2485 InputFlag = SDValue(Res, VTs.size()-1); 2486 if (EmitNodeInfo & OPFL_Chain) 2487 InputChain = SDValue(Res, VTs.size()-2); 2488 } else if (EmitNodeInfo & OPFL_Chain) 2489 InputChain = SDValue(Res, VTs.size()-1); 2490 2491 // If the OPFL_MemRefs flag is set on this node, slap all of the 2492 // accumulated memrefs onto it. 2493 // 2494 // FIXME: This is vastly incorrect for patterns with multiple outputs 2495 // instructions that access memory and for ComplexPatterns that match 2496 // loads. 2497 if (EmitNodeInfo & OPFL_MemRefs) { 2498 MachineSDNode::mmo_iterator MemRefs = 2499 MF->allocateMemRefsArray(MatchedMemRefs.size()); 2500 std::copy(MatchedMemRefs.begin(), MatchedMemRefs.end(), MemRefs); 2501 cast<MachineSDNode>(Res) 2502 ->setMemRefs(MemRefs, MemRefs + MatchedMemRefs.size()); 2503 } 2504 2505 DEBUG(errs() << " " 2506 << (Opcode == OPC_MorphNodeTo ? "Morphed" : "Created") 2507 << " node: "; Res->dump(CurDAG); errs() << "\n"); 2508 2509 // If this was a MorphNodeTo then we're completely done! 2510 if (Opcode == OPC_MorphNodeTo) { 2511 // Update chain and flag uses. 2512 UpdateChainsAndFlags(NodeToMatch, InputChain, ChainNodesMatched, 2513 InputFlag, FlagResultNodesMatched, true); 2514 return Res; 2515 } 2516 2517 continue; 2518 } 2519 2520 case OPC_MarkFlagResults: { 2521 unsigned NumNodes = MatcherTable[MatcherIndex++]; 2522 2523 // Read and remember all the flag-result nodes. 2524 for (unsigned i = 0; i != NumNodes; ++i) { 2525 unsigned RecNo = MatcherTable[MatcherIndex++]; 2526 if (RecNo & 128) 2527 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex); 2528 2529 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2530 FlagResultNodesMatched.push_back(RecordedNodes[RecNo].getNode()); 2531 } 2532 continue; 2533 } 2534 2535 case OPC_CompleteMatch: { 2536 // The match has been completed, and any new nodes (if any) have been 2537 // created. Patch up references to the matched dag to use the newly 2538 // created nodes. 2539 unsigned NumResults = MatcherTable[MatcherIndex++]; 2540 2541 for (unsigned i = 0; i != NumResults; ++i) { 2542 unsigned ResSlot = MatcherTable[MatcherIndex++]; 2543 if (ResSlot & 128) 2544 ResSlot = GetVBR(ResSlot, MatcherTable, MatcherIndex); 2545 2546 assert(ResSlot < RecordedNodes.size() && "Invalid CheckSame"); 2547 SDValue Res = RecordedNodes[ResSlot]; 2548 2549 assert(i < NodeToMatch->getNumValues() && 2550 NodeToMatch->getValueType(i) != MVT::Other && 2551 NodeToMatch->getValueType(i) != MVT::Flag && 2552 "Invalid number of results to complete!"); 2553 assert((NodeToMatch->getValueType(i) == Res.getValueType() || 2554 NodeToMatch->getValueType(i) == MVT::iPTR || 2555 Res.getValueType() == MVT::iPTR || 2556 NodeToMatch->getValueType(i).getSizeInBits() == 2557 Res.getValueType().getSizeInBits()) && 2558 "invalid replacement"); 2559 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, i), Res); 2560 } 2561 2562 // If the root node defines a flag, add it to the flag nodes to update 2563 // list. 2564 if (NodeToMatch->getValueType(NodeToMatch->getNumValues()-1) == MVT::Flag) 2565 FlagResultNodesMatched.push_back(NodeToMatch); 2566 2567 // Update chain and flag uses. 2568 UpdateChainsAndFlags(NodeToMatch, InputChain, ChainNodesMatched, 2569 InputFlag, FlagResultNodesMatched, false); 2570 2571 assert(NodeToMatch->use_empty() && 2572 "Didn't replace all uses of the node?"); 2573 2574 // FIXME: We just return here, which interacts correctly with SelectRoot 2575 // above. We should fix this to not return an SDNode* anymore. 2576 return 0; 2577 } 2578 } 2579 2580 // If the code reached this point, then the match failed. See if there is 2581 // another child to try in the current 'Scope', otherwise pop it until we 2582 // find a case to check. 2583 DEBUG(errs() << " Match failed at index " << CurrentOpcodeIndex << "\n"); 2584 ++NumDAGIselRetries; 2585 while (1) { 2586 if (MatchScopes.empty()) { 2587 CannotYetSelect(NodeToMatch); 2588 return 0; 2589 } 2590 2591 // Restore the interpreter state back to the point where the scope was 2592 // formed. 2593 MatchScope &LastScope = MatchScopes.back(); 2594 RecordedNodes.resize(LastScope.NumRecordedNodes); 2595 NodeStack.clear(); 2596 NodeStack.append(LastScope.NodeStack.begin(), LastScope.NodeStack.end()); 2597 N = NodeStack.back(); 2598 2599 if (LastScope.NumMatchedMemRefs != MatchedMemRefs.size()) 2600 MatchedMemRefs.resize(LastScope.NumMatchedMemRefs); 2601 MatcherIndex = LastScope.FailIndex; 2602 2603 DEBUG(errs() << " Continuing at " << MatcherIndex << "\n"); 2604 2605 InputChain = LastScope.InputChain; 2606 InputFlag = LastScope.InputFlag; 2607 if (!LastScope.HasChainNodesMatched) 2608 ChainNodesMatched.clear(); 2609 if (!LastScope.HasFlagResultNodesMatched) 2610 FlagResultNodesMatched.clear(); 2611 2612 // Check to see what the offset is at the new MatcherIndex. If it is zero 2613 // we have reached the end of this scope, otherwise we have another child 2614 // in the current scope to try. 2615 unsigned NumToSkip = MatcherTable[MatcherIndex++]; 2616 if (NumToSkip & 128) 2617 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex); 2618 2619 // If we have another child in this scope to match, update FailIndex and 2620 // try it. 2621 if (NumToSkip != 0) { 2622 LastScope.FailIndex = MatcherIndex+NumToSkip; 2623 break; 2624 } 2625 2626 // End of this scope, pop it and try the next child in the containing 2627 // scope. 2628 MatchScopes.pop_back(); 2629 } 2630 } 2631} 2632 2633 2634 2635void SelectionDAGISel::CannotYetSelect(SDNode *N) { 2636 std::string msg; 2637 raw_string_ostream Msg(msg); 2638 Msg << "Cannot yet select: "; 2639 2640 if (N->getOpcode() != ISD::INTRINSIC_W_CHAIN && 2641 N->getOpcode() != ISD::INTRINSIC_WO_CHAIN && 2642 N->getOpcode() != ISD::INTRINSIC_VOID) { 2643 N->printrFull(Msg, CurDAG); 2644 } else { 2645 bool HasInputChain = N->getOperand(0).getValueType() == MVT::Other; 2646 unsigned iid = 2647 cast<ConstantSDNode>(N->getOperand(HasInputChain))->getZExtValue(); 2648 if (iid < Intrinsic::num_intrinsics) 2649 Msg << "intrinsic %" << Intrinsic::getName((Intrinsic::ID)iid); 2650 else if (const TargetIntrinsicInfo *TII = TM.getIntrinsicInfo()) 2651 Msg << "target intrinsic %" << TII->getName(iid); 2652 else 2653 Msg << "unknown intrinsic #" << iid; 2654 } 2655 report_fatal_error(Msg.str()); 2656} 2657 2658char SelectionDAGISel::ID = 0; 2659