SelectionDAGISel.cpp revision 206274
1//===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This implements the SelectionDAGISel class. 11// 12//===----------------------------------------------------------------------===// 13 14#define DEBUG_TYPE "isel" 15#include "ScheduleDAGSDNodes.h" 16#include "SelectionDAGBuilder.h" 17#include "FunctionLoweringInfo.h" 18#include "llvm/CodeGen/SelectionDAGISel.h" 19#include "llvm/Analysis/AliasAnalysis.h" 20#include "llvm/Analysis/DebugInfo.h" 21#include "llvm/Constants.h" 22#include "llvm/CallingConv.h" 23#include "llvm/DerivedTypes.h" 24#include "llvm/Function.h" 25#include "llvm/GlobalVariable.h" 26#include "llvm/InlineAsm.h" 27#include "llvm/Instructions.h" 28#include "llvm/Intrinsics.h" 29#include "llvm/IntrinsicInst.h" 30#include "llvm/LLVMContext.h" 31#include "llvm/CodeGen/FastISel.h" 32#include "llvm/CodeGen/GCStrategy.h" 33#include "llvm/CodeGen/GCMetadata.h" 34#include "llvm/CodeGen/MachineFunction.h" 35#include "llvm/CodeGen/MachineFunctionAnalysis.h" 36#include "llvm/CodeGen/MachineFrameInfo.h" 37#include "llvm/CodeGen/MachineInstrBuilder.h" 38#include "llvm/CodeGen/MachineJumpTableInfo.h" 39#include "llvm/CodeGen/MachineModuleInfo.h" 40#include "llvm/CodeGen/MachineRegisterInfo.h" 41#include "llvm/CodeGen/ScheduleHazardRecognizer.h" 42#include "llvm/CodeGen/SchedulerRegistry.h" 43#include "llvm/CodeGen/SelectionDAG.h" 44#include "llvm/Target/TargetRegisterInfo.h" 45#include "llvm/Target/TargetData.h" 46#include "llvm/Target/TargetFrameInfo.h" 47#include "llvm/Target/TargetIntrinsicInfo.h" 48#include "llvm/Target/TargetInstrInfo.h" 49#include "llvm/Target/TargetLowering.h" 50#include "llvm/Target/TargetMachine.h" 51#include "llvm/Target/TargetOptions.h" 52#include "llvm/Support/Compiler.h" 53#include "llvm/Support/Debug.h" 54#include "llvm/Support/ErrorHandling.h" 55#include "llvm/Support/MathExtras.h" 56#include "llvm/Support/Timer.h" 57#include "llvm/Support/raw_ostream.h" 58#include "llvm/ADT/Statistic.h" 59#include <algorithm> 60using namespace llvm; 61 62STATISTIC(NumFastIselFailures, "Number of instructions fast isel failed on"); 63STATISTIC(NumDAGIselRetries,"Number of times dag isel has to try another path"); 64 65static cl::opt<bool> 66EnableFastISelVerbose("fast-isel-verbose", cl::Hidden, 67 cl::desc("Enable verbose messages in the \"fast\" " 68 "instruction selector")); 69static cl::opt<bool> 70EnableFastISelAbort("fast-isel-abort", cl::Hidden, 71 cl::desc("Enable abort calls when \"fast\" instruction fails")); 72static cl::opt<bool> 73SchedLiveInCopies("schedule-livein-copies", cl::Hidden, 74 cl::desc("Schedule copies of livein registers"), 75 cl::init(false)); 76 77#ifndef NDEBUG 78static cl::opt<bool> 79ViewDAGCombine1("view-dag-combine1-dags", cl::Hidden, 80 cl::desc("Pop up a window to show dags before the first " 81 "dag combine pass")); 82static cl::opt<bool> 83ViewLegalizeTypesDAGs("view-legalize-types-dags", cl::Hidden, 84 cl::desc("Pop up a window to show dags before legalize types")); 85static cl::opt<bool> 86ViewLegalizeDAGs("view-legalize-dags", cl::Hidden, 87 cl::desc("Pop up a window to show dags before legalize")); 88static cl::opt<bool> 89ViewDAGCombine2("view-dag-combine2-dags", cl::Hidden, 90 cl::desc("Pop up a window to show dags before the second " 91 "dag combine pass")); 92static cl::opt<bool> 93ViewDAGCombineLT("view-dag-combine-lt-dags", cl::Hidden, 94 cl::desc("Pop up a window to show dags before the post legalize types" 95 " dag combine pass")); 96static cl::opt<bool> 97ViewISelDAGs("view-isel-dags", cl::Hidden, 98 cl::desc("Pop up a window to show isel dags as they are selected")); 99static cl::opt<bool> 100ViewSchedDAGs("view-sched-dags", cl::Hidden, 101 cl::desc("Pop up a window to show sched dags as they are processed")); 102static cl::opt<bool> 103ViewSUnitDAGs("view-sunit-dags", cl::Hidden, 104 cl::desc("Pop up a window to show SUnit dags after they are processed")); 105#else 106static const bool ViewDAGCombine1 = false, 107 ViewLegalizeTypesDAGs = false, ViewLegalizeDAGs = false, 108 ViewDAGCombine2 = false, 109 ViewDAGCombineLT = false, 110 ViewISelDAGs = false, ViewSchedDAGs = false, 111 ViewSUnitDAGs = false; 112#endif 113 114//===---------------------------------------------------------------------===// 115/// 116/// RegisterScheduler class - Track the registration of instruction schedulers. 117/// 118//===---------------------------------------------------------------------===// 119MachinePassRegistry RegisterScheduler::Registry; 120 121//===---------------------------------------------------------------------===// 122/// 123/// ISHeuristic command line option for instruction schedulers. 124/// 125//===---------------------------------------------------------------------===// 126static cl::opt<RegisterScheduler::FunctionPassCtor, false, 127 RegisterPassParser<RegisterScheduler> > 128ISHeuristic("pre-RA-sched", 129 cl::init(&createDefaultScheduler), 130 cl::desc("Instruction schedulers available (before register" 131 " allocation):")); 132 133static RegisterScheduler 134defaultListDAGScheduler("default", "Best scheduler for the target", 135 createDefaultScheduler); 136 137namespace llvm { 138 //===--------------------------------------------------------------------===// 139 /// createDefaultScheduler - This creates an instruction scheduler appropriate 140 /// for the target. 141 ScheduleDAGSDNodes* createDefaultScheduler(SelectionDAGISel *IS, 142 CodeGenOpt::Level OptLevel) { 143 const TargetLowering &TLI = IS->getTargetLowering(); 144 145 if (OptLevel == CodeGenOpt::None) 146 return createFastDAGScheduler(IS, OptLevel); 147 if (TLI.getSchedulingPreference() == TargetLowering::SchedulingForLatency) 148 return createTDListDAGScheduler(IS, OptLevel); 149 assert(TLI.getSchedulingPreference() == 150 TargetLowering::SchedulingForRegPressure && "Unknown sched type!"); 151 return createBURRListDAGScheduler(IS, OptLevel); 152 } 153} 154 155// EmitInstrWithCustomInserter - This method should be implemented by targets 156// that mark instructions with the 'usesCustomInserter' flag. These 157// instructions are special in various ways, which require special support to 158// insert. The specified MachineInstr is created but not inserted into any 159// basic blocks, and this method is called to expand it into a sequence of 160// instructions, potentially also creating new basic blocks and control flow. 161// When new basic blocks are inserted and the edges from MBB to its successors 162// are modified, the method should insert pairs of <OldSucc, NewSucc> into the 163// DenseMap. 164MachineBasicBlock *TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 165 MachineBasicBlock *MBB, 166 DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) const { 167#ifndef NDEBUG 168 dbgs() << "If a target marks an instruction with " 169 "'usesCustomInserter', it must implement " 170 "TargetLowering::EmitInstrWithCustomInserter!"; 171#endif 172 llvm_unreachable(0); 173 return 0; 174} 175 176/// EmitLiveInCopy - Emit a copy for a live in physical register. If the 177/// physical register has only a single copy use, then coalesced the copy 178/// if possible. 179static void EmitLiveInCopy(MachineBasicBlock *MBB, 180 MachineBasicBlock::iterator &InsertPos, 181 unsigned VirtReg, unsigned PhysReg, 182 const TargetRegisterClass *RC, 183 DenseMap<MachineInstr*, unsigned> &CopyRegMap, 184 const MachineRegisterInfo &MRI, 185 const TargetRegisterInfo &TRI, 186 const TargetInstrInfo &TII) { 187 unsigned NumUses = 0; 188 MachineInstr *UseMI = NULL; 189 for (MachineRegisterInfo::use_iterator UI = MRI.use_begin(VirtReg), 190 UE = MRI.use_end(); UI != UE; ++UI) { 191 UseMI = &*UI; 192 if (++NumUses > 1) 193 break; 194 } 195 196 // If the number of uses is not one, or the use is not a move instruction, 197 // don't coalesce. Also, only coalesce away a virtual register to virtual 198 // register copy. 199 bool Coalesced = false; 200 unsigned SrcReg, DstReg, SrcSubReg, DstSubReg; 201 if (NumUses == 1 && 202 TII.isMoveInstr(*UseMI, SrcReg, DstReg, SrcSubReg, DstSubReg) && 203 TargetRegisterInfo::isVirtualRegister(DstReg)) { 204 VirtReg = DstReg; 205 Coalesced = true; 206 } 207 208 // Now find an ideal location to insert the copy. 209 MachineBasicBlock::iterator Pos = InsertPos; 210 while (Pos != MBB->begin()) { 211 MachineInstr *PrevMI = prior(Pos); 212 DenseMap<MachineInstr*, unsigned>::iterator RI = CopyRegMap.find(PrevMI); 213 // copyRegToReg might emit multiple instructions to do a copy. 214 unsigned CopyDstReg = (RI == CopyRegMap.end()) ? 0 : RI->second; 215 if (CopyDstReg && !TRI.regsOverlap(CopyDstReg, PhysReg)) 216 // This is what the BB looks like right now: 217 // r1024 = mov r0 218 // ... 219 // r1 = mov r1024 220 // 221 // We want to insert "r1025 = mov r1". Inserting this copy below the 222 // move to r1024 makes it impossible for that move to be coalesced. 223 // 224 // r1025 = mov r1 225 // r1024 = mov r0 226 // ... 227 // r1 = mov 1024 228 // r2 = mov 1025 229 break; // Woot! Found a good location. 230 --Pos; 231 } 232 233 bool Emitted = TII.copyRegToReg(*MBB, Pos, VirtReg, PhysReg, RC, RC); 234 assert(Emitted && "Unable to issue a live-in copy instruction!\n"); 235 (void) Emitted; 236 237 CopyRegMap.insert(std::make_pair(prior(Pos), VirtReg)); 238 if (Coalesced) { 239 if (&*InsertPos == UseMI) ++InsertPos; 240 MBB->erase(UseMI); 241 } 242} 243 244/// EmitLiveInCopies - If this is the first basic block in the function, 245/// and if it has live ins that need to be copied into vregs, emit the 246/// copies into the block. 247static void EmitLiveInCopies(MachineBasicBlock *EntryMBB, 248 const MachineRegisterInfo &MRI, 249 const TargetRegisterInfo &TRI, 250 const TargetInstrInfo &TII) { 251 if (SchedLiveInCopies) { 252 // Emit the copies at a heuristically-determined location in the block. 253 DenseMap<MachineInstr*, unsigned> CopyRegMap; 254 MachineBasicBlock::iterator InsertPos = EntryMBB->begin(); 255 for (MachineRegisterInfo::livein_iterator LI = MRI.livein_begin(), 256 E = MRI.livein_end(); LI != E; ++LI) 257 if (LI->second) { 258 const TargetRegisterClass *RC = MRI.getRegClass(LI->second); 259 EmitLiveInCopy(EntryMBB, InsertPos, LI->second, LI->first, 260 RC, CopyRegMap, MRI, TRI, TII); 261 } 262 } else { 263 // Emit the copies into the top of the block. 264 for (MachineRegisterInfo::livein_iterator LI = MRI.livein_begin(), 265 E = MRI.livein_end(); LI != E; ++LI) 266 if (LI->second) { 267 const TargetRegisterClass *RC = MRI.getRegClass(LI->second); 268 bool Emitted = TII.copyRegToReg(*EntryMBB, EntryMBB->begin(), 269 LI->second, LI->first, RC, RC); 270 assert(Emitted && "Unable to issue a live-in copy instruction!\n"); 271 (void) Emitted; 272 } 273 } 274} 275 276//===----------------------------------------------------------------------===// 277// SelectionDAGISel code 278//===----------------------------------------------------------------------===// 279 280SelectionDAGISel::SelectionDAGISel(TargetMachine &tm, CodeGenOpt::Level OL) : 281 MachineFunctionPass(&ID), TM(tm), TLI(*tm.getTargetLowering()), 282 FuncInfo(new FunctionLoweringInfo(TLI)), 283 CurDAG(new SelectionDAG(TLI, *FuncInfo)), 284 SDB(new SelectionDAGBuilder(*CurDAG, TLI, *FuncInfo, OL)), 285 GFI(), 286 OptLevel(OL), 287 DAGSize(0) 288{} 289 290SelectionDAGISel::~SelectionDAGISel() { 291 delete SDB; 292 delete CurDAG; 293 delete FuncInfo; 294} 295 296unsigned SelectionDAGISel::MakeReg(EVT VT) { 297 return RegInfo->createVirtualRegister(TLI.getRegClassFor(VT)); 298} 299 300void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const { 301 AU.addRequired<AliasAnalysis>(); 302 AU.addPreserved<AliasAnalysis>(); 303 AU.addRequired<GCModuleInfo>(); 304 AU.addPreserved<GCModuleInfo>(); 305 MachineFunctionPass::getAnalysisUsage(AU); 306} 307 308bool SelectionDAGISel::runOnMachineFunction(MachineFunction &mf) { 309 Function &Fn = *mf.getFunction(); 310 311 // Do some sanity-checking on the command-line options. 312 assert((!EnableFastISelVerbose || EnableFastISel) && 313 "-fast-isel-verbose requires -fast-isel"); 314 assert((!EnableFastISelAbort || EnableFastISel) && 315 "-fast-isel-abort requires -fast-isel"); 316 317 // Get alias analysis for load/store combining. 318 AA = &getAnalysis<AliasAnalysis>(); 319 320 MF = &mf; 321 const TargetInstrInfo &TII = *TM.getInstrInfo(); 322 const TargetRegisterInfo &TRI = *TM.getRegisterInfo(); 323 324 if (Fn.hasGC()) 325 GFI = &getAnalysis<GCModuleInfo>().getFunctionInfo(Fn); 326 else 327 GFI = 0; 328 RegInfo = &MF->getRegInfo(); 329 DEBUG(dbgs() << "\n\n\n=== " << Fn.getName() << "\n"); 330 331 CurDAG->init(*MF); 332 FuncInfo->set(Fn, *MF, EnableFastISel); 333 SDB->init(GFI, *AA); 334 335 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I) 336 if (InvokeInst *Invoke = dyn_cast<InvokeInst>(I->getTerminator())) 337 // Mark landing pad. 338 FuncInfo->MBBMap[Invoke->getSuccessor(1)]->setIsLandingPad(); 339 340 SelectAllBasicBlocks(Fn, *MF, TII); 341 342 // If the first basic block in the function has live ins that need to be 343 // copied into vregs, emit the copies into the top of the block before 344 // emitting the code for the block. 345 EmitLiveInCopies(MF->begin(), *RegInfo, TRI, TII); 346 347 // Add function live-ins to entry block live-in set. 348 for (MachineRegisterInfo::livein_iterator I = RegInfo->livein_begin(), 349 E = RegInfo->livein_end(); I != E; ++I) 350 MF->begin()->addLiveIn(I->first); 351 352#ifndef NDEBUG 353 assert(FuncInfo->CatchInfoFound.size() == FuncInfo->CatchInfoLost.size() && 354 "Not all catch info was assigned to a landing pad!"); 355#endif 356 357 FuncInfo->clear(); 358 359 return true; 360} 361 362/// SetDebugLoc - Update MF's and SDB's DebugLocs if debug information is 363/// attached with this instruction. 364static void SetDebugLoc(Instruction *I, SelectionDAGBuilder *SDB, 365 FastISel *FastIS, MachineFunction *MF) { 366 DebugLoc DL = I->getDebugLoc(); 367 if (DL.isUnknown()) return; 368 369 SDB->setCurDebugLoc(DL); 370 371 if (FastIS) 372 FastIS->setCurDebugLoc(DL); 373 374 // If the function doesn't have a default debug location yet, set 375 // it. This is kind of a hack. 376 if (MF->getDefaultDebugLoc().isUnknown()) 377 MF->setDefaultDebugLoc(DL); 378} 379 380/// ResetDebugLoc - Set MF's and SDB's DebugLocs to Unknown. 381static void ResetDebugLoc(SelectionDAGBuilder *SDB, FastISel *FastIS) { 382 SDB->setCurDebugLoc(DebugLoc()); 383 if (FastIS) 384 FastIS->setCurDebugLoc(DebugLoc()); 385} 386 387void SelectionDAGISel::SelectBasicBlock(BasicBlock *LLVMBB, 388 BasicBlock::iterator Begin, 389 BasicBlock::iterator End, 390 bool &HadTailCall) { 391 SDB->setCurrentBasicBlock(BB); 392 393 // Lower all of the non-terminator instructions. If a call is emitted 394 // as a tail call, cease emitting nodes for this block. 395 for (BasicBlock::iterator I = Begin; I != End && !SDB->HasTailCall; ++I) { 396 SetDebugLoc(I, SDB, 0, MF); 397 398 if (!isa<TerminatorInst>(I)) { 399 SDB->visit(*I); 400 401 // Set the current debug location back to "unknown" so that it doesn't 402 // spuriously apply to subsequent instructions. 403 ResetDebugLoc(SDB, 0); 404 } 405 } 406 407 if (!SDB->HasTailCall) { 408 // Ensure that all instructions which are used outside of their defining 409 // blocks are available as virtual registers. Invoke is handled elsewhere. 410 for (BasicBlock::iterator I = Begin; I != End; ++I) 411 if (!isa<PHINode>(I) && !isa<InvokeInst>(I)) 412 SDB->CopyToExportRegsIfNeeded(I); 413 414 // Handle PHI nodes in successor blocks. 415 if (End == LLVMBB->end()) { 416 HandlePHINodesInSuccessorBlocks(LLVMBB); 417 418 // Lower the terminator after the copies are emitted. 419 SetDebugLoc(LLVMBB->getTerminator(), SDB, 0, MF); 420 SDB->visit(*LLVMBB->getTerminator()); 421 ResetDebugLoc(SDB, 0); 422 } 423 } 424 425 // Make sure the root of the DAG is up-to-date. 426 CurDAG->setRoot(SDB->getControlRoot()); 427 428 // Final step, emit the lowered DAG as machine code. 429 CodeGenAndEmitDAG(); 430 HadTailCall = SDB->HasTailCall; 431 SDB->clear(); 432} 433 434namespace { 435/// WorkListRemover - This class is a DAGUpdateListener that removes any deleted 436/// nodes from the worklist. 437class SDOPsWorkListRemover : public SelectionDAG::DAGUpdateListener { 438 SmallVector<SDNode*, 128> &Worklist; 439 SmallPtrSet<SDNode*, 128> &InWorklist; 440public: 441 SDOPsWorkListRemover(SmallVector<SDNode*, 128> &wl, 442 SmallPtrSet<SDNode*, 128> &inwl) 443 : Worklist(wl), InWorklist(inwl) {} 444 445 void RemoveFromWorklist(SDNode *N) { 446 if (!InWorklist.erase(N)) return; 447 448 SmallVector<SDNode*, 128>::iterator I = 449 std::find(Worklist.begin(), Worklist.end(), N); 450 assert(I != Worklist.end() && "Not in worklist"); 451 452 *I = Worklist.back(); 453 Worklist.pop_back(); 454 } 455 456 virtual void NodeDeleted(SDNode *N, SDNode *E) { 457 RemoveFromWorklist(N); 458 } 459 460 virtual void NodeUpdated(SDNode *N) { 461 // Ignore updates. 462 } 463}; 464} 465 466/// TrivialTruncElim - Eliminate some trivial nops that can result from 467/// ShrinkDemandedOps: (trunc (ext n)) -> n. 468static bool TrivialTruncElim(SDValue Op, 469 TargetLowering::TargetLoweringOpt &TLO) { 470 SDValue N0 = Op.getOperand(0); 471 EVT VT = Op.getValueType(); 472 if ((N0.getOpcode() == ISD::ZERO_EXTEND || 473 N0.getOpcode() == ISD::SIGN_EXTEND || 474 N0.getOpcode() == ISD::ANY_EXTEND) && 475 N0.getOperand(0).getValueType() == VT) { 476 return TLO.CombineTo(Op, N0.getOperand(0)); 477 } 478 return false; 479} 480 481/// ShrinkDemandedOps - A late transformation pass that shrink expressions 482/// using TargetLowering::TargetLoweringOpt::ShrinkDemandedOp. It converts 483/// x+y to (VT)((SmallVT)x+(SmallVT)y) if the casts are free. 484void SelectionDAGISel::ShrinkDemandedOps() { 485 SmallVector<SDNode*, 128> Worklist; 486 SmallPtrSet<SDNode*, 128> InWorklist; 487 488 // Add all the dag nodes to the worklist. 489 Worklist.reserve(CurDAG->allnodes_size()); 490 for (SelectionDAG::allnodes_iterator I = CurDAG->allnodes_begin(), 491 E = CurDAG->allnodes_end(); I != E; ++I) { 492 Worklist.push_back(I); 493 InWorklist.insert(I); 494 } 495 496 TargetLowering::TargetLoweringOpt TLO(*CurDAG, true); 497 while (!Worklist.empty()) { 498 SDNode *N = Worklist.pop_back_val(); 499 InWorklist.erase(N); 500 501 if (N->use_empty() && N != CurDAG->getRoot().getNode()) { 502 // Deleting this node may make its operands dead, add them to the worklist 503 // if they aren't already there. 504 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 505 if (InWorklist.insert(N->getOperand(i).getNode())) 506 Worklist.push_back(N->getOperand(i).getNode()); 507 508 CurDAG->DeleteNode(N); 509 continue; 510 } 511 512 // Run ShrinkDemandedOp on scalar binary operations. 513 if (N->getNumValues() != 1 || 514 !N->getValueType(0).isSimple() || !N->getValueType(0).isInteger()) 515 continue; 516 517 unsigned BitWidth = N->getValueType(0).getScalarType().getSizeInBits(); 518 APInt Demanded = APInt::getAllOnesValue(BitWidth); 519 APInt KnownZero, KnownOne; 520 if (!TLI.SimplifyDemandedBits(SDValue(N, 0), Demanded, 521 KnownZero, KnownOne, TLO) && 522 (N->getOpcode() != ISD::TRUNCATE || 523 !TrivialTruncElim(SDValue(N, 0), TLO))) 524 continue; 525 526 // Revisit the node. 527 assert(!InWorklist.count(N) && "Already in worklist"); 528 Worklist.push_back(N); 529 InWorklist.insert(N); 530 531 // Replace the old value with the new one. 532 DEBUG(errs() << "\nShrinkDemandedOps replacing "; 533 TLO.Old.getNode()->dump(CurDAG); 534 errs() << "\nWith: "; 535 TLO.New.getNode()->dump(CurDAG); 536 errs() << '\n'); 537 538 if (InWorklist.insert(TLO.New.getNode())) 539 Worklist.push_back(TLO.New.getNode()); 540 541 SDOPsWorkListRemover DeadNodes(Worklist, InWorklist); 542 CurDAG->ReplaceAllUsesOfValueWith(TLO.Old, TLO.New, &DeadNodes); 543 544 if (!TLO.Old.getNode()->use_empty()) continue; 545 546 for (unsigned i = 0, e = TLO.Old.getNode()->getNumOperands(); 547 i != e; ++i) { 548 SDNode *OpNode = TLO.Old.getNode()->getOperand(i).getNode(); 549 if (OpNode->hasOneUse()) { 550 // Add OpNode to the end of the list to revisit. 551 DeadNodes.RemoveFromWorklist(OpNode); 552 Worklist.push_back(OpNode); 553 InWorklist.insert(OpNode); 554 } 555 } 556 557 DeadNodes.RemoveFromWorklist(TLO.Old.getNode()); 558 CurDAG->DeleteNode(TLO.Old.getNode()); 559 } 560} 561 562void SelectionDAGISel::ComputeLiveOutVRegInfo() { 563 SmallPtrSet<SDNode*, 128> VisitedNodes; 564 SmallVector<SDNode*, 128> Worklist; 565 566 Worklist.push_back(CurDAG->getRoot().getNode()); 567 568 APInt Mask; 569 APInt KnownZero; 570 APInt KnownOne; 571 572 do { 573 SDNode *N = Worklist.pop_back_val(); 574 575 // If we've already seen this node, ignore it. 576 if (!VisitedNodes.insert(N)) 577 continue; 578 579 // Otherwise, add all chain operands to the worklist. 580 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 581 if (N->getOperand(i).getValueType() == MVT::Other) 582 Worklist.push_back(N->getOperand(i).getNode()); 583 584 // If this is a CopyToReg with a vreg dest, process it. 585 if (N->getOpcode() != ISD::CopyToReg) 586 continue; 587 588 unsigned DestReg = cast<RegisterSDNode>(N->getOperand(1))->getReg(); 589 if (!TargetRegisterInfo::isVirtualRegister(DestReg)) 590 continue; 591 592 // Ignore non-scalar or non-integer values. 593 SDValue Src = N->getOperand(2); 594 EVT SrcVT = Src.getValueType(); 595 if (!SrcVT.isInteger() || SrcVT.isVector()) 596 continue; 597 598 unsigned NumSignBits = CurDAG->ComputeNumSignBits(Src); 599 Mask = APInt::getAllOnesValue(SrcVT.getSizeInBits()); 600 CurDAG->ComputeMaskedBits(Src, Mask, KnownZero, KnownOne); 601 602 // Only install this information if it tells us something. 603 if (NumSignBits != 1 || KnownZero != 0 || KnownOne != 0) { 604 DestReg -= TargetRegisterInfo::FirstVirtualRegister; 605 if (DestReg >= FuncInfo->LiveOutRegInfo.size()) 606 FuncInfo->LiveOutRegInfo.resize(DestReg+1); 607 FunctionLoweringInfo::LiveOutInfo &LOI = 608 FuncInfo->LiveOutRegInfo[DestReg]; 609 LOI.NumSignBits = NumSignBits; 610 LOI.KnownOne = KnownOne; 611 LOI.KnownZero = KnownZero; 612 } 613 } while (!Worklist.empty()); 614} 615 616void SelectionDAGISel::CodeGenAndEmitDAG() { 617 std::string GroupName; 618 if (TimePassesIsEnabled) 619 GroupName = "Instruction Selection and Scheduling"; 620 std::string BlockName; 621 if (ViewDAGCombine1 || ViewLegalizeTypesDAGs || ViewLegalizeDAGs || 622 ViewDAGCombine2 || ViewDAGCombineLT || ViewISelDAGs || ViewSchedDAGs || 623 ViewSUnitDAGs) 624 BlockName = MF->getFunction()->getNameStr() + ":" + 625 BB->getBasicBlock()->getNameStr(); 626 627 DEBUG(dbgs() << "Initial selection DAG:\n"); 628 DEBUG(CurDAG->dump()); 629 630 if (ViewDAGCombine1) CurDAG->viewGraph("dag-combine1 input for " + BlockName); 631 632 // Run the DAG combiner in pre-legalize mode. 633 if (TimePassesIsEnabled) { 634 NamedRegionTimer T("DAG Combining 1", GroupName); 635 CurDAG->Combine(Unrestricted, *AA, OptLevel); 636 } else { 637 CurDAG->Combine(Unrestricted, *AA, OptLevel); 638 } 639 640 DEBUG(dbgs() << "Optimized lowered selection DAG:\n"); 641 DEBUG(CurDAG->dump()); 642 643 // Second step, hack on the DAG until it only uses operations and types that 644 // the target supports. 645 if (ViewLegalizeTypesDAGs) CurDAG->viewGraph("legalize-types input for " + 646 BlockName); 647 648 bool Changed; 649 if (TimePassesIsEnabled) { 650 NamedRegionTimer T("Type Legalization", GroupName); 651 Changed = CurDAG->LegalizeTypes(); 652 } else { 653 Changed = CurDAG->LegalizeTypes(); 654 } 655 656 DEBUG(dbgs() << "Type-legalized selection DAG:\n"); 657 DEBUG(CurDAG->dump()); 658 659 if (Changed) { 660 if (ViewDAGCombineLT) 661 CurDAG->viewGraph("dag-combine-lt input for " + BlockName); 662 663 // Run the DAG combiner in post-type-legalize mode. 664 if (TimePassesIsEnabled) { 665 NamedRegionTimer T("DAG Combining after legalize types", GroupName); 666 CurDAG->Combine(NoIllegalTypes, *AA, OptLevel); 667 } else { 668 CurDAG->Combine(NoIllegalTypes, *AA, OptLevel); 669 } 670 671 DEBUG(dbgs() << "Optimized type-legalized selection DAG:\n"); 672 DEBUG(CurDAG->dump()); 673 } 674 675 if (TimePassesIsEnabled) { 676 NamedRegionTimer T("Vector Legalization", GroupName); 677 Changed = CurDAG->LegalizeVectors(); 678 } else { 679 Changed = CurDAG->LegalizeVectors(); 680 } 681 682 if (Changed) { 683 if (TimePassesIsEnabled) { 684 NamedRegionTimer T("Type Legalization 2", GroupName); 685 CurDAG->LegalizeTypes(); 686 } else { 687 CurDAG->LegalizeTypes(); 688 } 689 690 if (ViewDAGCombineLT) 691 CurDAG->viewGraph("dag-combine-lv input for " + BlockName); 692 693 // Run the DAG combiner in post-type-legalize mode. 694 if (TimePassesIsEnabled) { 695 NamedRegionTimer T("DAG Combining after legalize vectors", GroupName); 696 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel); 697 } else { 698 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel); 699 } 700 701 DEBUG(dbgs() << "Optimized vector-legalized selection DAG:\n"); 702 DEBUG(CurDAG->dump()); 703 } 704 705 if (ViewLegalizeDAGs) CurDAG->viewGraph("legalize input for " + BlockName); 706 707 if (TimePassesIsEnabled) { 708 NamedRegionTimer T("DAG Legalization", GroupName); 709 CurDAG->Legalize(OptLevel); 710 } else { 711 CurDAG->Legalize(OptLevel); 712 } 713 714 DEBUG(dbgs() << "Legalized selection DAG:\n"); 715 DEBUG(CurDAG->dump()); 716 717 if (ViewDAGCombine2) CurDAG->viewGraph("dag-combine2 input for " + BlockName); 718 719 // Run the DAG combiner in post-legalize mode. 720 if (TimePassesIsEnabled) { 721 NamedRegionTimer T("DAG Combining 2", GroupName); 722 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel); 723 } else { 724 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel); 725 } 726 727 DEBUG(dbgs() << "Optimized legalized selection DAG:\n"); 728 DEBUG(CurDAG->dump()); 729 730 if (OptLevel != CodeGenOpt::None) { 731 ShrinkDemandedOps(); 732 ComputeLiveOutVRegInfo(); 733 } 734 735 if (ViewISelDAGs) CurDAG->viewGraph("isel input for " + BlockName); 736 737 // Third, instruction select all of the operations to machine code, adding the 738 // code to the MachineBasicBlock. 739 if (TimePassesIsEnabled) { 740 NamedRegionTimer T("Instruction Selection", GroupName); 741 DoInstructionSelection(); 742 } else { 743 DoInstructionSelection(); 744 } 745 746 DEBUG(dbgs() << "Selected selection DAG:\n"); 747 DEBUG(CurDAG->dump()); 748 749 if (ViewSchedDAGs) CurDAG->viewGraph("scheduler input for " + BlockName); 750 751 // Schedule machine code. 752 ScheduleDAGSDNodes *Scheduler = CreateScheduler(); 753 if (TimePassesIsEnabled) { 754 NamedRegionTimer T("Instruction Scheduling", GroupName); 755 Scheduler->Run(CurDAG, BB, BB->end()); 756 } else { 757 Scheduler->Run(CurDAG, BB, BB->end()); 758 } 759 760 if (ViewSUnitDAGs) Scheduler->viewGraph(); 761 762 // Emit machine code to BB. This can change 'BB' to the last block being 763 // inserted into. 764 if (TimePassesIsEnabled) { 765 NamedRegionTimer T("Instruction Creation", GroupName); 766 BB = Scheduler->EmitSchedule(&SDB->EdgeMapping); 767 } else { 768 BB = Scheduler->EmitSchedule(&SDB->EdgeMapping); 769 } 770 771 // Free the scheduler state. 772 if (TimePassesIsEnabled) { 773 NamedRegionTimer T("Instruction Scheduling Cleanup", GroupName); 774 delete Scheduler; 775 } else { 776 delete Scheduler; 777 } 778 779 DEBUG(dbgs() << "Selected machine code:\n"); 780 DEBUG(BB->dump()); 781} 782 783void SelectionDAGISel::DoInstructionSelection() { 784 DEBUG(errs() << "===== Instruction selection begins:\n"); 785 786 PreprocessISelDAG(); 787 788 // Select target instructions for the DAG. 789 { 790 // Number all nodes with a topological order and set DAGSize. 791 DAGSize = CurDAG->AssignTopologicalOrder(); 792 793 // Create a dummy node (which is not added to allnodes), that adds 794 // a reference to the root node, preventing it from being deleted, 795 // and tracking any changes of the root. 796 HandleSDNode Dummy(CurDAG->getRoot()); 797 ISelPosition = SelectionDAG::allnodes_iterator(CurDAG->getRoot().getNode()); 798 ++ISelPosition; 799 800 // The AllNodes list is now topological-sorted. Visit the 801 // nodes by starting at the end of the list (the root of the 802 // graph) and preceding back toward the beginning (the entry 803 // node). 804 while (ISelPosition != CurDAG->allnodes_begin()) { 805 SDNode *Node = --ISelPosition; 806 // Skip dead nodes. DAGCombiner is expected to eliminate all dead nodes, 807 // but there are currently some corner cases that it misses. Also, this 808 // makes it theoretically possible to disable the DAGCombiner. 809 if (Node->use_empty()) 810 continue; 811 812 SDNode *ResNode = Select(Node); 813 814 // FIXME: This is pretty gross. 'Select' should be changed to not return 815 // anything at all and this code should be nuked with a tactical strike. 816 817 // If node should not be replaced, continue with the next one. 818 if (ResNode == Node || Node->getOpcode() == ISD::DELETED_NODE) 819 continue; 820 // Replace node. 821 if (ResNode) 822 ReplaceUses(Node, ResNode); 823 824 // If after the replacement this node is not used any more, 825 // remove this dead node. 826 if (Node->use_empty()) { // Don't delete EntryToken, etc. 827 ISelUpdater ISU(ISelPosition); 828 CurDAG->RemoveDeadNode(Node, &ISU); 829 } 830 } 831 832 CurDAG->setRoot(Dummy.getValue()); 833 } 834 DEBUG(errs() << "===== Instruction selection ends:\n"); 835 836 PostprocessISelDAG(); 837} 838 839 840void SelectionDAGISel::SelectAllBasicBlocks(Function &Fn, 841 MachineFunction &MF, 842 const TargetInstrInfo &TII) { 843 // Initialize the Fast-ISel state, if needed. 844 FastISel *FastIS = 0; 845 if (EnableFastISel) 846 FastIS = TLI.createFastISel(MF, FuncInfo->ValueMap, FuncInfo->MBBMap, 847 FuncInfo->StaticAllocaMap 848#ifndef NDEBUG 849 , FuncInfo->CatchInfoLost 850#endif 851 ); 852 853 // Iterate over all basic blocks in the function. 854 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I) { 855 BasicBlock *LLVMBB = &*I; 856 BB = FuncInfo->MBBMap[LLVMBB]; 857 858 BasicBlock::iterator const Begin = LLVMBB->begin(); 859 BasicBlock::iterator const End = LLVMBB->end(); 860 BasicBlock::iterator BI = Begin; 861 862 // Lower any arguments needed in this block if this is the entry block. 863 bool SuppressFastISel = false; 864 if (LLVMBB == &Fn.getEntryBlock()) { 865 LowerArguments(LLVMBB); 866 867 // If any of the arguments has the byval attribute, forgo 868 // fast-isel in the entry block. 869 if (FastIS) { 870 unsigned j = 1; 871 for (Function::arg_iterator I = Fn.arg_begin(), E = Fn.arg_end(); 872 I != E; ++I, ++j) 873 if (Fn.paramHasAttr(j, Attribute::ByVal)) { 874 if (EnableFastISelVerbose || EnableFastISelAbort) 875 dbgs() << "FastISel skips entry block due to byval argument\n"; 876 SuppressFastISel = true; 877 break; 878 } 879 } 880 } 881 882 if (BB->isLandingPad()) { 883 // Add a label to mark the beginning of the landing pad. Deletion of the 884 // landing pad can thus be detected via the MachineModuleInfo. 885 MCSymbol *Label = MF.getMMI().addLandingPad(BB); 886 887 const TargetInstrDesc &II = TII.get(TargetOpcode::EH_LABEL); 888 BuildMI(BB, SDB->getCurDebugLoc(), II).addSym(Label); 889 890 // Mark exception register as live in. 891 unsigned Reg = TLI.getExceptionAddressRegister(); 892 if (Reg) BB->addLiveIn(Reg); 893 894 // Mark exception selector register as live in. 895 Reg = TLI.getExceptionSelectorRegister(); 896 if (Reg) BB->addLiveIn(Reg); 897 898 // FIXME: Hack around an exception handling flaw (PR1508): the personality 899 // function and list of typeids logically belong to the invoke (or, if you 900 // like, the basic block containing the invoke), and need to be associated 901 // with it in the dwarf exception handling tables. Currently however the 902 // information is provided by an intrinsic (eh.selector) that can be moved 903 // to unexpected places by the optimizers: if the unwind edge is critical, 904 // then breaking it can result in the intrinsics being in the successor of 905 // the landing pad, not the landing pad itself. This results 906 // in exceptions not being caught because no typeids are associated with 907 // the invoke. This may not be the only way things can go wrong, but it 908 // is the only way we try to work around for the moment. 909 BranchInst *Br = dyn_cast<BranchInst>(LLVMBB->getTerminator()); 910 911 if (Br && Br->isUnconditional()) { // Critical edge? 912 BasicBlock::iterator I, E; 913 for (I = LLVMBB->begin(), E = --LLVMBB->end(); I != E; ++I) 914 if (isa<EHSelectorInst>(I)) 915 break; 916 917 if (I == E) 918 // No catch info found - try to extract some from the successor. 919 CopyCatchInfo(Br->getSuccessor(0), LLVMBB, &MF.getMMI(), *FuncInfo); 920 } 921 } 922 923 // Before doing SelectionDAG ISel, see if FastISel has been requested. 924 if (FastIS && !SuppressFastISel) { 925 // Emit code for any incoming arguments. This must happen before 926 // beginning FastISel on the entry block. 927 if (LLVMBB == &Fn.getEntryBlock()) { 928 CurDAG->setRoot(SDB->getControlRoot()); 929 CodeGenAndEmitDAG(); 930 SDB->clear(); 931 } 932 FastIS->startNewBlock(BB); 933 // Do FastISel on as many instructions as possible. 934 for (; BI != End; ++BI) { 935 // Just before the terminator instruction, insert instructions to 936 // feed PHI nodes in successor blocks. 937 if (isa<TerminatorInst>(BI)) 938 if (!HandlePHINodesInSuccessorBlocksFast(LLVMBB, FastIS)) { 939 ++NumFastIselFailures; 940 ResetDebugLoc(SDB, FastIS); 941 if (EnableFastISelVerbose || EnableFastISelAbort) { 942 dbgs() << "FastISel miss: "; 943 BI->dump(); 944 } 945 assert(!EnableFastISelAbort && 946 "FastISel didn't handle a PHI in a successor"); 947 break; 948 } 949 950 SetDebugLoc(BI, SDB, FastIS, &MF); 951 952 // Try to select the instruction with FastISel. 953 if (FastIS->SelectInstruction(BI)) { 954 ResetDebugLoc(SDB, FastIS); 955 continue; 956 } 957 958 // Clear out the debug location so that it doesn't carry over to 959 // unrelated instructions. 960 ResetDebugLoc(SDB, FastIS); 961 962 // Then handle certain instructions as single-LLVM-Instruction blocks. 963 if (isa<CallInst>(BI)) { 964 ++NumFastIselFailures; 965 if (EnableFastISelVerbose || EnableFastISelAbort) { 966 dbgs() << "FastISel missed call: "; 967 BI->dump(); 968 } 969 970 if (!BI->getType()->isVoidTy()) { 971 unsigned &R = FuncInfo->ValueMap[BI]; 972 if (!R) 973 R = FuncInfo->CreateRegForValue(BI); 974 } 975 976 bool HadTailCall = false; 977 SelectBasicBlock(LLVMBB, BI, llvm::next(BI), HadTailCall); 978 979 // If the call was emitted as a tail call, we're done with the block. 980 if (HadTailCall) { 981 BI = End; 982 break; 983 } 984 985 // If the instruction was codegen'd with multiple blocks, 986 // inform the FastISel object where to resume inserting. 987 FastIS->setCurrentBlock(BB); 988 continue; 989 } 990 991 // Otherwise, give up on FastISel for the rest of the block. 992 // For now, be a little lenient about non-branch terminators. 993 if (!isa<TerminatorInst>(BI) || isa<BranchInst>(BI)) { 994 ++NumFastIselFailures; 995 if (EnableFastISelVerbose || EnableFastISelAbort) { 996 dbgs() << "FastISel miss: "; 997 BI->dump(); 998 } 999 if (EnableFastISelAbort) 1000 // The "fast" selector couldn't handle something and bailed. 1001 // For the purpose of debugging, just abort. 1002 llvm_unreachable("FastISel didn't select the entire block"); 1003 } 1004 break; 1005 } 1006 } 1007 1008 // Run SelectionDAG instruction selection on the remainder of the block 1009 // not handled by FastISel. If FastISel is not run, this is the entire 1010 // block. 1011 if (BI != End) { 1012 bool HadTailCall; 1013 SelectBasicBlock(LLVMBB, BI, End, HadTailCall); 1014 } 1015 1016 FinishBasicBlock(); 1017 } 1018 1019 delete FastIS; 1020} 1021 1022void 1023SelectionDAGISel::FinishBasicBlock() { 1024 1025 DEBUG(dbgs() << "Target-post-processed machine code:\n"); 1026 DEBUG(BB->dump()); 1027 1028 DEBUG(dbgs() << "Total amount of phi nodes to update: " 1029 << SDB->PHINodesToUpdate.size() << "\n"); 1030 DEBUG(for (unsigned i = 0, e = SDB->PHINodesToUpdate.size(); i != e; ++i) 1031 dbgs() << "Node " << i << " : (" 1032 << SDB->PHINodesToUpdate[i].first 1033 << ", " << SDB->PHINodesToUpdate[i].second << ")\n"); 1034 1035 // Next, now that we know what the last MBB the LLVM BB expanded is, update 1036 // PHI nodes in successors. 1037 if (SDB->SwitchCases.empty() && 1038 SDB->JTCases.empty() && 1039 SDB->BitTestCases.empty()) { 1040 for (unsigned i = 0, e = SDB->PHINodesToUpdate.size(); i != e; ++i) { 1041 MachineInstr *PHI = SDB->PHINodesToUpdate[i].first; 1042 assert(PHI->isPHI() && 1043 "This is not a machine PHI node that we are updating!"); 1044 if (!BB->isSuccessor(PHI->getParent())) 1045 continue; 1046 PHI->addOperand(MachineOperand::CreateReg(SDB->PHINodesToUpdate[i].second, 1047 false)); 1048 PHI->addOperand(MachineOperand::CreateMBB(BB)); 1049 } 1050 SDB->PHINodesToUpdate.clear(); 1051 return; 1052 } 1053 1054 for (unsigned i = 0, e = SDB->BitTestCases.size(); i != e; ++i) { 1055 // Lower header first, if it wasn't already lowered 1056 if (!SDB->BitTestCases[i].Emitted) { 1057 // Set the current basic block to the mbb we wish to insert the code into 1058 BB = SDB->BitTestCases[i].Parent; 1059 SDB->setCurrentBasicBlock(BB); 1060 // Emit the code 1061 SDB->visitBitTestHeader(SDB->BitTestCases[i]); 1062 CurDAG->setRoot(SDB->getRoot()); 1063 CodeGenAndEmitDAG(); 1064 SDB->clear(); 1065 } 1066 1067 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); j != ej; ++j) { 1068 // Set the current basic block to the mbb we wish to insert the code into 1069 BB = SDB->BitTestCases[i].Cases[j].ThisBB; 1070 SDB->setCurrentBasicBlock(BB); 1071 // Emit the code 1072 if (j+1 != ej) 1073 SDB->visitBitTestCase(SDB->BitTestCases[i].Cases[j+1].ThisBB, 1074 SDB->BitTestCases[i].Reg, 1075 SDB->BitTestCases[i].Cases[j]); 1076 else 1077 SDB->visitBitTestCase(SDB->BitTestCases[i].Default, 1078 SDB->BitTestCases[i].Reg, 1079 SDB->BitTestCases[i].Cases[j]); 1080 1081 1082 CurDAG->setRoot(SDB->getRoot()); 1083 CodeGenAndEmitDAG(); 1084 SDB->clear(); 1085 } 1086 1087 // Update PHI Nodes 1088 for (unsigned pi = 0, pe = SDB->PHINodesToUpdate.size(); pi != pe; ++pi) { 1089 MachineInstr *PHI = SDB->PHINodesToUpdate[pi].first; 1090 MachineBasicBlock *PHIBB = PHI->getParent(); 1091 assert(PHI->isPHI() && 1092 "This is not a machine PHI node that we are updating!"); 1093 // This is "default" BB. We have two jumps to it. From "header" BB and 1094 // from last "case" BB. 1095 if (PHIBB == SDB->BitTestCases[i].Default) { 1096 PHI->addOperand(MachineOperand:: 1097 CreateReg(SDB->PHINodesToUpdate[pi].second, false)); 1098 PHI->addOperand(MachineOperand::CreateMBB(SDB->BitTestCases[i].Parent)); 1099 PHI->addOperand(MachineOperand:: 1100 CreateReg(SDB->PHINodesToUpdate[pi].second, false)); 1101 PHI->addOperand(MachineOperand::CreateMBB(SDB->BitTestCases[i].Cases. 1102 back().ThisBB)); 1103 } 1104 // One of "cases" BB. 1105 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); 1106 j != ej; ++j) { 1107 MachineBasicBlock* cBB = SDB->BitTestCases[i].Cases[j].ThisBB; 1108 if (cBB->isSuccessor(PHIBB)) { 1109 PHI->addOperand(MachineOperand:: 1110 CreateReg(SDB->PHINodesToUpdate[pi].second, false)); 1111 PHI->addOperand(MachineOperand::CreateMBB(cBB)); 1112 } 1113 } 1114 } 1115 } 1116 SDB->BitTestCases.clear(); 1117 1118 // If the JumpTable record is filled in, then we need to emit a jump table. 1119 // Updating the PHI nodes is tricky in this case, since we need to determine 1120 // whether the PHI is a successor of the range check MBB or the jump table MBB 1121 for (unsigned i = 0, e = SDB->JTCases.size(); i != e; ++i) { 1122 // Lower header first, if it wasn't already lowered 1123 if (!SDB->JTCases[i].first.Emitted) { 1124 // Set the current basic block to the mbb we wish to insert the code into 1125 BB = SDB->JTCases[i].first.HeaderBB; 1126 SDB->setCurrentBasicBlock(BB); 1127 // Emit the code 1128 SDB->visitJumpTableHeader(SDB->JTCases[i].second, SDB->JTCases[i].first); 1129 CurDAG->setRoot(SDB->getRoot()); 1130 CodeGenAndEmitDAG(); 1131 SDB->clear(); 1132 } 1133 1134 // Set the current basic block to the mbb we wish to insert the code into 1135 BB = SDB->JTCases[i].second.MBB; 1136 SDB->setCurrentBasicBlock(BB); 1137 // Emit the code 1138 SDB->visitJumpTable(SDB->JTCases[i].second); 1139 CurDAG->setRoot(SDB->getRoot()); 1140 CodeGenAndEmitDAG(); 1141 SDB->clear(); 1142 1143 // Update PHI Nodes 1144 for (unsigned pi = 0, pe = SDB->PHINodesToUpdate.size(); pi != pe; ++pi) { 1145 MachineInstr *PHI = SDB->PHINodesToUpdate[pi].first; 1146 MachineBasicBlock *PHIBB = PHI->getParent(); 1147 assert(PHI->isPHI() && 1148 "This is not a machine PHI node that we are updating!"); 1149 // "default" BB. We can go there only from header BB. 1150 if (PHIBB == SDB->JTCases[i].second.Default) { 1151 PHI->addOperand 1152 (MachineOperand::CreateReg(SDB->PHINodesToUpdate[pi].second, false)); 1153 PHI->addOperand 1154 (MachineOperand::CreateMBB(SDB->JTCases[i].first.HeaderBB)); 1155 } 1156 // JT BB. Just iterate over successors here 1157 if (BB->isSuccessor(PHIBB)) { 1158 PHI->addOperand 1159 (MachineOperand::CreateReg(SDB->PHINodesToUpdate[pi].second, false)); 1160 PHI->addOperand(MachineOperand::CreateMBB(BB)); 1161 } 1162 } 1163 } 1164 SDB->JTCases.clear(); 1165 1166 // If the switch block involved a branch to one of the actual successors, we 1167 // need to update PHI nodes in that block. 1168 for (unsigned i = 0, e = SDB->PHINodesToUpdate.size(); i != e; ++i) { 1169 MachineInstr *PHI = SDB->PHINodesToUpdate[i].first; 1170 assert(PHI->isPHI() && 1171 "This is not a machine PHI node that we are updating!"); 1172 if (BB->isSuccessor(PHI->getParent())) { 1173 PHI->addOperand(MachineOperand::CreateReg(SDB->PHINodesToUpdate[i].second, 1174 false)); 1175 PHI->addOperand(MachineOperand::CreateMBB(BB)); 1176 } 1177 } 1178 1179 // If we generated any switch lowering information, build and codegen any 1180 // additional DAGs necessary. 1181 for (unsigned i = 0, e = SDB->SwitchCases.size(); i != e; ++i) { 1182 // Set the current basic block to the mbb we wish to insert the code into 1183 MachineBasicBlock *ThisBB = BB = SDB->SwitchCases[i].ThisBB; 1184 SDB->setCurrentBasicBlock(BB); 1185 1186 // Emit the code 1187 SDB->visitSwitchCase(SDB->SwitchCases[i]); 1188 CurDAG->setRoot(SDB->getRoot()); 1189 CodeGenAndEmitDAG(); 1190 1191 // Handle any PHI nodes in successors of this chunk, as if we were coming 1192 // from the original BB before switch expansion. Note that PHI nodes can 1193 // occur multiple times in PHINodesToUpdate. We have to be very careful to 1194 // handle them the right number of times. 1195 while ((BB = SDB->SwitchCases[i].TrueBB)) { // Handle LHS and RHS. 1196 // If new BB's are created during scheduling, the edges may have been 1197 // updated. That is, the edge from ThisBB to BB may have been split and 1198 // BB's predecessor is now another block. 1199 DenseMap<MachineBasicBlock*, MachineBasicBlock*>::iterator EI = 1200 SDB->EdgeMapping.find(BB); 1201 if (EI != SDB->EdgeMapping.end()) 1202 ThisBB = EI->second; 1203 1204 // BB may have been removed from the CFG if a branch was constant folded. 1205 if (ThisBB->isSuccessor(BB)) { 1206 for (MachineBasicBlock::iterator Phi = BB->begin(); 1207 Phi != BB->end() && Phi->isPHI(); 1208 ++Phi) { 1209 // This value for this PHI node is recorded in PHINodesToUpdate. 1210 for (unsigned pn = 0; ; ++pn) { 1211 assert(pn != SDB->PHINodesToUpdate.size() && 1212 "Didn't find PHI entry!"); 1213 if (SDB->PHINodesToUpdate[pn].first == Phi) { 1214 Phi->addOperand(MachineOperand:: 1215 CreateReg(SDB->PHINodesToUpdate[pn].second, 1216 false)); 1217 Phi->addOperand(MachineOperand::CreateMBB(ThisBB)); 1218 break; 1219 } 1220 } 1221 } 1222 } 1223 1224 // Don't process RHS if same block as LHS. 1225 if (BB == SDB->SwitchCases[i].FalseBB) 1226 SDB->SwitchCases[i].FalseBB = 0; 1227 1228 // If we haven't handled the RHS, do so now. Otherwise, we're done. 1229 SDB->SwitchCases[i].TrueBB = SDB->SwitchCases[i].FalseBB; 1230 SDB->SwitchCases[i].FalseBB = 0; 1231 } 1232 assert(SDB->SwitchCases[i].TrueBB == 0 && SDB->SwitchCases[i].FalseBB == 0); 1233 SDB->clear(); 1234 } 1235 SDB->SwitchCases.clear(); 1236 1237 SDB->PHINodesToUpdate.clear(); 1238} 1239 1240 1241/// Create the scheduler. If a specific scheduler was specified 1242/// via the SchedulerRegistry, use it, otherwise select the 1243/// one preferred by the target. 1244/// 1245ScheduleDAGSDNodes *SelectionDAGISel::CreateScheduler() { 1246 RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault(); 1247 1248 if (!Ctor) { 1249 Ctor = ISHeuristic; 1250 RegisterScheduler::setDefault(Ctor); 1251 } 1252 1253 return Ctor(this, OptLevel); 1254} 1255 1256ScheduleHazardRecognizer *SelectionDAGISel::CreateTargetHazardRecognizer() { 1257 return new ScheduleHazardRecognizer(); 1258} 1259 1260//===----------------------------------------------------------------------===// 1261// Helper functions used by the generated instruction selector. 1262//===----------------------------------------------------------------------===// 1263// Calls to these methods are generated by tblgen. 1264 1265/// CheckAndMask - The isel is trying to match something like (and X, 255). If 1266/// the dag combiner simplified the 255, we still want to match. RHS is the 1267/// actual value in the DAG on the RHS of an AND, and DesiredMaskS is the value 1268/// specified in the .td file (e.g. 255). 1269bool SelectionDAGISel::CheckAndMask(SDValue LHS, ConstantSDNode *RHS, 1270 int64_t DesiredMaskS) const { 1271 const APInt &ActualMask = RHS->getAPIntValue(); 1272 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS); 1273 1274 // If the actual mask exactly matches, success! 1275 if (ActualMask == DesiredMask) 1276 return true; 1277 1278 // If the actual AND mask is allowing unallowed bits, this doesn't match. 1279 if (ActualMask.intersects(~DesiredMask)) 1280 return false; 1281 1282 // Otherwise, the DAG Combiner may have proven that the value coming in is 1283 // either already zero or is not demanded. Check for known zero input bits. 1284 APInt NeededMask = DesiredMask & ~ActualMask; 1285 if (CurDAG->MaskedValueIsZero(LHS, NeededMask)) 1286 return true; 1287 1288 // TODO: check to see if missing bits are just not demanded. 1289 1290 // Otherwise, this pattern doesn't match. 1291 return false; 1292} 1293 1294/// CheckOrMask - The isel is trying to match something like (or X, 255). If 1295/// the dag combiner simplified the 255, we still want to match. RHS is the 1296/// actual value in the DAG on the RHS of an OR, and DesiredMaskS is the value 1297/// specified in the .td file (e.g. 255). 1298bool SelectionDAGISel::CheckOrMask(SDValue LHS, ConstantSDNode *RHS, 1299 int64_t DesiredMaskS) const { 1300 const APInt &ActualMask = RHS->getAPIntValue(); 1301 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS); 1302 1303 // If the actual mask exactly matches, success! 1304 if (ActualMask == DesiredMask) 1305 return true; 1306 1307 // If the actual AND mask is allowing unallowed bits, this doesn't match. 1308 if (ActualMask.intersects(~DesiredMask)) 1309 return false; 1310 1311 // Otherwise, the DAG Combiner may have proven that the value coming in is 1312 // either already zero or is not demanded. Check for known zero input bits. 1313 APInt NeededMask = DesiredMask & ~ActualMask; 1314 1315 APInt KnownZero, KnownOne; 1316 CurDAG->ComputeMaskedBits(LHS, NeededMask, KnownZero, KnownOne); 1317 1318 // If all the missing bits in the or are already known to be set, match! 1319 if ((NeededMask & KnownOne) == NeededMask) 1320 return true; 1321 1322 // TODO: check to see if missing bits are just not demanded. 1323 1324 // Otherwise, this pattern doesn't match. 1325 return false; 1326} 1327 1328 1329/// SelectInlineAsmMemoryOperands - Calls to this are automatically generated 1330/// by tblgen. Others should not call it. 1331void SelectionDAGISel:: 1332SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops) { 1333 std::vector<SDValue> InOps; 1334 std::swap(InOps, Ops); 1335 1336 Ops.push_back(InOps[0]); // input chain. 1337 Ops.push_back(InOps[1]); // input asm string. 1338 1339 unsigned i = 2, e = InOps.size(); 1340 if (InOps[e-1].getValueType() == MVT::Flag) 1341 --e; // Don't process a flag operand if it is here. 1342 1343 while (i != e) { 1344 unsigned Flags = cast<ConstantSDNode>(InOps[i])->getZExtValue(); 1345 if ((Flags & 7) != 4 /*MEM*/) { 1346 // Just skip over this operand, copying the operands verbatim. 1347 Ops.insert(Ops.end(), InOps.begin()+i, 1348 InOps.begin()+i+InlineAsm::getNumOperandRegisters(Flags) + 1); 1349 i += InlineAsm::getNumOperandRegisters(Flags) + 1; 1350 } else { 1351 assert(InlineAsm::getNumOperandRegisters(Flags) == 1 && 1352 "Memory operand with multiple values?"); 1353 // Otherwise, this is a memory operand. Ask the target to select it. 1354 std::vector<SDValue> SelOps; 1355 if (SelectInlineAsmMemoryOperand(InOps[i+1], 'm', SelOps)) { 1356 llvm_report_error("Could not match memory address. Inline asm" 1357 " failure!"); 1358 } 1359 1360 // Add this to the output node. 1361 Ops.push_back(CurDAG->getTargetConstant(4/*MEM*/ | (SelOps.size()<< 3), 1362 MVT::i32)); 1363 Ops.insert(Ops.end(), SelOps.begin(), SelOps.end()); 1364 i += 2; 1365 } 1366 } 1367 1368 // Add the flag input back if present. 1369 if (e != InOps.size()) 1370 Ops.push_back(InOps.back()); 1371} 1372 1373/// findFlagUse - Return use of EVT::Flag value produced by the specified 1374/// SDNode. 1375/// 1376static SDNode *findFlagUse(SDNode *N) { 1377 unsigned FlagResNo = N->getNumValues()-1; 1378 for (SDNode::use_iterator I = N->use_begin(), E = N->use_end(); I != E; ++I) { 1379 SDUse &Use = I.getUse(); 1380 if (Use.getResNo() == FlagResNo) 1381 return Use.getUser(); 1382 } 1383 return NULL; 1384} 1385 1386/// findNonImmUse - Return true if "Use" is a non-immediate use of "Def". 1387/// This function recursively traverses up the operand chain, ignoring 1388/// certain nodes. 1389static bool findNonImmUse(SDNode *Use, SDNode* Def, SDNode *ImmedUse, 1390 SDNode *Root, SmallPtrSet<SDNode*, 16> &Visited, 1391 bool IgnoreChains) { 1392 // The NodeID's are given uniques ID's where a node ID is guaranteed to be 1393 // greater than all of its (recursive) operands. If we scan to a point where 1394 // 'use' is smaller than the node we're scanning for, then we know we will 1395 // never find it. 1396 // 1397 // The Use may be -1 (unassigned) if it is a newly allocated node. This can 1398 // happen because we scan down to newly selected nodes in the case of flag 1399 // uses. 1400 if ((Use->getNodeId() < Def->getNodeId() && Use->getNodeId() != -1)) 1401 return false; 1402 1403 // Don't revisit nodes if we already scanned it and didn't fail, we know we 1404 // won't fail if we scan it again. 1405 if (!Visited.insert(Use)) 1406 return false; 1407 1408 for (unsigned i = 0, e = Use->getNumOperands(); i != e; ++i) { 1409 // Ignore chain uses, they are validated by HandleMergeInputChains. 1410 if (Use->getOperand(i).getValueType() == MVT::Other && IgnoreChains) 1411 continue; 1412 1413 SDNode *N = Use->getOperand(i).getNode(); 1414 if (N == Def) { 1415 if (Use == ImmedUse || Use == Root) 1416 continue; // We are not looking for immediate use. 1417 assert(N != Root); 1418 return true; 1419 } 1420 1421 // Traverse up the operand chain. 1422 if (findNonImmUse(N, Def, ImmedUse, Root, Visited, IgnoreChains)) 1423 return true; 1424 } 1425 return false; 1426} 1427 1428/// IsProfitableToFold - Returns true if it's profitable to fold the specific 1429/// operand node N of U during instruction selection that starts at Root. 1430bool SelectionDAGISel::IsProfitableToFold(SDValue N, SDNode *U, 1431 SDNode *Root) const { 1432 if (OptLevel == CodeGenOpt::None) return false; 1433 return N.hasOneUse(); 1434} 1435 1436/// IsLegalToFold - Returns true if the specific operand node N of 1437/// U can be folded during instruction selection that starts at Root. 1438bool SelectionDAGISel::IsLegalToFold(SDValue N, SDNode *U, SDNode *Root, 1439 bool IgnoreChains) const { 1440 if (OptLevel == CodeGenOpt::None) return false; 1441 1442 // If Root use can somehow reach N through a path that that doesn't contain 1443 // U then folding N would create a cycle. e.g. In the following 1444 // diagram, Root can reach N through X. If N is folded into into Root, then 1445 // X is both a predecessor and a successor of U. 1446 // 1447 // [N*] // 1448 // ^ ^ // 1449 // / \ // 1450 // [U*] [X]? // 1451 // ^ ^ // 1452 // \ / // 1453 // \ / // 1454 // [Root*] // 1455 // 1456 // * indicates nodes to be folded together. 1457 // 1458 // If Root produces a flag, then it gets (even more) interesting. Since it 1459 // will be "glued" together with its flag use in the scheduler, we need to 1460 // check if it might reach N. 1461 // 1462 // [N*] // 1463 // ^ ^ // 1464 // / \ // 1465 // [U*] [X]? // 1466 // ^ ^ // 1467 // \ \ // 1468 // \ | // 1469 // [Root*] | // 1470 // ^ | // 1471 // f | // 1472 // | / // 1473 // [Y] / // 1474 // ^ / // 1475 // f / // 1476 // | / // 1477 // [FU] // 1478 // 1479 // If FU (flag use) indirectly reaches N (the load), and Root folds N 1480 // (call it Fold), then X is a predecessor of FU and a successor of 1481 // Fold. But since Fold and FU are flagged together, this will create 1482 // a cycle in the scheduling graph. 1483 1484 // If the node has flags, walk down the graph to the "lowest" node in the 1485 // flagged set. 1486 EVT VT = Root->getValueType(Root->getNumValues()-1); 1487 while (VT == MVT::Flag) { 1488 SDNode *FU = findFlagUse(Root); 1489 if (FU == NULL) 1490 break; 1491 Root = FU; 1492 VT = Root->getValueType(Root->getNumValues()-1); 1493 1494 // If our query node has a flag result with a use, we've walked up it. If 1495 // the user (which has already been selected) has a chain or indirectly uses 1496 // the chain, our WalkChainUsers predicate will not consider it. Because of 1497 // this, we cannot ignore chains in this predicate. 1498 IgnoreChains = false; 1499 } 1500 1501 1502 SmallPtrSet<SDNode*, 16> Visited; 1503 return !findNonImmUse(Root, N.getNode(), U, Root, Visited, IgnoreChains); 1504} 1505 1506SDNode *SelectionDAGISel::Select_INLINEASM(SDNode *N) { 1507 std::vector<SDValue> Ops(N->op_begin(), N->op_end()); 1508 SelectInlineAsmMemoryOperands(Ops); 1509 1510 std::vector<EVT> VTs; 1511 VTs.push_back(MVT::Other); 1512 VTs.push_back(MVT::Flag); 1513 SDValue New = CurDAG->getNode(ISD::INLINEASM, N->getDebugLoc(), 1514 VTs, &Ops[0], Ops.size()); 1515 New->setNodeId(-1); 1516 return New.getNode(); 1517} 1518 1519SDNode *SelectionDAGISel::Select_UNDEF(SDNode *N) { 1520 return CurDAG->SelectNodeTo(N, TargetOpcode::IMPLICIT_DEF,N->getValueType(0)); 1521} 1522 1523/// GetVBR - decode a vbr encoding whose top bit is set. 1524ALWAYS_INLINE static uint64_t 1525GetVBR(uint64_t Val, const unsigned char *MatcherTable, unsigned &Idx) { 1526 assert(Val >= 128 && "Not a VBR"); 1527 Val &= 127; // Remove first vbr bit. 1528 1529 unsigned Shift = 7; 1530 uint64_t NextBits; 1531 do { 1532 NextBits = MatcherTable[Idx++]; 1533 Val |= (NextBits&127) << Shift; 1534 Shift += 7; 1535 } while (NextBits & 128); 1536 1537 return Val; 1538} 1539 1540 1541/// UpdateChainsAndFlags - When a match is complete, this method updates uses of 1542/// interior flag and chain results to use the new flag and chain results. 1543void SelectionDAGISel:: 1544UpdateChainsAndFlags(SDNode *NodeToMatch, SDValue InputChain, 1545 const SmallVectorImpl<SDNode*> &ChainNodesMatched, 1546 SDValue InputFlag, 1547 const SmallVectorImpl<SDNode*> &FlagResultNodesMatched, 1548 bool isMorphNodeTo) { 1549 SmallVector<SDNode*, 4> NowDeadNodes; 1550 1551 ISelUpdater ISU(ISelPosition); 1552 1553 // Now that all the normal results are replaced, we replace the chain and 1554 // flag results if present. 1555 if (!ChainNodesMatched.empty()) { 1556 assert(InputChain.getNode() != 0 && 1557 "Matched input chains but didn't produce a chain"); 1558 // Loop over all of the nodes we matched that produced a chain result. 1559 // Replace all the chain results with the final chain we ended up with. 1560 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) { 1561 SDNode *ChainNode = ChainNodesMatched[i]; 1562 1563 // If this node was already deleted, don't look at it. 1564 if (ChainNode->getOpcode() == ISD::DELETED_NODE) 1565 continue; 1566 1567 // Don't replace the results of the root node if we're doing a 1568 // MorphNodeTo. 1569 if (ChainNode == NodeToMatch && isMorphNodeTo) 1570 continue; 1571 1572 SDValue ChainVal = SDValue(ChainNode, ChainNode->getNumValues()-1); 1573 if (ChainVal.getValueType() == MVT::Flag) 1574 ChainVal = ChainVal.getValue(ChainVal->getNumValues()-2); 1575 assert(ChainVal.getValueType() == MVT::Other && "Not a chain?"); 1576 CurDAG->ReplaceAllUsesOfValueWith(ChainVal, InputChain, &ISU); 1577 1578 // If the node became dead and we haven't already seen it, delete it. 1579 if (ChainNode->use_empty() && 1580 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), ChainNode)) 1581 NowDeadNodes.push_back(ChainNode); 1582 } 1583 } 1584 1585 // If the result produces a flag, update any flag results in the matched 1586 // pattern with the flag result. 1587 if (InputFlag.getNode() != 0) { 1588 // Handle any interior nodes explicitly marked. 1589 for (unsigned i = 0, e = FlagResultNodesMatched.size(); i != e; ++i) { 1590 SDNode *FRN = FlagResultNodesMatched[i]; 1591 1592 // If this node was already deleted, don't look at it. 1593 if (FRN->getOpcode() == ISD::DELETED_NODE) 1594 continue; 1595 1596 assert(FRN->getValueType(FRN->getNumValues()-1) == MVT::Flag && 1597 "Doesn't have a flag result"); 1598 CurDAG->ReplaceAllUsesOfValueWith(SDValue(FRN, FRN->getNumValues()-1), 1599 InputFlag, &ISU); 1600 1601 // If the node became dead and we haven't already seen it, delete it. 1602 if (FRN->use_empty() && 1603 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), FRN)) 1604 NowDeadNodes.push_back(FRN); 1605 } 1606 } 1607 1608 if (!NowDeadNodes.empty()) 1609 CurDAG->RemoveDeadNodes(NowDeadNodes, &ISU); 1610 1611 DEBUG(errs() << "ISEL: Match complete!\n"); 1612} 1613 1614enum ChainResult { 1615 CR_Simple, 1616 CR_InducesCycle, 1617 CR_LeadsToInteriorNode 1618}; 1619 1620/// WalkChainUsers - Walk down the users of the specified chained node that is 1621/// part of the pattern we're matching, looking at all of the users we find. 1622/// This determines whether something is an interior node, whether we have a 1623/// non-pattern node in between two pattern nodes (which prevent folding because 1624/// it would induce a cycle) and whether we have a TokenFactor node sandwiched 1625/// between pattern nodes (in which case the TF becomes part of the pattern). 1626/// 1627/// The walk we do here is guaranteed to be small because we quickly get down to 1628/// already selected nodes "below" us. 1629static ChainResult 1630WalkChainUsers(SDNode *ChainedNode, 1631 SmallVectorImpl<SDNode*> &ChainedNodesInPattern, 1632 SmallVectorImpl<SDNode*> &InteriorChainedNodes) { 1633 ChainResult Result = CR_Simple; 1634 1635 for (SDNode::use_iterator UI = ChainedNode->use_begin(), 1636 E = ChainedNode->use_end(); UI != E; ++UI) { 1637 // Make sure the use is of the chain, not some other value we produce. 1638 if (UI.getUse().getValueType() != MVT::Other) continue; 1639 1640 SDNode *User = *UI; 1641 1642 // If we see an already-selected machine node, then we've gone beyond the 1643 // pattern that we're selecting down into the already selected chunk of the 1644 // DAG. 1645 if (User->isMachineOpcode() || 1646 User->getOpcode() == ISD::HANDLENODE) // Root of the graph. 1647 continue; 1648 1649 if (User->getOpcode() == ISD::CopyToReg || 1650 User->getOpcode() == ISD::CopyFromReg || 1651 User->getOpcode() == ISD::INLINEASM || 1652 User->getOpcode() == ISD::EH_LABEL) { 1653 // If their node ID got reset to -1 then they've already been selected. 1654 // Treat them like a MachineOpcode. 1655 if (User->getNodeId() == -1) 1656 continue; 1657 } 1658 1659 // If we have a TokenFactor, we handle it specially. 1660 if (User->getOpcode() != ISD::TokenFactor) { 1661 // If the node isn't a token factor and isn't part of our pattern, then it 1662 // must be a random chained node in between two nodes we're selecting. 1663 // This happens when we have something like: 1664 // x = load ptr 1665 // call 1666 // y = x+4 1667 // store y -> ptr 1668 // Because we structurally match the load/store as a read/modify/write, 1669 // but the call is chained between them. We cannot fold in this case 1670 // because it would induce a cycle in the graph. 1671 if (!std::count(ChainedNodesInPattern.begin(), 1672 ChainedNodesInPattern.end(), User)) 1673 return CR_InducesCycle; 1674 1675 // Otherwise we found a node that is part of our pattern. For example in: 1676 // x = load ptr 1677 // y = x+4 1678 // store y -> ptr 1679 // This would happen when we're scanning down from the load and see the 1680 // store as a user. Record that there is a use of ChainedNode that is 1681 // part of the pattern and keep scanning uses. 1682 Result = CR_LeadsToInteriorNode; 1683 InteriorChainedNodes.push_back(User); 1684 continue; 1685 } 1686 1687 // If we found a TokenFactor, there are two cases to consider: first if the 1688 // TokenFactor is just hanging "below" the pattern we're matching (i.e. no 1689 // uses of the TF are in our pattern) we just want to ignore it. Second, 1690 // the TokenFactor can be sandwiched in between two chained nodes, like so: 1691 // [Load chain] 1692 // ^ 1693 // | 1694 // [Load] 1695 // ^ ^ 1696 // | \ DAG's like cheese 1697 // / \ do you? 1698 // / | 1699 // [TokenFactor] [Op] 1700 // ^ ^ 1701 // | | 1702 // \ / 1703 // \ / 1704 // [Store] 1705 // 1706 // In this case, the TokenFactor becomes part of our match and we rewrite it 1707 // as a new TokenFactor. 1708 // 1709 // To distinguish these two cases, do a recursive walk down the uses. 1710 switch (WalkChainUsers(User, ChainedNodesInPattern, InteriorChainedNodes)) { 1711 case CR_Simple: 1712 // If the uses of the TokenFactor are just already-selected nodes, ignore 1713 // it, it is "below" our pattern. 1714 continue; 1715 case CR_InducesCycle: 1716 // If the uses of the TokenFactor lead to nodes that are not part of our 1717 // pattern that are not selected, folding would turn this into a cycle, 1718 // bail out now. 1719 return CR_InducesCycle; 1720 case CR_LeadsToInteriorNode: 1721 break; // Otherwise, keep processing. 1722 } 1723 1724 // Okay, we know we're in the interesting interior case. The TokenFactor 1725 // is now going to be considered part of the pattern so that we rewrite its 1726 // uses (it may have uses that are not part of the pattern) with the 1727 // ultimate chain result of the generated code. We will also add its chain 1728 // inputs as inputs to the ultimate TokenFactor we create. 1729 Result = CR_LeadsToInteriorNode; 1730 ChainedNodesInPattern.push_back(User); 1731 InteriorChainedNodes.push_back(User); 1732 continue; 1733 } 1734 1735 return Result; 1736} 1737 1738/// HandleMergeInputChains - This implements the OPC_EmitMergeInputChains 1739/// operation for when the pattern matched at least one node with a chains. The 1740/// input vector contains a list of all of the chained nodes that we match. We 1741/// must determine if this is a valid thing to cover (i.e. matching it won't 1742/// induce cycles in the DAG) and if so, creating a TokenFactor node. that will 1743/// be used as the input node chain for the generated nodes. 1744static SDValue 1745HandleMergeInputChains(SmallVectorImpl<SDNode*> &ChainNodesMatched, 1746 SelectionDAG *CurDAG) { 1747 // Walk all of the chained nodes we've matched, recursively scanning down the 1748 // users of the chain result. This adds any TokenFactor nodes that are caught 1749 // in between chained nodes to the chained and interior nodes list. 1750 SmallVector<SDNode*, 3> InteriorChainedNodes; 1751 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) { 1752 if (WalkChainUsers(ChainNodesMatched[i], ChainNodesMatched, 1753 InteriorChainedNodes) == CR_InducesCycle) 1754 return SDValue(); // Would induce a cycle. 1755 } 1756 1757 // Okay, we have walked all the matched nodes and collected TokenFactor nodes 1758 // that we are interested in. Form our input TokenFactor node. 1759 SmallVector<SDValue, 3> InputChains; 1760 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) { 1761 // Add the input chain of this node to the InputChains list (which will be 1762 // the operands of the generated TokenFactor) if it's not an interior node. 1763 SDNode *N = ChainNodesMatched[i]; 1764 if (N->getOpcode() != ISD::TokenFactor) { 1765 if (std::count(InteriorChainedNodes.begin(),InteriorChainedNodes.end(),N)) 1766 continue; 1767 1768 // Otherwise, add the input chain. 1769 SDValue InChain = ChainNodesMatched[i]->getOperand(0); 1770 assert(InChain.getValueType() == MVT::Other && "Not a chain"); 1771 InputChains.push_back(InChain); 1772 continue; 1773 } 1774 1775 // If we have a token factor, we want to add all inputs of the token factor 1776 // that are not part of the pattern we're matching. 1777 for (unsigned op = 0, e = N->getNumOperands(); op != e; ++op) { 1778 if (!std::count(ChainNodesMatched.begin(), ChainNodesMatched.end(), 1779 N->getOperand(op).getNode())) 1780 InputChains.push_back(N->getOperand(op)); 1781 } 1782 } 1783 1784 SDValue Res; 1785 if (InputChains.size() == 1) 1786 return InputChains[0]; 1787 return CurDAG->getNode(ISD::TokenFactor, ChainNodesMatched[0]->getDebugLoc(), 1788 MVT::Other, &InputChains[0], InputChains.size()); 1789} 1790 1791/// MorphNode - Handle morphing a node in place for the selector. 1792SDNode *SelectionDAGISel:: 1793MorphNode(SDNode *Node, unsigned TargetOpc, SDVTList VTList, 1794 const SDValue *Ops, unsigned NumOps, unsigned EmitNodeInfo) { 1795 // It is possible we're using MorphNodeTo to replace a node with no 1796 // normal results with one that has a normal result (or we could be 1797 // adding a chain) and the input could have flags and chains as well. 1798 // In this case we need to shift the operands down. 1799 // FIXME: This is a horrible hack and broken in obscure cases, no worse 1800 // than the old isel though. 1801 int OldFlagResultNo = -1, OldChainResultNo = -1; 1802 1803 unsigned NTMNumResults = Node->getNumValues(); 1804 if (Node->getValueType(NTMNumResults-1) == MVT::Flag) { 1805 OldFlagResultNo = NTMNumResults-1; 1806 if (NTMNumResults != 1 && 1807 Node->getValueType(NTMNumResults-2) == MVT::Other) 1808 OldChainResultNo = NTMNumResults-2; 1809 } else if (Node->getValueType(NTMNumResults-1) == MVT::Other) 1810 OldChainResultNo = NTMNumResults-1; 1811 1812 // Call the underlying SelectionDAG routine to do the transmogrification. Note 1813 // that this deletes operands of the old node that become dead. 1814 SDNode *Res = CurDAG->MorphNodeTo(Node, ~TargetOpc, VTList, Ops, NumOps); 1815 1816 // MorphNodeTo can operate in two ways: if an existing node with the 1817 // specified operands exists, it can just return it. Otherwise, it 1818 // updates the node in place to have the requested operands. 1819 if (Res == Node) { 1820 // If we updated the node in place, reset the node ID. To the isel, 1821 // this should be just like a newly allocated machine node. 1822 Res->setNodeId(-1); 1823 } 1824 1825 unsigned ResNumResults = Res->getNumValues(); 1826 // Move the flag if needed. 1827 if ((EmitNodeInfo & OPFL_FlagOutput) && OldFlagResultNo != -1 && 1828 (unsigned)OldFlagResultNo != ResNumResults-1) 1829 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldFlagResultNo), 1830 SDValue(Res, ResNumResults-1)); 1831 1832 if ((EmitNodeInfo & OPFL_FlagOutput) != 0) 1833 --ResNumResults; 1834 1835 // Move the chain reference if needed. 1836 if ((EmitNodeInfo & OPFL_Chain) && OldChainResultNo != -1 && 1837 (unsigned)OldChainResultNo != ResNumResults-1) 1838 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldChainResultNo), 1839 SDValue(Res, ResNumResults-1)); 1840 1841 // Otherwise, no replacement happened because the node already exists. Replace 1842 // Uses of the old node with the new one. 1843 if (Res != Node) 1844 CurDAG->ReplaceAllUsesWith(Node, Res); 1845 1846 return Res; 1847} 1848 1849/// CheckPatternPredicate - Implements OP_CheckPatternPredicate. 1850ALWAYS_INLINE static bool 1851CheckSame(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1852 SDValue N, const SmallVectorImpl<SDValue> &RecordedNodes) { 1853 // Accept if it is exactly the same as a previously recorded node. 1854 unsigned RecNo = MatcherTable[MatcherIndex++]; 1855 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 1856 return N == RecordedNodes[RecNo]; 1857} 1858 1859/// CheckPatternPredicate - Implements OP_CheckPatternPredicate. 1860ALWAYS_INLINE static bool 1861CheckPatternPredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1862 SelectionDAGISel &SDISel) { 1863 return SDISel.CheckPatternPredicate(MatcherTable[MatcherIndex++]); 1864} 1865 1866/// CheckNodePredicate - Implements OP_CheckNodePredicate. 1867ALWAYS_INLINE static bool 1868CheckNodePredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1869 SelectionDAGISel &SDISel, SDNode *N) { 1870 return SDISel.CheckNodePredicate(N, MatcherTable[MatcherIndex++]); 1871} 1872 1873ALWAYS_INLINE static bool 1874CheckOpcode(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1875 SDNode *N) { 1876 uint16_t Opc = MatcherTable[MatcherIndex++]; 1877 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8; 1878 return N->getOpcode() == Opc; 1879} 1880 1881ALWAYS_INLINE static bool 1882CheckType(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1883 SDValue N, const TargetLowering &TLI) { 1884 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 1885 if (N.getValueType() == VT) return true; 1886 1887 // Handle the case when VT is iPTR. 1888 return VT == MVT::iPTR && N.getValueType() == TLI.getPointerTy(); 1889} 1890 1891ALWAYS_INLINE static bool 1892CheckChildType(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1893 SDValue N, const TargetLowering &TLI, 1894 unsigned ChildNo) { 1895 if (ChildNo >= N.getNumOperands()) 1896 return false; // Match fails if out of range child #. 1897 return ::CheckType(MatcherTable, MatcherIndex, N.getOperand(ChildNo), TLI); 1898} 1899 1900 1901ALWAYS_INLINE static bool 1902CheckCondCode(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1903 SDValue N) { 1904 return cast<CondCodeSDNode>(N)->get() == 1905 (ISD::CondCode)MatcherTable[MatcherIndex++]; 1906} 1907 1908ALWAYS_INLINE static bool 1909CheckValueType(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1910 SDValue N, const TargetLowering &TLI) { 1911 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 1912 if (cast<VTSDNode>(N)->getVT() == VT) 1913 return true; 1914 1915 // Handle the case when VT is iPTR. 1916 return VT == MVT::iPTR && cast<VTSDNode>(N)->getVT() == TLI.getPointerTy(); 1917} 1918 1919ALWAYS_INLINE static bool 1920CheckInteger(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1921 SDValue N) { 1922 int64_t Val = MatcherTable[MatcherIndex++]; 1923 if (Val & 128) 1924 Val = GetVBR(Val, MatcherTable, MatcherIndex); 1925 1926 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N); 1927 return C != 0 && C->getSExtValue() == Val; 1928} 1929 1930ALWAYS_INLINE static bool 1931CheckAndImm(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1932 SDValue N, SelectionDAGISel &SDISel) { 1933 int64_t Val = MatcherTable[MatcherIndex++]; 1934 if (Val & 128) 1935 Val = GetVBR(Val, MatcherTable, MatcherIndex); 1936 1937 if (N->getOpcode() != ISD::AND) return false; 1938 1939 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1)); 1940 return C != 0 && SDISel.CheckAndMask(N.getOperand(0), C, Val); 1941} 1942 1943ALWAYS_INLINE static bool 1944CheckOrImm(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1945 SDValue N, SelectionDAGISel &SDISel) { 1946 int64_t Val = MatcherTable[MatcherIndex++]; 1947 if (Val & 128) 1948 Val = GetVBR(Val, MatcherTable, MatcherIndex); 1949 1950 if (N->getOpcode() != ISD::OR) return false; 1951 1952 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1)); 1953 return C != 0 && SDISel.CheckOrMask(N.getOperand(0), C, Val); 1954} 1955 1956/// IsPredicateKnownToFail - If we know how and can do so without pushing a 1957/// scope, evaluate the current node. If the current predicate is known to 1958/// fail, set Result=true and return anything. If the current predicate is 1959/// known to pass, set Result=false and return the MatcherIndex to continue 1960/// with. If the current predicate is unknown, set Result=false and return the 1961/// MatcherIndex to continue with. 1962static unsigned IsPredicateKnownToFail(const unsigned char *Table, 1963 unsigned Index, SDValue N, 1964 bool &Result, SelectionDAGISel &SDISel, 1965 SmallVectorImpl<SDValue> &RecordedNodes){ 1966 switch (Table[Index++]) { 1967 default: 1968 Result = false; 1969 return Index-1; // Could not evaluate this predicate. 1970 case SelectionDAGISel::OPC_CheckSame: 1971 Result = !::CheckSame(Table, Index, N, RecordedNodes); 1972 return Index; 1973 case SelectionDAGISel::OPC_CheckPatternPredicate: 1974 Result = !::CheckPatternPredicate(Table, Index, SDISel); 1975 return Index; 1976 case SelectionDAGISel::OPC_CheckPredicate: 1977 Result = !::CheckNodePredicate(Table, Index, SDISel, N.getNode()); 1978 return Index; 1979 case SelectionDAGISel::OPC_CheckOpcode: 1980 Result = !::CheckOpcode(Table, Index, N.getNode()); 1981 return Index; 1982 case SelectionDAGISel::OPC_CheckType: 1983 Result = !::CheckType(Table, Index, N, SDISel.TLI); 1984 return Index; 1985 case SelectionDAGISel::OPC_CheckChild0Type: 1986 case SelectionDAGISel::OPC_CheckChild1Type: 1987 case SelectionDAGISel::OPC_CheckChild2Type: 1988 case SelectionDAGISel::OPC_CheckChild3Type: 1989 case SelectionDAGISel::OPC_CheckChild4Type: 1990 case SelectionDAGISel::OPC_CheckChild5Type: 1991 case SelectionDAGISel::OPC_CheckChild6Type: 1992 case SelectionDAGISel::OPC_CheckChild7Type: 1993 Result = !::CheckChildType(Table, Index, N, SDISel.TLI, 1994 Table[Index-1] - SelectionDAGISel::OPC_CheckChild0Type); 1995 return Index; 1996 case SelectionDAGISel::OPC_CheckCondCode: 1997 Result = !::CheckCondCode(Table, Index, N); 1998 return Index; 1999 case SelectionDAGISel::OPC_CheckValueType: 2000 Result = !::CheckValueType(Table, Index, N, SDISel.TLI); 2001 return Index; 2002 case SelectionDAGISel::OPC_CheckInteger: 2003 Result = !::CheckInteger(Table, Index, N); 2004 return Index; 2005 case SelectionDAGISel::OPC_CheckAndImm: 2006 Result = !::CheckAndImm(Table, Index, N, SDISel); 2007 return Index; 2008 case SelectionDAGISel::OPC_CheckOrImm: 2009 Result = !::CheckOrImm(Table, Index, N, SDISel); 2010 return Index; 2011 } 2012} 2013 2014 2015struct MatchScope { 2016 /// FailIndex - If this match fails, this is the index to continue with. 2017 unsigned FailIndex; 2018 2019 /// NodeStack - The node stack when the scope was formed. 2020 SmallVector<SDValue, 4> NodeStack; 2021 2022 /// NumRecordedNodes - The number of recorded nodes when the scope was formed. 2023 unsigned NumRecordedNodes; 2024 2025 /// NumMatchedMemRefs - The number of matched memref entries. 2026 unsigned NumMatchedMemRefs; 2027 2028 /// InputChain/InputFlag - The current chain/flag 2029 SDValue InputChain, InputFlag; 2030 2031 /// HasChainNodesMatched - True if the ChainNodesMatched list is non-empty. 2032 bool HasChainNodesMatched, HasFlagResultNodesMatched; 2033}; 2034 2035SDNode *SelectionDAGISel:: 2036SelectCodeCommon(SDNode *NodeToMatch, const unsigned char *MatcherTable, 2037 unsigned TableSize) { 2038 // FIXME: Should these even be selected? Handle these cases in the caller? 2039 switch (NodeToMatch->getOpcode()) { 2040 default: 2041 break; 2042 case ISD::EntryToken: // These nodes remain the same. 2043 case ISD::BasicBlock: 2044 case ISD::Register: 2045 //case ISD::VALUETYPE: 2046 //case ISD::CONDCODE: 2047 case ISD::HANDLENODE: 2048 case ISD::TargetConstant: 2049 case ISD::TargetConstantFP: 2050 case ISD::TargetConstantPool: 2051 case ISD::TargetFrameIndex: 2052 case ISD::TargetExternalSymbol: 2053 case ISD::TargetBlockAddress: 2054 case ISD::TargetJumpTable: 2055 case ISD::TargetGlobalTLSAddress: 2056 case ISD::TargetGlobalAddress: 2057 case ISD::TokenFactor: 2058 case ISD::CopyFromReg: 2059 case ISD::CopyToReg: 2060 case ISD::EH_LABEL: 2061 NodeToMatch->setNodeId(-1); // Mark selected. 2062 return 0; 2063 case ISD::AssertSext: 2064 case ISD::AssertZext: 2065 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, 0), 2066 NodeToMatch->getOperand(0)); 2067 return 0; 2068 case ISD::INLINEASM: return Select_INLINEASM(NodeToMatch); 2069 case ISD::UNDEF: return Select_UNDEF(NodeToMatch); 2070 } 2071 2072 assert(!NodeToMatch->isMachineOpcode() && "Node already selected!"); 2073 2074 // Set up the node stack with NodeToMatch as the only node on the stack. 2075 SmallVector<SDValue, 8> NodeStack; 2076 SDValue N = SDValue(NodeToMatch, 0); 2077 NodeStack.push_back(N); 2078 2079 // MatchScopes - Scopes used when matching, if a match failure happens, this 2080 // indicates where to continue checking. 2081 SmallVector<MatchScope, 8> MatchScopes; 2082 2083 // RecordedNodes - This is the set of nodes that have been recorded by the 2084 // state machine. 2085 SmallVector<SDValue, 8> RecordedNodes; 2086 2087 // MatchedMemRefs - This is the set of MemRef's we've seen in the input 2088 // pattern. 2089 SmallVector<MachineMemOperand*, 2> MatchedMemRefs; 2090 2091 // These are the current input chain and flag for use when generating nodes. 2092 // Various Emit operations change these. For example, emitting a copytoreg 2093 // uses and updates these. 2094 SDValue InputChain, InputFlag; 2095 2096 // ChainNodesMatched - If a pattern matches nodes that have input/output 2097 // chains, the OPC_EmitMergeInputChains operation is emitted which indicates 2098 // which ones they are. The result is captured into this list so that we can 2099 // update the chain results when the pattern is complete. 2100 SmallVector<SDNode*, 3> ChainNodesMatched; 2101 SmallVector<SDNode*, 3> FlagResultNodesMatched; 2102 2103 DEBUG(errs() << "ISEL: Starting pattern match on root node: "; 2104 NodeToMatch->dump(CurDAG); 2105 errs() << '\n'); 2106 2107 // Determine where to start the interpreter. Normally we start at opcode #0, 2108 // but if the state machine starts with an OPC_SwitchOpcode, then we 2109 // accelerate the first lookup (which is guaranteed to be hot) with the 2110 // OpcodeOffset table. 2111 unsigned MatcherIndex = 0; 2112 2113 if (!OpcodeOffset.empty()) { 2114 // Already computed the OpcodeOffset table, just index into it. 2115 if (N.getOpcode() < OpcodeOffset.size()) 2116 MatcherIndex = OpcodeOffset[N.getOpcode()]; 2117 DEBUG(errs() << " Initial Opcode index to " << MatcherIndex << "\n"); 2118 2119 } else if (MatcherTable[0] == OPC_SwitchOpcode) { 2120 // Otherwise, the table isn't computed, but the state machine does start 2121 // with an OPC_SwitchOpcode instruction. Populate the table now, since this 2122 // is the first time we're selecting an instruction. 2123 unsigned Idx = 1; 2124 while (1) { 2125 // Get the size of this case. 2126 unsigned CaseSize = MatcherTable[Idx++]; 2127 if (CaseSize & 128) 2128 CaseSize = GetVBR(CaseSize, MatcherTable, Idx); 2129 if (CaseSize == 0) break; 2130 2131 // Get the opcode, add the index to the table. 2132 uint16_t Opc = MatcherTable[Idx++]; 2133 Opc |= (unsigned short)MatcherTable[Idx++] << 8; 2134 if (Opc >= OpcodeOffset.size()) 2135 OpcodeOffset.resize((Opc+1)*2); 2136 OpcodeOffset[Opc] = Idx; 2137 Idx += CaseSize; 2138 } 2139 2140 // Okay, do the lookup for the first opcode. 2141 if (N.getOpcode() < OpcodeOffset.size()) 2142 MatcherIndex = OpcodeOffset[N.getOpcode()]; 2143 } 2144 2145 while (1) { 2146 assert(MatcherIndex < TableSize && "Invalid index"); 2147#ifndef NDEBUG 2148 unsigned CurrentOpcodeIndex = MatcherIndex; 2149#endif 2150 BuiltinOpcodes Opcode = (BuiltinOpcodes)MatcherTable[MatcherIndex++]; 2151 switch (Opcode) { 2152 case OPC_Scope: { 2153 // Okay, the semantics of this operation are that we should push a scope 2154 // then evaluate the first child. However, pushing a scope only to have 2155 // the first check fail (which then pops it) is inefficient. If we can 2156 // determine immediately that the first check (or first several) will 2157 // immediately fail, don't even bother pushing a scope for them. 2158 unsigned FailIndex; 2159 2160 while (1) { 2161 unsigned NumToSkip = MatcherTable[MatcherIndex++]; 2162 if (NumToSkip & 128) 2163 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex); 2164 // Found the end of the scope with no match. 2165 if (NumToSkip == 0) { 2166 FailIndex = 0; 2167 break; 2168 } 2169 2170 FailIndex = MatcherIndex+NumToSkip; 2171 2172 unsigned MatcherIndexOfPredicate = MatcherIndex; 2173 (void)MatcherIndexOfPredicate; // silence warning. 2174 2175 // If we can't evaluate this predicate without pushing a scope (e.g. if 2176 // it is a 'MoveParent') or if the predicate succeeds on this node, we 2177 // push the scope and evaluate the full predicate chain. 2178 bool Result; 2179 MatcherIndex = IsPredicateKnownToFail(MatcherTable, MatcherIndex, N, 2180 Result, *this, RecordedNodes); 2181 if (!Result) 2182 break; 2183 2184 DEBUG(errs() << " Skipped scope entry (due to false predicate) at " 2185 << "index " << MatcherIndexOfPredicate 2186 << ", continuing at " << FailIndex << "\n"); 2187 ++NumDAGIselRetries; 2188 2189 // Otherwise, we know that this case of the Scope is guaranteed to fail, 2190 // move to the next case. 2191 MatcherIndex = FailIndex; 2192 } 2193 2194 // If the whole scope failed to match, bail. 2195 if (FailIndex == 0) break; 2196 2197 // Push a MatchScope which indicates where to go if the first child fails 2198 // to match. 2199 MatchScope NewEntry; 2200 NewEntry.FailIndex = FailIndex; 2201 NewEntry.NodeStack.append(NodeStack.begin(), NodeStack.end()); 2202 NewEntry.NumRecordedNodes = RecordedNodes.size(); 2203 NewEntry.NumMatchedMemRefs = MatchedMemRefs.size(); 2204 NewEntry.InputChain = InputChain; 2205 NewEntry.InputFlag = InputFlag; 2206 NewEntry.HasChainNodesMatched = !ChainNodesMatched.empty(); 2207 NewEntry.HasFlagResultNodesMatched = !FlagResultNodesMatched.empty(); 2208 MatchScopes.push_back(NewEntry); 2209 continue; 2210 } 2211 case OPC_RecordNode: 2212 // Remember this node, it may end up being an operand in the pattern. 2213 RecordedNodes.push_back(N); 2214 continue; 2215 2216 case OPC_RecordChild0: case OPC_RecordChild1: 2217 case OPC_RecordChild2: case OPC_RecordChild3: 2218 case OPC_RecordChild4: case OPC_RecordChild5: 2219 case OPC_RecordChild6: case OPC_RecordChild7: { 2220 unsigned ChildNo = Opcode-OPC_RecordChild0; 2221 if (ChildNo >= N.getNumOperands()) 2222 break; // Match fails if out of range child #. 2223 2224 RecordedNodes.push_back(N->getOperand(ChildNo)); 2225 continue; 2226 } 2227 case OPC_RecordMemRef: 2228 MatchedMemRefs.push_back(cast<MemSDNode>(N)->getMemOperand()); 2229 continue; 2230 2231 case OPC_CaptureFlagInput: 2232 // If the current node has an input flag, capture it in InputFlag. 2233 if (N->getNumOperands() != 0 && 2234 N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Flag) 2235 InputFlag = N->getOperand(N->getNumOperands()-1); 2236 continue; 2237 2238 case OPC_MoveChild: { 2239 unsigned ChildNo = MatcherTable[MatcherIndex++]; 2240 if (ChildNo >= N.getNumOperands()) 2241 break; // Match fails if out of range child #. 2242 N = N.getOperand(ChildNo); 2243 NodeStack.push_back(N); 2244 continue; 2245 } 2246 2247 case OPC_MoveParent: 2248 // Pop the current node off the NodeStack. 2249 NodeStack.pop_back(); 2250 assert(!NodeStack.empty() && "Node stack imbalance!"); 2251 N = NodeStack.back(); 2252 continue; 2253 2254 case OPC_CheckSame: 2255 if (!::CheckSame(MatcherTable, MatcherIndex, N, RecordedNodes)) break; 2256 continue; 2257 case OPC_CheckPatternPredicate: 2258 if (!::CheckPatternPredicate(MatcherTable, MatcherIndex, *this)) break; 2259 continue; 2260 case OPC_CheckPredicate: 2261 if (!::CheckNodePredicate(MatcherTable, MatcherIndex, *this, 2262 N.getNode())) 2263 break; 2264 continue; 2265 case OPC_CheckComplexPat: { 2266 unsigned CPNum = MatcherTable[MatcherIndex++]; 2267 unsigned RecNo = MatcherTable[MatcherIndex++]; 2268 assert(RecNo < RecordedNodes.size() && "Invalid CheckComplexPat"); 2269 if (!CheckComplexPattern(NodeToMatch, RecordedNodes[RecNo], CPNum, 2270 RecordedNodes)) 2271 break; 2272 continue; 2273 } 2274 case OPC_CheckOpcode: 2275 if (!::CheckOpcode(MatcherTable, MatcherIndex, N.getNode())) break; 2276 continue; 2277 2278 case OPC_CheckType: 2279 if (!::CheckType(MatcherTable, MatcherIndex, N, TLI)) break; 2280 continue; 2281 2282 case OPC_SwitchOpcode: { 2283 unsigned CurNodeOpcode = N.getOpcode(); 2284 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart; 2285 unsigned CaseSize; 2286 while (1) { 2287 // Get the size of this case. 2288 CaseSize = MatcherTable[MatcherIndex++]; 2289 if (CaseSize & 128) 2290 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex); 2291 if (CaseSize == 0) break; 2292 2293 uint16_t Opc = MatcherTable[MatcherIndex++]; 2294 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8; 2295 2296 // If the opcode matches, then we will execute this case. 2297 if (CurNodeOpcode == Opc) 2298 break; 2299 2300 // Otherwise, skip over this case. 2301 MatcherIndex += CaseSize; 2302 } 2303 2304 // If no cases matched, bail out. 2305 if (CaseSize == 0) break; 2306 2307 // Otherwise, execute the case we found. 2308 DEBUG(errs() << " OpcodeSwitch from " << SwitchStart 2309 << " to " << MatcherIndex << "\n"); 2310 continue; 2311 } 2312 2313 case OPC_SwitchType: { 2314 MVT::SimpleValueType CurNodeVT = N.getValueType().getSimpleVT().SimpleTy; 2315 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart; 2316 unsigned CaseSize; 2317 while (1) { 2318 // Get the size of this case. 2319 CaseSize = MatcherTable[MatcherIndex++]; 2320 if (CaseSize & 128) 2321 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex); 2322 if (CaseSize == 0) break; 2323 2324 MVT::SimpleValueType CaseVT = 2325 (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2326 if (CaseVT == MVT::iPTR) 2327 CaseVT = TLI.getPointerTy().SimpleTy; 2328 2329 // If the VT matches, then we will execute this case. 2330 if (CurNodeVT == CaseVT) 2331 break; 2332 2333 // Otherwise, skip over this case. 2334 MatcherIndex += CaseSize; 2335 } 2336 2337 // If no cases matched, bail out. 2338 if (CaseSize == 0) break; 2339 2340 // Otherwise, execute the case we found. 2341 DEBUG(errs() << " TypeSwitch[" << EVT(CurNodeVT).getEVTString() 2342 << "] from " << SwitchStart << " to " << MatcherIndex<<'\n'); 2343 continue; 2344 } 2345 case OPC_CheckChild0Type: case OPC_CheckChild1Type: 2346 case OPC_CheckChild2Type: case OPC_CheckChild3Type: 2347 case OPC_CheckChild4Type: case OPC_CheckChild5Type: 2348 case OPC_CheckChild6Type: case OPC_CheckChild7Type: 2349 if (!::CheckChildType(MatcherTable, MatcherIndex, N, TLI, 2350 Opcode-OPC_CheckChild0Type)) 2351 break; 2352 continue; 2353 case OPC_CheckCondCode: 2354 if (!::CheckCondCode(MatcherTable, MatcherIndex, N)) break; 2355 continue; 2356 case OPC_CheckValueType: 2357 if (!::CheckValueType(MatcherTable, MatcherIndex, N, TLI)) break; 2358 continue; 2359 case OPC_CheckInteger: 2360 if (!::CheckInteger(MatcherTable, MatcherIndex, N)) break; 2361 continue; 2362 case OPC_CheckAndImm: 2363 if (!::CheckAndImm(MatcherTable, MatcherIndex, N, *this)) break; 2364 continue; 2365 case OPC_CheckOrImm: 2366 if (!::CheckOrImm(MatcherTable, MatcherIndex, N, *this)) break; 2367 continue; 2368 2369 case OPC_CheckFoldableChainNode: { 2370 assert(NodeStack.size() != 1 && "No parent node"); 2371 // Verify that all intermediate nodes between the root and this one have 2372 // a single use. 2373 bool HasMultipleUses = false; 2374 for (unsigned i = 1, e = NodeStack.size()-1; i != e; ++i) 2375 if (!NodeStack[i].hasOneUse()) { 2376 HasMultipleUses = true; 2377 break; 2378 } 2379 if (HasMultipleUses) break; 2380 2381 // Check to see that the target thinks this is profitable to fold and that 2382 // we can fold it without inducing cycles in the graph. 2383 if (!IsProfitableToFold(N, NodeStack[NodeStack.size()-2].getNode(), 2384 NodeToMatch) || 2385 !IsLegalToFold(N, NodeStack[NodeStack.size()-2].getNode(), 2386 NodeToMatch, true/*We validate our own chains*/)) 2387 break; 2388 2389 continue; 2390 } 2391 case OPC_EmitInteger: { 2392 MVT::SimpleValueType VT = 2393 (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2394 int64_t Val = MatcherTable[MatcherIndex++]; 2395 if (Val & 128) 2396 Val = GetVBR(Val, MatcherTable, MatcherIndex); 2397 RecordedNodes.push_back(CurDAG->getTargetConstant(Val, VT)); 2398 continue; 2399 } 2400 case OPC_EmitRegister: { 2401 MVT::SimpleValueType VT = 2402 (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2403 unsigned RegNo = MatcherTable[MatcherIndex++]; 2404 RecordedNodes.push_back(CurDAG->getRegister(RegNo, VT)); 2405 continue; 2406 } 2407 2408 case OPC_EmitConvertToTarget: { 2409 // Convert from IMM/FPIMM to target version. 2410 unsigned RecNo = MatcherTable[MatcherIndex++]; 2411 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2412 SDValue Imm = RecordedNodes[RecNo]; 2413 2414 if (Imm->getOpcode() == ISD::Constant) { 2415 int64_t Val = cast<ConstantSDNode>(Imm)->getZExtValue(); 2416 Imm = CurDAG->getTargetConstant(Val, Imm.getValueType()); 2417 } else if (Imm->getOpcode() == ISD::ConstantFP) { 2418 const ConstantFP *Val=cast<ConstantFPSDNode>(Imm)->getConstantFPValue(); 2419 Imm = CurDAG->getTargetConstantFP(*Val, Imm.getValueType()); 2420 } 2421 2422 RecordedNodes.push_back(Imm); 2423 continue; 2424 } 2425 2426 case OPC_EmitMergeInputChains1_0: // OPC_EmitMergeInputChains, 1, 0 2427 case OPC_EmitMergeInputChains1_1: { // OPC_EmitMergeInputChains, 1, 1 2428 // These are space-optimized forms of OPC_EmitMergeInputChains. 2429 assert(InputChain.getNode() == 0 && 2430 "EmitMergeInputChains should be the first chain producing node"); 2431 assert(ChainNodesMatched.empty() && 2432 "Should only have one EmitMergeInputChains per match"); 2433 2434 // Read all of the chained nodes. 2435 unsigned RecNo = Opcode == OPC_EmitMergeInputChains1_1; 2436 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2437 ChainNodesMatched.push_back(RecordedNodes[RecNo].getNode()); 2438 2439 // FIXME: What if other value results of the node have uses not matched 2440 // by this pattern? 2441 if (ChainNodesMatched.back() != NodeToMatch && 2442 !RecordedNodes[RecNo].hasOneUse()) { 2443 ChainNodesMatched.clear(); 2444 break; 2445 } 2446 2447 // Merge the input chains if they are not intra-pattern references. 2448 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG); 2449 2450 if (InputChain.getNode() == 0) 2451 break; // Failed to merge. 2452 continue; 2453 } 2454 2455 case OPC_EmitMergeInputChains: { 2456 assert(InputChain.getNode() == 0 && 2457 "EmitMergeInputChains should be the first chain producing node"); 2458 // This node gets a list of nodes we matched in the input that have 2459 // chains. We want to token factor all of the input chains to these nodes 2460 // together. However, if any of the input chains is actually one of the 2461 // nodes matched in this pattern, then we have an intra-match reference. 2462 // Ignore these because the newly token factored chain should not refer to 2463 // the old nodes. 2464 unsigned NumChains = MatcherTable[MatcherIndex++]; 2465 assert(NumChains != 0 && "Can't TF zero chains"); 2466 2467 assert(ChainNodesMatched.empty() && 2468 "Should only have one EmitMergeInputChains per match"); 2469 2470 // Read all of the chained nodes. 2471 for (unsigned i = 0; i != NumChains; ++i) { 2472 unsigned RecNo = MatcherTable[MatcherIndex++]; 2473 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2474 ChainNodesMatched.push_back(RecordedNodes[RecNo].getNode()); 2475 2476 // FIXME: What if other value results of the node have uses not matched 2477 // by this pattern? 2478 if (ChainNodesMatched.back() != NodeToMatch && 2479 !RecordedNodes[RecNo].hasOneUse()) { 2480 ChainNodesMatched.clear(); 2481 break; 2482 } 2483 } 2484 2485 // If the inner loop broke out, the match fails. 2486 if (ChainNodesMatched.empty()) 2487 break; 2488 2489 // Merge the input chains if they are not intra-pattern references. 2490 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG); 2491 2492 if (InputChain.getNode() == 0) 2493 break; // Failed to merge. 2494 2495 continue; 2496 } 2497 2498 case OPC_EmitCopyToReg: { 2499 unsigned RecNo = MatcherTable[MatcherIndex++]; 2500 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2501 unsigned DestPhysReg = MatcherTable[MatcherIndex++]; 2502 2503 if (InputChain.getNode() == 0) 2504 InputChain = CurDAG->getEntryNode(); 2505 2506 InputChain = CurDAG->getCopyToReg(InputChain, NodeToMatch->getDebugLoc(), 2507 DestPhysReg, RecordedNodes[RecNo], 2508 InputFlag); 2509 2510 InputFlag = InputChain.getValue(1); 2511 continue; 2512 } 2513 2514 case OPC_EmitNodeXForm: { 2515 unsigned XFormNo = MatcherTable[MatcherIndex++]; 2516 unsigned RecNo = MatcherTable[MatcherIndex++]; 2517 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2518 RecordedNodes.push_back(RunSDNodeXForm(RecordedNodes[RecNo], XFormNo)); 2519 continue; 2520 } 2521 2522 case OPC_EmitNode: 2523 case OPC_MorphNodeTo: { 2524 uint16_t TargetOpc = MatcherTable[MatcherIndex++]; 2525 TargetOpc |= (unsigned short)MatcherTable[MatcherIndex++] << 8; 2526 unsigned EmitNodeInfo = MatcherTable[MatcherIndex++]; 2527 // Get the result VT list. 2528 unsigned NumVTs = MatcherTable[MatcherIndex++]; 2529 SmallVector<EVT, 4> VTs; 2530 for (unsigned i = 0; i != NumVTs; ++i) { 2531 MVT::SimpleValueType VT = 2532 (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2533 if (VT == MVT::iPTR) VT = TLI.getPointerTy().SimpleTy; 2534 VTs.push_back(VT); 2535 } 2536 2537 if (EmitNodeInfo & OPFL_Chain) 2538 VTs.push_back(MVT::Other); 2539 if (EmitNodeInfo & OPFL_FlagOutput) 2540 VTs.push_back(MVT::Flag); 2541 2542 // This is hot code, so optimize the two most common cases of 1 and 2 2543 // results. 2544 SDVTList VTList; 2545 if (VTs.size() == 1) 2546 VTList = CurDAG->getVTList(VTs[0]); 2547 else if (VTs.size() == 2) 2548 VTList = CurDAG->getVTList(VTs[0], VTs[1]); 2549 else 2550 VTList = CurDAG->getVTList(VTs.data(), VTs.size()); 2551 2552 // Get the operand list. 2553 unsigned NumOps = MatcherTable[MatcherIndex++]; 2554 SmallVector<SDValue, 8> Ops; 2555 for (unsigned i = 0; i != NumOps; ++i) { 2556 unsigned RecNo = MatcherTable[MatcherIndex++]; 2557 if (RecNo & 128) 2558 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex); 2559 2560 assert(RecNo < RecordedNodes.size() && "Invalid EmitNode"); 2561 Ops.push_back(RecordedNodes[RecNo]); 2562 } 2563 2564 // If there are variadic operands to add, handle them now. 2565 if (EmitNodeInfo & OPFL_VariadicInfo) { 2566 // Determine the start index to copy from. 2567 unsigned FirstOpToCopy = getNumFixedFromVariadicInfo(EmitNodeInfo); 2568 FirstOpToCopy += (EmitNodeInfo & OPFL_Chain) ? 1 : 0; 2569 assert(NodeToMatch->getNumOperands() >= FirstOpToCopy && 2570 "Invalid variadic node"); 2571 // Copy all of the variadic operands, not including a potential flag 2572 // input. 2573 for (unsigned i = FirstOpToCopy, e = NodeToMatch->getNumOperands(); 2574 i != e; ++i) { 2575 SDValue V = NodeToMatch->getOperand(i); 2576 if (V.getValueType() == MVT::Flag) break; 2577 Ops.push_back(V); 2578 } 2579 } 2580 2581 // If this has chain/flag inputs, add them. 2582 if (EmitNodeInfo & OPFL_Chain) 2583 Ops.push_back(InputChain); 2584 if ((EmitNodeInfo & OPFL_FlagInput) && InputFlag.getNode() != 0) 2585 Ops.push_back(InputFlag); 2586 2587 // Create the node. 2588 SDNode *Res = 0; 2589 if (Opcode != OPC_MorphNodeTo) { 2590 // If this is a normal EmitNode command, just create the new node and 2591 // add the results to the RecordedNodes list. 2592 Res = CurDAG->getMachineNode(TargetOpc, NodeToMatch->getDebugLoc(), 2593 VTList, Ops.data(), Ops.size()); 2594 2595 // Add all the non-flag/non-chain results to the RecordedNodes list. 2596 for (unsigned i = 0, e = VTs.size(); i != e; ++i) { 2597 if (VTs[i] == MVT::Other || VTs[i] == MVT::Flag) break; 2598 RecordedNodes.push_back(SDValue(Res, i)); 2599 } 2600 2601 } else { 2602 Res = MorphNode(NodeToMatch, TargetOpc, VTList, Ops.data(), Ops.size(), 2603 EmitNodeInfo); 2604 } 2605 2606 // If the node had chain/flag results, update our notion of the current 2607 // chain and flag. 2608 if (EmitNodeInfo & OPFL_FlagOutput) { 2609 InputFlag = SDValue(Res, VTs.size()-1); 2610 if (EmitNodeInfo & OPFL_Chain) 2611 InputChain = SDValue(Res, VTs.size()-2); 2612 } else if (EmitNodeInfo & OPFL_Chain) 2613 InputChain = SDValue(Res, VTs.size()-1); 2614 2615 // If the OPFL_MemRefs flag is set on this node, slap all of the 2616 // accumulated memrefs onto it. 2617 // 2618 // FIXME: This is vastly incorrect for patterns with multiple outputs 2619 // instructions that access memory and for ComplexPatterns that match 2620 // loads. 2621 if (EmitNodeInfo & OPFL_MemRefs) { 2622 MachineSDNode::mmo_iterator MemRefs = 2623 MF->allocateMemRefsArray(MatchedMemRefs.size()); 2624 std::copy(MatchedMemRefs.begin(), MatchedMemRefs.end(), MemRefs); 2625 cast<MachineSDNode>(Res) 2626 ->setMemRefs(MemRefs, MemRefs + MatchedMemRefs.size()); 2627 } 2628 2629 DEBUG(errs() << " " 2630 << (Opcode == OPC_MorphNodeTo ? "Morphed" : "Created") 2631 << " node: "; Res->dump(CurDAG); errs() << "\n"); 2632 2633 // If this was a MorphNodeTo then we're completely done! 2634 if (Opcode == OPC_MorphNodeTo) { 2635 // Update chain and flag uses. 2636 UpdateChainsAndFlags(NodeToMatch, InputChain, ChainNodesMatched, 2637 InputFlag, FlagResultNodesMatched, true); 2638 return Res; 2639 } 2640 2641 continue; 2642 } 2643 2644 case OPC_MarkFlagResults: { 2645 unsigned NumNodes = MatcherTable[MatcherIndex++]; 2646 2647 // Read and remember all the flag-result nodes. 2648 for (unsigned i = 0; i != NumNodes; ++i) { 2649 unsigned RecNo = MatcherTable[MatcherIndex++]; 2650 if (RecNo & 128) 2651 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex); 2652 2653 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2654 FlagResultNodesMatched.push_back(RecordedNodes[RecNo].getNode()); 2655 } 2656 continue; 2657 } 2658 2659 case OPC_CompleteMatch: { 2660 // The match has been completed, and any new nodes (if any) have been 2661 // created. Patch up references to the matched dag to use the newly 2662 // created nodes. 2663 unsigned NumResults = MatcherTable[MatcherIndex++]; 2664 2665 for (unsigned i = 0; i != NumResults; ++i) { 2666 unsigned ResSlot = MatcherTable[MatcherIndex++]; 2667 if (ResSlot & 128) 2668 ResSlot = GetVBR(ResSlot, MatcherTable, MatcherIndex); 2669 2670 assert(ResSlot < RecordedNodes.size() && "Invalid CheckSame"); 2671 SDValue Res = RecordedNodes[ResSlot]; 2672 2673 assert(i < NodeToMatch->getNumValues() && 2674 NodeToMatch->getValueType(i) != MVT::Other && 2675 NodeToMatch->getValueType(i) != MVT::Flag && 2676 "Invalid number of results to complete!"); 2677 assert((NodeToMatch->getValueType(i) == Res.getValueType() || 2678 NodeToMatch->getValueType(i) == MVT::iPTR || 2679 Res.getValueType() == MVT::iPTR || 2680 NodeToMatch->getValueType(i).getSizeInBits() == 2681 Res.getValueType().getSizeInBits()) && 2682 "invalid replacement"); 2683 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, i), Res); 2684 } 2685 2686 // If the root node defines a flag, add it to the flag nodes to update 2687 // list. 2688 if (NodeToMatch->getValueType(NodeToMatch->getNumValues()-1) == MVT::Flag) 2689 FlagResultNodesMatched.push_back(NodeToMatch); 2690 2691 // Update chain and flag uses. 2692 UpdateChainsAndFlags(NodeToMatch, InputChain, ChainNodesMatched, 2693 InputFlag, FlagResultNodesMatched, false); 2694 2695 assert(NodeToMatch->use_empty() && 2696 "Didn't replace all uses of the node?"); 2697 2698 // FIXME: We just return here, which interacts correctly with SelectRoot 2699 // above. We should fix this to not return an SDNode* anymore. 2700 return 0; 2701 } 2702 } 2703 2704 // If the code reached this point, then the match failed. See if there is 2705 // another child to try in the current 'Scope', otherwise pop it until we 2706 // find a case to check. 2707 DEBUG(errs() << " Match failed at index " << CurrentOpcodeIndex << "\n"); 2708 ++NumDAGIselRetries; 2709 while (1) { 2710 if (MatchScopes.empty()) { 2711 CannotYetSelect(NodeToMatch); 2712 return 0; 2713 } 2714 2715 // Restore the interpreter state back to the point where the scope was 2716 // formed. 2717 MatchScope &LastScope = MatchScopes.back(); 2718 RecordedNodes.resize(LastScope.NumRecordedNodes); 2719 NodeStack.clear(); 2720 NodeStack.append(LastScope.NodeStack.begin(), LastScope.NodeStack.end()); 2721 N = NodeStack.back(); 2722 2723 if (LastScope.NumMatchedMemRefs != MatchedMemRefs.size()) 2724 MatchedMemRefs.resize(LastScope.NumMatchedMemRefs); 2725 MatcherIndex = LastScope.FailIndex; 2726 2727 DEBUG(errs() << " Continuing at " << MatcherIndex << "\n"); 2728 2729 InputChain = LastScope.InputChain; 2730 InputFlag = LastScope.InputFlag; 2731 if (!LastScope.HasChainNodesMatched) 2732 ChainNodesMatched.clear(); 2733 if (!LastScope.HasFlagResultNodesMatched) 2734 FlagResultNodesMatched.clear(); 2735 2736 // Check to see what the offset is at the new MatcherIndex. If it is zero 2737 // we have reached the end of this scope, otherwise we have another child 2738 // in the current scope to try. 2739 unsigned NumToSkip = MatcherTable[MatcherIndex++]; 2740 if (NumToSkip & 128) 2741 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex); 2742 2743 // If we have another child in this scope to match, update FailIndex and 2744 // try it. 2745 if (NumToSkip != 0) { 2746 LastScope.FailIndex = MatcherIndex+NumToSkip; 2747 break; 2748 } 2749 2750 // End of this scope, pop it and try the next child in the containing 2751 // scope. 2752 MatchScopes.pop_back(); 2753 } 2754 } 2755} 2756 2757 2758 2759void SelectionDAGISel::CannotYetSelect(SDNode *N) { 2760 std::string msg; 2761 raw_string_ostream Msg(msg); 2762 Msg << "Cannot yet select: "; 2763 2764 if (N->getOpcode() != ISD::INTRINSIC_W_CHAIN && 2765 N->getOpcode() != ISD::INTRINSIC_WO_CHAIN && 2766 N->getOpcode() != ISD::INTRINSIC_VOID) { 2767 N->printrFull(Msg, CurDAG); 2768 } else { 2769 bool HasInputChain = N->getOperand(0).getValueType() == MVT::Other; 2770 unsigned iid = 2771 cast<ConstantSDNode>(N->getOperand(HasInputChain))->getZExtValue(); 2772 if (iid < Intrinsic::num_intrinsics) 2773 Msg << "intrinsic %" << Intrinsic::getName((Intrinsic::ID)iid); 2774 else if (const TargetIntrinsicInfo *TII = TM.getIntrinsicInfo()) 2775 Msg << "target intrinsic %" << TII->getName(iid); 2776 else 2777 Msg << "unknown intrinsic #" << iid; 2778 } 2779 llvm_report_error(Msg.str()); 2780} 2781 2782char SelectionDAGISel::ID = 0; 2783