InstrEmitter.cpp revision 327952
1//==--- InstrEmitter.cpp - Emit MachineInstrs for the SelectionDAG class ---==// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This implements the Emit routines for the SelectionDAG class, which creates 11// MachineInstrs based on the decisions of the SelectionDAG instruction 12// selection. 13// 14//===----------------------------------------------------------------------===// 15 16#include "InstrEmitter.h" 17#include "SDNodeDbgValue.h" 18#include "llvm/ADT/Statistic.h" 19#include "llvm/CodeGen/MachineConstantPool.h" 20#include "llvm/CodeGen/MachineFunction.h" 21#include "llvm/CodeGen/MachineInstrBuilder.h" 22#include "llvm/CodeGen/MachineRegisterInfo.h" 23#include "llvm/CodeGen/StackMaps.h" 24#include "llvm/CodeGen/TargetInstrInfo.h" 25#include "llvm/CodeGen/TargetLowering.h" 26#include "llvm/CodeGen/TargetSubtargetInfo.h" 27#include "llvm/IR/DataLayout.h" 28#include "llvm/IR/DebugInfo.h" 29#include "llvm/Support/Debug.h" 30#include "llvm/Support/ErrorHandling.h" 31#include "llvm/Support/MathExtras.h" 32using namespace llvm; 33 34#define DEBUG_TYPE "instr-emitter" 35 36/// MinRCSize - Smallest register class we allow when constraining virtual 37/// registers. If satisfying all register class constraints would require 38/// using a smaller register class, emit a COPY to a new virtual register 39/// instead. 40const unsigned MinRCSize = 4; 41 42/// CountResults - The results of target nodes have register or immediate 43/// operands first, then an optional chain, and optional glue operands (which do 44/// not go into the resulting MachineInstr). 45unsigned InstrEmitter::CountResults(SDNode *Node) { 46 unsigned N = Node->getNumValues(); 47 while (N && Node->getValueType(N - 1) == MVT::Glue) 48 --N; 49 if (N && Node->getValueType(N - 1) == MVT::Other) 50 --N; // Skip over chain result. 51 return N; 52} 53 54/// countOperands - The inputs to target nodes have any actual inputs first, 55/// followed by an optional chain operand, then an optional glue operand. 56/// Compute the number of actual operands that will go into the resulting 57/// MachineInstr. 58/// 59/// Also count physreg RegisterSDNode and RegisterMaskSDNode operands preceding 60/// the chain and glue. These operands may be implicit on the machine instr. 61static unsigned countOperands(SDNode *Node, unsigned NumExpUses, 62 unsigned &NumImpUses) { 63 unsigned N = Node->getNumOperands(); 64 while (N && Node->getOperand(N - 1).getValueType() == MVT::Glue) 65 --N; 66 if (N && Node->getOperand(N - 1).getValueType() == MVT::Other) 67 --N; // Ignore chain if it exists. 68 69 // Count RegisterSDNode and RegisterMaskSDNode operands for NumImpUses. 70 NumImpUses = N - NumExpUses; 71 for (unsigned I = N; I > NumExpUses; --I) { 72 if (isa<RegisterMaskSDNode>(Node->getOperand(I - 1))) 73 continue; 74 if (RegisterSDNode *RN = dyn_cast<RegisterSDNode>(Node->getOperand(I - 1))) 75 if (TargetRegisterInfo::isPhysicalRegister(RN->getReg())) 76 continue; 77 NumImpUses = N - I; 78 break; 79 } 80 81 return N; 82} 83 84/// EmitCopyFromReg - Generate machine code for an CopyFromReg node or an 85/// implicit physical register output. 86void InstrEmitter:: 87EmitCopyFromReg(SDNode *Node, unsigned ResNo, bool IsClone, bool IsCloned, 88 unsigned SrcReg, DenseMap<SDValue, unsigned> &VRBaseMap) { 89 unsigned VRBase = 0; 90 if (TargetRegisterInfo::isVirtualRegister(SrcReg)) { 91 // Just use the input register directly! 92 SDValue Op(Node, ResNo); 93 if (IsClone) 94 VRBaseMap.erase(Op); 95 bool isNew = VRBaseMap.insert(std::make_pair(Op, SrcReg)).second; 96 (void)isNew; // Silence compiler warning. 97 assert(isNew && "Node emitted out of order - early"); 98 return; 99 } 100 101 // If the node is only used by a CopyToReg and the dest reg is a vreg, use 102 // the CopyToReg'd destination register instead of creating a new vreg. 103 bool MatchReg = true; 104 const TargetRegisterClass *UseRC = nullptr; 105 MVT VT = Node->getSimpleValueType(ResNo); 106 107 // Stick to the preferred register classes for legal types. 108 if (TLI->isTypeLegal(VT)) 109 UseRC = TLI->getRegClassFor(VT); 110 111 if (!IsClone && !IsCloned) 112 for (SDNode *User : Node->uses()) { 113 bool Match = true; 114 if (User->getOpcode() == ISD::CopyToReg && 115 User->getOperand(2).getNode() == Node && 116 User->getOperand(2).getResNo() == ResNo) { 117 unsigned DestReg = cast<RegisterSDNode>(User->getOperand(1))->getReg(); 118 if (TargetRegisterInfo::isVirtualRegister(DestReg)) { 119 VRBase = DestReg; 120 Match = false; 121 } else if (DestReg != SrcReg) 122 Match = false; 123 } else { 124 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) { 125 SDValue Op = User->getOperand(i); 126 if (Op.getNode() != Node || Op.getResNo() != ResNo) 127 continue; 128 MVT VT = Node->getSimpleValueType(Op.getResNo()); 129 if (VT == MVT::Other || VT == MVT::Glue) 130 continue; 131 Match = false; 132 if (User->isMachineOpcode()) { 133 const MCInstrDesc &II = TII->get(User->getMachineOpcode()); 134 const TargetRegisterClass *RC = nullptr; 135 if (i+II.getNumDefs() < II.getNumOperands()) { 136 RC = TRI->getAllocatableClass( 137 TII->getRegClass(II, i+II.getNumDefs(), TRI, *MF)); 138 } 139 if (!UseRC) 140 UseRC = RC; 141 else if (RC) { 142 const TargetRegisterClass *ComRC = 143 TRI->getCommonSubClass(UseRC, RC, VT.SimpleTy); 144 // If multiple uses expect disjoint register classes, we emit 145 // copies in AddRegisterOperand. 146 if (ComRC) 147 UseRC = ComRC; 148 } 149 } 150 } 151 } 152 MatchReg &= Match; 153 if (VRBase) 154 break; 155 } 156 157 const TargetRegisterClass *SrcRC = nullptr, *DstRC = nullptr; 158 SrcRC = TRI->getMinimalPhysRegClass(SrcReg, VT); 159 160 // Figure out the register class to create for the destreg. 161 if (VRBase) { 162 DstRC = MRI->getRegClass(VRBase); 163 } else if (UseRC) { 164 assert(TRI->isTypeLegalForClass(*UseRC, VT) && 165 "Incompatible phys register def and uses!"); 166 DstRC = UseRC; 167 } else { 168 DstRC = TLI->getRegClassFor(VT); 169 } 170 171 // If all uses are reading from the src physical register and copying the 172 // register is either impossible or very expensive, then don't create a copy. 173 if (MatchReg && SrcRC->getCopyCost() < 0) { 174 VRBase = SrcReg; 175 } else { 176 // Create the reg, emit the copy. 177 VRBase = MRI->createVirtualRegister(DstRC); 178 BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->get(TargetOpcode::COPY), 179 VRBase).addReg(SrcReg); 180 } 181 182 SDValue Op(Node, ResNo); 183 if (IsClone) 184 VRBaseMap.erase(Op); 185 bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBase)).second; 186 (void)isNew; // Silence compiler warning. 187 assert(isNew && "Node emitted out of order - early"); 188} 189 190/// getDstOfCopyToRegUse - If the only use of the specified result number of 191/// node is a CopyToReg, return its destination register. Return 0 otherwise. 192unsigned InstrEmitter::getDstOfOnlyCopyToRegUse(SDNode *Node, 193 unsigned ResNo) const { 194 if (!Node->hasOneUse()) 195 return 0; 196 197 SDNode *User = *Node->use_begin(); 198 if (User->getOpcode() == ISD::CopyToReg && 199 User->getOperand(2).getNode() == Node && 200 User->getOperand(2).getResNo() == ResNo) { 201 unsigned Reg = cast<RegisterSDNode>(User->getOperand(1))->getReg(); 202 if (TargetRegisterInfo::isVirtualRegister(Reg)) 203 return Reg; 204 } 205 return 0; 206} 207 208void InstrEmitter::CreateVirtualRegisters(SDNode *Node, 209 MachineInstrBuilder &MIB, 210 const MCInstrDesc &II, 211 bool IsClone, bool IsCloned, 212 DenseMap<SDValue, unsigned> &VRBaseMap) { 213 assert(Node->getMachineOpcode() != TargetOpcode::IMPLICIT_DEF && 214 "IMPLICIT_DEF should have been handled as a special case elsewhere!"); 215 216 unsigned NumResults = CountResults(Node); 217 for (unsigned i = 0; i < II.getNumDefs(); ++i) { 218 // If the specific node value is only used by a CopyToReg and the dest reg 219 // is a vreg in the same register class, use the CopyToReg'd destination 220 // register instead of creating a new vreg. 221 unsigned VRBase = 0; 222 const TargetRegisterClass *RC = 223 TRI->getAllocatableClass(TII->getRegClass(II, i, TRI, *MF)); 224 // Always let the value type influence the used register class. The 225 // constraints on the instruction may be too lax to represent the value 226 // type correctly. For example, a 64-bit float (X86::FR64) can't live in 227 // the 32-bit float super-class (X86::FR32). 228 if (i < NumResults && TLI->isTypeLegal(Node->getSimpleValueType(i))) { 229 const TargetRegisterClass *VTRC = 230 TLI->getRegClassFor(Node->getSimpleValueType(i)); 231 if (RC) 232 VTRC = TRI->getCommonSubClass(RC, VTRC); 233 if (VTRC) 234 RC = VTRC; 235 } 236 237 if (II.OpInfo[i].isOptionalDef()) { 238 // Optional def must be a physical register. 239 VRBase = cast<RegisterSDNode>(Node->getOperand(i-NumResults))->getReg(); 240 assert(TargetRegisterInfo::isPhysicalRegister(VRBase)); 241 MIB.addReg(VRBase, RegState::Define); 242 } 243 244 if (!VRBase && !IsClone && !IsCloned) 245 for (SDNode *User : Node->uses()) { 246 if (User->getOpcode() == ISD::CopyToReg && 247 User->getOperand(2).getNode() == Node && 248 User->getOperand(2).getResNo() == i) { 249 unsigned Reg = cast<RegisterSDNode>(User->getOperand(1))->getReg(); 250 if (TargetRegisterInfo::isVirtualRegister(Reg)) { 251 const TargetRegisterClass *RegRC = MRI->getRegClass(Reg); 252 if (RegRC == RC) { 253 VRBase = Reg; 254 MIB.addReg(VRBase, RegState::Define); 255 break; 256 } 257 } 258 } 259 } 260 261 // Create the result registers for this node and add the result regs to 262 // the machine instruction. 263 if (VRBase == 0) { 264 assert(RC && "Isn't a register operand!"); 265 VRBase = MRI->createVirtualRegister(RC); 266 MIB.addReg(VRBase, RegState::Define); 267 } 268 269 // If this def corresponds to a result of the SDNode insert the VRBase into 270 // the lookup map. 271 if (i < NumResults) { 272 SDValue Op(Node, i); 273 if (IsClone) 274 VRBaseMap.erase(Op); 275 bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBase)).second; 276 (void)isNew; // Silence compiler warning. 277 assert(isNew && "Node emitted out of order - early"); 278 } 279 } 280} 281 282/// getVR - Return the virtual register corresponding to the specified result 283/// of the specified node. 284unsigned InstrEmitter::getVR(SDValue Op, 285 DenseMap<SDValue, unsigned> &VRBaseMap) { 286 if (Op.isMachineOpcode() && 287 Op.getMachineOpcode() == TargetOpcode::IMPLICIT_DEF) { 288 // Add an IMPLICIT_DEF instruction before every use. 289 unsigned VReg = getDstOfOnlyCopyToRegUse(Op.getNode(), Op.getResNo()); 290 // IMPLICIT_DEF can produce any type of result so its MCInstrDesc 291 // does not include operand register class info. 292 if (!VReg) { 293 const TargetRegisterClass *RC = 294 TLI->getRegClassFor(Op.getSimpleValueType()); 295 VReg = MRI->createVirtualRegister(RC); 296 } 297 BuildMI(*MBB, InsertPos, Op.getDebugLoc(), 298 TII->get(TargetOpcode::IMPLICIT_DEF), VReg); 299 return VReg; 300 } 301 302 DenseMap<SDValue, unsigned>::iterator I = VRBaseMap.find(Op); 303 assert(I != VRBaseMap.end() && "Node emitted out of order - late"); 304 return I->second; 305} 306 307 308/// AddRegisterOperand - Add the specified register as an operand to the 309/// specified machine instr. Insert register copies if the register is 310/// not in the required register class. 311void 312InstrEmitter::AddRegisterOperand(MachineInstrBuilder &MIB, 313 SDValue Op, 314 unsigned IIOpNum, 315 const MCInstrDesc *II, 316 DenseMap<SDValue, unsigned> &VRBaseMap, 317 bool IsDebug, bool IsClone, bool IsCloned) { 318 assert(Op.getValueType() != MVT::Other && 319 Op.getValueType() != MVT::Glue && 320 "Chain and glue operands should occur at end of operand list!"); 321 // Get/emit the operand. 322 unsigned VReg = getVR(Op, VRBaseMap); 323 324 const MCInstrDesc &MCID = MIB->getDesc(); 325 bool isOptDef = IIOpNum < MCID.getNumOperands() && 326 MCID.OpInfo[IIOpNum].isOptionalDef(); 327 328 // If the instruction requires a register in a different class, create 329 // a new virtual register and copy the value into it, but first attempt to 330 // shrink VReg's register class within reason. For example, if VReg == GR32 331 // and II requires a GR32_NOSP, just constrain VReg to GR32_NOSP. 332 if (II) { 333 const TargetRegisterClass *OpRC = nullptr; 334 if (IIOpNum < II->getNumOperands()) 335 OpRC = TII->getRegClass(*II, IIOpNum, TRI, *MF); 336 337 if (OpRC) { 338 const TargetRegisterClass *ConstrainedRC 339 = MRI->constrainRegClass(VReg, OpRC, MinRCSize); 340 if (!ConstrainedRC) { 341 OpRC = TRI->getAllocatableClass(OpRC); 342 assert(OpRC && "Constraints cannot be fulfilled for allocation"); 343 unsigned NewVReg = MRI->createVirtualRegister(OpRC); 344 BuildMI(*MBB, InsertPos, Op.getNode()->getDebugLoc(), 345 TII->get(TargetOpcode::COPY), NewVReg).addReg(VReg); 346 VReg = NewVReg; 347 } else { 348 assert(ConstrainedRC->isAllocatable() && 349 "Constraining an allocatable VReg produced an unallocatable class?"); 350 } 351 } 352 } 353 354 // If this value has only one use, that use is a kill. This is a 355 // conservative approximation. InstrEmitter does trivial coalescing 356 // with CopyFromReg nodes, so don't emit kill flags for them. 357 // Avoid kill flags on Schedule cloned nodes, since there will be 358 // multiple uses. 359 // Tied operands are never killed, so we need to check that. And that 360 // means we need to determine the index of the operand. 361 bool isKill = Op.hasOneUse() && 362 Op.getNode()->getOpcode() != ISD::CopyFromReg && 363 !IsDebug && 364 !(IsClone || IsCloned); 365 if (isKill) { 366 unsigned Idx = MIB->getNumOperands(); 367 while (Idx > 0 && 368 MIB->getOperand(Idx-1).isReg() && 369 MIB->getOperand(Idx-1).isImplicit()) 370 --Idx; 371 bool isTied = MCID.getOperandConstraint(Idx, MCOI::TIED_TO) != -1; 372 if (isTied) 373 isKill = false; 374 } 375 376 MIB.addReg(VReg, getDefRegState(isOptDef) | getKillRegState(isKill) | 377 getDebugRegState(IsDebug)); 378} 379 380/// AddOperand - Add the specified operand to the specified machine instr. II 381/// specifies the instruction information for the node, and IIOpNum is the 382/// operand number (in the II) that we are adding. 383void InstrEmitter::AddOperand(MachineInstrBuilder &MIB, 384 SDValue Op, 385 unsigned IIOpNum, 386 const MCInstrDesc *II, 387 DenseMap<SDValue, unsigned> &VRBaseMap, 388 bool IsDebug, bool IsClone, bool IsCloned) { 389 if (Op.isMachineOpcode()) { 390 AddRegisterOperand(MIB, Op, IIOpNum, II, VRBaseMap, 391 IsDebug, IsClone, IsCloned); 392 } else if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 393 MIB.addImm(C->getSExtValue()); 394 } else if (ConstantFPSDNode *F = dyn_cast<ConstantFPSDNode>(Op)) { 395 MIB.addFPImm(F->getConstantFPValue()); 396 } else if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(Op)) { 397 // Turn additional physreg operands into implicit uses on non-variadic 398 // instructions. This is used by call and return instructions passing 399 // arguments in registers. 400 bool Imp = II && (IIOpNum >= II->getNumOperands() && !II->isVariadic()); 401 MIB.addReg(R->getReg(), getImplRegState(Imp)); 402 } else if (RegisterMaskSDNode *RM = dyn_cast<RegisterMaskSDNode>(Op)) { 403 MIB.addRegMask(RM->getRegMask()); 404 } else if (GlobalAddressSDNode *TGA = dyn_cast<GlobalAddressSDNode>(Op)) { 405 MIB.addGlobalAddress(TGA->getGlobal(), TGA->getOffset(), 406 TGA->getTargetFlags()); 407 } else if (BasicBlockSDNode *BBNode = dyn_cast<BasicBlockSDNode>(Op)) { 408 MIB.addMBB(BBNode->getBasicBlock()); 409 } else if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(Op)) { 410 MIB.addFrameIndex(FI->getIndex()); 411 } else if (JumpTableSDNode *JT = dyn_cast<JumpTableSDNode>(Op)) { 412 MIB.addJumpTableIndex(JT->getIndex(), JT->getTargetFlags()); 413 } else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op)) { 414 int Offset = CP->getOffset(); 415 unsigned Align = CP->getAlignment(); 416 Type *Type = CP->getType(); 417 // MachineConstantPool wants an explicit alignment. 418 if (Align == 0) { 419 Align = MF->getDataLayout().getPrefTypeAlignment(Type); 420 if (Align == 0) { 421 // Alignment of vector types. FIXME! 422 Align = MF->getDataLayout().getTypeAllocSize(Type); 423 } 424 } 425 426 unsigned Idx; 427 MachineConstantPool *MCP = MF->getConstantPool(); 428 if (CP->isMachineConstantPoolEntry()) 429 Idx = MCP->getConstantPoolIndex(CP->getMachineCPVal(), Align); 430 else 431 Idx = MCP->getConstantPoolIndex(CP->getConstVal(), Align); 432 MIB.addConstantPoolIndex(Idx, Offset, CP->getTargetFlags()); 433 } else if (ExternalSymbolSDNode *ES = dyn_cast<ExternalSymbolSDNode>(Op)) { 434 MIB.addExternalSymbol(ES->getSymbol(), ES->getTargetFlags()); 435 } else if (auto *SymNode = dyn_cast<MCSymbolSDNode>(Op)) { 436 MIB.addSym(SymNode->getMCSymbol()); 437 } else if (BlockAddressSDNode *BA = dyn_cast<BlockAddressSDNode>(Op)) { 438 MIB.addBlockAddress(BA->getBlockAddress(), 439 BA->getOffset(), 440 BA->getTargetFlags()); 441 } else if (TargetIndexSDNode *TI = dyn_cast<TargetIndexSDNode>(Op)) { 442 MIB.addTargetIndex(TI->getIndex(), TI->getOffset(), TI->getTargetFlags()); 443 } else { 444 assert(Op.getValueType() != MVT::Other && 445 Op.getValueType() != MVT::Glue && 446 "Chain and glue operands should occur at end of operand list!"); 447 AddRegisterOperand(MIB, Op, IIOpNum, II, VRBaseMap, 448 IsDebug, IsClone, IsCloned); 449 } 450} 451 452unsigned InstrEmitter::ConstrainForSubReg(unsigned VReg, unsigned SubIdx, 453 MVT VT, const DebugLoc &DL) { 454 const TargetRegisterClass *VRC = MRI->getRegClass(VReg); 455 const TargetRegisterClass *RC = TRI->getSubClassWithSubReg(VRC, SubIdx); 456 457 // RC is a sub-class of VRC that supports SubIdx. Try to constrain VReg 458 // within reason. 459 if (RC && RC != VRC) 460 RC = MRI->constrainRegClass(VReg, RC, MinRCSize); 461 462 // VReg has been adjusted. It can be used with SubIdx operands now. 463 if (RC) 464 return VReg; 465 466 // VReg couldn't be reasonably constrained. Emit a COPY to a new virtual 467 // register instead. 468 RC = TRI->getSubClassWithSubReg(TLI->getRegClassFor(VT), SubIdx); 469 assert(RC && "No legal register class for VT supports that SubIdx"); 470 unsigned NewReg = MRI->createVirtualRegister(RC); 471 BuildMI(*MBB, InsertPos, DL, TII->get(TargetOpcode::COPY), NewReg) 472 .addReg(VReg); 473 return NewReg; 474} 475 476/// EmitSubregNode - Generate machine code for subreg nodes. 477/// 478void InstrEmitter::EmitSubregNode(SDNode *Node, 479 DenseMap<SDValue, unsigned> &VRBaseMap, 480 bool IsClone, bool IsCloned) { 481 unsigned VRBase = 0; 482 unsigned Opc = Node->getMachineOpcode(); 483 484 // If the node is only used by a CopyToReg and the dest reg is a vreg, use 485 // the CopyToReg'd destination register instead of creating a new vreg. 486 for (SDNode *User : Node->uses()) { 487 if (User->getOpcode() == ISD::CopyToReg && 488 User->getOperand(2).getNode() == Node) { 489 unsigned DestReg = cast<RegisterSDNode>(User->getOperand(1))->getReg(); 490 if (TargetRegisterInfo::isVirtualRegister(DestReg)) { 491 VRBase = DestReg; 492 break; 493 } 494 } 495 } 496 497 if (Opc == TargetOpcode::EXTRACT_SUBREG) { 498 // EXTRACT_SUBREG is lowered as %dst = COPY %src:sub. There are no 499 // constraints on the %dst register, COPY can target all legal register 500 // classes. 501 unsigned SubIdx = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue(); 502 const TargetRegisterClass *TRC = 503 TLI->getRegClassFor(Node->getSimpleValueType(0)); 504 505 unsigned Reg; 506 MachineInstr *DefMI; 507 RegisterSDNode *R = dyn_cast<RegisterSDNode>(Node->getOperand(0)); 508 if (R && TargetRegisterInfo::isPhysicalRegister(R->getReg())) { 509 Reg = R->getReg(); 510 DefMI = nullptr; 511 } else { 512 Reg = getVR(Node->getOperand(0), VRBaseMap); 513 DefMI = MRI->getVRegDef(Reg); 514 } 515 516 unsigned SrcReg, DstReg, DefSubIdx; 517 if (DefMI && 518 TII->isCoalescableExtInstr(*DefMI, SrcReg, DstReg, DefSubIdx) && 519 SubIdx == DefSubIdx && 520 TRC == MRI->getRegClass(SrcReg)) { 521 // Optimize these: 522 // r1025 = s/zext r1024, 4 523 // r1026 = extract_subreg r1025, 4 524 // to a copy 525 // r1026 = copy r1024 526 VRBase = MRI->createVirtualRegister(TRC); 527 BuildMI(*MBB, InsertPos, Node->getDebugLoc(), 528 TII->get(TargetOpcode::COPY), VRBase).addReg(SrcReg); 529 MRI->clearKillFlags(SrcReg); 530 } else { 531 // Reg may not support a SubIdx sub-register, and we may need to 532 // constrain its register class or issue a COPY to a compatible register 533 // class. 534 if (TargetRegisterInfo::isVirtualRegister(Reg)) 535 Reg = ConstrainForSubReg(Reg, SubIdx, 536 Node->getOperand(0).getSimpleValueType(), 537 Node->getDebugLoc()); 538 539 // Create the destreg if it is missing. 540 if (VRBase == 0) 541 VRBase = MRI->createVirtualRegister(TRC); 542 543 // Create the extract_subreg machine instruction. 544 MachineInstrBuilder CopyMI = 545 BuildMI(*MBB, InsertPos, Node->getDebugLoc(), 546 TII->get(TargetOpcode::COPY), VRBase); 547 if (TargetRegisterInfo::isVirtualRegister(Reg)) 548 CopyMI.addReg(Reg, 0, SubIdx); 549 else 550 CopyMI.addReg(TRI->getSubReg(Reg, SubIdx)); 551 } 552 } else if (Opc == TargetOpcode::INSERT_SUBREG || 553 Opc == TargetOpcode::SUBREG_TO_REG) { 554 SDValue N0 = Node->getOperand(0); 555 SDValue N1 = Node->getOperand(1); 556 SDValue N2 = Node->getOperand(2); 557 unsigned SubIdx = cast<ConstantSDNode>(N2)->getZExtValue(); 558 559 // Figure out the register class to create for the destreg. It should be 560 // the largest legal register class supporting SubIdx sub-registers. 561 // RegisterCoalescer will constrain it further if it decides to eliminate 562 // the INSERT_SUBREG instruction. 563 // 564 // %dst = INSERT_SUBREG %src, %sub, SubIdx 565 // 566 // is lowered by TwoAddressInstructionPass to: 567 // 568 // %dst = COPY %src 569 // %dst:SubIdx = COPY %sub 570 // 571 // There is no constraint on the %src register class. 572 // 573 const TargetRegisterClass *SRC = TLI->getRegClassFor(Node->getSimpleValueType(0)); 574 SRC = TRI->getSubClassWithSubReg(SRC, SubIdx); 575 assert(SRC && "No register class supports VT and SubIdx for INSERT_SUBREG"); 576 577 if (VRBase == 0 || !SRC->hasSubClassEq(MRI->getRegClass(VRBase))) 578 VRBase = MRI->createVirtualRegister(SRC); 579 580 // Create the insert_subreg or subreg_to_reg machine instruction. 581 MachineInstrBuilder MIB = 582 BuildMI(*MF, Node->getDebugLoc(), TII->get(Opc), VRBase); 583 584 // If creating a subreg_to_reg, then the first input operand 585 // is an implicit value immediate, otherwise it's a register 586 if (Opc == TargetOpcode::SUBREG_TO_REG) { 587 const ConstantSDNode *SD = cast<ConstantSDNode>(N0); 588 MIB.addImm(SD->getZExtValue()); 589 } else 590 AddOperand(MIB, N0, 0, nullptr, VRBaseMap, /*IsDebug=*/false, 591 IsClone, IsCloned); 592 // Add the subregister being inserted 593 AddOperand(MIB, N1, 0, nullptr, VRBaseMap, /*IsDebug=*/false, 594 IsClone, IsCloned); 595 MIB.addImm(SubIdx); 596 MBB->insert(InsertPos, MIB); 597 } else 598 llvm_unreachable("Node is not insert_subreg, extract_subreg, or subreg_to_reg"); 599 600 SDValue Op(Node, 0); 601 bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBase)).second; 602 (void)isNew; // Silence compiler warning. 603 assert(isNew && "Node emitted out of order - early"); 604} 605 606/// EmitCopyToRegClassNode - Generate machine code for COPY_TO_REGCLASS nodes. 607/// COPY_TO_REGCLASS is just a normal copy, except that the destination 608/// register is constrained to be in a particular register class. 609/// 610void 611InstrEmitter::EmitCopyToRegClassNode(SDNode *Node, 612 DenseMap<SDValue, unsigned> &VRBaseMap) { 613 unsigned VReg = getVR(Node->getOperand(0), VRBaseMap); 614 615 // Create the new VReg in the destination class and emit a copy. 616 unsigned DstRCIdx = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue(); 617 const TargetRegisterClass *DstRC = 618 TRI->getAllocatableClass(TRI->getRegClass(DstRCIdx)); 619 unsigned NewVReg = MRI->createVirtualRegister(DstRC); 620 BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->get(TargetOpcode::COPY), 621 NewVReg).addReg(VReg); 622 623 SDValue Op(Node, 0); 624 bool isNew = VRBaseMap.insert(std::make_pair(Op, NewVReg)).second; 625 (void)isNew; // Silence compiler warning. 626 assert(isNew && "Node emitted out of order - early"); 627} 628 629/// EmitRegSequence - Generate machine code for REG_SEQUENCE nodes. 630/// 631void InstrEmitter::EmitRegSequence(SDNode *Node, 632 DenseMap<SDValue, unsigned> &VRBaseMap, 633 bool IsClone, bool IsCloned) { 634 unsigned DstRCIdx = cast<ConstantSDNode>(Node->getOperand(0))->getZExtValue(); 635 const TargetRegisterClass *RC = TRI->getRegClass(DstRCIdx); 636 unsigned NewVReg = MRI->createVirtualRegister(TRI->getAllocatableClass(RC)); 637 const MCInstrDesc &II = TII->get(TargetOpcode::REG_SEQUENCE); 638 MachineInstrBuilder MIB = BuildMI(*MF, Node->getDebugLoc(), II, NewVReg); 639 unsigned NumOps = Node->getNumOperands(); 640 assert((NumOps & 1) == 1 && 641 "REG_SEQUENCE must have an odd number of operands!"); 642 for (unsigned i = 1; i != NumOps; ++i) { 643 SDValue Op = Node->getOperand(i); 644 if ((i & 1) == 0) { 645 RegisterSDNode *R = dyn_cast<RegisterSDNode>(Node->getOperand(i-1)); 646 // Skip physical registers as they don't have a vreg to get and we'll 647 // insert copies for them in TwoAddressInstructionPass anyway. 648 if (!R || !TargetRegisterInfo::isPhysicalRegister(R->getReg())) { 649 unsigned SubIdx = cast<ConstantSDNode>(Op)->getZExtValue(); 650 unsigned SubReg = getVR(Node->getOperand(i-1), VRBaseMap); 651 const TargetRegisterClass *TRC = MRI->getRegClass(SubReg); 652 const TargetRegisterClass *SRC = 653 TRI->getMatchingSuperRegClass(RC, TRC, SubIdx); 654 if (SRC && SRC != RC) { 655 MRI->setRegClass(NewVReg, SRC); 656 RC = SRC; 657 } 658 } 659 } 660 AddOperand(MIB, Op, i+1, &II, VRBaseMap, /*IsDebug=*/false, 661 IsClone, IsCloned); 662 } 663 664 MBB->insert(InsertPos, MIB); 665 SDValue Op(Node, 0); 666 bool isNew = VRBaseMap.insert(std::make_pair(Op, NewVReg)).second; 667 (void)isNew; // Silence compiler warning. 668 assert(isNew && "Node emitted out of order - early"); 669} 670 671/// EmitDbgValue - Generate machine instruction for a dbg_value node. 672/// 673MachineInstr * 674InstrEmitter::EmitDbgValue(SDDbgValue *SD, 675 DenseMap<SDValue, unsigned> &VRBaseMap) { 676 MDNode *Var = SD->getVariable(); 677 MDNode *Expr = SD->getExpression(); 678 DebugLoc DL = SD->getDebugLoc(); 679 assert(cast<DILocalVariable>(Var)->isValidLocationForIntrinsic(DL) && 680 "Expected inlined-at fields to agree"); 681 682 if (SD->getKind() == SDDbgValue::FRAMEIX) { 683 // Stack address; this needs to be lowered in target-dependent fashion. 684 // EmitTargetCodeForFrameDebugValue is responsible for allocation. 685 return BuildMI(*MF, DL, TII->get(TargetOpcode::DBG_VALUE)) 686 .addFrameIndex(SD->getFrameIx()) 687 .addImm(0) 688 .addMetadata(Var) 689 .addMetadata(Expr); 690 } 691 // Otherwise, we're going to create an instruction here. 692 const MCInstrDesc &II = TII->get(TargetOpcode::DBG_VALUE); 693 MachineInstrBuilder MIB = BuildMI(*MF, DL, II); 694 if (SD->getKind() == SDDbgValue::SDNODE) { 695 SDNode *Node = SD->getSDNode(); 696 SDValue Op = SDValue(Node, SD->getResNo()); 697 // It's possible we replaced this SDNode with other(s) and therefore 698 // didn't generate code for it. It's better to catch these cases where 699 // they happen and transfer the debug info, but trying to guarantee that 700 // in all cases would be very fragile; this is a safeguard for any 701 // that were missed. 702 DenseMap<SDValue, unsigned>::iterator I = VRBaseMap.find(Op); 703 if (I==VRBaseMap.end()) 704 MIB.addReg(0U); // undef 705 else 706 AddOperand(MIB, Op, (*MIB).getNumOperands(), &II, VRBaseMap, 707 /*IsDebug=*/true, /*IsClone=*/false, /*IsCloned=*/false); 708 } else if (SD->getKind() == SDDbgValue::CONST) { 709 const Value *V = SD->getConst(); 710 if (const ConstantInt *CI = dyn_cast<ConstantInt>(V)) { 711 if (CI->getBitWidth() > 64) 712 MIB.addCImm(CI); 713 else 714 MIB.addImm(CI->getSExtValue()); 715 } else if (const ConstantFP *CF = dyn_cast<ConstantFP>(V)) { 716 MIB.addFPImm(CF); 717 } else { 718 // Could be an Undef. In any case insert an Undef so we can see what we 719 // dropped. 720 MIB.addReg(0U); 721 } 722 } else { 723 // Insert an Undef so we can see what we dropped. 724 MIB.addReg(0U); 725 } 726 727 // Indirect addressing is indicated by an Imm as the second parameter. 728 if (SD->isIndirect()) 729 MIB.addImm(0U); 730 else 731 MIB.addReg(0U, RegState::Debug); 732 733 MIB.addMetadata(Var); 734 MIB.addMetadata(Expr); 735 736 return &*MIB; 737} 738 739/// EmitMachineNode - Generate machine code for a target-specific node and 740/// needed dependencies. 741/// 742void InstrEmitter:: 743EmitMachineNode(SDNode *Node, bool IsClone, bool IsCloned, 744 DenseMap<SDValue, unsigned> &VRBaseMap) { 745 unsigned Opc = Node->getMachineOpcode(); 746 747 // Handle subreg insert/extract specially 748 if (Opc == TargetOpcode::EXTRACT_SUBREG || 749 Opc == TargetOpcode::INSERT_SUBREG || 750 Opc == TargetOpcode::SUBREG_TO_REG) { 751 EmitSubregNode(Node, VRBaseMap, IsClone, IsCloned); 752 return; 753 } 754 755 // Handle COPY_TO_REGCLASS specially. 756 if (Opc == TargetOpcode::COPY_TO_REGCLASS) { 757 EmitCopyToRegClassNode(Node, VRBaseMap); 758 return; 759 } 760 761 // Handle REG_SEQUENCE specially. 762 if (Opc == TargetOpcode::REG_SEQUENCE) { 763 EmitRegSequence(Node, VRBaseMap, IsClone, IsCloned); 764 return; 765 } 766 767 if (Opc == TargetOpcode::IMPLICIT_DEF) 768 // We want a unique VR for each IMPLICIT_DEF use. 769 return; 770 771 const MCInstrDesc &II = TII->get(Opc); 772 unsigned NumResults = CountResults(Node); 773 unsigned NumDefs = II.getNumDefs(); 774 const MCPhysReg *ScratchRegs = nullptr; 775 776 // Handle STACKMAP and PATCHPOINT specially and then use the generic code. 777 if (Opc == TargetOpcode::STACKMAP || Opc == TargetOpcode::PATCHPOINT) { 778 // Stackmaps do not have arguments and do not preserve their calling 779 // convention. However, to simplify runtime support, they clobber the same 780 // scratch registers as AnyRegCC. 781 unsigned CC = CallingConv::AnyReg; 782 if (Opc == TargetOpcode::PATCHPOINT) { 783 CC = Node->getConstantOperandVal(PatchPointOpers::CCPos); 784 NumDefs = NumResults; 785 } 786 ScratchRegs = TLI->getScratchRegisters((CallingConv::ID) CC); 787 } 788 789 unsigned NumImpUses = 0; 790 unsigned NodeOperands = 791 countOperands(Node, II.getNumOperands() - NumDefs, NumImpUses); 792 bool HasPhysRegOuts = NumResults > NumDefs && II.getImplicitDefs()!=nullptr; 793#ifndef NDEBUG 794 unsigned NumMIOperands = NodeOperands + NumResults; 795 if (II.isVariadic()) 796 assert(NumMIOperands >= II.getNumOperands() && 797 "Too few operands for a variadic node!"); 798 else 799 assert(NumMIOperands >= II.getNumOperands() && 800 NumMIOperands <= II.getNumOperands() + II.getNumImplicitDefs() + 801 NumImpUses && 802 "#operands for dag node doesn't match .td file!"); 803#endif 804 805 // Create the new machine instruction. 806 MachineInstrBuilder MIB = BuildMI(*MF, Node->getDebugLoc(), II); 807 808 // Add result register values for things that are defined by this 809 // instruction. 810 if (NumResults) 811 CreateVirtualRegisters(Node, MIB, II, IsClone, IsCloned, VRBaseMap); 812 813 // Emit all of the actual operands of this instruction, adding them to the 814 // instruction as appropriate. 815 bool HasOptPRefs = NumDefs > NumResults; 816 assert((!HasOptPRefs || !HasPhysRegOuts) && 817 "Unable to cope with optional defs and phys regs defs!"); 818 unsigned NumSkip = HasOptPRefs ? NumDefs - NumResults : 0; 819 for (unsigned i = NumSkip; i != NodeOperands; ++i) 820 AddOperand(MIB, Node->getOperand(i), i-NumSkip+NumDefs, &II, 821 VRBaseMap, /*IsDebug=*/false, IsClone, IsCloned); 822 823 // Add scratch registers as implicit def and early clobber 824 if (ScratchRegs) 825 for (unsigned i = 0; ScratchRegs[i]; ++i) 826 MIB.addReg(ScratchRegs[i], RegState::ImplicitDefine | 827 RegState::EarlyClobber); 828 829 // Transfer all of the memory reference descriptions of this instruction. 830 MIB.setMemRefs(cast<MachineSDNode>(Node)->memoperands_begin(), 831 cast<MachineSDNode>(Node)->memoperands_end()); 832 833 // Insert the instruction into position in the block. This needs to 834 // happen before any custom inserter hook is called so that the 835 // hook knows where in the block to insert the replacement code. 836 MBB->insert(InsertPos, MIB); 837 838 // The MachineInstr may also define physregs instead of virtregs. These 839 // physreg values can reach other instructions in different ways: 840 // 841 // 1. When there is a use of a Node value beyond the explicitly defined 842 // virtual registers, we emit a CopyFromReg for one of the implicitly 843 // defined physregs. This only happens when HasPhysRegOuts is true. 844 // 845 // 2. A CopyFromReg reading a physreg may be glued to this instruction. 846 // 847 // 3. A glued instruction may implicitly use a physreg. 848 // 849 // 4. A glued instruction may use a RegisterSDNode operand. 850 // 851 // Collect all the used physreg defs, and make sure that any unused physreg 852 // defs are marked as dead. 853 SmallVector<unsigned, 8> UsedRegs; 854 855 // Additional results must be physical register defs. 856 if (HasPhysRegOuts) { 857 for (unsigned i = NumDefs; i < NumResults; ++i) { 858 unsigned Reg = II.getImplicitDefs()[i - NumDefs]; 859 if (!Node->hasAnyUseOfValue(i)) 860 continue; 861 // This implicitly defined physreg has a use. 862 UsedRegs.push_back(Reg); 863 EmitCopyFromReg(Node, i, IsClone, IsCloned, Reg, VRBaseMap); 864 } 865 } 866 867 // Scan the glue chain for any used physregs. 868 if (Node->getValueType(Node->getNumValues()-1) == MVT::Glue) { 869 for (SDNode *F = Node->getGluedUser(); F; F = F->getGluedUser()) { 870 if (F->getOpcode() == ISD::CopyFromReg) { 871 UsedRegs.push_back(cast<RegisterSDNode>(F->getOperand(1))->getReg()); 872 continue; 873 } else if (F->getOpcode() == ISD::CopyToReg) { 874 // Skip CopyToReg nodes that are internal to the glue chain. 875 continue; 876 } 877 // Collect declared implicit uses. 878 const MCInstrDesc &MCID = TII->get(F->getMachineOpcode()); 879 UsedRegs.append(MCID.getImplicitUses(), 880 MCID.getImplicitUses() + MCID.getNumImplicitUses()); 881 // In addition to declared implicit uses, we must also check for 882 // direct RegisterSDNode operands. 883 for (unsigned i = 0, e = F->getNumOperands(); i != e; ++i) 884 if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(F->getOperand(i))) { 885 unsigned Reg = R->getReg(); 886 if (TargetRegisterInfo::isPhysicalRegister(Reg)) 887 UsedRegs.push_back(Reg); 888 } 889 } 890 } 891 892 // Finally mark unused registers as dead. 893 if (!UsedRegs.empty() || II.getImplicitDefs()) 894 MIB->setPhysRegsDeadExcept(UsedRegs, *TRI); 895 896 // Run post-isel target hook to adjust this instruction if needed. 897 if (II.hasPostISelHook()) 898 TLI->AdjustInstrPostInstrSelection(*MIB, Node); 899} 900 901/// EmitSpecialNode - Generate machine code for a target-independent node and 902/// needed dependencies. 903void InstrEmitter:: 904EmitSpecialNode(SDNode *Node, bool IsClone, bool IsCloned, 905 DenseMap<SDValue, unsigned> &VRBaseMap) { 906 switch (Node->getOpcode()) { 907 default: 908#ifndef NDEBUG 909 Node->dump(); 910#endif 911 llvm_unreachable("This target-independent node should have been selected!"); 912 case ISD::EntryToken: 913 llvm_unreachable("EntryToken should have been excluded from the schedule!"); 914 case ISD::MERGE_VALUES: 915 case ISD::TokenFactor: // fall thru 916 break; 917 case ISD::CopyToReg: { 918 unsigned SrcReg; 919 SDValue SrcVal = Node->getOperand(2); 920 if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(SrcVal)) 921 SrcReg = R->getReg(); 922 else 923 SrcReg = getVR(SrcVal, VRBaseMap); 924 925 unsigned DestReg = cast<RegisterSDNode>(Node->getOperand(1))->getReg(); 926 if (SrcReg == DestReg) // Coalesced away the copy? Ignore. 927 break; 928 929 BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->get(TargetOpcode::COPY), 930 DestReg).addReg(SrcReg); 931 break; 932 } 933 case ISD::CopyFromReg: { 934 unsigned SrcReg = cast<RegisterSDNode>(Node->getOperand(1))->getReg(); 935 EmitCopyFromReg(Node, 0, IsClone, IsCloned, SrcReg, VRBaseMap); 936 break; 937 } 938 case ISD::EH_LABEL: 939 case ISD::ANNOTATION_LABEL: { 940 unsigned Opc = (Node->getOpcode() == ISD::EH_LABEL) 941 ? TargetOpcode::EH_LABEL 942 : TargetOpcode::ANNOTATION_LABEL; 943 MCSymbol *S = cast<LabelSDNode>(Node)->getLabel(); 944 BuildMI(*MBB, InsertPos, Node->getDebugLoc(), 945 TII->get(Opc)).addSym(S); 946 break; 947 } 948 949 case ISD::LIFETIME_START: 950 case ISD::LIFETIME_END: { 951 unsigned TarOp = (Node->getOpcode() == ISD::LIFETIME_START) ? 952 TargetOpcode::LIFETIME_START : TargetOpcode::LIFETIME_END; 953 954 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(Node->getOperand(1)); 955 BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->get(TarOp)) 956 .addFrameIndex(FI->getIndex()); 957 break; 958 } 959 960 case ISD::INLINEASM: { 961 unsigned NumOps = Node->getNumOperands(); 962 if (Node->getOperand(NumOps-1).getValueType() == MVT::Glue) 963 --NumOps; // Ignore the glue operand. 964 965 // Create the inline asm machine instruction. 966 MachineInstrBuilder MIB = BuildMI(*MF, Node->getDebugLoc(), 967 TII->get(TargetOpcode::INLINEASM)); 968 969 // Add the asm string as an external symbol operand. 970 SDValue AsmStrV = Node->getOperand(InlineAsm::Op_AsmString); 971 const char *AsmStr = cast<ExternalSymbolSDNode>(AsmStrV)->getSymbol(); 972 MIB.addExternalSymbol(AsmStr); 973 974 // Add the HasSideEffect, isAlignStack, AsmDialect, MayLoad and MayStore 975 // bits. 976 int64_t ExtraInfo = 977 cast<ConstantSDNode>(Node->getOperand(InlineAsm::Op_ExtraInfo))-> 978 getZExtValue(); 979 MIB.addImm(ExtraInfo); 980 981 // Remember to operand index of the group flags. 982 SmallVector<unsigned, 8> GroupIdx; 983 984 // Remember registers that are part of early-clobber defs. 985 SmallVector<unsigned, 8> ECRegs; 986 987 // Add all of the operand registers to the instruction. 988 for (unsigned i = InlineAsm::Op_FirstOperand; i != NumOps;) { 989 unsigned Flags = 990 cast<ConstantSDNode>(Node->getOperand(i))->getZExtValue(); 991 const unsigned NumVals = InlineAsm::getNumOperandRegisters(Flags); 992 993 GroupIdx.push_back(MIB->getNumOperands()); 994 MIB.addImm(Flags); 995 ++i; // Skip the ID value. 996 997 switch (InlineAsm::getKind(Flags)) { 998 default: llvm_unreachable("Bad flags!"); 999 case InlineAsm::Kind_RegDef: 1000 for (unsigned j = 0; j != NumVals; ++j, ++i) { 1001 unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg(); 1002 // FIXME: Add dead flags for physical and virtual registers defined. 1003 // For now, mark physical register defs as implicit to help fast 1004 // regalloc. This makes inline asm look a lot like calls. 1005 MIB.addReg(Reg, RegState::Define | 1006 getImplRegState(TargetRegisterInfo::isPhysicalRegister(Reg))); 1007 } 1008 break; 1009 case InlineAsm::Kind_RegDefEarlyClobber: 1010 case InlineAsm::Kind_Clobber: 1011 for (unsigned j = 0; j != NumVals; ++j, ++i) { 1012 unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg(); 1013 MIB.addReg(Reg, RegState::Define | RegState::EarlyClobber | 1014 getImplRegState(TargetRegisterInfo::isPhysicalRegister(Reg))); 1015 ECRegs.push_back(Reg); 1016 } 1017 break; 1018 case InlineAsm::Kind_RegUse: // Use of register. 1019 case InlineAsm::Kind_Imm: // Immediate. 1020 case InlineAsm::Kind_Mem: // Addressing mode. 1021 // The addressing mode has been selected, just add all of the 1022 // operands to the machine instruction. 1023 for (unsigned j = 0; j != NumVals; ++j, ++i) 1024 AddOperand(MIB, Node->getOperand(i), 0, nullptr, VRBaseMap, 1025 /*IsDebug=*/false, IsClone, IsCloned); 1026 1027 // Manually set isTied bits. 1028 if (InlineAsm::getKind(Flags) == InlineAsm::Kind_RegUse) { 1029 unsigned DefGroup = 0; 1030 if (InlineAsm::isUseOperandTiedToDef(Flags, DefGroup)) { 1031 unsigned DefIdx = GroupIdx[DefGroup] + 1; 1032 unsigned UseIdx = GroupIdx.back() + 1; 1033 for (unsigned j = 0; j != NumVals; ++j) 1034 MIB->tieOperands(DefIdx + j, UseIdx + j); 1035 } 1036 } 1037 break; 1038 } 1039 } 1040 1041 // GCC inline assembly allows input operands to also be early-clobber 1042 // output operands (so long as the operand is written only after it's 1043 // used), but this does not match the semantics of our early-clobber flag. 1044 // If an early-clobber operand register is also an input operand register, 1045 // then remove the early-clobber flag. 1046 for (unsigned Reg : ECRegs) { 1047 if (MIB->readsRegister(Reg, TRI)) { 1048 MachineOperand *MO = MIB->findRegisterDefOperand(Reg, false, TRI); 1049 assert(MO && "No def operand for clobbered register?"); 1050 MO->setIsEarlyClobber(false); 1051 } 1052 } 1053 1054 // Get the mdnode from the asm if it exists and add it to the instruction. 1055 SDValue MDV = Node->getOperand(InlineAsm::Op_MDNode); 1056 const MDNode *MD = cast<MDNodeSDNode>(MDV)->getMD(); 1057 if (MD) 1058 MIB.addMetadata(MD); 1059 1060 MBB->insert(InsertPos, MIB); 1061 break; 1062 } 1063 } 1064} 1065 1066/// InstrEmitter - Construct an InstrEmitter and set it to start inserting 1067/// at the given position in the given block. 1068InstrEmitter::InstrEmitter(MachineBasicBlock *mbb, 1069 MachineBasicBlock::iterator insertpos) 1070 : MF(mbb->getParent()), MRI(&MF->getRegInfo()), 1071 TII(MF->getSubtarget().getInstrInfo()), 1072 TRI(MF->getSubtarget().getRegisterInfo()), 1073 TLI(MF->getSubtarget().getTargetLowering()), MBB(mbb), 1074 InsertPos(insertpos) {} 1075