InstrEmitter.cpp revision 198892
1//==--- InstrEmitter.cpp - Emit MachineInstrs for the SelectionDAG class ---==// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This implements the Emit routines for the SelectionDAG class, which creates 11// MachineInstrs based on the decisions of the SelectionDAG instruction 12// selection. 13// 14//===----------------------------------------------------------------------===// 15 16#define DEBUG_TYPE "instr-emitter" 17#include "InstrEmitter.h" 18#include "llvm/CodeGen/MachineConstantPool.h" 19#include "llvm/CodeGen/MachineFunction.h" 20#include "llvm/CodeGen/MachineInstrBuilder.h" 21#include "llvm/CodeGen/MachineRegisterInfo.h" 22#include "llvm/Target/TargetData.h" 23#include "llvm/Target/TargetMachine.h" 24#include "llvm/Target/TargetInstrInfo.h" 25#include "llvm/Target/TargetLowering.h" 26#include "llvm/ADT/Statistic.h" 27#include "llvm/Support/CommandLine.h" 28#include "llvm/Support/Debug.h" 29#include "llvm/Support/ErrorHandling.h" 30#include "llvm/Support/MathExtras.h" 31using namespace llvm; 32 33/// CountResults - The results of target nodes have register or immediate 34/// operands first, then an optional chain, and optional flag operands (which do 35/// not go into the resulting MachineInstr). 36unsigned InstrEmitter::CountResults(SDNode *Node) { 37 unsigned N = Node->getNumValues(); 38 while (N && Node->getValueType(N - 1) == MVT::Flag) 39 --N; 40 if (N && Node->getValueType(N - 1) == MVT::Other) 41 --N; // Skip over chain result. 42 return N; 43} 44 45/// CountOperands - The inputs to target nodes have any actual inputs first, 46/// followed by an optional chain operand, then an optional flag operand. 47/// Compute the number of actual operands that will go into the resulting 48/// MachineInstr. 49unsigned InstrEmitter::CountOperands(SDNode *Node) { 50 unsigned N = Node->getNumOperands(); 51 while (N && Node->getOperand(N - 1).getValueType() == MVT::Flag) 52 --N; 53 if (N && Node->getOperand(N - 1).getValueType() == MVT::Other) 54 --N; // Ignore chain if it exists. 55 return N; 56} 57 58/// EmitCopyFromReg - Generate machine code for an CopyFromReg node or an 59/// implicit physical register output. 60void InstrEmitter:: 61EmitCopyFromReg(SDNode *Node, unsigned ResNo, bool IsClone, bool IsCloned, 62 unsigned SrcReg, DenseMap<SDValue, unsigned> &VRBaseMap) { 63 unsigned VRBase = 0; 64 if (TargetRegisterInfo::isVirtualRegister(SrcReg)) { 65 // Just use the input register directly! 66 SDValue Op(Node, ResNo); 67 if (IsClone) 68 VRBaseMap.erase(Op); 69 bool isNew = VRBaseMap.insert(std::make_pair(Op, SrcReg)).second; 70 isNew = isNew; // Silence compiler warning. 71 assert(isNew && "Node emitted out of order - early"); 72 return; 73 } 74 75 // If the node is only used by a CopyToReg and the dest reg is a vreg, use 76 // the CopyToReg'd destination register instead of creating a new vreg. 77 bool MatchReg = true; 78 const TargetRegisterClass *UseRC = NULL; 79 if (!IsClone && !IsCloned) 80 for (SDNode::use_iterator UI = Node->use_begin(), E = Node->use_end(); 81 UI != E; ++UI) { 82 SDNode *User = *UI; 83 bool Match = true; 84 if (User->getOpcode() == ISD::CopyToReg && 85 User->getOperand(2).getNode() == Node && 86 User->getOperand(2).getResNo() == ResNo) { 87 unsigned DestReg = cast<RegisterSDNode>(User->getOperand(1))->getReg(); 88 if (TargetRegisterInfo::isVirtualRegister(DestReg)) { 89 VRBase = DestReg; 90 Match = false; 91 } else if (DestReg != SrcReg) 92 Match = false; 93 } else { 94 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) { 95 SDValue Op = User->getOperand(i); 96 if (Op.getNode() != Node || Op.getResNo() != ResNo) 97 continue; 98 EVT VT = Node->getValueType(Op.getResNo()); 99 if (VT == MVT::Other || VT == MVT::Flag) 100 continue; 101 Match = false; 102 if (User->isMachineOpcode()) { 103 const TargetInstrDesc &II = TII->get(User->getMachineOpcode()); 104 const TargetRegisterClass *RC = 0; 105 if (i+II.getNumDefs() < II.getNumOperands()) 106 RC = II.OpInfo[i+II.getNumDefs()].getRegClass(TRI); 107 if (!UseRC) 108 UseRC = RC; 109 else if (RC) { 110 const TargetRegisterClass *ComRC = getCommonSubClass(UseRC, RC); 111 // If multiple uses expect disjoint register classes, we emit 112 // copies in AddRegisterOperand. 113 if (ComRC) 114 UseRC = ComRC; 115 } 116 } 117 } 118 } 119 MatchReg &= Match; 120 if (VRBase) 121 break; 122 } 123 124 EVT VT = Node->getValueType(ResNo); 125 const TargetRegisterClass *SrcRC = 0, *DstRC = 0; 126 SrcRC = TRI->getPhysicalRegisterRegClass(SrcReg, VT); 127 128 // Figure out the register class to create for the destreg. 129 if (VRBase) { 130 DstRC = MRI->getRegClass(VRBase); 131 } else if (UseRC) { 132 assert(UseRC->hasType(VT) && "Incompatible phys register def and uses!"); 133 DstRC = UseRC; 134 } else { 135 DstRC = TLI->getRegClassFor(VT); 136 } 137 138 // If all uses are reading from the src physical register and copying the 139 // register is either impossible or very expensive, then don't create a copy. 140 if (MatchReg && SrcRC->getCopyCost() < 0) { 141 VRBase = SrcReg; 142 } else { 143 // Create the reg, emit the copy. 144 VRBase = MRI->createVirtualRegister(DstRC); 145 bool Emitted = TII->copyRegToReg(*MBB, InsertPos, VRBase, SrcReg, 146 DstRC, SrcRC); 147 148 assert(Emitted && "Unable to issue a copy instruction!\n"); 149 (void) Emitted; 150 } 151 152 SDValue Op(Node, ResNo); 153 if (IsClone) 154 VRBaseMap.erase(Op); 155 bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBase)).second; 156 isNew = isNew; // Silence compiler warning. 157 assert(isNew && "Node emitted out of order - early"); 158} 159 160/// getDstOfCopyToRegUse - If the only use of the specified result number of 161/// node is a CopyToReg, return its destination register. Return 0 otherwise. 162unsigned InstrEmitter::getDstOfOnlyCopyToRegUse(SDNode *Node, 163 unsigned ResNo) const { 164 if (!Node->hasOneUse()) 165 return 0; 166 167 SDNode *User = *Node->use_begin(); 168 if (User->getOpcode() == ISD::CopyToReg && 169 User->getOperand(2).getNode() == Node && 170 User->getOperand(2).getResNo() == ResNo) { 171 unsigned Reg = cast<RegisterSDNode>(User->getOperand(1))->getReg(); 172 if (TargetRegisterInfo::isVirtualRegister(Reg)) 173 return Reg; 174 } 175 return 0; 176} 177 178void InstrEmitter::CreateVirtualRegisters(SDNode *Node, MachineInstr *MI, 179 const TargetInstrDesc &II, 180 bool IsClone, bool IsCloned, 181 DenseMap<SDValue, unsigned> &VRBaseMap) { 182 assert(Node->getMachineOpcode() != TargetInstrInfo::IMPLICIT_DEF && 183 "IMPLICIT_DEF should have been handled as a special case elsewhere!"); 184 185 for (unsigned i = 0; i < II.getNumDefs(); ++i) { 186 // If the specific node value is only used by a CopyToReg and the dest reg 187 // is a vreg in the same register class, use the CopyToReg'd destination 188 // register instead of creating a new vreg. 189 unsigned VRBase = 0; 190 const TargetRegisterClass *RC = II.OpInfo[i].getRegClass(TRI); 191 if (II.OpInfo[i].isOptionalDef()) { 192 // Optional def must be a physical register. 193 unsigned NumResults = CountResults(Node); 194 VRBase = cast<RegisterSDNode>(Node->getOperand(i-NumResults))->getReg(); 195 assert(TargetRegisterInfo::isPhysicalRegister(VRBase)); 196 MI->addOperand(MachineOperand::CreateReg(VRBase, true)); 197 } 198 199 if (!VRBase && !IsClone && !IsCloned) 200 for (SDNode::use_iterator UI = Node->use_begin(), E = Node->use_end(); 201 UI != E; ++UI) { 202 SDNode *User = *UI; 203 if (User->getOpcode() == ISD::CopyToReg && 204 User->getOperand(2).getNode() == Node && 205 User->getOperand(2).getResNo() == i) { 206 unsigned Reg = cast<RegisterSDNode>(User->getOperand(1))->getReg(); 207 if (TargetRegisterInfo::isVirtualRegister(Reg)) { 208 const TargetRegisterClass *RegRC = MRI->getRegClass(Reg); 209 if (RegRC == RC) { 210 VRBase = Reg; 211 MI->addOperand(MachineOperand::CreateReg(Reg, true)); 212 break; 213 } 214 } 215 } 216 } 217 218 // Create the result registers for this node and add the result regs to 219 // the machine instruction. 220 if (VRBase == 0) { 221 assert(RC && "Isn't a register operand!"); 222 VRBase = MRI->createVirtualRegister(RC); 223 MI->addOperand(MachineOperand::CreateReg(VRBase, true)); 224 } 225 226 SDValue Op(Node, i); 227 if (IsClone) 228 VRBaseMap.erase(Op); 229 bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBase)).second; 230 isNew = isNew; // Silence compiler warning. 231 assert(isNew && "Node emitted out of order - early"); 232 } 233} 234 235/// getVR - Return the virtual register corresponding to the specified result 236/// of the specified node. 237unsigned InstrEmitter::getVR(SDValue Op, 238 DenseMap<SDValue, unsigned> &VRBaseMap) { 239 if (Op.isMachineOpcode() && 240 Op.getMachineOpcode() == TargetInstrInfo::IMPLICIT_DEF) { 241 // Add an IMPLICIT_DEF instruction before every use. 242 unsigned VReg = getDstOfOnlyCopyToRegUse(Op.getNode(), Op.getResNo()); 243 // IMPLICIT_DEF can produce any type of result so its TargetInstrDesc 244 // does not include operand register class info. 245 if (!VReg) { 246 const TargetRegisterClass *RC = TLI->getRegClassFor(Op.getValueType()); 247 VReg = MRI->createVirtualRegister(RC); 248 } 249 BuildMI(MBB, Op.getDebugLoc(), 250 TII->get(TargetInstrInfo::IMPLICIT_DEF), VReg); 251 return VReg; 252 } 253 254 DenseMap<SDValue, unsigned>::iterator I = VRBaseMap.find(Op); 255 assert(I != VRBaseMap.end() && "Node emitted out of order - late"); 256 return I->second; 257} 258 259 260/// AddRegisterOperand - Add the specified register as an operand to the 261/// specified machine instr. Insert register copies if the register is 262/// not in the required register class. 263void 264InstrEmitter::AddRegisterOperand(MachineInstr *MI, SDValue Op, 265 unsigned IIOpNum, 266 const TargetInstrDesc *II, 267 DenseMap<SDValue, unsigned> &VRBaseMap) { 268 assert(Op.getValueType() != MVT::Other && 269 Op.getValueType() != MVT::Flag && 270 "Chain and flag operands should occur at end of operand list!"); 271 // Get/emit the operand. 272 unsigned VReg = getVR(Op, VRBaseMap); 273 assert(TargetRegisterInfo::isVirtualRegister(VReg) && "Not a vreg?"); 274 275 const TargetInstrDesc &TID = MI->getDesc(); 276 bool isOptDef = IIOpNum < TID.getNumOperands() && 277 TID.OpInfo[IIOpNum].isOptionalDef(); 278 279 // If the instruction requires a register in a different class, create 280 // a new virtual register and copy the value into it. 281 if (II) { 282 const TargetRegisterClass *SrcRC = MRI->getRegClass(VReg); 283 const TargetRegisterClass *DstRC = 0; 284 if (IIOpNum < II->getNumOperands()) 285 DstRC = II->OpInfo[IIOpNum].getRegClass(TRI); 286 assert((DstRC || (TID.isVariadic() && IIOpNum >= TID.getNumOperands())) && 287 "Don't have operand info for this instruction!"); 288 if (DstRC && SrcRC != DstRC && !SrcRC->hasSuperClass(DstRC)) { 289 unsigned NewVReg = MRI->createVirtualRegister(DstRC); 290 bool Emitted = TII->copyRegToReg(*MBB, InsertPos, NewVReg, VReg, 291 DstRC, SrcRC); 292 assert(Emitted && "Unable to issue a copy instruction!\n"); 293 (void) Emitted; 294 VReg = NewVReg; 295 } 296 } 297 298 MI->addOperand(MachineOperand::CreateReg(VReg, isOptDef)); 299} 300 301/// AddOperand - Add the specified operand to the specified machine instr. II 302/// specifies the instruction information for the node, and IIOpNum is the 303/// operand number (in the II) that we are adding. IIOpNum and II are used for 304/// assertions only. 305void InstrEmitter::AddOperand(MachineInstr *MI, SDValue Op, 306 unsigned IIOpNum, 307 const TargetInstrDesc *II, 308 DenseMap<SDValue, unsigned> &VRBaseMap) { 309 if (Op.isMachineOpcode()) { 310 AddRegisterOperand(MI, Op, IIOpNum, II, VRBaseMap); 311 } else if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 312 MI->addOperand(MachineOperand::CreateImm(C->getSExtValue())); 313 } else if (ConstantFPSDNode *F = dyn_cast<ConstantFPSDNode>(Op)) { 314 const ConstantFP *CFP = F->getConstantFPValue(); 315 MI->addOperand(MachineOperand::CreateFPImm(CFP)); 316 } else if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(Op)) { 317 MI->addOperand(MachineOperand::CreateReg(R->getReg(), false)); 318 } else if (GlobalAddressSDNode *TGA = dyn_cast<GlobalAddressSDNode>(Op)) { 319 MI->addOperand(MachineOperand::CreateGA(TGA->getGlobal(), TGA->getOffset(), 320 TGA->getTargetFlags())); 321 } else if (BasicBlockSDNode *BBNode = dyn_cast<BasicBlockSDNode>(Op)) { 322 MI->addOperand(MachineOperand::CreateMBB(BBNode->getBasicBlock())); 323 } else if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(Op)) { 324 MI->addOperand(MachineOperand::CreateFI(FI->getIndex())); 325 } else if (JumpTableSDNode *JT = dyn_cast<JumpTableSDNode>(Op)) { 326 MI->addOperand(MachineOperand::CreateJTI(JT->getIndex(), 327 JT->getTargetFlags())); 328 } else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op)) { 329 int Offset = CP->getOffset(); 330 unsigned Align = CP->getAlignment(); 331 const Type *Type = CP->getType(); 332 // MachineConstantPool wants an explicit alignment. 333 if (Align == 0) { 334 Align = TM->getTargetData()->getPrefTypeAlignment(Type); 335 if (Align == 0) { 336 // Alignment of vector types. FIXME! 337 Align = TM->getTargetData()->getTypeAllocSize(Type); 338 } 339 } 340 341 unsigned Idx; 342 MachineConstantPool *MCP = MF->getConstantPool(); 343 if (CP->isMachineConstantPoolEntry()) 344 Idx = MCP->getConstantPoolIndex(CP->getMachineCPVal(), Align); 345 else 346 Idx = MCP->getConstantPoolIndex(CP->getConstVal(), Align); 347 MI->addOperand(MachineOperand::CreateCPI(Idx, Offset, 348 CP->getTargetFlags())); 349 } else if (ExternalSymbolSDNode *ES = dyn_cast<ExternalSymbolSDNode>(Op)) { 350 MI->addOperand(MachineOperand::CreateES(ES->getSymbol(), 351 ES->getTargetFlags())); 352 } else if (BlockAddressSDNode *BA = dyn_cast<BlockAddressSDNode>(Op)) { 353 MI->addOperand(MachineOperand::CreateBA(BA->getBlockAddress())); 354 } else { 355 assert(Op.getValueType() != MVT::Other && 356 Op.getValueType() != MVT::Flag && 357 "Chain and flag operands should occur at end of operand list!"); 358 AddRegisterOperand(MI, Op, IIOpNum, II, VRBaseMap); 359 } 360} 361 362/// getSuperRegisterRegClass - Returns the register class of a superreg A whose 363/// "SubIdx"'th sub-register class is the specified register class and whose 364/// type matches the specified type. 365static const TargetRegisterClass* 366getSuperRegisterRegClass(const TargetRegisterClass *TRC, 367 unsigned SubIdx, EVT VT) { 368 // Pick the register class of the superegister for this type 369 for (TargetRegisterInfo::regclass_iterator I = TRC->superregclasses_begin(), 370 E = TRC->superregclasses_end(); I != E; ++I) 371 if ((*I)->hasType(VT) && (*I)->getSubRegisterRegClass(SubIdx) == TRC) 372 return *I; 373 assert(false && "Couldn't find the register class"); 374 return 0; 375} 376 377/// EmitSubregNode - Generate machine code for subreg nodes. 378/// 379void InstrEmitter::EmitSubregNode(SDNode *Node, 380 DenseMap<SDValue, unsigned> &VRBaseMap){ 381 unsigned VRBase = 0; 382 unsigned Opc = Node->getMachineOpcode(); 383 384 // If the node is only used by a CopyToReg and the dest reg is a vreg, use 385 // the CopyToReg'd destination register instead of creating a new vreg. 386 for (SDNode::use_iterator UI = Node->use_begin(), E = Node->use_end(); 387 UI != E; ++UI) { 388 SDNode *User = *UI; 389 if (User->getOpcode() == ISD::CopyToReg && 390 User->getOperand(2).getNode() == Node) { 391 unsigned DestReg = cast<RegisterSDNode>(User->getOperand(1))->getReg(); 392 if (TargetRegisterInfo::isVirtualRegister(DestReg)) { 393 VRBase = DestReg; 394 break; 395 } 396 } 397 } 398 399 if (Opc == TargetInstrInfo::EXTRACT_SUBREG) { 400 unsigned SubIdx = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue(); 401 402 // Create the extract_subreg machine instruction. 403 MachineInstr *MI = BuildMI(*MF, Node->getDebugLoc(), 404 TII->get(TargetInstrInfo::EXTRACT_SUBREG)); 405 406 // Figure out the register class to create for the destreg. 407 unsigned VReg = getVR(Node->getOperand(0), VRBaseMap); 408 const TargetRegisterClass *TRC = MRI->getRegClass(VReg); 409 const TargetRegisterClass *SRC = TRC->getSubRegisterRegClass(SubIdx); 410 assert(SRC && "Invalid subregister index in EXTRACT_SUBREG"); 411 412 // Figure out the register class to create for the destreg. 413 // Note that if we're going to directly use an existing register, 414 // it must be precisely the required class, and not a subclass 415 // thereof. 416 if (VRBase == 0 || SRC != MRI->getRegClass(VRBase)) { 417 // Create the reg 418 assert(SRC && "Couldn't find source register class"); 419 VRBase = MRI->createVirtualRegister(SRC); 420 } 421 422 // Add def, source, and subreg index 423 MI->addOperand(MachineOperand::CreateReg(VRBase, true)); 424 AddOperand(MI, Node->getOperand(0), 0, 0, VRBaseMap); 425 MI->addOperand(MachineOperand::CreateImm(SubIdx)); 426 MBB->insert(InsertPos, MI); 427 } else if (Opc == TargetInstrInfo::INSERT_SUBREG || 428 Opc == TargetInstrInfo::SUBREG_TO_REG) { 429 SDValue N0 = Node->getOperand(0); 430 SDValue N1 = Node->getOperand(1); 431 SDValue N2 = Node->getOperand(2); 432 unsigned SubReg = getVR(N1, VRBaseMap); 433 unsigned SubIdx = cast<ConstantSDNode>(N2)->getZExtValue(); 434 const TargetRegisterClass *TRC = MRI->getRegClass(SubReg); 435 const TargetRegisterClass *SRC = 436 getSuperRegisterRegClass(TRC, SubIdx, 437 Node->getValueType(0)); 438 439 // Figure out the register class to create for the destreg. 440 // Note that if we're going to directly use an existing register, 441 // it must be precisely the required class, and not a subclass 442 // thereof. 443 if (VRBase == 0 || SRC != MRI->getRegClass(VRBase)) { 444 // Create the reg 445 assert(SRC && "Couldn't find source register class"); 446 VRBase = MRI->createVirtualRegister(SRC); 447 } 448 449 // Create the insert_subreg or subreg_to_reg machine instruction. 450 MachineInstr *MI = BuildMI(*MF, Node->getDebugLoc(), TII->get(Opc)); 451 MI->addOperand(MachineOperand::CreateReg(VRBase, true)); 452 453 // If creating a subreg_to_reg, then the first input operand 454 // is an implicit value immediate, otherwise it's a register 455 if (Opc == TargetInstrInfo::SUBREG_TO_REG) { 456 const ConstantSDNode *SD = cast<ConstantSDNode>(N0); 457 MI->addOperand(MachineOperand::CreateImm(SD->getZExtValue())); 458 } else 459 AddOperand(MI, N0, 0, 0, VRBaseMap); 460 // Add the subregster being inserted 461 AddOperand(MI, N1, 0, 0, VRBaseMap); 462 MI->addOperand(MachineOperand::CreateImm(SubIdx)); 463 MBB->insert(InsertPos, MI); 464 } else 465 llvm_unreachable("Node is not insert_subreg, extract_subreg, or subreg_to_reg"); 466 467 SDValue Op(Node, 0); 468 bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBase)).second; 469 isNew = isNew; // Silence compiler warning. 470 assert(isNew && "Node emitted out of order - early"); 471} 472 473/// EmitCopyToRegClassNode - Generate machine code for COPY_TO_REGCLASS nodes. 474/// COPY_TO_REGCLASS is just a normal copy, except that the destination 475/// register is constrained to be in a particular register class. 476/// 477void 478InstrEmitter::EmitCopyToRegClassNode(SDNode *Node, 479 DenseMap<SDValue, unsigned> &VRBaseMap) { 480 unsigned VReg = getVR(Node->getOperand(0), VRBaseMap); 481 const TargetRegisterClass *SrcRC = MRI->getRegClass(VReg); 482 483 unsigned DstRCIdx = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue(); 484 const TargetRegisterClass *DstRC = TRI->getRegClass(DstRCIdx); 485 486 // Create the new VReg in the destination class and emit a copy. 487 unsigned NewVReg = MRI->createVirtualRegister(DstRC); 488 bool Emitted = TII->copyRegToReg(*MBB, InsertPos, NewVReg, VReg, 489 DstRC, SrcRC); 490 assert(Emitted && 491 "Unable to issue a copy instruction for a COPY_TO_REGCLASS node!\n"); 492 (void) Emitted; 493 494 SDValue Op(Node, 0); 495 bool isNew = VRBaseMap.insert(std::make_pair(Op, NewVReg)).second; 496 isNew = isNew; // Silence compiler warning. 497 assert(isNew && "Node emitted out of order - early"); 498} 499 500/// EmitNode - Generate machine code for an node and needed dependencies. 501/// 502void InstrEmitter::EmitNode(SDNode *Node, bool IsClone, bool IsCloned, 503 DenseMap<SDValue, unsigned> &VRBaseMap, 504 DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) { 505 // If machine instruction 506 if (Node->isMachineOpcode()) { 507 unsigned Opc = Node->getMachineOpcode(); 508 509 // Handle subreg insert/extract specially 510 if (Opc == TargetInstrInfo::EXTRACT_SUBREG || 511 Opc == TargetInstrInfo::INSERT_SUBREG || 512 Opc == TargetInstrInfo::SUBREG_TO_REG) { 513 EmitSubregNode(Node, VRBaseMap); 514 return; 515 } 516 517 // Handle COPY_TO_REGCLASS specially. 518 if (Opc == TargetInstrInfo::COPY_TO_REGCLASS) { 519 EmitCopyToRegClassNode(Node, VRBaseMap); 520 return; 521 } 522 523 if (Opc == TargetInstrInfo::IMPLICIT_DEF) 524 // We want a unique VR for each IMPLICIT_DEF use. 525 return; 526 527 const TargetInstrDesc &II = TII->get(Opc); 528 unsigned NumResults = CountResults(Node); 529 unsigned NodeOperands = CountOperands(Node); 530 bool HasPhysRegOuts = (NumResults > II.getNumDefs()) && 531 II.getImplicitDefs() != 0; 532#ifndef NDEBUG 533 unsigned NumMIOperands = NodeOperands + NumResults; 534 assert((II.getNumOperands() == NumMIOperands || 535 HasPhysRegOuts || II.isVariadic()) && 536 "#operands for dag node doesn't match .td file!"); 537#endif 538 539 // Create the new machine instruction. 540 MachineInstr *MI = BuildMI(*MF, Node->getDebugLoc(), II); 541 542 // Add result register values for things that are defined by this 543 // instruction. 544 if (NumResults) 545 CreateVirtualRegisters(Node, MI, II, IsClone, IsCloned, VRBaseMap); 546 547 // Emit all of the actual operands of this instruction, adding them to the 548 // instruction as appropriate. 549 bool HasOptPRefs = II.getNumDefs() > NumResults; 550 assert((!HasOptPRefs || !HasPhysRegOuts) && 551 "Unable to cope with optional defs and phys regs defs!"); 552 unsigned NumSkip = HasOptPRefs ? II.getNumDefs() - NumResults : 0; 553 for (unsigned i = NumSkip; i != NodeOperands; ++i) 554 AddOperand(MI, Node->getOperand(i), i-NumSkip+II.getNumDefs(), &II, 555 VRBaseMap); 556 557 // Transfer all of the memory reference descriptions of this instruction. 558 MI->setMemRefs(cast<MachineSDNode>(Node)->memoperands_begin(), 559 cast<MachineSDNode>(Node)->memoperands_end()); 560 561 if (II.usesCustomInsertionHook()) { 562 // Insert this instruction into the basic block using a target 563 // specific inserter which may returns a new basic block. 564 MBB = TLI->EmitInstrWithCustomInserter(MI, MBB, EM); 565 InsertPos = MBB->end(); 566 } else { 567 MBB->insert(InsertPos, MI); 568 } 569 570 // Additional results must be an physical register def. 571 if (HasPhysRegOuts) { 572 for (unsigned i = II.getNumDefs(); i < NumResults; ++i) { 573 unsigned Reg = II.getImplicitDefs()[i - II.getNumDefs()]; 574 if (Node->hasAnyUseOfValue(i)) 575 EmitCopyFromReg(Node, i, IsClone, IsCloned, Reg, VRBaseMap); 576 // If there are no uses, mark the register as dead now, so that 577 // MachineLICM/Sink can see that it's dead. Don't do this if the 578 // node has a Flag value, for the benefit of targets still using 579 // Flag for values in physregs. 580 else if (Node->getValueType(Node->getNumValues()-1) != MVT::Flag) 581 MI->addRegisterDead(Reg, TRI); 582 } 583 } 584 return; 585 } 586 587 switch (Node->getOpcode()) { 588 default: 589#ifndef NDEBUG 590 Node->dump(); 591#endif 592 llvm_unreachable("This target-independent node should have been selected!"); 593 break; 594 case ISD::EntryToken: 595 llvm_unreachable("EntryToken should have been excluded from the schedule!"); 596 break; 597 case ISD::MERGE_VALUES: 598 case ISD::TokenFactor: // fall thru 599 break; 600 case ISD::CopyToReg: { 601 unsigned SrcReg; 602 SDValue SrcVal = Node->getOperand(2); 603 if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(SrcVal)) 604 SrcReg = R->getReg(); 605 else 606 SrcReg = getVR(SrcVal, VRBaseMap); 607 608 unsigned DestReg = cast<RegisterSDNode>(Node->getOperand(1))->getReg(); 609 if (SrcReg == DestReg) // Coalesced away the copy? Ignore. 610 break; 611 612 const TargetRegisterClass *SrcTRC = 0, *DstTRC = 0; 613 // Get the register classes of the src/dst. 614 if (TargetRegisterInfo::isVirtualRegister(SrcReg)) 615 SrcTRC = MRI->getRegClass(SrcReg); 616 else 617 SrcTRC = TRI->getPhysicalRegisterRegClass(SrcReg,SrcVal.getValueType()); 618 619 if (TargetRegisterInfo::isVirtualRegister(DestReg)) 620 DstTRC = MRI->getRegClass(DestReg); 621 else 622 DstTRC = TRI->getPhysicalRegisterRegClass(DestReg, 623 Node->getOperand(1).getValueType()); 624 625 bool Emitted = TII->copyRegToReg(*MBB, InsertPos, DestReg, SrcReg, 626 DstTRC, SrcTRC); 627 assert(Emitted && "Unable to issue a copy instruction!\n"); 628 (void) Emitted; 629 break; 630 } 631 case ISD::CopyFromReg: { 632 unsigned SrcReg = cast<RegisterSDNode>(Node->getOperand(1))->getReg(); 633 EmitCopyFromReg(Node, 0, IsClone, IsCloned, SrcReg, VRBaseMap); 634 break; 635 } 636 case ISD::INLINEASM: { 637 unsigned NumOps = Node->getNumOperands(); 638 if (Node->getOperand(NumOps-1).getValueType() == MVT::Flag) 639 --NumOps; // Ignore the flag operand. 640 641 // Create the inline asm machine instruction. 642 MachineInstr *MI = BuildMI(*MF, Node->getDebugLoc(), 643 TII->get(TargetInstrInfo::INLINEASM)); 644 645 // Add the asm string as an external symbol operand. 646 const char *AsmStr = 647 cast<ExternalSymbolSDNode>(Node->getOperand(1))->getSymbol(); 648 MI->addOperand(MachineOperand::CreateES(AsmStr)); 649 650 // Add all of the operand registers to the instruction. 651 for (unsigned i = 2; i != NumOps;) { 652 unsigned Flags = 653 cast<ConstantSDNode>(Node->getOperand(i))->getZExtValue(); 654 unsigned NumVals = InlineAsm::getNumOperandRegisters(Flags); 655 656 MI->addOperand(MachineOperand::CreateImm(Flags)); 657 ++i; // Skip the ID value. 658 659 switch (Flags & 7) { 660 default: llvm_unreachable("Bad flags!"); 661 case 2: // Def of register. 662 for (; NumVals; --NumVals, ++i) { 663 unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg(); 664 MI->addOperand(MachineOperand::CreateReg(Reg, true)); 665 } 666 break; 667 case 6: // Def of earlyclobber register. 668 for (; NumVals; --NumVals, ++i) { 669 unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg(); 670 MI->addOperand(MachineOperand::CreateReg(Reg, true, false, false, 671 false, false, true)); 672 } 673 break; 674 case 1: // Use of register. 675 case 3: // Immediate. 676 case 4: // Addressing mode. 677 // The addressing mode has been selected, just add all of the 678 // operands to the machine instruction. 679 for (; NumVals; --NumVals, ++i) 680 AddOperand(MI, Node->getOperand(i), 0, 0, VRBaseMap); 681 break; 682 } 683 } 684 MBB->insert(InsertPos, MI); 685 break; 686 } 687 } 688} 689 690/// InstrEmitter - Construct an InstrEmitter and set it to start inserting 691/// at the given position in the given block. 692InstrEmitter::InstrEmitter(MachineBasicBlock *mbb, 693 MachineBasicBlock::iterator insertpos) 694 : MF(mbb->getParent()), 695 MRI(&MF->getRegInfo()), 696 TM(&MF->getTarget()), 697 TII(TM->getInstrInfo()), 698 TRI(TM->getRegisterInfo()), 699 TLI(TM->getTargetLowering()), 700 MBB(mbb), InsertPos(insertpos) { 701} 702