MachineSink.cpp revision 206274
11558Srgrimes//===-- MachineSink.cpp - Sinking for machine instructions ----------------===// 257449Smarkm// 31558Srgrimes// The LLVM Compiler Infrastructure 41558Srgrimes// 5192674Srmacklem// This file is distributed under the University of Illinois Open Source 61558Srgrimes// License. See LICENSE.TXT for details. 71558Srgrimes// 8//===----------------------------------------------------------------------===// 9// 10// This pass moves instructions into successor blocks, when possible, so that 11// they aren't executed on paths where their results aren't needed. 12// 13// This pass is not intended to be a replacement or a complete alternative 14// for an LLVM-IR-level sinking pass. It is only designed to sink simple 15// constructs that are not exposed before lowering and instruction selection. 16// 17//===----------------------------------------------------------------------===// 18 19#define DEBUG_TYPE "machine-sink" 20#include "llvm/CodeGen/Passes.h" 21#include "llvm/CodeGen/MachineRegisterInfo.h" 22#include "llvm/CodeGen/MachineDominators.h" 23#include "llvm/Analysis/AliasAnalysis.h" 24#include "llvm/Target/TargetRegisterInfo.h" 25#include "llvm/Target/TargetInstrInfo.h" 26#include "llvm/Target/TargetMachine.h" 27#include "llvm/ADT/Statistic.h" 28#include "llvm/Support/Debug.h" 29#include "llvm/Support/raw_ostream.h" 30using namespace llvm; 31 32STATISTIC(NumSunk, "Number of machine instructions sunk"); 33 34namespace { 35 class MachineSinking : public MachineFunctionPass { 36 const TargetInstrInfo *TII; 37 const TargetRegisterInfo *TRI; 38 MachineRegisterInfo *RegInfo; // Machine register information 39 MachineDominatorTree *DT; // Machine dominator tree 40 AliasAnalysis *AA; 41 BitVector AllocatableSet; // Which physregs are allocatable? 42 43 public: 44 static char ID; // Pass identification 45 MachineSinking() : MachineFunctionPass(&ID) {} 46 47 virtual bool runOnMachineFunction(MachineFunction &MF); 48 49 virtual void getAnalysisUsage(AnalysisUsage &AU) const { 50 AU.setPreservesCFG(); 51 MachineFunctionPass::getAnalysisUsage(AU); 52 AU.addRequired<AliasAnalysis>(); 53 AU.addRequired<MachineDominatorTree>(); 54 AU.addPreserved<MachineDominatorTree>(); 55 } 56 private: 57 bool ProcessBlock(MachineBasicBlock &MBB); 58 bool SinkInstruction(MachineInstr *MI, bool &SawStore); 59 bool AllUsesDominatedByBlock(unsigned Reg, MachineBasicBlock *MBB) const; 60 }; 61} // end anonymous namespace 62 63char MachineSinking::ID = 0; 64static RegisterPass<MachineSinking> 65X("machine-sink", "Machine code sinking"); 66 67FunctionPass *llvm::createMachineSinkingPass() { return new MachineSinking(); } 68 69/// AllUsesDominatedByBlock - Return true if all uses of the specified register 70/// occur in blocks dominated by the specified block. 71bool MachineSinking::AllUsesDominatedByBlock(unsigned Reg, 72 MachineBasicBlock *MBB) const { 73 assert(TargetRegisterInfo::isVirtualRegister(Reg) && 74 "Only makes sense for vregs"); 75 // Ignoring debug uses is necessary so debug info doesn't affect the code. 76 // This may leave a referencing dbg_value in the original block, before 77 // the definition of the vreg. Dwarf generator handles this although the 78 // user might not get the right info at runtime. 79 for (MachineRegisterInfo::use_nodbg_iterator I = 80 RegInfo->use_nodbg_begin(Reg), 81 E = RegInfo->use_nodbg_end(); I != E; ++I) { 82 // Determine the block of the use. 83 MachineInstr *UseInst = &*I; 84 MachineBasicBlock *UseBlock = UseInst->getParent(); 85 if (UseInst->isPHI()) { 86 // PHI nodes use the operand in the predecessor block, not the block with 87 // the PHI. 88 UseBlock = UseInst->getOperand(I.getOperandNo()+1).getMBB(); 89 } 90 // Check that it dominates. 91 if (!DT->dominates(MBB, UseBlock)) 92 return false; 93 } 94 return true; 95} 96 97bool MachineSinking::runOnMachineFunction(MachineFunction &MF) { 98 DEBUG(dbgs() << "******** Machine Sinking ********\n"); 99 100 const TargetMachine &TM = MF.getTarget(); 101 TII = TM.getInstrInfo(); 102 TRI = TM.getRegisterInfo(); 103 RegInfo = &MF.getRegInfo(); 104 DT = &getAnalysis<MachineDominatorTree>(); 105 AA = &getAnalysis<AliasAnalysis>(); 106 AllocatableSet = TRI->getAllocatableSet(MF); 107 108 bool EverMadeChange = false; 109 110 while (1) { 111 bool MadeChange = false; 112 113 // Process all basic blocks. 114 for (MachineFunction::iterator I = MF.begin(), E = MF.end(); 115 I != E; ++I) 116 MadeChange |= ProcessBlock(*I); 117 118 // If this iteration over the code changed anything, keep iterating. 119 if (!MadeChange) break; 120 EverMadeChange = true; 121 } 122 return EverMadeChange; 123} 124 125bool MachineSinking::ProcessBlock(MachineBasicBlock &MBB) { 126 // Can't sink anything out of a block that has less than two successors. 127 if (MBB.succ_size() <= 1 || MBB.empty()) return false; 128 129 // Don't bother sinking code out of unreachable blocks. In addition to being 130 // unprofitable, it can also lead to infinite looping, because in an unreachable 131 // loop there may be nowhere to stop. 132 if (!DT->isReachableFromEntry(&MBB)) return false; 133 134 bool MadeChange = false; 135 136 // Walk the basic block bottom-up. Remember if we saw a store. 137 MachineBasicBlock::iterator I = MBB.end(); 138 --I; 139 bool ProcessedBegin, SawStore = false; 140 do { 141 MachineInstr *MI = I; // The instruction to sink. 142 143 // Predecrement I (if it's not begin) so that it isn't invalidated by 144 // sinking. 145 ProcessedBegin = I == MBB.begin(); 146 if (!ProcessedBegin) 147 --I; 148 149 if (MI->isDebugValue()) 150 continue; 151 152 if (SinkInstruction(MI, SawStore)) 153 ++NumSunk, MadeChange = true; 154 155 // If we just processed the first instruction in the block, we're done. 156 } while (!ProcessedBegin); 157 158 return MadeChange; 159} 160 161/// SinkInstruction - Determine whether it is safe to sink the specified machine 162/// instruction out of its current block into a successor. 163bool MachineSinking::SinkInstruction(MachineInstr *MI, bool &SawStore) { 164 // Check if it's safe to move the instruction. 165 if (!MI->isSafeToMove(TII, AA, SawStore)) 166 return false; 167 168 // FIXME: This should include support for sinking instructions within the 169 // block they are currently in to shorten the live ranges. We often get 170 // instructions sunk into the top of a large block, but it would be better to 171 // also sink them down before their first use in the block. This xform has to 172 // be careful not to *increase* register pressure though, e.g. sinking 173 // "x = y + z" down if it kills y and z would increase the live ranges of y 174 // and z and only shrink the live range of x. 175 176 // Loop over all the operands of the specified instruction. If there is 177 // anything we can't handle, bail out. 178 MachineBasicBlock *ParentBlock = MI->getParent(); 179 180 // SuccToSinkTo - This is the successor to sink this instruction to, once we 181 // decide. 182 MachineBasicBlock *SuccToSinkTo = 0; 183 184 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 185 const MachineOperand &MO = MI->getOperand(i); 186 if (!MO.isReg()) continue; // Ignore non-register operands. 187 188 unsigned Reg = MO.getReg(); 189 if (Reg == 0) continue; 190 191 if (TargetRegisterInfo::isPhysicalRegister(Reg)) { 192 if (MO.isUse()) { 193 // If the physreg has no defs anywhere, it's just an ambient register 194 // and we can freely move its uses. Alternatively, if it's allocatable, 195 // it could get allocated to something with a def during allocation. 196 if (!RegInfo->def_empty(Reg)) 197 return false; 198 if (AllocatableSet.test(Reg)) 199 return false; 200 // Check for a def among the register's aliases too. 201 for (const unsigned *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias) { 202 unsigned AliasReg = *Alias; 203 if (!RegInfo->def_empty(AliasReg)) 204 return false; 205 if (AllocatableSet.test(AliasReg)) 206 return false; 207 } 208 } else if (!MO.isDead()) { 209 // A def that isn't dead. We can't move it. 210 return false; 211 } 212 } else { 213 // Virtual register uses are always safe to sink. 214 if (MO.isUse()) continue; 215 216 // If it's not safe to move defs of the register class, then abort. 217 if (!TII->isSafeToMoveRegClassDefs(RegInfo->getRegClass(Reg))) 218 return false; 219 220 // FIXME: This picks a successor to sink into based on having one 221 // successor that dominates all the uses. However, there are cases where 222 // sinking can happen but where the sink point isn't a successor. For 223 // example: 224 // x = computation 225 // if () {} else {} 226 // use x 227 // the instruction could be sunk over the whole diamond for the 228 // if/then/else (or loop, etc), allowing it to be sunk into other blocks 229 // after that. 230 231 // Virtual register defs can only be sunk if all their uses are in blocks 232 // dominated by one of the successors. 233 if (SuccToSinkTo) { 234 // If a previous operand picked a block to sink to, then this operand 235 // must be sinkable to the same block. 236 if (!AllUsesDominatedByBlock(Reg, SuccToSinkTo)) 237 return false; 238 continue; 239 } 240 241 // Otherwise, we should look at all the successors and decide which one 242 // we should sink to. 243 for (MachineBasicBlock::succ_iterator SI = ParentBlock->succ_begin(), 244 E = ParentBlock->succ_end(); SI != E; ++SI) { 245 if (AllUsesDominatedByBlock(Reg, *SI)) { 246 SuccToSinkTo = *SI; 247 break; 248 } 249 } 250 251 // If we couldn't find a block to sink to, ignore this instruction. 252 if (SuccToSinkTo == 0) 253 return false; 254 } 255 } 256 257 // If there are no outputs, it must have side-effects. 258 if (SuccToSinkTo == 0) 259 return false; 260 261 // It's not safe to sink instructions to EH landing pad. Control flow into 262 // landing pad is implicitly defined. 263 if (SuccToSinkTo->isLandingPad()) 264 return false; 265 266 // It is not possible to sink an instruction into its own block. This can 267 // happen with loops. 268 if (MI->getParent() == SuccToSinkTo) 269 return false; 270 271 DEBUG(dbgs() << "Sink instr " << *MI); 272 DEBUG(dbgs() << "to block " << *SuccToSinkTo); 273 274 // If the block has multiple predecessors, this would introduce computation on 275 // a path that it doesn't already exist. We could split the critical edge, 276 // but for now we just punt. 277 // FIXME: Split critical edges if not backedges. 278 if (SuccToSinkTo->pred_size() > 1) { 279 DEBUG(dbgs() << " *** PUNTING: Critical edge found\n"); 280 return false; 281 } 282 283 // Determine where to insert into. Skip phi nodes. 284 MachineBasicBlock::iterator InsertPos = SuccToSinkTo->begin(); 285 while (InsertPos != SuccToSinkTo->end() && InsertPos->isPHI()) 286 ++InsertPos; 287 288 // Move the instruction. 289 SuccToSinkTo->splice(InsertPos, ParentBlock, MI, 290 ++MachineBasicBlock::iterator(MI)); 291 return true; 292} 293