ExpandPostRAPseudos.cpp revision 341825
1226584Sdim//===-- ExpandPostRAPseudos.cpp - Pseudo instruction expansion pass -------===// 2226584Sdim// 3226584Sdim// The LLVM Compiler Infrastructure 4226584Sdim// 5226584Sdim// This file is distributed under the University of Illinois Open Source 6226584Sdim// License. See LICENSE.TXT for details. 7226584Sdim// 8226584Sdim//===----------------------------------------------------------------------===// 9226584Sdim// 10226584Sdim// This file defines a pass that expands COPY and SUBREG_TO_REG pseudo 11226584Sdim// instructions after register allocation. 12226584Sdim// 13226584Sdim//===----------------------------------------------------------------------===// 14226584Sdim 15226584Sdim#include "llvm/CodeGen/MachineFunctionPass.h" 16226584Sdim#include "llvm/CodeGen/MachineInstr.h" 17226584Sdim#include "llvm/CodeGen/MachineInstrBuilder.h" 18226584Sdim#include "llvm/CodeGen/MachineRegisterInfo.h" 19321369Sdim#include "llvm/CodeGen/Passes.h" 20327952Sdim#include "llvm/CodeGen/TargetInstrInfo.h" 21327952Sdim#include "llvm/CodeGen/TargetRegisterInfo.h" 22327952Sdim#include "llvm/CodeGen/TargetSubtargetInfo.h" 23249423Sdim#include "llvm/Support/Debug.h" 24249423Sdim#include "llvm/Support/raw_ostream.h" 25280031Sdim 26226584Sdimusing namespace llvm; 27226584Sdim 28276479Sdim#define DEBUG_TYPE "postrapseudos" 29276479Sdim 30226584Sdimnamespace { 31226584Sdimstruct ExpandPostRA : public MachineFunctionPass { 32226584Sdimprivate: 33226584Sdim const TargetRegisterInfo *TRI; 34226584Sdim const TargetInstrInfo *TII; 35226584Sdim 36226584Sdimpublic: 37226584Sdim static char ID; // Pass identification, replacement for typeid 38226584Sdim ExpandPostRA() : MachineFunctionPass(ID) {} 39226584Sdim 40276479Sdim void getAnalysisUsage(AnalysisUsage &AU) const override { 41226584Sdim AU.setPreservesCFG(); 42226584Sdim AU.addPreservedID(MachineLoopInfoID); 43226584Sdim AU.addPreservedID(MachineDominatorsID); 44226584Sdim MachineFunctionPass::getAnalysisUsage(AU); 45226584Sdim } 46226584Sdim 47226584Sdim /// runOnMachineFunction - pass entry point 48276479Sdim bool runOnMachineFunction(MachineFunction&) override; 49226584Sdim 50226584Sdimprivate: 51226584Sdim bool LowerSubregToReg(MachineInstr *MI); 52226584Sdim bool LowerCopy(MachineInstr *MI); 53226584Sdim 54309124Sdim void TransferImplicitOperands(MachineInstr *MI); 55226584Sdim}; 56226584Sdim} // end anonymous namespace 57226584Sdim 58226584Sdimchar ExpandPostRA::ID = 0; 59234353Sdimchar &llvm::ExpandPostRAPseudosID = ExpandPostRA::ID; 60226584Sdim 61321369SdimINITIALIZE_PASS(ExpandPostRA, DEBUG_TYPE, 62234353Sdim "Post-RA pseudo instruction expansion pass", false, false) 63226584Sdim 64309124Sdim/// TransferImplicitOperands - MI is a pseudo-instruction, and the lowered 65309124Sdim/// replacement instructions immediately precede it. Copy any implicit 66226584Sdim/// operands from MI to the replacement instruction. 67309124Sdimvoid ExpandPostRA::TransferImplicitOperands(MachineInstr *MI) { 68226584Sdim MachineBasicBlock::iterator CopyMI = MI; 69226584Sdim --CopyMI; 70226584Sdim 71309124Sdim for (const MachineOperand &MO : MI->implicit_operands()) 72309124Sdim if (MO.isReg()) 73309124Sdim CopyMI->addOperand(MO); 74226584Sdim} 75226584Sdim 76226584Sdimbool ExpandPostRA::LowerSubregToReg(MachineInstr *MI) { 77226584Sdim MachineBasicBlock *MBB = MI->getParent(); 78226584Sdim assert((MI->getOperand(0).isReg() && MI->getOperand(0).isDef()) && 79226584Sdim MI->getOperand(1).isImm() && 80226584Sdim (MI->getOperand(2).isReg() && MI->getOperand(2).isUse()) && 81226584Sdim MI->getOperand(3).isImm() && "Invalid subreg_to_reg"); 82226584Sdim 83226584Sdim unsigned DstReg = MI->getOperand(0).getReg(); 84226584Sdim unsigned InsReg = MI->getOperand(2).getReg(); 85226584Sdim assert(!MI->getOperand(2).getSubReg() && "SubIdx on physreg?"); 86226584Sdim unsigned SubIdx = MI->getOperand(3).getImm(); 87226584Sdim 88226584Sdim assert(SubIdx != 0 && "Invalid index for insert_subreg"); 89226584Sdim unsigned DstSubReg = TRI->getSubReg(DstReg, SubIdx); 90226584Sdim 91226584Sdim assert(TargetRegisterInfo::isPhysicalRegister(DstReg) && 92226584Sdim "Insert destination must be in a physical register"); 93226584Sdim assert(TargetRegisterInfo::isPhysicalRegister(InsReg) && 94226584Sdim "Inserted value must be in a physical register"); 95226584Sdim 96341825Sdim LLVM_DEBUG(dbgs() << "subreg: CONVERTING: " << *MI); 97226584Sdim 98249423Sdim if (MI->allDefsAreDead()) { 99249423Sdim MI->setDesc(TII->get(TargetOpcode::KILL)); 100341825Sdim LLVM_DEBUG(dbgs() << "subreg: replaced by: " << *MI); 101249423Sdim return true; 102249423Sdim } 103249423Sdim 104226584Sdim if (DstSubReg == InsReg) { 105261991Sdim // No need to insert an identity copy instruction. 106226584Sdim // Watch out for case like this: 107327952Sdim // %rax = SUBREG_TO_REG 0, killed %eax, 3 108327952Sdim // We must leave %rax live. 109226584Sdim if (DstReg != InsReg) { 110226584Sdim MI->setDesc(TII->get(TargetOpcode::KILL)); 111226584Sdim MI->RemoveOperand(3); // SubIdx 112226584Sdim MI->RemoveOperand(1); // Imm 113341825Sdim LLVM_DEBUG(dbgs() << "subreg: replace by: " << *MI); 114226584Sdim return true; 115226584Sdim } 116341825Sdim LLVM_DEBUG(dbgs() << "subreg: eliminated!"); 117226584Sdim } else { 118226584Sdim TII->copyPhysReg(*MBB, MI, MI->getDebugLoc(), DstSubReg, InsReg, 119226584Sdim MI->getOperand(2).isKill()); 120239462Sdim 121239462Sdim // Implicitly define DstReg for subsequent uses. 122239462Sdim MachineBasicBlock::iterator CopyMI = MI; 123239462Sdim --CopyMI; 124239462Sdim CopyMI->addRegisterDefined(DstReg); 125341825Sdim LLVM_DEBUG(dbgs() << "subreg: " << *CopyMI); 126226584Sdim } 127226584Sdim 128341825Sdim LLVM_DEBUG(dbgs() << '\n'); 129226584Sdim MBB->erase(MI); 130226584Sdim return true; 131226584Sdim} 132226584Sdim 133226584Sdimbool ExpandPostRA::LowerCopy(MachineInstr *MI) { 134249423Sdim 135249423Sdim if (MI->allDefsAreDead()) { 136341825Sdim LLVM_DEBUG(dbgs() << "dead copy: " << *MI); 137249423Sdim MI->setDesc(TII->get(TargetOpcode::KILL)); 138341825Sdim LLVM_DEBUG(dbgs() << "replaced by: " << *MI); 139249423Sdim return true; 140249423Sdim } 141249423Sdim 142226584Sdim MachineOperand &DstMO = MI->getOperand(0); 143226584Sdim MachineOperand &SrcMO = MI->getOperand(1); 144226584Sdim 145321369Sdim bool IdentityCopy = (SrcMO.getReg() == DstMO.getReg()); 146321369Sdim if (IdentityCopy || SrcMO.isUndef()) { 147341825Sdim LLVM_DEBUG(dbgs() << (IdentityCopy ? "identity copy: " : "undef copy: ") 148341825Sdim << *MI); 149226584Sdim // No need to insert an identity copy instruction, but replace with a KILL 150226584Sdim // if liveness is changed. 151249423Sdim if (SrcMO.isUndef() || MI->getNumOperands() > 2) { 152226584Sdim // We must make sure the super-register gets killed. Replace the 153226584Sdim // instruction with KILL. 154226584Sdim MI->setDesc(TII->get(TargetOpcode::KILL)); 155341825Sdim LLVM_DEBUG(dbgs() << "replaced by: " << *MI); 156226584Sdim return true; 157226584Sdim } 158226584Sdim // Vanilla identity copy. 159226584Sdim MI->eraseFromParent(); 160226584Sdim return true; 161226584Sdim } 162226584Sdim 163341825Sdim LLVM_DEBUG(dbgs() << "real copy: " << *MI); 164226584Sdim TII->copyPhysReg(*MI->getParent(), MI, MI->getDebugLoc(), 165226584Sdim DstMO.getReg(), SrcMO.getReg(), SrcMO.isKill()); 166226584Sdim 167226584Sdim if (MI->getNumOperands() > 2) 168309124Sdim TransferImplicitOperands(MI); 169341825Sdim LLVM_DEBUG({ 170226584Sdim MachineBasicBlock::iterator dMI = MI; 171226584Sdim dbgs() << "replaced by: " << *(--dMI); 172226584Sdim }); 173226584Sdim MI->eraseFromParent(); 174226584Sdim return true; 175226584Sdim} 176226584Sdim 177226584Sdim/// runOnMachineFunction - Reduce subregister inserts and extracts to register 178226584Sdim/// copies. 179226584Sdim/// 180226584Sdimbool ExpandPostRA::runOnMachineFunction(MachineFunction &MF) { 181341825Sdim LLVM_DEBUG(dbgs() << "Machine Function\n" 182341825Sdim << "********** EXPANDING POST-RA PSEUDO INSTRS **********\n" 183341825Sdim << "********** Function: " << MF.getName() << '\n'); 184280031Sdim TRI = MF.getSubtarget().getRegisterInfo(); 185280031Sdim TII = MF.getSubtarget().getInstrInfo(); 186226584Sdim 187226584Sdim bool MadeChange = false; 188226584Sdim 189226584Sdim for (MachineFunction::iterator mbbi = MF.begin(), mbbe = MF.end(); 190226584Sdim mbbi != mbbe; ++mbbi) { 191226584Sdim for (MachineBasicBlock::iterator mi = mbbi->begin(), me = mbbi->end(); 192226584Sdim mi != me;) { 193309124Sdim MachineInstr &MI = *mi; 194226584Sdim // Advance iterator here because MI may be erased. 195226584Sdim ++mi; 196226584Sdim 197226584Sdim // Only expand pseudos. 198309124Sdim if (!MI.isPseudo()) 199226584Sdim continue; 200226584Sdim 201226584Sdim // Give targets a chance to expand even standard pseudos. 202226584Sdim if (TII->expandPostRAPseudo(MI)) { 203226584Sdim MadeChange = true; 204226584Sdim continue; 205226584Sdim } 206226584Sdim 207226584Sdim // Expand standard pseudos. 208309124Sdim switch (MI.getOpcode()) { 209226584Sdim case TargetOpcode::SUBREG_TO_REG: 210309124Sdim MadeChange |= LowerSubregToReg(&MI); 211226584Sdim break; 212226584Sdim case TargetOpcode::COPY: 213309124Sdim MadeChange |= LowerCopy(&MI); 214226584Sdim break; 215226584Sdim case TargetOpcode::DBG_VALUE: 216226584Sdim continue; 217226584Sdim case TargetOpcode::INSERT_SUBREG: 218226584Sdim case TargetOpcode::EXTRACT_SUBREG: 219226584Sdim llvm_unreachable("Sub-register pseudos should have been eliminated."); 220226584Sdim } 221226584Sdim } 222226584Sdim } 223226584Sdim 224226584Sdim return MadeChange; 225226584Sdim} 226