AllocationOrder.cpp revision 239462
1218885Sdim//===-- llvm/CodeGen/AllocationOrder.cpp - Allocation Order ---------------===// 2218885Sdim// 3218885Sdim// The LLVM Compiler Infrastructure 4218885Sdim// 5218885Sdim// This file is distributed under the University of Illinois Open Source 6218885Sdim// License. See LICENSE.TXT for details. 7218885Sdim// 8218885Sdim//===----------------------------------------------------------------------===// 9218885Sdim// 10218885Sdim// This file implements an allocation order for virtual registers. 11218885Sdim// 12218885Sdim// The preferred allocation order for a virtual register depends on allocation 13218885Sdim// hints and target hooks. The AllocationOrder class encapsulates all of that. 14218885Sdim// 15218885Sdim//===----------------------------------------------------------------------===// 16218885Sdim 17218885Sdim#include "AllocationOrder.h" 18218885Sdim#include "VirtRegMap.h" 19218885Sdim#include "llvm/CodeGen/MachineRegisterInfo.h" 20239462Sdim#include "llvm/CodeGen/RegisterClassInfo.h" 21218885Sdim 22218885Sdimusing namespace llvm; 23218885Sdim 24218885Sdim// Compare VirtRegMap::getRegAllocPref(). 25218885SdimAllocationOrder::AllocationOrder(unsigned VirtReg, 26218885Sdim const VirtRegMap &VRM, 27223017Sdim const RegisterClassInfo &RegClassInfo) 28223017Sdim : Begin(0), End(0), Pos(0), RCI(RegClassInfo), OwnedBegin(false) { 29218885Sdim const TargetRegisterClass *RC = VRM.getRegInfo().getRegClass(VirtReg); 30218885Sdim std::pair<unsigned, unsigned> HintPair = 31218885Sdim VRM.getRegInfo().getRegAllocationHint(VirtReg); 32218885Sdim 33218885Sdim // HintPair.second is a register, phys or virt. 34218885Sdim Hint = HintPair.second; 35218885Sdim 36218885Sdim // Translate to physreg, or 0 if not assigned yet. 37218885Sdim if (TargetRegisterInfo::isVirtualRegister(Hint)) 38218885Sdim Hint = VRM.getPhys(Hint); 39218885Sdim 40223017Sdim // The first hint pair component indicates a target-specific hint. 41223017Sdim if (HintPair.first) { 42223017Sdim const TargetRegisterInfo &TRI = VRM.getTargetRegInfo(); 43223017Sdim // The remaining allocation order may depend on the hint. 44234353Sdim ArrayRef<uint16_t> Order = 45224145Sdim TRI.getRawAllocationOrder(RC, HintPair.first, Hint, 46224145Sdim VRM.getMachineFunction()); 47224145Sdim if (Order.empty()) 48223017Sdim return; 49218885Sdim 50223017Sdim // Copy the allocation order with reserved registers removed. 51223017Sdim OwnedBegin = true; 52224145Sdim unsigned *P = new unsigned[Order.size()]; 53223017Sdim Begin = P; 54224145Sdim for (unsigned i = 0; i != Order.size(); ++i) 55224145Sdim if (!RCI.isReserved(Order[i])) 56224145Sdim *P++ = Order[i]; 57223017Sdim End = P; 58223017Sdim 59223017Sdim // Target-dependent hints require resolution. 60223017Sdim Hint = TRI.ResolveRegAllocHint(HintPair.first, Hint, 61223017Sdim VRM.getMachineFunction()); 62223017Sdim } else { 63223017Sdim // If there is no hint or just a normal hint, use the cached allocation 64223017Sdim // order from RegisterClassInfo. 65223017Sdim ArrayRef<unsigned> O = RCI.getOrder(RC); 66223017Sdim Begin = O.begin(); 67223017Sdim End = O.end(); 68223017Sdim } 69223017Sdim 70218885Sdim // The hint must be a valid physreg for allocation. 71218885Sdim if (Hint && (!TargetRegisterInfo::isPhysicalRegister(Hint) || 72223017Sdim !RC->contains(Hint) || RCI.isReserved(Hint))) 73218885Sdim Hint = 0; 74218885Sdim} 75218885Sdim 76223017SdimAllocationOrder::~AllocationOrder() { 77223017Sdim if (OwnedBegin) 78223017Sdim delete [] Begin; 79218885Sdim} 80