TargetSelectionDAG.td revision 363496
1//===- TargetSelectionDAG.td - Common code for DAG isels ---*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file defines the target-independent interfaces used by SelectionDAG 10// instruction selection generators. 11// 12//===----------------------------------------------------------------------===// 13 14//===----------------------------------------------------------------------===// 15// Selection DAG Type Constraint definitions. 16// 17// Note that the semantics of these constraints are hard coded into tblgen. To 18// modify or add constraints, you have to hack tblgen. 19// 20 21class SDTypeConstraint<int opnum> { 22 int OperandNum = opnum; 23} 24 25// SDTCisVT - The specified operand has exactly this VT. 26class SDTCisVT<int OpNum, ValueType vt> : SDTypeConstraint<OpNum> { 27 ValueType VT = vt; 28} 29 30class SDTCisPtrTy<int OpNum> : SDTypeConstraint<OpNum>; 31 32// SDTCisInt - The specified operand has integer type. 33class SDTCisInt<int OpNum> : SDTypeConstraint<OpNum>; 34 35// SDTCisFP - The specified operand has floating-point type. 36class SDTCisFP<int OpNum> : SDTypeConstraint<OpNum>; 37 38// SDTCisVec - The specified operand has a vector type. 39class SDTCisVec<int OpNum> : SDTypeConstraint<OpNum>; 40 41// SDTCisSameAs - The two specified operands have identical types. 42class SDTCisSameAs<int OpNum, int OtherOp> : SDTypeConstraint<OpNum> { 43 int OtherOperandNum = OtherOp; 44} 45 46// SDTCisVTSmallerThanOp - The specified operand is a VT SDNode, and its type is 47// smaller than the 'Other' operand. 48class SDTCisVTSmallerThanOp<int OpNum, int OtherOp> : SDTypeConstraint<OpNum> { 49 int OtherOperandNum = OtherOp; 50} 51 52class SDTCisOpSmallerThanOp<int SmallOp, int BigOp> : SDTypeConstraint<SmallOp>{ 53 int BigOperandNum = BigOp; 54} 55 56/// SDTCisEltOfVec - This indicates that ThisOp is a scalar type of the same 57/// type as the element type of OtherOp, which is a vector type. 58class SDTCisEltOfVec<int ThisOp, int OtherOp> 59 : SDTypeConstraint<ThisOp> { 60 int OtherOpNum = OtherOp; 61} 62 63/// SDTCisSubVecOfVec - This indicates that ThisOp is a vector type 64/// with length less that of OtherOp, which is a vector type. 65class SDTCisSubVecOfVec<int ThisOp, int OtherOp> 66 : SDTypeConstraint<ThisOp> { 67 int OtherOpNum = OtherOp; 68} 69 70// SDTCVecEltisVT - The specified operand is vector type with element type 71// of VT. 72class SDTCVecEltisVT<int OpNum, ValueType vt> : SDTypeConstraint<OpNum> { 73 ValueType VT = vt; 74} 75 76// SDTCisSameNumEltsAs - The two specified operands have identical number 77// of elements. 78class SDTCisSameNumEltsAs<int OpNum, int OtherOp> : SDTypeConstraint<OpNum> { 79 int OtherOperandNum = OtherOp; 80} 81 82// SDTCisSameSizeAs - The two specified operands have identical size. 83class SDTCisSameSizeAs<int OpNum, int OtherOp> : SDTypeConstraint<OpNum> { 84 int OtherOperandNum = OtherOp; 85} 86 87//===----------------------------------------------------------------------===// 88// Selection DAG Type Profile definitions. 89// 90// These use the constraints defined above to describe the type requirements of 91// the various nodes. These are not hard coded into tblgen, allowing targets to 92// add their own if needed. 93// 94 95// SDTypeProfile - This profile describes the type requirements of a Selection 96// DAG node. 97class SDTypeProfile<int numresults, int numoperands, 98 list<SDTypeConstraint> constraints> { 99 int NumResults = numresults; 100 int NumOperands = numoperands; 101 list<SDTypeConstraint> Constraints = constraints; 102} 103 104// Builtin profiles. 105def SDTIntLeaf: SDTypeProfile<1, 0, [SDTCisInt<0>]>; // for 'imm'. 106def SDTFPLeaf : SDTypeProfile<1, 0, [SDTCisFP<0>]>; // for 'fpimm'. 107def SDTPtrLeaf: SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>; // for '&g'. 108def SDTOther : SDTypeProfile<1, 0, [SDTCisVT<0, OtherVT>]>; // for 'vt'. 109def SDTUNDEF : SDTypeProfile<1, 0, []>; // for 'undef'. 110def SDTUnaryOp : SDTypeProfile<1, 1, []>; // for bitconvert. 111 112def SDTIntBinOp : SDTypeProfile<1, 2, [ // add, and, or, xor, udiv, etc. 113 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisInt<0> 114]>; 115def SDTIntShiftOp : SDTypeProfile<1, 2, [ // shl, sra, srl 116 SDTCisSameAs<0, 1>, SDTCisInt<0>, SDTCisInt<2> 117]>; 118def SDTIntShiftDOp: SDTypeProfile<1, 3, [ // fshl, fshr 119 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisInt<0>, SDTCisInt<3> 120]>; 121def SDTIntSatNoShOp : SDTypeProfile<1, 2, [ // ssat with no shift 122 SDTCisSameAs<0, 1>, SDTCisInt<2> 123]>; 124def SDTIntBinHiLoOp : SDTypeProfile<2, 2, [ // mulhi, mullo, sdivrem, udivrem 125 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>,SDTCisInt<0> 126]>; 127def SDTIntScaledBinOp : SDTypeProfile<1, 3, [ // smulfix, sdivfix, etc 128 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisInt<0>, SDTCisInt<3> 129]>; 130 131def SDTFPBinOp : SDTypeProfile<1, 2, [ // fadd, fmul, etc. 132 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisFP<0> 133]>; 134def SDTFPSignOp : SDTypeProfile<1, 2, [ // fcopysign. 135 SDTCisSameAs<0, 1>, SDTCisFP<0>, SDTCisFP<2> 136]>; 137def SDTFPTernaryOp : SDTypeProfile<1, 3, [ // fmadd, fnmsub, etc. 138 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>, SDTCisFP<0> 139]>; 140def SDTIntUnaryOp : SDTypeProfile<1, 1, [ // bitreverse 141 SDTCisSameAs<0, 1>, SDTCisInt<0> 142]>; 143def SDTIntBitCountUnaryOp : SDTypeProfile<1, 1, [ // ctlz, cttz 144 SDTCisInt<0>, SDTCisInt<1> 145]>; 146def SDTIntExtendOp : SDTypeProfile<1, 1, [ // sext, zext, anyext 147 SDTCisInt<0>, SDTCisInt<1>, SDTCisOpSmallerThanOp<1, 0>, SDTCisSameNumEltsAs<0, 1> 148]>; 149def SDTIntTruncOp : SDTypeProfile<1, 1, [ // trunc 150 SDTCisInt<0>, SDTCisInt<1>, SDTCisOpSmallerThanOp<0, 1>, SDTCisSameNumEltsAs<0, 1> 151]>; 152def SDTFPUnaryOp : SDTypeProfile<1, 1, [ // fneg, fsqrt, etc 153 SDTCisSameAs<0, 1>, SDTCisFP<0> 154]>; 155def SDTFPRoundOp : SDTypeProfile<1, 1, [ // fround 156 SDTCisFP<0>, SDTCisFP<1>, SDTCisOpSmallerThanOp<0, 1>, SDTCisSameNumEltsAs<0, 1> 157]>; 158def SDTFPExtendOp : SDTypeProfile<1, 1, [ // fextend 159 SDTCisFP<0>, SDTCisFP<1>, SDTCisOpSmallerThanOp<1, 0>, SDTCisSameNumEltsAs<0, 1> 160]>; 161def SDTIntToFPOp : SDTypeProfile<1, 1, [ // [su]int_to_fp 162 SDTCisFP<0>, SDTCisInt<1>, SDTCisSameNumEltsAs<0, 1> 163]>; 164def SDTFPToIntOp : SDTypeProfile<1, 1, [ // fp_to_[su]int 165 SDTCisInt<0>, SDTCisFP<1>, SDTCisSameNumEltsAs<0, 1> 166]>; 167def SDTExtInreg : SDTypeProfile<1, 2, [ // sext_inreg 168 SDTCisSameAs<0, 1>, SDTCisInt<0>, SDTCisVT<2, OtherVT>, 169 SDTCisVTSmallerThanOp<2, 1> 170]>; 171def SDTExtInvec : SDTypeProfile<1, 1, [ // sext_invec 172 SDTCisInt<0>, SDTCisVec<0>, SDTCisInt<1>, SDTCisVec<1>, 173 SDTCisOpSmallerThanOp<1, 0> 174]>; 175 176def SDTSetCC : SDTypeProfile<1, 3, [ // setcc 177 SDTCisInt<0>, SDTCisSameAs<1, 2>, SDTCisVT<3, OtherVT> 178]>; 179 180def SDTSelect : SDTypeProfile<1, 3, [ // select 181 SDTCisInt<1>, SDTCisSameAs<0, 2>, SDTCisSameAs<2, 3> 182]>; 183 184def SDTVSelect : SDTypeProfile<1, 3, [ // vselect 185 SDTCisVec<0>, SDTCisInt<1>, SDTCisSameAs<0, 2>, SDTCisSameAs<2, 3>, SDTCisSameNumEltsAs<0, 1> 186]>; 187 188def SDTSelectCC : SDTypeProfile<1, 5, [ // select_cc 189 SDTCisSameAs<1, 2>, SDTCisSameAs<3, 4>, SDTCisSameAs<0, 3>, 190 SDTCisVT<5, OtherVT> 191]>; 192 193def SDTBr : SDTypeProfile<0, 1, [ // br 194 SDTCisVT<0, OtherVT> 195]>; 196 197def SDTBrCC : SDTypeProfile<0, 4, [ // brcc 198 SDTCisVT<0, OtherVT>, SDTCisSameAs<1, 2>, SDTCisVT<3, OtherVT> 199]>; 200 201def SDTBrcond : SDTypeProfile<0, 2, [ // brcond 202 SDTCisInt<0>, SDTCisVT<1, OtherVT> 203]>; 204 205def SDTBrind : SDTypeProfile<0, 1, [ // brind 206 SDTCisPtrTy<0> 207]>; 208 209def SDTCatchret : SDTypeProfile<0, 2, [ // catchret 210 SDTCisVT<0, OtherVT>, SDTCisVT<1, OtherVT> 211]>; 212 213def SDTNone : SDTypeProfile<0, 0, []>; // ret, trap 214 215def SDTLoad : SDTypeProfile<1, 1, [ // load 216 SDTCisPtrTy<1> 217]>; 218 219def SDTStore : SDTypeProfile<0, 2, [ // store 220 SDTCisPtrTy<1> 221]>; 222 223def SDTIStore : SDTypeProfile<1, 3, [ // indexed store 224 SDTCisSameAs<0, 2>, SDTCisPtrTy<0>, SDTCisPtrTy<3> 225]>; 226 227def SDTMaskedStore: SDTypeProfile<0, 4, [ // masked store 228 SDTCisVec<0>, SDTCisPtrTy<1>, SDTCisPtrTy<2>, SDTCisVec<3>, SDTCisSameNumEltsAs<0, 3> 229]>; 230 231def SDTMaskedLoad: SDTypeProfile<1, 4, [ // masked load 232 SDTCisVec<0>, SDTCisPtrTy<1>, SDTCisPtrTy<2>, SDTCisVec<3>, SDTCisSameAs<0, 4>, 233 SDTCisSameNumEltsAs<0, 3> 234]>; 235 236def SDTVecShuffle : SDTypeProfile<1, 2, [ 237 SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2> 238]>; 239def SDTVecExtract : SDTypeProfile<1, 2, [ // vector extract 240 SDTCisEltOfVec<0, 1>, SDTCisPtrTy<2> 241]>; 242def SDTVecInsert : SDTypeProfile<1, 3, [ // vector insert 243 SDTCisEltOfVec<2, 1>, SDTCisSameAs<0, 1>, SDTCisPtrTy<3> 244]>; 245def SDTVecReduce : SDTypeProfile<1, 1, [ // vector reduction 246 SDTCisInt<0>, SDTCisVec<1> 247]>; 248 249def SDTSubVecExtract : SDTypeProfile<1, 2, [// subvector extract 250 SDTCisSubVecOfVec<0,1>, SDTCisInt<2> 251]>; 252def SDTSubVecInsert : SDTypeProfile<1, 3, [ // subvector insert 253 SDTCisSubVecOfVec<2, 1>, SDTCisSameAs<0,1>, SDTCisInt<3> 254]>; 255 256def SDTPrefetch : SDTypeProfile<0, 4, [ // prefetch 257 SDTCisPtrTy<0>, SDTCisSameAs<1, 2>, SDTCisSameAs<1, 3>, SDTCisInt<1> 258]>; 259 260def SDTMemBarrier : SDTypeProfile<0, 5, [ // memory barrier 261 SDTCisSameAs<0,1>, SDTCisSameAs<0,2>, SDTCisSameAs<0,3>, SDTCisSameAs<0,4>, 262 SDTCisInt<0> 263]>; 264def SDTAtomicFence : SDTypeProfile<0, 2, [ 265 SDTCisSameAs<0,1>, SDTCisPtrTy<0> 266]>; 267def SDTAtomic3 : SDTypeProfile<1, 3, [ 268 SDTCisSameAs<0,2>, SDTCisSameAs<0,3>, SDTCisInt<0>, SDTCisPtrTy<1> 269]>; 270def SDTAtomic2 : SDTypeProfile<1, 2, [ 271 SDTCisSameAs<0,2>, SDTCisInt<0>, SDTCisPtrTy<1> 272]>; 273 274def SDTFPAtomic2 : SDTypeProfile<1, 2, [ 275 SDTCisSameAs<0,2>, SDTCisFP<0>, SDTCisPtrTy<1> 276]>; 277 278def SDTAtomicStore : SDTypeProfile<0, 2, [ 279 SDTCisPtrTy<0>, SDTCisInt<1> 280]>; 281def SDTAtomicLoad : SDTypeProfile<1, 1, [ 282 SDTCisInt<0>, SDTCisPtrTy<1> 283]>; 284 285def SDTConvertOp : SDTypeProfile<1, 5, [ //cvtss, su, us, uu, ff, fs, fu, sf, su 286 SDTCisVT<2, OtherVT>, SDTCisVT<3, OtherVT>, SDTCisPtrTy<4>, SDTCisPtrTy<5> 287]>; 288 289class SDCallSeqStart<list<SDTypeConstraint> constraints> : 290 SDTypeProfile<0, 2, constraints>; 291class SDCallSeqEnd<list<SDTypeConstraint> constraints> : 292 SDTypeProfile<0, 2, constraints>; 293 294//===----------------------------------------------------------------------===// 295// Selection DAG Node definitions. 296// 297class SDNode<string opcode, SDTypeProfile typeprof, 298 list<SDNodeProperty> props = [], string sdclass = "SDNode"> 299 : SDPatternOperator { 300 string Opcode = opcode; 301 string SDClass = sdclass; 302 let Properties = props; 303 SDTypeProfile TypeProfile = typeprof; 304} 305 306// Special TableGen-recognized dag nodes 307def set; 308def implicit; 309def node; 310def srcvalue; 311 312def imm : SDNode<"ISD::Constant" , SDTIntLeaf , [], "ConstantSDNode">; 313def timm : SDNode<"ISD::TargetConstant",SDTIntLeaf, [], "ConstantSDNode">; 314def fpimm : SDNode<"ISD::ConstantFP", SDTFPLeaf , [], "ConstantFPSDNode">; 315def vt : SDNode<"ISD::VALUETYPE" , SDTOther , [], "VTSDNode">; 316def bb : SDNode<"ISD::BasicBlock", SDTOther , [], "BasicBlockSDNode">; 317def cond : SDNode<"ISD::CONDCODE" , SDTOther , [], "CondCodeSDNode">; 318def undef : SDNode<"ISD::UNDEF" , SDTUNDEF , []>; 319def globaladdr : SDNode<"ISD::GlobalAddress", SDTPtrLeaf, [], 320 "GlobalAddressSDNode">; 321def tglobaladdr : SDNode<"ISD::TargetGlobalAddress", SDTPtrLeaf, [], 322 "GlobalAddressSDNode">; 323def globaltlsaddr : SDNode<"ISD::GlobalTLSAddress", SDTPtrLeaf, [], 324 "GlobalAddressSDNode">; 325def tglobaltlsaddr : SDNode<"ISD::TargetGlobalTLSAddress", SDTPtrLeaf, [], 326 "GlobalAddressSDNode">; 327def constpool : SDNode<"ISD::ConstantPool", SDTPtrLeaf, [], 328 "ConstantPoolSDNode">; 329def tconstpool : SDNode<"ISD::TargetConstantPool", SDTPtrLeaf, [], 330 "ConstantPoolSDNode">; 331def jumptable : SDNode<"ISD::JumpTable", SDTPtrLeaf, [], 332 "JumpTableSDNode">; 333def tjumptable : SDNode<"ISD::TargetJumpTable", SDTPtrLeaf, [], 334 "JumpTableSDNode">; 335def frameindex : SDNode<"ISD::FrameIndex", SDTPtrLeaf, [], 336 "FrameIndexSDNode">; 337def tframeindex : SDNode<"ISD::TargetFrameIndex", SDTPtrLeaf, [], 338 "FrameIndexSDNode">; 339def externalsym : SDNode<"ISD::ExternalSymbol", SDTPtrLeaf, [], 340 "ExternalSymbolSDNode">; 341def texternalsym: SDNode<"ISD::TargetExternalSymbol", SDTPtrLeaf, [], 342 "ExternalSymbolSDNode">; 343def mcsym: SDNode<"ISD::MCSymbol", SDTPtrLeaf, [], "MCSymbolSDNode">; 344def blockaddress : SDNode<"ISD::BlockAddress", SDTPtrLeaf, [], 345 "BlockAddressSDNode">; 346def tblockaddress: SDNode<"ISD::TargetBlockAddress", SDTPtrLeaf, [], 347 "BlockAddressSDNode">; 348 349def add : SDNode<"ISD::ADD" , SDTIntBinOp , 350 [SDNPCommutative, SDNPAssociative]>; 351def sub : SDNode<"ISD::SUB" , SDTIntBinOp>; 352def mul : SDNode<"ISD::MUL" , SDTIntBinOp, 353 [SDNPCommutative, SDNPAssociative]>; 354def mulhs : SDNode<"ISD::MULHS" , SDTIntBinOp, [SDNPCommutative]>; 355def mulhu : SDNode<"ISD::MULHU" , SDTIntBinOp, [SDNPCommutative]>; 356def smullohi : SDNode<"ISD::SMUL_LOHI" , SDTIntBinHiLoOp, [SDNPCommutative]>; 357def umullohi : SDNode<"ISD::UMUL_LOHI" , SDTIntBinHiLoOp, [SDNPCommutative]>; 358def sdiv : SDNode<"ISD::SDIV" , SDTIntBinOp>; 359def udiv : SDNode<"ISD::UDIV" , SDTIntBinOp>; 360def srem : SDNode<"ISD::SREM" , SDTIntBinOp>; 361def urem : SDNode<"ISD::UREM" , SDTIntBinOp>; 362def sdivrem : SDNode<"ISD::SDIVREM" , SDTIntBinHiLoOp>; 363def udivrem : SDNode<"ISD::UDIVREM" , SDTIntBinHiLoOp>; 364def srl : SDNode<"ISD::SRL" , SDTIntShiftOp>; 365def sra : SDNode<"ISD::SRA" , SDTIntShiftOp>; 366def shl : SDNode<"ISD::SHL" , SDTIntShiftOp>; 367def rotl : SDNode<"ISD::ROTL" , SDTIntShiftOp>; 368def rotr : SDNode<"ISD::ROTR" , SDTIntShiftOp>; 369def fshl : SDNode<"ISD::FSHL" , SDTIntShiftDOp>; 370def fshr : SDNode<"ISD::FSHR" , SDTIntShiftDOp>; 371def and : SDNode<"ISD::AND" , SDTIntBinOp, 372 [SDNPCommutative, SDNPAssociative]>; 373def or : SDNode<"ISD::OR" , SDTIntBinOp, 374 [SDNPCommutative, SDNPAssociative]>; 375def xor : SDNode<"ISD::XOR" , SDTIntBinOp, 376 [SDNPCommutative, SDNPAssociative]>; 377def addc : SDNode<"ISD::ADDC" , SDTIntBinOp, 378 [SDNPCommutative, SDNPOutGlue]>; 379def adde : SDNode<"ISD::ADDE" , SDTIntBinOp, 380 [SDNPCommutative, SDNPOutGlue, SDNPInGlue]>; 381def subc : SDNode<"ISD::SUBC" , SDTIntBinOp, 382 [SDNPOutGlue]>; 383def sube : SDNode<"ISD::SUBE" , SDTIntBinOp, 384 [SDNPOutGlue, SDNPInGlue]>; 385def smin : SDNode<"ISD::SMIN" , SDTIntBinOp, 386 [SDNPCommutative, SDNPAssociative]>; 387def smax : SDNode<"ISD::SMAX" , SDTIntBinOp, 388 [SDNPCommutative, SDNPAssociative]>; 389def umin : SDNode<"ISD::UMIN" , SDTIntBinOp, 390 [SDNPCommutative, SDNPAssociative]>; 391def umax : SDNode<"ISD::UMAX" , SDTIntBinOp, 392 [SDNPCommutative, SDNPAssociative]>; 393 394def saddsat : SDNode<"ISD::SADDSAT" , SDTIntBinOp, [SDNPCommutative]>; 395def uaddsat : SDNode<"ISD::UADDSAT" , SDTIntBinOp, [SDNPCommutative]>; 396def ssubsat : SDNode<"ISD::SSUBSAT" , SDTIntBinOp>; 397def usubsat : SDNode<"ISD::USUBSAT" , SDTIntBinOp>; 398 399def smulfix : SDNode<"ISD::SMULFIX" , SDTIntScaledBinOp, [SDNPCommutative]>; 400def smulfixsat : SDNode<"ISD::SMULFIXSAT", SDTIntScaledBinOp, [SDNPCommutative]>; 401def umulfix : SDNode<"ISD::UMULFIX" , SDTIntScaledBinOp, [SDNPCommutative]>; 402def umulfixsat : SDNode<"ISD::UMULFIXSAT", SDTIntScaledBinOp, [SDNPCommutative]>; 403def sdivfix : SDNode<"ISD::SDIVFIX" , SDTIntScaledBinOp>; 404def udivfix : SDNode<"ISD::UDIVFIX" , SDTIntScaledBinOp>; 405 406def sext_inreg : SDNode<"ISD::SIGN_EXTEND_INREG", SDTExtInreg>; 407def sext_invec : SDNode<"ISD::SIGN_EXTEND_VECTOR_INREG", SDTExtInvec>; 408def zext_invec : SDNode<"ISD::ZERO_EXTEND_VECTOR_INREG", SDTExtInvec>; 409 410def abs : SDNode<"ISD::ABS" , SDTIntUnaryOp>; 411def bitreverse : SDNode<"ISD::BITREVERSE" , SDTIntUnaryOp>; 412def bswap : SDNode<"ISD::BSWAP" , SDTIntUnaryOp>; 413def ctlz : SDNode<"ISD::CTLZ" , SDTIntBitCountUnaryOp>; 414def cttz : SDNode<"ISD::CTTZ" , SDTIntBitCountUnaryOp>; 415def ctpop : SDNode<"ISD::CTPOP" , SDTIntBitCountUnaryOp>; 416def ctlz_zero_undef : SDNode<"ISD::CTLZ_ZERO_UNDEF", SDTIntBitCountUnaryOp>; 417def cttz_zero_undef : SDNode<"ISD::CTTZ_ZERO_UNDEF", SDTIntBitCountUnaryOp>; 418def sext : SDNode<"ISD::SIGN_EXTEND", SDTIntExtendOp>; 419def zext : SDNode<"ISD::ZERO_EXTEND", SDTIntExtendOp>; 420def anyext : SDNode<"ISD::ANY_EXTEND" , SDTIntExtendOp>; 421def trunc : SDNode<"ISD::TRUNCATE" , SDTIntTruncOp>; 422def bitconvert : SDNode<"ISD::BITCAST" , SDTUnaryOp>; 423def addrspacecast : SDNode<"ISD::ADDRSPACECAST", SDTUnaryOp>; 424def extractelt : SDNode<"ISD::EXTRACT_VECTOR_ELT", SDTVecExtract>; 425def insertelt : SDNode<"ISD::INSERT_VECTOR_ELT", SDTVecInsert>; 426 427def vecreduce_add : SDNode<"ISD::VECREDUCE_ADD", SDTVecReduce>; 428def vecreduce_smax : SDNode<"ISD::VECREDUCE_SMAX", SDTVecReduce>; 429def vecreduce_umax : SDNode<"ISD::VECREDUCE_UMAX", SDTVecReduce>; 430def vecreduce_smin : SDNode<"ISD::VECREDUCE_SMIN", SDTVecReduce>; 431def vecreduce_umin : SDNode<"ISD::VECREDUCE_UMIN", SDTVecReduce>; 432 433def fadd : SDNode<"ISD::FADD" , SDTFPBinOp, [SDNPCommutative]>; 434def fsub : SDNode<"ISD::FSUB" , SDTFPBinOp>; 435def fmul : SDNode<"ISD::FMUL" , SDTFPBinOp, [SDNPCommutative]>; 436def fdiv : SDNode<"ISD::FDIV" , SDTFPBinOp>; 437def frem : SDNode<"ISD::FREM" , SDTFPBinOp>; 438def fma : SDNode<"ISD::FMA" , SDTFPTernaryOp>; 439def fmad : SDNode<"ISD::FMAD" , SDTFPTernaryOp>; 440def fabs : SDNode<"ISD::FABS" , SDTFPUnaryOp>; 441def fminnum : SDNode<"ISD::FMINNUM" , SDTFPBinOp, 442 [SDNPCommutative, SDNPAssociative]>; 443def fmaxnum : SDNode<"ISD::FMAXNUM" , SDTFPBinOp, 444 [SDNPCommutative, SDNPAssociative]>; 445def fminnum_ieee : SDNode<"ISD::FMINNUM_IEEE", SDTFPBinOp, 446 [SDNPCommutative]>; 447def fmaxnum_ieee : SDNode<"ISD::FMAXNUM_IEEE", SDTFPBinOp, 448 [SDNPCommutative]>; 449def fminimum : SDNode<"ISD::FMINIMUM" , SDTFPBinOp, 450 [SDNPCommutative, SDNPAssociative]>; 451def fmaximum : SDNode<"ISD::FMAXIMUM" , SDTFPBinOp, 452 [SDNPCommutative, SDNPAssociative]>; 453def fgetsign : SDNode<"ISD::FGETSIGN" , SDTFPToIntOp>; 454def fcanonicalize : SDNode<"ISD::FCANONICALIZE", SDTFPUnaryOp>; 455def fneg : SDNode<"ISD::FNEG" , SDTFPUnaryOp>; 456def fsqrt : SDNode<"ISD::FSQRT" , SDTFPUnaryOp>; 457def fsin : SDNode<"ISD::FSIN" , SDTFPUnaryOp>; 458def fcos : SDNode<"ISD::FCOS" , SDTFPUnaryOp>; 459def fexp2 : SDNode<"ISD::FEXP2" , SDTFPUnaryOp>; 460def fpow : SDNode<"ISD::FPOW" , SDTFPBinOp>; 461def flog2 : SDNode<"ISD::FLOG2" , SDTFPUnaryOp>; 462def frint : SDNode<"ISD::FRINT" , SDTFPUnaryOp>; 463def ftrunc : SDNode<"ISD::FTRUNC" , SDTFPUnaryOp>; 464def fceil : SDNode<"ISD::FCEIL" , SDTFPUnaryOp>; 465def ffloor : SDNode<"ISD::FFLOOR" , SDTFPUnaryOp>; 466def fnearbyint : SDNode<"ISD::FNEARBYINT" , SDTFPUnaryOp>; 467def fround : SDNode<"ISD::FROUND" , SDTFPUnaryOp>; 468 469def lround : SDNode<"ISD::LROUND" , SDTFPToIntOp>; 470def llround : SDNode<"ISD::LLROUND" , SDTFPToIntOp>; 471def lrint : SDNode<"ISD::LRINT" , SDTFPToIntOp>; 472def llrint : SDNode<"ISD::LLRINT" , SDTFPToIntOp>; 473 474def fpround : SDNode<"ISD::FP_ROUND" , SDTFPRoundOp>; 475def fpextend : SDNode<"ISD::FP_EXTEND" , SDTFPExtendOp>; 476def fcopysign : SDNode<"ISD::FCOPYSIGN" , SDTFPSignOp>; 477 478def sint_to_fp : SDNode<"ISD::SINT_TO_FP" , SDTIntToFPOp>; 479def uint_to_fp : SDNode<"ISD::UINT_TO_FP" , SDTIntToFPOp>; 480def fp_to_sint : SDNode<"ISD::FP_TO_SINT" , SDTFPToIntOp>; 481def fp_to_uint : SDNode<"ISD::FP_TO_UINT" , SDTFPToIntOp>; 482def f16_to_fp : SDNode<"ISD::FP16_TO_FP" , SDTIntToFPOp>; 483def fp_to_f16 : SDNode<"ISD::FP_TO_FP16" , SDTFPToIntOp>; 484 485def strict_fadd : SDNode<"ISD::STRICT_FADD", 486 SDTFPBinOp, [SDNPHasChain, SDNPCommutative]>; 487def strict_fsub : SDNode<"ISD::STRICT_FSUB", 488 SDTFPBinOp, [SDNPHasChain]>; 489def strict_fmul : SDNode<"ISD::STRICT_FMUL", 490 SDTFPBinOp, [SDNPHasChain, SDNPCommutative]>; 491def strict_fdiv : SDNode<"ISD::STRICT_FDIV", 492 SDTFPBinOp, [SDNPHasChain]>; 493def strict_frem : SDNode<"ISD::STRICT_FREM", 494 SDTFPBinOp, [SDNPHasChain]>; 495def strict_fma : SDNode<"ISD::STRICT_FMA", 496 SDTFPTernaryOp, [SDNPHasChain]>; 497def strict_fsqrt : SDNode<"ISD::STRICT_FSQRT", 498 SDTFPUnaryOp, [SDNPHasChain]>; 499def strict_fsin : SDNode<"ISD::STRICT_FSIN", 500 SDTFPUnaryOp, [SDNPHasChain]>; 501def strict_fcos : SDNode<"ISD::STRICT_FCOS", 502 SDTFPUnaryOp, [SDNPHasChain]>; 503def strict_fexp2 : SDNode<"ISD::STRICT_FEXP2", 504 SDTFPUnaryOp, [SDNPHasChain]>; 505def strict_fpow : SDNode<"ISD::STRICT_FPOW", 506 SDTFPBinOp, [SDNPHasChain]>; 507def strict_flog2 : SDNode<"ISD::STRICT_FLOG2", 508 SDTFPUnaryOp, [SDNPHasChain]>; 509def strict_frint : SDNode<"ISD::STRICT_FRINT", 510 SDTFPUnaryOp, [SDNPHasChain]>; 511def strict_lrint : SDNode<"ISD::STRICT_LRINT", 512 SDTFPToIntOp, [SDNPHasChain]>; 513def strict_llrint : SDNode<"ISD::STRICT_LLRINT", 514 SDTFPToIntOp, [SDNPHasChain]>; 515def strict_fnearbyint : SDNode<"ISD::STRICT_FNEARBYINT", 516 SDTFPUnaryOp, [SDNPHasChain]>; 517def strict_fceil : SDNode<"ISD::STRICT_FCEIL", 518 SDTFPUnaryOp, [SDNPHasChain]>; 519def strict_ffloor : SDNode<"ISD::STRICT_FFLOOR", 520 SDTFPUnaryOp, [SDNPHasChain]>; 521def strict_lround : SDNode<"ISD::STRICT_LROUND", 522 SDTFPToIntOp, [SDNPHasChain]>; 523def strict_llround : SDNode<"ISD::STRICT_LLROUND", 524 SDTFPToIntOp, [SDNPHasChain]>; 525def strict_fround : SDNode<"ISD::STRICT_FROUND", 526 SDTFPUnaryOp, [SDNPHasChain]>; 527def strict_ftrunc : SDNode<"ISD::STRICT_FTRUNC", 528 SDTFPUnaryOp, [SDNPHasChain]>; 529def strict_fminnum : SDNode<"ISD::STRICT_FMINNUM", 530 SDTFPBinOp, [SDNPHasChain, 531 SDNPCommutative, SDNPAssociative]>; 532def strict_fmaxnum : SDNode<"ISD::STRICT_FMAXNUM", 533 SDTFPBinOp, [SDNPHasChain, 534 SDNPCommutative, SDNPAssociative]>; 535def strict_fminimum : SDNode<"ISD::STRICT_FMINIMUM", 536 SDTFPBinOp, [SDNPHasChain, 537 SDNPCommutative, SDNPAssociative]>; 538def strict_fmaximum : SDNode<"ISD::STRICT_FMAXIMUM", 539 SDTFPBinOp, [SDNPHasChain, 540 SDNPCommutative, SDNPAssociative]>; 541def strict_fpround : SDNode<"ISD::STRICT_FP_ROUND", 542 SDTFPRoundOp, [SDNPHasChain]>; 543def strict_fpextend : SDNode<"ISD::STRICT_FP_EXTEND", 544 SDTFPExtendOp, [SDNPHasChain]>; 545def strict_fp_to_sint : SDNode<"ISD::STRICT_FP_TO_SINT", 546 SDTFPToIntOp, [SDNPHasChain]>; 547def strict_fp_to_uint : SDNode<"ISD::STRICT_FP_TO_UINT", 548 SDTFPToIntOp, [SDNPHasChain]>; 549def strict_sint_to_fp : SDNode<"ISD::STRICT_SINT_TO_FP", 550 SDTIntToFPOp, [SDNPHasChain]>; 551def strict_uint_to_fp : SDNode<"ISD::STRICT_UINT_TO_FP", 552 SDTIntToFPOp, [SDNPHasChain]>; 553 554def setcc : SDNode<"ISD::SETCC" , SDTSetCC>; 555def select : SDNode<"ISD::SELECT" , SDTSelect>; 556def vselect : SDNode<"ISD::VSELECT" , SDTVSelect>; 557def selectcc : SDNode<"ISD::SELECT_CC" , SDTSelectCC>; 558 559def brcc : SDNode<"ISD::BR_CC" , SDTBrCC, [SDNPHasChain]>; 560def brcond : SDNode<"ISD::BRCOND" , SDTBrcond, [SDNPHasChain]>; 561def brind : SDNode<"ISD::BRIND" , SDTBrind, [SDNPHasChain]>; 562def br : SDNode<"ISD::BR" , SDTBr, [SDNPHasChain]>; 563def catchret : SDNode<"ISD::CATCHRET" , SDTCatchret, 564 [SDNPHasChain, SDNPSideEffect]>; 565def cleanupret : SDNode<"ISD::CLEANUPRET" , SDTNone, [SDNPHasChain]>; 566def catchpad : SDNode<"ISD::CATCHPAD" , SDTNone, 567 [SDNPHasChain, SDNPSideEffect]>; 568 569def trap : SDNode<"ISD::TRAP" , SDTNone, 570 [SDNPHasChain, SDNPSideEffect]>; 571def debugtrap : SDNode<"ISD::DEBUGTRAP" , SDTNone, 572 [SDNPHasChain, SDNPSideEffect]>; 573 574def prefetch : SDNode<"ISD::PREFETCH" , SDTPrefetch, 575 [SDNPHasChain, SDNPMayLoad, SDNPMayStore, 576 SDNPMemOperand]>; 577 578def readcyclecounter : SDNode<"ISD::READCYCLECOUNTER", SDTIntLeaf, 579 [SDNPHasChain, SDNPSideEffect]>; 580 581def atomic_fence : SDNode<"ISD::ATOMIC_FENCE" , SDTAtomicFence, 582 [SDNPHasChain, SDNPSideEffect]>; 583 584def atomic_cmp_swap : SDNode<"ISD::ATOMIC_CMP_SWAP" , SDTAtomic3, 585 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 586def atomic_load_add : SDNode<"ISD::ATOMIC_LOAD_ADD" , SDTAtomic2, 587 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 588def atomic_swap : SDNode<"ISD::ATOMIC_SWAP", SDTAtomic2, 589 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 590def atomic_load_sub : SDNode<"ISD::ATOMIC_LOAD_SUB" , SDTAtomic2, 591 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 592def atomic_load_and : SDNode<"ISD::ATOMIC_LOAD_AND" , SDTAtomic2, 593 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 594def atomic_load_clr : SDNode<"ISD::ATOMIC_LOAD_CLR" , SDTAtomic2, 595 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 596def atomic_load_or : SDNode<"ISD::ATOMIC_LOAD_OR" , SDTAtomic2, 597 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 598def atomic_load_xor : SDNode<"ISD::ATOMIC_LOAD_XOR" , SDTAtomic2, 599 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 600def atomic_load_nand: SDNode<"ISD::ATOMIC_LOAD_NAND", SDTAtomic2, 601 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 602def atomic_load_min : SDNode<"ISD::ATOMIC_LOAD_MIN", SDTAtomic2, 603 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 604def atomic_load_max : SDNode<"ISD::ATOMIC_LOAD_MAX", SDTAtomic2, 605 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 606def atomic_load_umin : SDNode<"ISD::ATOMIC_LOAD_UMIN", SDTAtomic2, 607 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 608def atomic_load_umax : SDNode<"ISD::ATOMIC_LOAD_UMAX", SDTAtomic2, 609 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 610def atomic_load_fadd : SDNode<"ISD::ATOMIC_LOAD_FADD" , SDTFPAtomic2, 611 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 612def atomic_load_fsub : SDNode<"ISD::ATOMIC_LOAD_FSUB" , SDTFPAtomic2, 613 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 614 615def atomic_load : SDNode<"ISD::ATOMIC_LOAD", SDTAtomicLoad, 616 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 617def atomic_store : SDNode<"ISD::ATOMIC_STORE", SDTAtomicStore, 618 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 619 620def masked_st : SDNode<"ISD::MSTORE", SDTMaskedStore, 621 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 622def masked_ld : SDNode<"ISD::MLOAD", SDTMaskedLoad, 623 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 624 625// Do not use ld, st directly. Use load, extload, sextload, zextload, store, 626// and truncst (see below). 627def ld : SDNode<"ISD::LOAD" , SDTLoad, 628 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 629def st : SDNode<"ISD::STORE" , SDTStore, 630 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 631def ist : SDNode<"ISD::STORE" , SDTIStore, 632 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 633 634def vector_shuffle : SDNode<"ISD::VECTOR_SHUFFLE", SDTVecShuffle, []>; 635def build_vector : SDNode<"ISD::BUILD_VECTOR", SDTypeProfile<1, -1, []>, []>; 636def scalar_to_vector : SDNode<"ISD::SCALAR_TO_VECTOR", SDTypeProfile<1, 1, []>, 637 []>; 638 639// vector_extract/vector_insert are deprecated. extractelt/insertelt 640// are preferred. 641def vector_extract : SDNode<"ISD::EXTRACT_VECTOR_ELT", 642 SDTypeProfile<1, 2, [SDTCisPtrTy<2>]>, []>; 643def vector_insert : SDNode<"ISD::INSERT_VECTOR_ELT", 644 SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisPtrTy<3>]>, []>; 645def concat_vectors : SDNode<"ISD::CONCAT_VECTORS", 646 SDTypeProfile<1, 2, [SDTCisSubVecOfVec<1, 0>, SDTCisSameAs<1, 2>]>,[]>; 647 648// This operator does not do subvector type checking. The ARM 649// backend, at least, needs it. 650def vector_extract_subvec : SDNode<"ISD::EXTRACT_SUBVECTOR", 651 SDTypeProfile<1, 2, [SDTCisInt<2>, SDTCisVec<1>, SDTCisVec<0>]>, 652 []>; 653 654// This operator does subvector type checking. 655def extract_subvector : SDNode<"ISD::EXTRACT_SUBVECTOR", SDTSubVecExtract, []>; 656def insert_subvector : SDNode<"ISD::INSERT_SUBVECTOR", SDTSubVecInsert, []>; 657 658// Nodes for intrinsics, you should use the intrinsic itself and let tblgen use 659// these internally. Don't reference these directly. 660def intrinsic_void : SDNode<"ISD::INTRINSIC_VOID", 661 SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>, 662 [SDNPHasChain]>; 663def intrinsic_w_chain : SDNode<"ISD::INTRINSIC_W_CHAIN", 664 SDTypeProfile<1, -1, [SDTCisPtrTy<1>]>, 665 [SDNPHasChain]>; 666def intrinsic_wo_chain : SDNode<"ISD::INTRINSIC_WO_CHAIN", 667 SDTypeProfile<1, -1, [SDTCisPtrTy<1>]>, []>; 668 669def SDT_assertext : SDTypeProfile<1, 1, 670 [SDTCisInt<0>, SDTCisInt<1>, SDTCisSameAs<1, 0>]>; 671def assertsext : SDNode<"ISD::AssertSext", SDT_assertext>; 672def assertzext : SDNode<"ISD::AssertZext", SDT_assertext>; 673 674 675//===----------------------------------------------------------------------===// 676// Selection DAG Condition Codes 677 678class CondCode<string fcmpName = "", string icmpName = ""> { 679 string ICmpPredicate = icmpName; 680 string FCmpPredicate = fcmpName; 681} 682 683// ISD::CondCode enums, and mapping to CmpInst::Predicate names 684def SETOEQ : CondCode<"FCMP_OEQ">; 685def SETOGT : CondCode<"FCMP_OGT">; 686def SETOGE : CondCode<"FCMP_OGE">; 687def SETOLT : CondCode<"FCMP_OLT">; 688def SETOLE : CondCode<"FCMP_OLE">; 689def SETONE : CondCode<"FCMP_ONE">; 690def SETO : CondCode<"FCMP_ORD">; 691def SETUO : CondCode<"FCMP_UNO">; 692def SETUEQ : CondCode<"FCMP_UEQ">; 693def SETUGT : CondCode<"FCMP_UGT", "ICMP_UGT">; 694def SETUGE : CondCode<"FCMP_UGE", "ICMP_UGE">; 695def SETULT : CondCode<"FCMP_ULT", "ICMP_ULT">; 696def SETULE : CondCode<"FCMP_ULE", "ICMP_ULE">; 697def SETUNE : CondCode<"FCMP_UNE">; 698def SETEQ : CondCode<"", "ICMP_EQ">; 699def SETGT : CondCode<"", "ICMP_SGT">; 700def SETGE : CondCode<"", "ICMP_SGE">; 701def SETLT : CondCode<"", "ICMP_SLT">; 702def SETLE : CondCode<"", "ICMP_SLE">; 703def SETNE : CondCode<"", "ICMP_NE">; 704 705//===----------------------------------------------------------------------===// 706// Selection DAG Node Transformation Functions. 707// 708// This mechanism allows targets to manipulate nodes in the output DAG once a 709// match has been formed. This is typically used to manipulate immediate 710// values. 711// 712class SDNodeXForm<SDNode opc, code xformFunction> { 713 SDNode Opcode = opc; 714 code XFormFunction = xformFunction; 715} 716 717def NOOP_SDNodeXForm : SDNodeXForm<imm, [{}]>; 718 719//===----------------------------------------------------------------------===// 720// PatPred Subclasses. 721// 722// These allow specifying different sorts of predicates that control whether a 723// node is matched. 724// 725class PatPred; 726 727class CodePatPred<code predicate> : PatPred { 728 code PredicateCode = predicate; 729} 730 731 732//===----------------------------------------------------------------------===// 733// Selection DAG Pattern Fragments. 734// 735// Pattern fragments are reusable chunks of dags that match specific things. 736// They can take arguments and have C++ predicates that control whether they 737// match. They are intended to make the patterns for common instructions more 738// compact and readable. 739// 740 741/// PatFrags - Represents a set of pattern fragments. Each single fragment 742/// can match something on the DAG, from a single node to multiple nested other 743/// fragments. The whole set of fragments matches if any of the single 744/// fragemnts match. This allows e.g. matching and "add with overflow" and 745/// a regular "add" with the same fragment set. 746/// 747class PatFrags<dag ops, list<dag> frags, code pred = [{}], 748 SDNodeXForm xform = NOOP_SDNodeXForm> : SDPatternOperator { 749 dag Operands = ops; 750 list<dag> Fragments = frags; 751 code PredicateCode = pred; 752 code GISelPredicateCode = [{}]; 753 code ImmediateCode = [{}]; 754 SDNodeXForm OperandTransform = xform; 755 756 // When this is set, the PredicateCode may refer to a constant Operands 757 // vector which contains the captured nodes of the DAG, in the order listed 758 // by the Operands field above. 759 // 760 // This is useful when Fragments involves associative / commutative 761 // operators: a single piece of code can easily refer to all operands even 762 // when re-associated / commuted variants of the fragment are matched. 763 bit PredicateCodeUsesOperands = 0; 764 765 // Define a few pre-packaged predicates. This helps GlobalISel import 766 // existing rules from SelectionDAG for many common cases. 767 // They will be tested prior to the code in pred and must not be used in 768 // ImmLeaf and its subclasses. 769 770 // Is the desired pre-packaged predicate for a load? 771 bit IsLoad = ?; 772 // Is the desired pre-packaged predicate for a store? 773 bit IsStore = ?; 774 // Is the desired pre-packaged predicate for an atomic? 775 bit IsAtomic = ?; 776 777 // cast<LoadSDNode>(N)->getAddressingMode() == ISD::UNINDEXED; 778 // cast<StoreSDNode>(N)->getAddressingMode() == ISD::UNINDEXED; 779 bit IsUnindexed = ?; 780 781 // cast<LoadSDNode>(N)->getExtensionType() != ISD::NON_EXTLOAD 782 bit IsNonExtLoad = ?; 783 // cast<LoadSDNode>(N)->getExtensionType() == ISD::EXTLOAD; 784 bit IsAnyExtLoad = ?; 785 // cast<LoadSDNode>(N)->getExtensionType() == ISD::SEXTLOAD; 786 bit IsSignExtLoad = ?; 787 // cast<LoadSDNode>(N)->getExtensionType() == ISD::ZEXTLOAD; 788 bit IsZeroExtLoad = ?; 789 // !cast<StoreSDNode>(N)->isTruncatingStore(); 790 // cast<StoreSDNode>(N)->isTruncatingStore(); 791 bit IsTruncStore = ?; 792 793 // cast<MemSDNode>(N)->getAddressSpace() == 794 // If this empty, accept any address space. 795 list<int> AddressSpaces = ?; 796 797 // cast<MemSDNode>(N)->getAlignment() >= 798 // If this is empty, accept any alignment. 799 int MinAlignment = ?; 800 801 // cast<AtomicSDNode>(N)->getOrdering() == AtomicOrdering::Monotonic 802 bit IsAtomicOrderingMonotonic = ?; 803 // cast<AtomicSDNode>(N)->getOrdering() == AtomicOrdering::Acquire 804 bit IsAtomicOrderingAcquire = ?; 805 // cast<AtomicSDNode>(N)->getOrdering() == AtomicOrdering::Release 806 bit IsAtomicOrderingRelease = ?; 807 // cast<AtomicSDNode>(N)->getOrdering() == AtomicOrdering::AcquireRelease 808 bit IsAtomicOrderingAcquireRelease = ?; 809 // cast<AtomicSDNode>(N)->getOrdering() == AtomicOrdering::SequentiallyConsistent 810 bit IsAtomicOrderingSequentiallyConsistent = ?; 811 812 // isAcquireOrStronger(cast<AtomicSDNode>(N)->getOrdering()) 813 // !isAcquireOrStronger(cast<AtomicSDNode>(N)->getOrdering()) 814 bit IsAtomicOrderingAcquireOrStronger = ?; 815 816 // isReleaseOrStronger(cast<AtomicSDNode>(N)->getOrdering()) 817 // !isReleaseOrStronger(cast<AtomicSDNode>(N)->getOrdering()) 818 bit IsAtomicOrderingReleaseOrStronger = ?; 819 820 // cast<LoadSDNode>(N)->getMemoryVT() == MVT::<VT>; 821 // cast<StoreSDNode>(N)->getMemoryVT() == MVT::<VT>; 822 ValueType MemoryVT = ?; 823 // cast<LoadSDNode>(N)->getMemoryVT().getScalarType() == MVT::<VT>; 824 // cast<StoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::<VT>; 825 ValueType ScalarMemoryVT = ?; 826} 827 828// PatFrag - A version of PatFrags matching only a single fragment. 829class PatFrag<dag ops, dag frag, code pred = [{}], 830 SDNodeXForm xform = NOOP_SDNodeXForm> 831 : PatFrags<ops, [frag], pred, xform>; 832 833// OutPatFrag is a pattern fragment that is used as part of an output pattern 834// (not an input pattern). These do not have predicates or transforms, but are 835// used to avoid repeated subexpressions in output patterns. 836class OutPatFrag<dag ops, dag frag> 837 : PatFrag<ops, frag, [{}], NOOP_SDNodeXForm>; 838 839// PatLeaf's are pattern fragments that have no operands. This is just a helper 840// to define immediates and other common things concisely. 841class PatLeaf<dag frag, code pred = [{}], SDNodeXForm xform = NOOP_SDNodeXForm> 842 : PatFrag<(ops), frag, pred, xform>; 843 844 845// ImmLeaf is a pattern fragment with a constraint on the immediate. The 846// constraint is a function that is run on the immediate (always with the value 847// sign extended out to an int64_t) as Imm. For example: 848// 849// def immSExt8 : ImmLeaf<i16, [{ return (char)Imm == Imm; }]>; 850// 851// this is a more convenient form to match 'imm' nodes in than PatLeaf and also 852// is preferred over using PatLeaf because it allows the code generator to 853// reason more about the constraint. 854// 855// If FastIsel should ignore all instructions that have an operand of this type, 856// the FastIselShouldIgnore flag can be set. This is an optimization to reduce 857// the code size of the generated fast instruction selector. 858class ImmLeaf<ValueType vt, code pred, SDNodeXForm xform = NOOP_SDNodeXForm, 859 SDNode ImmNode = imm> 860 : PatFrag<(ops), (vt ImmNode), [{}], xform> { 861 let ImmediateCode = pred; 862 bit FastIselShouldIgnore = 0; 863 864 // Is the data type of the immediate an APInt? 865 bit IsAPInt = 0; 866 867 // Is the data type of the immediate an APFloat? 868 bit IsAPFloat = 0; 869} 870 871// Convenience wrapper for ImmLeaf to use timm/TargetConstant instead 872// of imm/Constant. 873class TImmLeaf<ValueType vt, code pred, SDNodeXForm xform = NOOP_SDNodeXForm, 874 SDNode ImmNode = timm> : ImmLeaf<vt, pred, xform, ImmNode>; 875 876// An ImmLeaf except that Imm is an APInt. This is useful when you need to 877// zero-extend the immediate instead of sign-extend it. 878// 879// Note that FastISel does not currently understand IntImmLeaf and will not 880// generate code for rules that make use of it. As such, it does not make sense 881// to replace ImmLeaf with IntImmLeaf. However, replacing PatLeaf with an 882// IntImmLeaf will allow GlobalISel to import the rule. 883class IntImmLeaf<ValueType vt, code pred, SDNodeXForm xform = NOOP_SDNodeXForm> 884 : ImmLeaf<vt, pred, xform> { 885 let IsAPInt = 1; 886 let FastIselShouldIgnore = 1; 887} 888 889// An ImmLeaf except that Imm is an APFloat. 890// 891// Note that FastISel does not currently understand FPImmLeaf and will not 892// generate code for rules that make use of it. 893class FPImmLeaf<ValueType vt, code pred, SDNodeXForm xform = NOOP_SDNodeXForm> 894 : ImmLeaf<vt, pred, xform, fpimm> { 895 let IsAPFloat = 1; 896 let FastIselShouldIgnore = 1; 897} 898 899// Leaf fragments. 900 901def vtInt : PatLeaf<(vt), [{ return N->getVT().isInteger(); }]>; 902def vtFP : PatLeaf<(vt), [{ return N->getVT().isFloatingPoint(); }]>; 903 904// Use ISD::isBuildVectorAllOnes or ISD::isBuildVectorAllZeros to look for 905// the corresponding build_vector. Will look through bitcasts except when used 906// as a pattern root. 907def immAllOnesV; // ISD::isBuildVectorAllOnes 908def immAllZerosV; // ISD::isBuildVectorAllZeros 909 910// Other helper fragments. 911def not : PatFrag<(ops node:$in), (xor node:$in, -1)>; 912def vnot : PatFrag<(ops node:$in), (xor node:$in, immAllOnesV)>; 913def ineg : PatFrag<(ops node:$in), (sub 0, node:$in)>; 914 915// null_frag - The null pattern operator is used in multiclass instantiations 916// which accept an SDPatternOperator for use in matching patterns for internal 917// definitions. When expanding a pattern, if the null fragment is referenced 918// in the expansion, the pattern is discarded and it is as-if '[]' had been 919// specified. This allows multiclasses to have the isel patterns be optional. 920def null_frag : SDPatternOperator; 921 922// load fragments. 923def unindexedload : PatFrag<(ops node:$ptr), (ld node:$ptr)> { 924 let IsLoad = 1; 925 let IsUnindexed = 1; 926} 927def load : PatFrag<(ops node:$ptr), (unindexedload node:$ptr)> { 928 let IsLoad = 1; 929 let IsNonExtLoad = 1; 930} 931 932// extending load fragments. 933def extload : PatFrag<(ops node:$ptr), (unindexedload node:$ptr)> { 934 let IsLoad = 1; 935 let IsAnyExtLoad = 1; 936} 937def sextload : PatFrag<(ops node:$ptr), (unindexedload node:$ptr)> { 938 let IsLoad = 1; 939 let IsSignExtLoad = 1; 940} 941def zextload : PatFrag<(ops node:$ptr), (unindexedload node:$ptr)> { 942 let IsLoad = 1; 943 let IsZeroExtLoad = 1; 944} 945 946def extloadi1 : PatFrag<(ops node:$ptr), (extload node:$ptr)> { 947 let IsLoad = 1; 948 let MemoryVT = i1; 949} 950def extloadi8 : PatFrag<(ops node:$ptr), (extload node:$ptr)> { 951 let IsLoad = 1; 952 let MemoryVT = i8; 953} 954def extloadi16 : PatFrag<(ops node:$ptr), (extload node:$ptr)> { 955 let IsLoad = 1; 956 let MemoryVT = i16; 957} 958def extloadi32 : PatFrag<(ops node:$ptr), (extload node:$ptr)> { 959 let IsLoad = 1; 960 let MemoryVT = i32; 961} 962def extloadf16 : PatFrag<(ops node:$ptr), (extload node:$ptr)> { 963 let IsLoad = 1; 964 let MemoryVT = f16; 965} 966def extloadf32 : PatFrag<(ops node:$ptr), (extload node:$ptr)> { 967 let IsLoad = 1; 968 let MemoryVT = f32; 969} 970def extloadf64 : PatFrag<(ops node:$ptr), (extload node:$ptr)> { 971 let IsLoad = 1; 972 let MemoryVT = f64; 973} 974 975def sextloadi1 : PatFrag<(ops node:$ptr), (sextload node:$ptr)> { 976 let IsLoad = 1; 977 let MemoryVT = i1; 978} 979def sextloadi8 : PatFrag<(ops node:$ptr), (sextload node:$ptr)> { 980 let IsLoad = 1; 981 let MemoryVT = i8; 982} 983def sextloadi16 : PatFrag<(ops node:$ptr), (sextload node:$ptr)> { 984 let IsLoad = 1; 985 let MemoryVT = i16; 986} 987def sextloadi32 : PatFrag<(ops node:$ptr), (sextload node:$ptr)> { 988 let IsLoad = 1; 989 let MemoryVT = i32; 990} 991 992def zextloadi1 : PatFrag<(ops node:$ptr), (zextload node:$ptr)> { 993 let IsLoad = 1; 994 let MemoryVT = i1; 995} 996def zextloadi8 : PatFrag<(ops node:$ptr), (zextload node:$ptr)> { 997 let IsLoad = 1; 998 let MemoryVT = i8; 999} 1000def zextloadi16 : PatFrag<(ops node:$ptr), (zextload node:$ptr)> { 1001 let IsLoad = 1; 1002 let MemoryVT = i16; 1003} 1004def zextloadi32 : PatFrag<(ops node:$ptr), (zextload node:$ptr)> { 1005 let IsLoad = 1; 1006 let MemoryVT = i32; 1007} 1008 1009def extloadvi1 : PatFrag<(ops node:$ptr), (extload node:$ptr)> { 1010 let IsLoad = 1; 1011 let ScalarMemoryVT = i1; 1012} 1013def extloadvi8 : PatFrag<(ops node:$ptr), (extload node:$ptr)> { 1014 let IsLoad = 1; 1015 let ScalarMemoryVT = i8; 1016} 1017def extloadvi16 : PatFrag<(ops node:$ptr), (extload node:$ptr)> { 1018 let IsLoad = 1; 1019 let ScalarMemoryVT = i16; 1020} 1021def extloadvi32 : PatFrag<(ops node:$ptr), (extload node:$ptr)> { 1022 let IsLoad = 1; 1023 let ScalarMemoryVT = i32; 1024} 1025def extloadvf32 : PatFrag<(ops node:$ptr), (extload node:$ptr)> { 1026 let IsLoad = 1; 1027 let ScalarMemoryVT = f32; 1028} 1029def extloadvf64 : PatFrag<(ops node:$ptr), (extload node:$ptr)> { 1030 let IsLoad = 1; 1031 let ScalarMemoryVT = f64; 1032} 1033 1034def sextloadvi1 : PatFrag<(ops node:$ptr), (sextload node:$ptr)> { 1035 let IsLoad = 1; 1036 let ScalarMemoryVT = i1; 1037} 1038def sextloadvi8 : PatFrag<(ops node:$ptr), (sextload node:$ptr)> { 1039 let IsLoad = 1; 1040 let ScalarMemoryVT = i8; 1041} 1042def sextloadvi16 : PatFrag<(ops node:$ptr), (sextload node:$ptr)> { 1043 let IsLoad = 1; 1044 let ScalarMemoryVT = i16; 1045} 1046def sextloadvi32 : PatFrag<(ops node:$ptr), (sextload node:$ptr)> { 1047 let IsLoad = 1; 1048 let ScalarMemoryVT = i32; 1049} 1050 1051def zextloadvi1 : PatFrag<(ops node:$ptr), (zextload node:$ptr)> { 1052 let IsLoad = 1; 1053 let ScalarMemoryVT = i1; 1054} 1055def zextloadvi8 : PatFrag<(ops node:$ptr), (zextload node:$ptr)> { 1056 let IsLoad = 1; 1057 let ScalarMemoryVT = i8; 1058} 1059def zextloadvi16 : PatFrag<(ops node:$ptr), (zextload node:$ptr)> { 1060 let IsLoad = 1; 1061 let ScalarMemoryVT = i16; 1062} 1063def zextloadvi32 : PatFrag<(ops node:$ptr), (zextload node:$ptr)> { 1064 let IsLoad = 1; 1065 let ScalarMemoryVT = i32; 1066} 1067 1068// store fragments. 1069def unindexedstore : PatFrag<(ops node:$val, node:$ptr), 1070 (st node:$val, node:$ptr)> { 1071 let IsStore = 1; 1072 let IsUnindexed = 1; 1073} 1074def store : PatFrag<(ops node:$val, node:$ptr), 1075 (unindexedstore node:$val, node:$ptr)> { 1076 let IsStore = 1; 1077 let IsTruncStore = 0; 1078} 1079 1080// truncstore fragments. 1081def truncstore : PatFrag<(ops node:$val, node:$ptr), 1082 (unindexedstore node:$val, node:$ptr)> { 1083 let IsStore = 1; 1084 let IsTruncStore = 1; 1085} 1086def truncstorei8 : PatFrag<(ops node:$val, node:$ptr), 1087 (truncstore node:$val, node:$ptr)> { 1088 let IsStore = 1; 1089 let MemoryVT = i8; 1090} 1091def truncstorei16 : PatFrag<(ops node:$val, node:$ptr), 1092 (truncstore node:$val, node:$ptr)> { 1093 let IsStore = 1; 1094 let MemoryVT = i16; 1095} 1096def truncstorei32 : PatFrag<(ops node:$val, node:$ptr), 1097 (truncstore node:$val, node:$ptr)> { 1098 let IsStore = 1; 1099 let MemoryVT = i32; 1100} 1101def truncstoref16 : PatFrag<(ops node:$val, node:$ptr), 1102 (truncstore node:$val, node:$ptr)> { 1103 let IsStore = 1; 1104 let MemoryVT = f16; 1105} 1106def truncstoref32 : PatFrag<(ops node:$val, node:$ptr), 1107 (truncstore node:$val, node:$ptr)> { 1108 let IsStore = 1; 1109 let MemoryVT = f32; 1110} 1111def truncstoref64 : PatFrag<(ops node:$val, node:$ptr), 1112 (truncstore node:$val, node:$ptr)> { 1113 let IsStore = 1; 1114 let MemoryVT = f64; 1115} 1116 1117def truncstorevi8 : PatFrag<(ops node:$val, node:$ptr), 1118 (truncstore node:$val, node:$ptr)> { 1119 let IsStore = 1; 1120 let ScalarMemoryVT = i8; 1121} 1122 1123def truncstorevi16 : PatFrag<(ops node:$val, node:$ptr), 1124 (truncstore node:$val, node:$ptr)> { 1125 let IsStore = 1; 1126 let ScalarMemoryVT = i16; 1127} 1128 1129def truncstorevi32 : PatFrag<(ops node:$val, node:$ptr), 1130 (truncstore node:$val, node:$ptr)> { 1131 let IsStore = 1; 1132 let ScalarMemoryVT = i32; 1133} 1134 1135// indexed store fragments. 1136def istore : PatFrag<(ops node:$val, node:$base, node:$offset), 1137 (ist node:$val, node:$base, node:$offset)> { 1138 let IsStore = 1; 1139 let IsTruncStore = 0; 1140} 1141 1142def pre_store : PatFrag<(ops node:$val, node:$base, node:$offset), 1143 (istore node:$val, node:$base, node:$offset), [{ 1144 ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode(); 1145 return AM == ISD::PRE_INC || AM == ISD::PRE_DEC; 1146}]>; 1147 1148def itruncstore : PatFrag<(ops node:$val, node:$base, node:$offset), 1149 (ist node:$val, node:$base, node:$offset)> { 1150 let IsStore = 1; 1151 let IsTruncStore = 1; 1152} 1153def pre_truncst : PatFrag<(ops node:$val, node:$base, node:$offset), 1154 (itruncstore node:$val, node:$base, node:$offset), [{ 1155 ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode(); 1156 return AM == ISD::PRE_INC || AM == ISD::PRE_DEC; 1157}]>; 1158def pre_truncsti1 : PatFrag<(ops node:$val, node:$base, node:$offset), 1159 (pre_truncst node:$val, node:$base, node:$offset)> { 1160 let IsStore = 1; 1161 let MemoryVT = i1; 1162} 1163def pre_truncsti8 : PatFrag<(ops node:$val, node:$base, node:$offset), 1164 (pre_truncst node:$val, node:$base, node:$offset)> { 1165 let IsStore = 1; 1166 let MemoryVT = i8; 1167} 1168def pre_truncsti16 : PatFrag<(ops node:$val, node:$base, node:$offset), 1169 (pre_truncst node:$val, node:$base, node:$offset)> { 1170 let IsStore = 1; 1171 let MemoryVT = i16; 1172} 1173def pre_truncsti32 : PatFrag<(ops node:$val, node:$base, node:$offset), 1174 (pre_truncst node:$val, node:$base, node:$offset)> { 1175 let IsStore = 1; 1176 let MemoryVT = i32; 1177} 1178def pre_truncstf32 : PatFrag<(ops node:$val, node:$base, node:$offset), 1179 (pre_truncst node:$val, node:$base, node:$offset)> { 1180 let IsStore = 1; 1181 let MemoryVT = f32; 1182} 1183def pre_truncstvi8 : PatFrag<(ops node:$val, node:$base, node:$offset), 1184 (pre_truncst node:$val, node:$base, node:$offset)> { 1185 let IsStore = 1; 1186 let ScalarMemoryVT = i8; 1187} 1188def pre_truncstvi16 : PatFrag<(ops node:$val, node:$base, node:$offset), 1189 (pre_truncst node:$val, node:$base, node:$offset)> { 1190 let IsStore = 1; 1191 let ScalarMemoryVT = i16; 1192} 1193 1194def post_store : PatFrag<(ops node:$val, node:$ptr, node:$offset), 1195 (istore node:$val, node:$ptr, node:$offset), [{ 1196 ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode(); 1197 return AM == ISD::POST_INC || AM == ISD::POST_DEC; 1198}]>; 1199 1200def post_truncst : PatFrag<(ops node:$val, node:$base, node:$offset), 1201 (itruncstore node:$val, node:$base, node:$offset), [{ 1202 ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode(); 1203 return AM == ISD::POST_INC || AM == ISD::POST_DEC; 1204}]>; 1205def post_truncsti1 : PatFrag<(ops node:$val, node:$base, node:$offset), 1206 (post_truncst node:$val, node:$base, node:$offset)> { 1207 let IsStore = 1; 1208 let MemoryVT = i1; 1209} 1210def post_truncsti8 : PatFrag<(ops node:$val, node:$base, node:$offset), 1211 (post_truncst node:$val, node:$base, node:$offset)> { 1212 let IsStore = 1; 1213 let MemoryVT = i8; 1214} 1215def post_truncsti16 : PatFrag<(ops node:$val, node:$base, node:$offset), 1216 (post_truncst node:$val, node:$base, node:$offset)> { 1217 let IsStore = 1; 1218 let MemoryVT = i16; 1219} 1220def post_truncsti32 : PatFrag<(ops node:$val, node:$base, node:$offset), 1221 (post_truncst node:$val, node:$base, node:$offset)> { 1222 let IsStore = 1; 1223 let MemoryVT = i32; 1224} 1225def post_truncstf32 : PatFrag<(ops node:$val, node:$base, node:$offset), 1226 (post_truncst node:$val, node:$base, node:$offset)> { 1227 let IsStore = 1; 1228 let MemoryVT = f32; 1229} 1230def post_truncstvi8 : PatFrag<(ops node:$val, node:$base, node:$offset), 1231 (post_truncst node:$val, node:$base, node:$offset)> { 1232 let IsStore = 1; 1233 let ScalarMemoryVT = i8; 1234} 1235def post_truncstvi16 : PatFrag<(ops node:$val, node:$base, node:$offset), 1236 (post_truncst node:$val, node:$base, node:$offset)> { 1237 let IsStore = 1; 1238 let ScalarMemoryVT = i16; 1239} 1240 1241// TODO: Split these into volatile and unordered flavors to enable 1242// selectively legal optimizations for each. (See D66309) 1243def simple_load : PatFrag<(ops node:$ptr), 1244 (load node:$ptr), [{ 1245 return cast<LoadSDNode>(N)->isSimple(); 1246}]>; 1247def simple_store : PatFrag<(ops node:$val, node:$ptr), 1248 (store node:$val, node:$ptr), [{ 1249 return cast<StoreSDNode>(N)->isSimple(); 1250}]>; 1251 1252// nontemporal store fragments. 1253def nontemporalstore : PatFrag<(ops node:$val, node:$ptr), 1254 (store node:$val, node:$ptr), [{ 1255 return cast<StoreSDNode>(N)->isNonTemporal(); 1256}]>; 1257 1258def alignednontemporalstore : PatFrag<(ops node:$val, node:$ptr), 1259 (nontemporalstore node:$val, node:$ptr), [{ 1260 StoreSDNode *St = cast<StoreSDNode>(N); 1261 return St->getAlignment() >= St->getMemoryVT().getStoreSize(); 1262}]>; 1263 1264def unalignednontemporalstore : PatFrag<(ops node:$val, node:$ptr), 1265 (nontemporalstore node:$val, node:$ptr), [{ 1266 StoreSDNode *St = cast<StoreSDNode>(N); 1267 return St->getAlignment() < St->getMemoryVT().getStoreSize(); 1268}]>; 1269 1270// nontemporal load fragments. 1271def nontemporalload : PatFrag<(ops node:$ptr), 1272 (load node:$ptr), [{ 1273 return cast<LoadSDNode>(N)->isNonTemporal(); 1274}]>; 1275 1276def alignednontemporalload : PatFrag<(ops node:$ptr), 1277 (nontemporalload node:$ptr), [{ 1278 LoadSDNode *Ld = cast<LoadSDNode>(N); 1279 return Ld->getAlignment() >= Ld->getMemoryVT().getStoreSize(); 1280}]>; 1281 1282// setcc convenience fragments. 1283def setoeq : PatFrag<(ops node:$lhs, node:$rhs), 1284 (setcc node:$lhs, node:$rhs, SETOEQ)>; 1285def setogt : PatFrag<(ops node:$lhs, node:$rhs), 1286 (setcc node:$lhs, node:$rhs, SETOGT)>; 1287def setoge : PatFrag<(ops node:$lhs, node:$rhs), 1288 (setcc node:$lhs, node:$rhs, SETOGE)>; 1289def setolt : PatFrag<(ops node:$lhs, node:$rhs), 1290 (setcc node:$lhs, node:$rhs, SETOLT)>; 1291def setole : PatFrag<(ops node:$lhs, node:$rhs), 1292 (setcc node:$lhs, node:$rhs, SETOLE)>; 1293def setone : PatFrag<(ops node:$lhs, node:$rhs), 1294 (setcc node:$lhs, node:$rhs, SETONE)>; 1295def seto : PatFrag<(ops node:$lhs, node:$rhs), 1296 (setcc node:$lhs, node:$rhs, SETO)>; 1297def setuo : PatFrag<(ops node:$lhs, node:$rhs), 1298 (setcc node:$lhs, node:$rhs, SETUO)>; 1299def setueq : PatFrag<(ops node:$lhs, node:$rhs), 1300 (setcc node:$lhs, node:$rhs, SETUEQ)>; 1301def setugt : PatFrag<(ops node:$lhs, node:$rhs), 1302 (setcc node:$lhs, node:$rhs, SETUGT)>; 1303def setuge : PatFrag<(ops node:$lhs, node:$rhs), 1304 (setcc node:$lhs, node:$rhs, SETUGE)>; 1305def setult : PatFrag<(ops node:$lhs, node:$rhs), 1306 (setcc node:$lhs, node:$rhs, SETULT)>; 1307def setule : PatFrag<(ops node:$lhs, node:$rhs), 1308 (setcc node:$lhs, node:$rhs, SETULE)>; 1309def setune : PatFrag<(ops node:$lhs, node:$rhs), 1310 (setcc node:$lhs, node:$rhs, SETUNE)>; 1311def seteq : PatFrag<(ops node:$lhs, node:$rhs), 1312 (setcc node:$lhs, node:$rhs, SETEQ)>; 1313def setgt : PatFrag<(ops node:$lhs, node:$rhs), 1314 (setcc node:$lhs, node:$rhs, SETGT)>; 1315def setge : PatFrag<(ops node:$lhs, node:$rhs), 1316 (setcc node:$lhs, node:$rhs, SETGE)>; 1317def setlt : PatFrag<(ops node:$lhs, node:$rhs), 1318 (setcc node:$lhs, node:$rhs, SETLT)>; 1319def setle : PatFrag<(ops node:$lhs, node:$rhs), 1320 (setcc node:$lhs, node:$rhs, SETLE)>; 1321def setne : PatFrag<(ops node:$lhs, node:$rhs), 1322 (setcc node:$lhs, node:$rhs, SETNE)>; 1323 1324// We don't have strict FP extended loads as single DAG nodes, but we can 1325// still provide convenience fragments to match those operations. 1326def strict_extloadf32 : PatFrag<(ops node:$ptr), 1327 (strict_fpextend (f32 (load node:$ptr)))>; 1328def strict_extloadf64 : PatFrag<(ops node:$ptr), 1329 (strict_fpextend (f64 (load node:$ptr)))>; 1330 1331// Convenience fragments to match both strict and non-strict fp operations 1332def any_fadd : PatFrags<(ops node:$lhs, node:$rhs), 1333 [(strict_fadd node:$lhs, node:$rhs), 1334 (fadd node:$lhs, node:$rhs)]>; 1335def any_fsub : PatFrags<(ops node:$lhs, node:$rhs), 1336 [(strict_fsub node:$lhs, node:$rhs), 1337 (fsub node:$lhs, node:$rhs)]>; 1338def any_fmul : PatFrags<(ops node:$lhs, node:$rhs), 1339 [(strict_fmul node:$lhs, node:$rhs), 1340 (fmul node:$lhs, node:$rhs)]>; 1341def any_fdiv : PatFrags<(ops node:$lhs, node:$rhs), 1342 [(strict_fdiv node:$lhs, node:$rhs), 1343 (fdiv node:$lhs, node:$rhs)]>; 1344def any_frem : PatFrags<(ops node:$lhs, node:$rhs), 1345 [(strict_frem node:$lhs, node:$rhs), 1346 (frem node:$lhs, node:$rhs)]>; 1347def any_fma : PatFrags<(ops node:$src1, node:$src2, node:$src3), 1348 [(strict_fma node:$src1, node:$src2, node:$src3), 1349 (fma node:$src1, node:$src2, node:$src3)]>; 1350def any_fsqrt : PatFrags<(ops node:$src), 1351 [(strict_fsqrt node:$src), 1352 (fsqrt node:$src)]>; 1353def any_fsin : PatFrags<(ops node:$src), 1354 [(strict_fsin node:$src), 1355 (fsin node:$src)]>; 1356def any_fcos : PatFrags<(ops node:$src), 1357 [(strict_fcos node:$src), 1358 (fcos node:$src)]>; 1359def any_fexp2 : PatFrags<(ops node:$src), 1360 [(strict_fexp2 node:$src), 1361 (fexp2 node:$src)]>; 1362def any_fpow : PatFrags<(ops node:$lhs, node:$rhs), 1363 [(strict_fpow node:$lhs, node:$rhs), 1364 (fpow node:$lhs, node:$rhs)]>; 1365def any_flog2 : PatFrags<(ops node:$src), 1366 [(strict_flog2 node:$src), 1367 (flog2 node:$src)]>; 1368def any_frint : PatFrags<(ops node:$src), 1369 [(strict_frint node:$src), 1370 (frint node:$src)]>; 1371def any_lrint : PatFrags<(ops node:$src), 1372 [(strict_lrint node:$src), 1373 (lrint node:$src)]>; 1374def any_llrint : PatFrags<(ops node:$src), 1375 [(strict_llrint node:$src), 1376 (llrint node:$src)]>; 1377def any_fnearbyint : PatFrags<(ops node:$src), 1378 [(strict_fnearbyint node:$src), 1379 (fnearbyint node:$src)]>; 1380def any_fceil : PatFrags<(ops node:$src), 1381 [(strict_fceil node:$src), 1382 (fceil node:$src)]>; 1383def any_ffloor : PatFrags<(ops node:$src), 1384 [(strict_ffloor node:$src), 1385 (ffloor node:$src)]>; 1386def any_lround : PatFrags<(ops node:$src), 1387 [(strict_lround node:$src), 1388 (lround node:$src)]>; 1389def any_llround : PatFrags<(ops node:$src), 1390 [(strict_llround node:$src), 1391 (llround node:$src)]>; 1392def any_fround : PatFrags<(ops node:$src), 1393 [(strict_fround node:$src), 1394 (fround node:$src)]>; 1395def any_ftrunc : PatFrags<(ops node:$src), 1396 [(strict_ftrunc node:$src), 1397 (ftrunc node:$src)]>; 1398def any_fmaxnum : PatFrags<(ops node:$lhs, node:$rhs), 1399 [(strict_fmaxnum node:$lhs, node:$rhs), 1400 (fmaxnum node:$lhs, node:$rhs)]>; 1401def any_fminnum : PatFrags<(ops node:$lhs, node:$rhs), 1402 [(strict_fminnum node:$lhs, node:$rhs), 1403 (fminnum node:$lhs, node:$rhs)]>; 1404def any_fmaximum : PatFrags<(ops node:$lhs, node:$rhs), 1405 [(strict_fmaximum node:$lhs, node:$rhs), 1406 (fmaximum node:$lhs, node:$rhs)]>; 1407def any_fminimum : PatFrags<(ops node:$lhs, node:$rhs), 1408 [(strict_fminimum node:$lhs, node:$rhs), 1409 (fminimum node:$lhs, node:$rhs)]>; 1410def any_fpround : PatFrags<(ops node:$src), 1411 [(strict_fpround node:$src), 1412 (fpround node:$src)]>; 1413def any_fpextend : PatFrags<(ops node:$src), 1414 [(strict_fpextend node:$src), 1415 (fpextend node:$src)]>; 1416def any_extloadf32 : PatFrags<(ops node:$ptr), 1417 [(strict_extloadf32 node:$ptr), 1418 (extloadf32 node:$ptr)]>; 1419def any_extloadf64 : PatFrags<(ops node:$ptr), 1420 [(strict_extloadf64 node:$ptr), 1421 (extloadf64 node:$ptr)]>; 1422def any_fp_to_sint : PatFrags<(ops node:$src), 1423 [(strict_fp_to_sint node:$src), 1424 (fp_to_sint node:$src)]>; 1425def any_fp_to_uint : PatFrags<(ops node:$src), 1426 [(strict_fp_to_uint node:$src), 1427 (fp_to_uint node:$src)]>; 1428def any_sint_to_fp : PatFrags<(ops node:$src), 1429 [(strict_sint_to_fp node:$src), 1430 (sint_to_fp node:$src)]>; 1431def any_uint_to_fp : PatFrags<(ops node:$src), 1432 [(strict_uint_to_fp node:$src), 1433 (uint_to_fp node:$src)]>; 1434 1435multiclass binary_atomic_op_ord<SDNode atomic_op> { 1436 def #NAME#_monotonic : PatFrag<(ops node:$ptr, node:$val), 1437 (!cast<SDPatternOperator>(#NAME) node:$ptr, node:$val)> { 1438 let IsAtomic = 1; 1439 let IsAtomicOrderingMonotonic = 1; 1440 } 1441 def #NAME#_acquire : PatFrag<(ops node:$ptr, node:$val), 1442 (!cast<SDPatternOperator>(#NAME) node:$ptr, node:$val)> { 1443 let IsAtomic = 1; 1444 let IsAtomicOrderingAcquire = 1; 1445 } 1446 def #NAME#_release : PatFrag<(ops node:$ptr, node:$val), 1447 (!cast<SDPatternOperator>(#NAME) node:$ptr, node:$val)> { 1448 let IsAtomic = 1; 1449 let IsAtomicOrderingRelease = 1; 1450 } 1451 def #NAME#_acq_rel : PatFrag<(ops node:$ptr, node:$val), 1452 (!cast<SDPatternOperator>(#NAME) node:$ptr, node:$val)> { 1453 let IsAtomic = 1; 1454 let IsAtomicOrderingAcquireRelease = 1; 1455 } 1456 def #NAME#_seq_cst : PatFrag<(ops node:$ptr, node:$val), 1457 (!cast<SDPatternOperator>(#NAME) node:$ptr, node:$val)> { 1458 let IsAtomic = 1; 1459 let IsAtomicOrderingSequentiallyConsistent = 1; 1460 } 1461} 1462 1463multiclass ternary_atomic_op_ord<SDNode atomic_op> { 1464 def #NAME#_monotonic : PatFrag<(ops node:$ptr, node:$cmp, node:$val), 1465 (!cast<SDPatternOperator>(#NAME) node:$ptr, node:$cmp, node:$val)> { 1466 let IsAtomic = 1; 1467 let IsAtomicOrderingMonotonic = 1; 1468 } 1469 def #NAME#_acquire : PatFrag<(ops node:$ptr, node:$cmp, node:$val), 1470 (!cast<SDPatternOperator>(#NAME) node:$ptr, node:$cmp, node:$val)> { 1471 let IsAtomic = 1; 1472 let IsAtomicOrderingAcquire = 1; 1473 } 1474 def #NAME#_release : PatFrag<(ops node:$ptr, node:$cmp, node:$val), 1475 (!cast<SDPatternOperator>(#NAME) node:$ptr, node:$cmp, node:$val)> { 1476 let IsAtomic = 1; 1477 let IsAtomicOrderingRelease = 1; 1478 } 1479 def #NAME#_acq_rel : PatFrag<(ops node:$ptr, node:$cmp, node:$val), 1480 (!cast<SDPatternOperator>(#NAME) node:$ptr, node:$cmp, node:$val)> { 1481 let IsAtomic = 1; 1482 let IsAtomicOrderingAcquireRelease = 1; 1483 } 1484 def #NAME#_seq_cst : PatFrag<(ops node:$ptr, node:$cmp, node:$val), 1485 (!cast<SDPatternOperator>(#NAME) node:$ptr, node:$cmp, node:$val)> { 1486 let IsAtomic = 1; 1487 let IsAtomicOrderingSequentiallyConsistent = 1; 1488 } 1489} 1490 1491multiclass binary_atomic_op<SDNode atomic_op, bit IsInt = 1> { 1492 def _8 : PatFrag<(ops node:$ptr, node:$val), 1493 (atomic_op node:$ptr, node:$val)> { 1494 let IsAtomic = 1; 1495 let MemoryVT = !if(IsInt, i8, ?); 1496 } 1497 def _16 : PatFrag<(ops node:$ptr, node:$val), 1498 (atomic_op node:$ptr, node:$val)> { 1499 let IsAtomic = 1; 1500 let MemoryVT = !if(IsInt, i16, f16); 1501 } 1502 def _32 : PatFrag<(ops node:$ptr, node:$val), 1503 (atomic_op node:$ptr, node:$val)> { 1504 let IsAtomic = 1; 1505 let MemoryVT = !if(IsInt, i32, f32); 1506 } 1507 def _64 : PatFrag<(ops node:$ptr, node:$val), 1508 (atomic_op node:$ptr, node:$val)> { 1509 let IsAtomic = 1; 1510 let MemoryVT = !if(IsInt, i64, f64); 1511 } 1512 1513 defm NAME#_8 : binary_atomic_op_ord<atomic_op>; 1514 defm NAME#_16 : binary_atomic_op_ord<atomic_op>; 1515 defm NAME#_32 : binary_atomic_op_ord<atomic_op>; 1516 defm NAME#_64 : binary_atomic_op_ord<atomic_op>; 1517} 1518 1519multiclass ternary_atomic_op<SDNode atomic_op> { 1520 def _8 : PatFrag<(ops node:$ptr, node:$cmp, node:$val), 1521 (atomic_op node:$ptr, node:$cmp, node:$val)> { 1522 let IsAtomic = 1; 1523 let MemoryVT = i8; 1524 } 1525 def _16 : PatFrag<(ops node:$ptr, node:$cmp, node:$val), 1526 (atomic_op node:$ptr, node:$cmp, node:$val)> { 1527 let IsAtomic = 1; 1528 let MemoryVT = i16; 1529 } 1530 def _32 : PatFrag<(ops node:$ptr, node:$cmp, node:$val), 1531 (atomic_op node:$ptr, node:$cmp, node:$val)> { 1532 let IsAtomic = 1; 1533 let MemoryVT = i32; 1534 } 1535 def _64 : PatFrag<(ops node:$ptr, node:$cmp, node:$val), 1536 (atomic_op node:$ptr, node:$cmp, node:$val)> { 1537 let IsAtomic = 1; 1538 let MemoryVT = i64; 1539 } 1540 1541 defm NAME#_8 : ternary_atomic_op_ord<atomic_op>; 1542 defm NAME#_16 : ternary_atomic_op_ord<atomic_op>; 1543 defm NAME#_32 : ternary_atomic_op_ord<atomic_op>; 1544 defm NAME#_64 : ternary_atomic_op_ord<atomic_op>; 1545} 1546 1547defm atomic_load_add : binary_atomic_op<atomic_load_add>; 1548defm atomic_swap : binary_atomic_op<atomic_swap>; 1549defm atomic_load_sub : binary_atomic_op<atomic_load_sub>; 1550defm atomic_load_and : binary_atomic_op<atomic_load_and>; 1551defm atomic_load_clr : binary_atomic_op<atomic_load_clr>; 1552defm atomic_load_or : binary_atomic_op<atomic_load_or>; 1553defm atomic_load_xor : binary_atomic_op<atomic_load_xor>; 1554defm atomic_load_nand : binary_atomic_op<atomic_load_nand>; 1555defm atomic_load_min : binary_atomic_op<atomic_load_min>; 1556defm atomic_load_max : binary_atomic_op<atomic_load_max>; 1557defm atomic_load_umin : binary_atomic_op<atomic_load_umin>; 1558defm atomic_load_umax : binary_atomic_op<atomic_load_umax>; 1559defm atomic_store : binary_atomic_op<atomic_store>; 1560defm atomic_cmp_swap : ternary_atomic_op<atomic_cmp_swap>; 1561 1562def atomic_load_8 : 1563 PatFrag<(ops node:$ptr), 1564 (atomic_load node:$ptr)> { 1565 let IsAtomic = 1; 1566 let MemoryVT = i8; 1567} 1568def atomic_load_16 : 1569 PatFrag<(ops node:$ptr), 1570 (atomic_load node:$ptr)> { 1571 let IsAtomic = 1; 1572 let MemoryVT = i16; 1573} 1574def atomic_load_32 : 1575 PatFrag<(ops node:$ptr), 1576 (atomic_load node:$ptr)> { 1577 let IsAtomic = 1; 1578 let MemoryVT = i32; 1579} 1580def atomic_load_64 : 1581 PatFrag<(ops node:$ptr), 1582 (atomic_load node:$ptr)> { 1583 let IsAtomic = 1; 1584 let MemoryVT = i64; 1585} 1586 1587//===----------------------------------------------------------------------===// 1588// Selection DAG Pattern Support. 1589// 1590// Patterns are what are actually matched against by the target-flavored 1591// instruction selection DAG. Instructions defined by the target implicitly 1592// define patterns in most cases, but patterns can also be explicitly added when 1593// an operation is defined by a sequence of instructions (e.g. loading a large 1594// immediate value on RISC targets that do not support immediates as large as 1595// their GPRs). 1596// 1597 1598class Pattern<dag patternToMatch, list<dag> resultInstrs> { 1599 dag PatternToMatch = patternToMatch; 1600 list<dag> ResultInstrs = resultInstrs; 1601 list<Predicate> Predicates = []; // See class Instruction in Target.td. 1602 int AddedComplexity = 0; // See class Instruction in Target.td. 1603} 1604 1605// Pat - A simple (but common) form of a pattern, which produces a simple result 1606// not needing a full list. 1607class Pat<dag pattern, dag result> : Pattern<pattern, [result]>; 1608 1609//===----------------------------------------------------------------------===// 1610// Complex pattern definitions. 1611// 1612 1613// Complex patterns, e.g. X86 addressing mode, requires pattern matching code 1614// in C++. NumOperands is the number of operands returned by the select function; 1615// SelectFunc is the name of the function used to pattern match the max. pattern; 1616// RootNodes are the list of possible root nodes of the sub-dags to match. 1617// e.g. X86 addressing mode - def addr : ComplexPattern<4, "SelectAddr", [add]>; 1618// 1619class ComplexPattern<ValueType ty, int numops, string fn, 1620 list<SDNode> roots = [], list<SDNodeProperty> props = [], 1621 int complexity = -1> { 1622 ValueType Ty = ty; 1623 int NumOperands = numops; 1624 string SelectFunc = fn; 1625 list<SDNode> RootNodes = roots; 1626 list<SDNodeProperty> Properties = props; 1627 int Complexity = complexity; 1628} 1629