TargetSelectionDAG.td revision 205218
1//===- TargetSelectionDAG.td - Common code for DAG isels ---*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines the target-independent interfaces used by SelectionDAG 11// instruction selection generators. 12// 13//===----------------------------------------------------------------------===// 14 15//===----------------------------------------------------------------------===// 16// Selection DAG Type Constraint definitions. 17// 18// Note that the semantics of these constraints are hard coded into tblgen. To 19// modify or add constraints, you have to hack tblgen. 20// 21 22class SDTypeConstraint<int opnum> { 23 int OperandNum = opnum; 24} 25 26// SDTCisVT - The specified operand has exactly this VT. 27class SDTCisVT<int OpNum, ValueType vt> : SDTypeConstraint<OpNum> { 28 ValueType VT = vt; 29} 30 31class SDTCisPtrTy<int OpNum> : SDTypeConstraint<OpNum>; 32 33// SDTCisInt - The specified operand has integer type. 34class SDTCisInt<int OpNum> : SDTypeConstraint<OpNum>; 35 36// SDTCisFP - The specified operand has floating-point type. 37class SDTCisFP<int OpNum> : SDTypeConstraint<OpNum>; 38 39// SDTCisVec - The specified operand has a vector type. 40class SDTCisVec<int OpNum> : SDTypeConstraint<OpNum>; 41 42// SDTCisSameAs - The two specified operands have identical types. 43class SDTCisSameAs<int OpNum, int OtherOp> : SDTypeConstraint<OpNum> { 44 int OtherOperandNum = OtherOp; 45} 46 47// SDTCisVTSmallerThanOp - The specified operand is a VT SDNode, and its type is 48// smaller than the 'Other' operand. 49class SDTCisVTSmallerThanOp<int OpNum, int OtherOp> : SDTypeConstraint<OpNum> { 50 int OtherOperandNum = OtherOp; 51} 52 53class SDTCisOpSmallerThanOp<int SmallOp, int BigOp> : SDTypeConstraint<SmallOp>{ 54 int BigOperandNum = BigOp; 55} 56 57/// SDTCisEltOfVec - This indicates that ThisOp is a scalar type of the same 58/// type as the element type of OtherOp, which is a vector type. 59class SDTCisEltOfVec<int ThisOp, int OtherOp> 60 : SDTypeConstraint<ThisOp> { 61 int OtherOpNum = OtherOp; 62} 63 64//===----------------------------------------------------------------------===// 65// Selection DAG Type Profile definitions. 66// 67// These use the constraints defined above to describe the type requirements of 68// the various nodes. These are not hard coded into tblgen, allowing targets to 69// add their own if needed. 70// 71 72// SDTypeProfile - This profile describes the type requirements of a Selection 73// DAG node. 74class SDTypeProfile<int numresults, int numoperands, 75 list<SDTypeConstraint> constraints> { 76 int NumResults = numresults; 77 int NumOperands = numoperands; 78 list<SDTypeConstraint> Constraints = constraints; 79} 80 81// Builtin profiles. 82def SDTIntLeaf: SDTypeProfile<1, 0, [SDTCisInt<0>]>; // for 'imm'. 83def SDTFPLeaf : SDTypeProfile<1, 0, [SDTCisFP<0>]>; // for 'fpimm'. 84def SDTPtrLeaf: SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>; // for '&g'. 85def SDTOther : SDTypeProfile<1, 0, [SDTCisVT<0, OtherVT>]>; // for 'vt'. 86def SDTUNDEF : SDTypeProfile<1, 0, []>; // for 'undef'. 87def SDTUnaryOp : SDTypeProfile<1, 1, []>; // for bitconvert. 88 89def SDTIntBinOp : SDTypeProfile<1, 2, [ // add, and, or, xor, udiv, etc. 90 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisInt<0> 91]>; 92def SDTIntShiftOp : SDTypeProfile<1, 2, [ // shl, sra, srl 93 SDTCisSameAs<0, 1>, SDTCisInt<0>, SDTCisInt<2> 94]>; 95def SDTFPBinOp : SDTypeProfile<1, 2, [ // fadd, fmul, etc. 96 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisFP<0> 97]>; 98def SDTFPSignOp : SDTypeProfile<1, 2, [ // fcopysign. 99 SDTCisSameAs<0, 1>, SDTCisFP<0>, SDTCisFP<2> 100]>; 101def SDTFPTernaryOp : SDTypeProfile<1, 3, [ // fmadd, fnmsub, etc. 102 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>, SDTCisFP<0> 103]>; 104def SDTIntUnaryOp : SDTypeProfile<1, 1, [ // ctlz 105 SDTCisSameAs<0, 1>, SDTCisInt<0> 106]>; 107def SDTIntExtendOp : SDTypeProfile<1, 1, [ // sext, zext, anyext 108 SDTCisInt<0>, SDTCisInt<1>, SDTCisOpSmallerThanOp<1, 0> 109]>; 110def SDTIntTruncOp : SDTypeProfile<1, 1, [ // trunc 111 SDTCisInt<0>, SDTCisInt<1>, SDTCisOpSmallerThanOp<0, 1> 112]>; 113def SDTFPUnaryOp : SDTypeProfile<1, 1, [ // fneg, fsqrt, etc 114 SDTCisSameAs<0, 1>, SDTCisFP<0> 115]>; 116def SDTFPRoundOp : SDTypeProfile<1, 1, [ // fround 117 SDTCisFP<0>, SDTCisFP<1>, SDTCisOpSmallerThanOp<0, 1> 118]>; 119def SDTFPExtendOp : SDTypeProfile<1, 1, [ // fextend 120 SDTCisFP<0>, SDTCisFP<1>, SDTCisOpSmallerThanOp<1, 0> 121]>; 122def SDTIntToFPOp : SDTypeProfile<1, 1, [ // [su]int_to_fp 123 SDTCisFP<0>, SDTCisInt<1> 124]>; 125def SDTFPToIntOp : SDTypeProfile<1, 1, [ // fp_to_[su]int 126 SDTCisInt<0>, SDTCisFP<1> 127]>; 128def SDTExtInreg : SDTypeProfile<1, 2, [ // sext_inreg 129 SDTCisSameAs<0, 1>, SDTCisInt<0>, SDTCisVT<2, OtherVT>, 130 SDTCisVTSmallerThanOp<2, 1> 131]>; 132 133def SDTSetCC : SDTypeProfile<1, 3, [ // setcc 134 SDTCisInt<0>, SDTCisSameAs<1, 2>, SDTCisVT<3, OtherVT> 135]>; 136 137def SDTSelect : SDTypeProfile<1, 3, [ // select 138 SDTCisInt<1>, SDTCisSameAs<0, 2>, SDTCisSameAs<2, 3> 139]>; 140 141def SDTSelectCC : SDTypeProfile<1, 5, [ // select_cc 142 SDTCisSameAs<1, 2>, SDTCisSameAs<3, 4>, SDTCisSameAs<0, 3>, 143 SDTCisVT<5, OtherVT> 144]>; 145 146def SDTBr : SDTypeProfile<0, 1, [ // br 147 SDTCisVT<0, OtherVT> 148]>; 149 150def SDTBrcond : SDTypeProfile<0, 2, [ // brcond 151 SDTCisInt<0>, SDTCisVT<1, OtherVT> 152]>; 153 154def SDTBrind : SDTypeProfile<0, 1, [ // brind 155 SDTCisPtrTy<0> 156]>; 157 158def SDTNone : SDTypeProfile<0, 0, []>; // ret, trap 159 160def SDTLoad : SDTypeProfile<1, 1, [ // load 161 SDTCisPtrTy<1> 162]>; 163 164def SDTStore : SDTypeProfile<0, 2, [ // store 165 SDTCisPtrTy<1> 166]>; 167 168def SDTIStore : SDTypeProfile<1, 3, [ // indexed store 169 SDTCisSameAs<0, 2>, SDTCisPtrTy<0>, SDTCisPtrTy<3> 170]>; 171 172def SDTVecShuffle : SDTypeProfile<1, 2, [ 173 SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2> 174]>; 175def SDTVecExtract : SDTypeProfile<1, 2, [ // vector extract 176 SDTCisEltOfVec<0, 1>, SDTCisPtrTy<2> 177]>; 178def SDTVecInsert : SDTypeProfile<1, 3, [ // vector insert 179 SDTCisEltOfVec<2, 1>, SDTCisSameAs<0, 1>, SDTCisPtrTy<3> 180]>; 181 182def STDPrefetch : SDTypeProfile<0, 3, [ // prefetch 183 SDTCisPtrTy<0>, SDTCisSameAs<1, 2>, SDTCisInt<1> 184]>; 185 186def STDMemBarrier : SDTypeProfile<0, 5, [ // memory barier 187 SDTCisSameAs<0,1>, SDTCisSameAs<0,2>, SDTCisSameAs<0,3>, SDTCisSameAs<0,4>, 188 SDTCisInt<0> 189]>; 190def STDAtomic3 : SDTypeProfile<1, 3, [ 191 SDTCisSameAs<0,2>, SDTCisSameAs<0,3>, SDTCisInt<0>, SDTCisPtrTy<1> 192]>; 193def STDAtomic2 : SDTypeProfile<1, 2, [ 194 SDTCisSameAs<0,2>, SDTCisInt<0>, SDTCisPtrTy<1> 195]>; 196 197def SDTConvertOp : SDTypeProfile<1, 5, [ //cvtss, su, us, uu, ff, fs, fu, sf, su 198 SDTCisVT<2, OtherVT>, SDTCisVT<3, OtherVT>, SDTCisPtrTy<4>, SDTCisPtrTy<5> 199]>; 200 201class SDCallSeqStart<list<SDTypeConstraint> constraints> : 202 SDTypeProfile<0, 1, constraints>; 203class SDCallSeqEnd<list<SDTypeConstraint> constraints> : 204 SDTypeProfile<0, 2, constraints>; 205 206//===----------------------------------------------------------------------===// 207// Selection DAG Node Properties. 208// 209// Note: These are hard coded into tblgen. 210// 211class SDNodeProperty; 212def SDNPCommutative : SDNodeProperty; // X op Y == Y op X 213def SDNPAssociative : SDNodeProperty; // (X op Y) op Z == X op (Y op Z) 214def SDNPHasChain : SDNodeProperty; // R/W chain operand and result 215def SDNPOutFlag : SDNodeProperty; // Write a flag result 216def SDNPInFlag : SDNodeProperty; // Read a flag operand 217def SDNPOptInFlag : SDNodeProperty; // Optionally read a flag operand 218def SDNPMayStore : SDNodeProperty; // May write to memory, sets 'mayStore'. 219def SDNPMayLoad : SDNodeProperty; // May read memory, sets 'mayLoad'. 220def SDNPSideEffect : SDNodeProperty; // Sets 'HasUnmodelledSideEffects'. 221def SDNPMemOperand : SDNodeProperty; // Touches memory, has assoc MemOperand 222 223//===----------------------------------------------------------------------===// 224// Selection DAG Node definitions. 225// 226class SDNode<string opcode, SDTypeProfile typeprof, 227 list<SDNodeProperty> props = [], string sdclass = "SDNode"> { 228 string Opcode = opcode; 229 string SDClass = sdclass; 230 list<SDNodeProperty> Properties = props; 231 SDTypeProfile TypeProfile = typeprof; 232} 233 234// Special TableGen-recognized dag nodes 235def set; 236def implicit; 237def parallel; 238def node; 239def srcvalue; 240 241def imm : SDNode<"ISD::Constant" , SDTIntLeaf , [], "ConstantSDNode">; 242def timm : SDNode<"ISD::TargetConstant",SDTIntLeaf, [], "ConstantSDNode">; 243def fpimm : SDNode<"ISD::ConstantFP", SDTFPLeaf , [], "ConstantFPSDNode">; 244def vt : SDNode<"ISD::VALUETYPE" , SDTOther , [], "VTSDNode">; 245def bb : SDNode<"ISD::BasicBlock", SDTOther , [], "BasicBlockSDNode">; 246def cond : SDNode<"ISD::CONDCODE" , SDTOther , [], "CondCodeSDNode">; 247def undef : SDNode<"ISD::UNDEF" , SDTUNDEF , []>; 248def globaladdr : SDNode<"ISD::GlobalAddress", SDTPtrLeaf, [], 249 "GlobalAddressSDNode">; 250def tglobaladdr : SDNode<"ISD::TargetGlobalAddress", SDTPtrLeaf, [], 251 "GlobalAddressSDNode">; 252def globaltlsaddr : SDNode<"ISD::GlobalTLSAddress", SDTPtrLeaf, [], 253 "GlobalAddressSDNode">; 254def tglobaltlsaddr : SDNode<"ISD::TargetGlobalTLSAddress", SDTPtrLeaf, [], 255 "GlobalAddressSDNode">; 256def constpool : SDNode<"ISD::ConstantPool", SDTPtrLeaf, [], 257 "ConstantPoolSDNode">; 258def tconstpool : SDNode<"ISD::TargetConstantPool", SDTPtrLeaf, [], 259 "ConstantPoolSDNode">; 260def jumptable : SDNode<"ISD::JumpTable", SDTPtrLeaf, [], 261 "JumpTableSDNode">; 262def tjumptable : SDNode<"ISD::TargetJumpTable", SDTPtrLeaf, [], 263 "JumpTableSDNode">; 264def frameindex : SDNode<"ISD::FrameIndex", SDTPtrLeaf, [], 265 "FrameIndexSDNode">; 266def tframeindex : SDNode<"ISD::TargetFrameIndex", SDTPtrLeaf, [], 267 "FrameIndexSDNode">; 268def externalsym : SDNode<"ISD::ExternalSymbol", SDTPtrLeaf, [], 269 "ExternalSymbolSDNode">; 270def texternalsym: SDNode<"ISD::TargetExternalSymbol", SDTPtrLeaf, [], 271 "ExternalSymbolSDNode">; 272def blockaddress : SDNode<"ISD::BlockAddress", SDTPtrLeaf, [], 273 "BlockAddressSDNode">; 274def tblockaddress: SDNode<"ISD::TargetBlockAddress", SDTPtrLeaf, [], 275 "BlockAddressSDNode">; 276 277def add : SDNode<"ISD::ADD" , SDTIntBinOp , 278 [SDNPCommutative, SDNPAssociative]>; 279def sub : SDNode<"ISD::SUB" , SDTIntBinOp>; 280def mul : SDNode<"ISD::MUL" , SDTIntBinOp, 281 [SDNPCommutative, SDNPAssociative]>; 282def mulhs : SDNode<"ISD::MULHS" , SDTIntBinOp, [SDNPCommutative]>; 283def mulhu : SDNode<"ISD::MULHU" , SDTIntBinOp, [SDNPCommutative]>; 284def sdiv : SDNode<"ISD::SDIV" , SDTIntBinOp>; 285def udiv : SDNode<"ISD::UDIV" , SDTIntBinOp>; 286def srem : SDNode<"ISD::SREM" , SDTIntBinOp>; 287def urem : SDNode<"ISD::UREM" , SDTIntBinOp>; 288def srl : SDNode<"ISD::SRL" , SDTIntShiftOp>; 289def sra : SDNode<"ISD::SRA" , SDTIntShiftOp>; 290def shl : SDNode<"ISD::SHL" , SDTIntShiftOp>; 291def rotl : SDNode<"ISD::ROTL" , SDTIntShiftOp>; 292def rotr : SDNode<"ISD::ROTR" , SDTIntShiftOp>; 293def and : SDNode<"ISD::AND" , SDTIntBinOp, 294 [SDNPCommutative, SDNPAssociative]>; 295def or : SDNode<"ISD::OR" , SDTIntBinOp, 296 [SDNPCommutative, SDNPAssociative]>; 297def xor : SDNode<"ISD::XOR" , SDTIntBinOp, 298 [SDNPCommutative, SDNPAssociative]>; 299def addc : SDNode<"ISD::ADDC" , SDTIntBinOp, 300 [SDNPCommutative, SDNPOutFlag]>; 301def adde : SDNode<"ISD::ADDE" , SDTIntBinOp, 302 [SDNPCommutative, SDNPOutFlag, SDNPInFlag]>; 303def subc : SDNode<"ISD::SUBC" , SDTIntBinOp, 304 [SDNPOutFlag]>; 305def sube : SDNode<"ISD::SUBE" , SDTIntBinOp, 306 [SDNPOutFlag, SDNPInFlag]>; 307 308def sext_inreg : SDNode<"ISD::SIGN_EXTEND_INREG", SDTExtInreg>; 309def bswap : SDNode<"ISD::BSWAP" , SDTIntUnaryOp>; 310def ctlz : SDNode<"ISD::CTLZ" , SDTIntUnaryOp>; 311def cttz : SDNode<"ISD::CTTZ" , SDTIntUnaryOp>; 312def ctpop : SDNode<"ISD::CTPOP" , SDTIntUnaryOp>; 313def sext : SDNode<"ISD::SIGN_EXTEND", SDTIntExtendOp>; 314def zext : SDNode<"ISD::ZERO_EXTEND", SDTIntExtendOp>; 315def anyext : SDNode<"ISD::ANY_EXTEND" , SDTIntExtendOp>; 316def trunc : SDNode<"ISD::TRUNCATE" , SDTIntTruncOp>; 317def bitconvert : SDNode<"ISD::BIT_CONVERT", SDTUnaryOp>; 318def extractelt : SDNode<"ISD::EXTRACT_VECTOR_ELT", SDTVecExtract>; 319def insertelt : SDNode<"ISD::INSERT_VECTOR_ELT", SDTVecInsert>; 320 321 322def fadd : SDNode<"ISD::FADD" , SDTFPBinOp, [SDNPCommutative]>; 323def fsub : SDNode<"ISD::FSUB" , SDTFPBinOp>; 324def fmul : SDNode<"ISD::FMUL" , SDTFPBinOp, [SDNPCommutative]>; 325def fdiv : SDNode<"ISD::FDIV" , SDTFPBinOp>; 326def frem : SDNode<"ISD::FREM" , SDTFPBinOp>; 327def fabs : SDNode<"ISD::FABS" , SDTFPUnaryOp>; 328def fneg : SDNode<"ISD::FNEG" , SDTFPUnaryOp>; 329def fsqrt : SDNode<"ISD::FSQRT" , SDTFPUnaryOp>; 330def fsin : SDNode<"ISD::FSIN" , SDTFPUnaryOp>; 331def fcos : SDNode<"ISD::FCOS" , SDTFPUnaryOp>; 332def fexp2 : SDNode<"ISD::FEXP2" , SDTFPUnaryOp>; 333def flog2 : SDNode<"ISD::FLOG2" , SDTFPUnaryOp>; 334def frint : SDNode<"ISD::FRINT" , SDTFPUnaryOp>; 335def ftrunc : SDNode<"ISD::FTRUNC" , SDTFPUnaryOp>; 336def fceil : SDNode<"ISD::FCEIL" , SDTFPUnaryOp>; 337def ffloor : SDNode<"ISD::FFLOOR" , SDTFPUnaryOp>; 338def fnearbyint : SDNode<"ISD::FNEARBYINT" , SDTFPUnaryOp>; 339 340def fround : SDNode<"ISD::FP_ROUND" , SDTFPRoundOp>; 341def fextend : SDNode<"ISD::FP_EXTEND" , SDTFPExtendOp>; 342def fcopysign : SDNode<"ISD::FCOPYSIGN" , SDTFPSignOp>; 343 344def sint_to_fp : SDNode<"ISD::SINT_TO_FP" , SDTIntToFPOp>; 345def uint_to_fp : SDNode<"ISD::UINT_TO_FP" , SDTIntToFPOp>; 346def fp_to_sint : SDNode<"ISD::FP_TO_SINT" , SDTFPToIntOp>; 347def fp_to_uint : SDNode<"ISD::FP_TO_UINT" , SDTFPToIntOp>; 348def f16_to_f32 : SDNode<"ISD::FP16_TO_FP32", SDTIntToFPOp>; 349def f32_to_f16 : SDNode<"ISD::FP32_TO_FP16", SDTFPToIntOp>; 350 351def setcc : SDNode<"ISD::SETCC" , SDTSetCC>; 352def select : SDNode<"ISD::SELECT" , SDTSelect>; 353def selectcc : SDNode<"ISD::SELECT_CC" , SDTSelectCC>; 354def vsetcc : SDNode<"ISD::VSETCC" , SDTSetCC>; 355 356def brcond : SDNode<"ISD::BRCOND" , SDTBrcond, [SDNPHasChain]>; 357def brind : SDNode<"ISD::BRIND" , SDTBrind, [SDNPHasChain]>; 358def br : SDNode<"ISD::BR" , SDTBr, [SDNPHasChain]>; 359def trap : SDNode<"ISD::TRAP" , SDTNone, 360 [SDNPHasChain, SDNPSideEffect]>; 361 362def prefetch : SDNode<"ISD::PREFETCH" , STDPrefetch, 363 [SDNPHasChain, SDNPMayLoad, SDNPMayStore]>; 364 365def membarrier : SDNode<"ISD::MEMBARRIER" , STDMemBarrier, 366 [SDNPHasChain, SDNPSideEffect]>; 367 368def atomic_cmp_swap : SDNode<"ISD::ATOMIC_CMP_SWAP" , STDAtomic3, 369 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 370def atomic_load_add : SDNode<"ISD::ATOMIC_LOAD_ADD" , STDAtomic2, 371 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 372def atomic_swap : SDNode<"ISD::ATOMIC_SWAP", STDAtomic2, 373 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 374def atomic_load_sub : SDNode<"ISD::ATOMIC_LOAD_SUB" , STDAtomic2, 375 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 376def atomic_load_and : SDNode<"ISD::ATOMIC_LOAD_AND" , STDAtomic2, 377 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 378def atomic_load_or : SDNode<"ISD::ATOMIC_LOAD_OR" , STDAtomic2, 379 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 380def atomic_load_xor : SDNode<"ISD::ATOMIC_LOAD_XOR" , STDAtomic2, 381 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 382def atomic_load_nand: SDNode<"ISD::ATOMIC_LOAD_NAND", STDAtomic2, 383 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 384def atomic_load_min : SDNode<"ISD::ATOMIC_LOAD_MIN", STDAtomic2, 385 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 386def atomic_load_max : SDNode<"ISD::ATOMIC_LOAD_MAX", STDAtomic2, 387 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 388def atomic_load_umin : SDNode<"ISD::ATOMIC_LOAD_UMIN", STDAtomic2, 389 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 390def atomic_load_umax : SDNode<"ISD::ATOMIC_LOAD_UMAX", STDAtomic2, 391 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 392 393// Do not use ld, st directly. Use load, extload, sextload, zextload, store, 394// and truncst (see below). 395def ld : SDNode<"ISD::LOAD" , SDTLoad, 396 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 397def st : SDNode<"ISD::STORE" , SDTStore, 398 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 399def ist : SDNode<"ISD::STORE" , SDTIStore, 400 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 401 402def vector_shuffle : SDNode<"ISD::VECTOR_SHUFFLE", SDTVecShuffle, []>; 403def build_vector : SDNode<"ISD::BUILD_VECTOR", SDTypeProfile<1, -1, []>, []>; 404def scalar_to_vector : SDNode<"ISD::SCALAR_TO_VECTOR", SDTypeProfile<1, 1, []>, 405 []>; 406def vector_extract : SDNode<"ISD::EXTRACT_VECTOR_ELT", 407 SDTypeProfile<1, 2, [SDTCisPtrTy<2>]>, []>; 408def vector_insert : SDNode<"ISD::INSERT_VECTOR_ELT", 409 SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisPtrTy<3>]>, []>; 410 411// Nodes for intrinsics, you should use the intrinsic itself and let tblgen use 412// these internally. Don't reference these directly. 413def intrinsic_void : SDNode<"ISD::INTRINSIC_VOID", 414 SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>, 415 [SDNPHasChain]>; 416def intrinsic_w_chain : SDNode<"ISD::INTRINSIC_W_CHAIN", 417 SDTypeProfile<1, -1, [SDTCisPtrTy<1>]>, 418 [SDNPHasChain]>; 419def intrinsic_wo_chain : SDNode<"ISD::INTRINSIC_WO_CHAIN", 420 SDTypeProfile<1, -1, [SDTCisPtrTy<1>]>, []>; 421 422// Do not use cvt directly. Use cvt forms below 423def cvt : SDNode<"ISD::CONVERT_RNDSAT", SDTConvertOp>; 424 425//===----------------------------------------------------------------------===// 426// Selection DAG Condition Codes 427 428class CondCode; // ISD::CondCode enums 429def SETOEQ : CondCode; def SETOGT : CondCode; 430def SETOGE : CondCode; def SETOLT : CondCode; def SETOLE : CondCode; 431def SETONE : CondCode; def SETO : CondCode; def SETUO : CondCode; 432def SETUEQ : CondCode; def SETUGT : CondCode; def SETUGE : CondCode; 433def SETULT : CondCode; def SETULE : CondCode; def SETUNE : CondCode; 434 435def SETEQ : CondCode; def SETGT : CondCode; def SETGE : CondCode; 436def SETLT : CondCode; def SETLE : CondCode; def SETNE : CondCode; 437 438 439//===----------------------------------------------------------------------===// 440// Selection DAG Node Transformation Functions. 441// 442// This mechanism allows targets to manipulate nodes in the output DAG once a 443// match has been formed. This is typically used to manipulate immediate 444// values. 445// 446class SDNodeXForm<SDNode opc, code xformFunction> { 447 SDNode Opcode = opc; 448 code XFormFunction = xformFunction; 449} 450 451def NOOP_SDNodeXForm : SDNodeXForm<imm, [{}]>; 452 453 454//===----------------------------------------------------------------------===// 455// Selection DAG Pattern Fragments. 456// 457// Pattern fragments are reusable chunks of dags that match specific things. 458// They can take arguments and have C++ predicates that control whether they 459// match. They are intended to make the patterns for common instructions more 460// compact and readable. 461// 462 463/// PatFrag - Represents a pattern fragment. This can match something on the 464/// DAG, frame a single node to multiply nested other fragments. 465/// 466class PatFrag<dag ops, dag frag, code pred = [{}], 467 SDNodeXForm xform = NOOP_SDNodeXForm> { 468 dag Operands = ops; 469 dag Fragment = frag; 470 code Predicate = pred; 471 SDNodeXForm OperandTransform = xform; 472} 473 474// PatLeaf's are pattern fragments that have no operands. This is just a helper 475// to define immediates and other common things concisely. 476class PatLeaf<dag frag, code pred = [{}], SDNodeXForm xform = NOOP_SDNodeXForm> 477 : PatFrag<(ops), frag, pred, xform>; 478 479// Leaf fragments. 480 481def vtInt : PatLeaf<(vt), [{ return N->getVT().isInteger(); }]>; 482def vtFP : PatLeaf<(vt), [{ return N->getVT().isFloatingPoint(); }]>; 483 484def immAllOnesV: PatLeaf<(build_vector), [{ 485 return ISD::isBuildVectorAllOnes(N); 486}]>; 487def immAllOnesV_bc: PatLeaf<(bitconvert), [{ 488 return ISD::isBuildVectorAllOnes(N); 489}]>; 490def immAllZerosV: PatLeaf<(build_vector), [{ 491 return ISD::isBuildVectorAllZeros(N); 492}]>; 493def immAllZerosV_bc: PatLeaf<(bitconvert), [{ 494 return ISD::isBuildVectorAllZeros(N); 495}]>; 496 497 498 499// Other helper fragments. 500def not : PatFrag<(ops node:$in), (xor node:$in, -1)>; 501def vnot : PatFrag<(ops node:$in), (xor node:$in, immAllOnesV)>; 502def vnot_conv : PatFrag<(ops node:$in), (xor node:$in, immAllOnesV_bc)>; 503def ineg : PatFrag<(ops node:$in), (sub 0, node:$in)>; 504 505// load fragments. 506def unindexedload : PatFrag<(ops node:$ptr), (ld node:$ptr), [{ 507 return cast<LoadSDNode>(N)->getAddressingMode() == ISD::UNINDEXED; 508}]>; 509def load : PatFrag<(ops node:$ptr), (unindexedload node:$ptr), [{ 510 return cast<LoadSDNode>(N)->getExtensionType() == ISD::NON_EXTLOAD; 511}]>; 512 513// extending load fragments. 514def extload : PatFrag<(ops node:$ptr), (unindexedload node:$ptr), [{ 515 return cast<LoadSDNode>(N)->getExtensionType() == ISD::EXTLOAD; 516}]>; 517def sextload : PatFrag<(ops node:$ptr), (unindexedload node:$ptr), [{ 518 return cast<LoadSDNode>(N)->getExtensionType() == ISD::SEXTLOAD; 519}]>; 520def zextload : PatFrag<(ops node:$ptr), (unindexedload node:$ptr), [{ 521 return cast<LoadSDNode>(N)->getExtensionType() == ISD::ZEXTLOAD; 522}]>; 523 524def extloadi1 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{ 525 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i1; 526}]>; 527def extloadi8 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{ 528 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i8; 529}]>; 530def extloadi16 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{ 531 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i16; 532}]>; 533def extloadi32 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{ 534 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i32; 535}]>; 536def extloadf32 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{ 537 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::f32; 538}]>; 539def extloadf64 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{ 540 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::f64; 541}]>; 542 543def sextloadi1 : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{ 544 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i1; 545}]>; 546def sextloadi8 : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{ 547 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i8; 548}]>; 549def sextloadi16 : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{ 550 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i16; 551}]>; 552def sextloadi32 : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{ 553 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i32; 554}]>; 555 556def zextloadi1 : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{ 557 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i1; 558}]>; 559def zextloadi8 : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{ 560 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i8; 561}]>; 562def zextloadi16 : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{ 563 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i16; 564}]>; 565def zextloadi32 : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{ 566 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i32; 567}]>; 568 569// store fragments. 570def unindexedstore : PatFrag<(ops node:$val, node:$ptr), 571 (st node:$val, node:$ptr), [{ 572 return cast<StoreSDNode>(N)->getAddressingMode() == ISD::UNINDEXED; 573}]>; 574def store : PatFrag<(ops node:$val, node:$ptr), 575 (unindexedstore node:$val, node:$ptr), [{ 576 return !cast<StoreSDNode>(N)->isTruncatingStore(); 577}]>; 578 579// truncstore fragments. 580def truncstore : PatFrag<(ops node:$val, node:$ptr), 581 (unindexedstore node:$val, node:$ptr), [{ 582 return cast<StoreSDNode>(N)->isTruncatingStore(); 583}]>; 584def truncstorei8 : PatFrag<(ops node:$val, node:$ptr), 585 (truncstore node:$val, node:$ptr), [{ 586 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i8; 587}]>; 588def truncstorei16 : PatFrag<(ops node:$val, node:$ptr), 589 (truncstore node:$val, node:$ptr), [{ 590 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i16; 591}]>; 592def truncstorei32 : PatFrag<(ops node:$val, node:$ptr), 593 (truncstore node:$val, node:$ptr), [{ 594 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i32; 595}]>; 596def truncstoref32 : PatFrag<(ops node:$val, node:$ptr), 597 (truncstore node:$val, node:$ptr), [{ 598 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::f32; 599}]>; 600def truncstoref64 : PatFrag<(ops node:$val, node:$ptr), 601 (truncstore node:$val, node:$ptr), [{ 602 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::f64; 603}]>; 604 605// indexed store fragments. 606def istore : PatFrag<(ops node:$val, node:$base, node:$offset), 607 (ist node:$val, node:$base, node:$offset), [{ 608 return !cast<StoreSDNode>(N)->isTruncatingStore(); 609}]>; 610 611def pre_store : PatFrag<(ops node:$val, node:$base, node:$offset), 612 (istore node:$val, node:$base, node:$offset), [{ 613 ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode(); 614 return AM == ISD::PRE_INC || AM == ISD::PRE_DEC; 615}]>; 616 617def itruncstore : PatFrag<(ops node:$val, node:$base, node:$offset), 618 (ist node:$val, node:$base, node:$offset), [{ 619 return cast<StoreSDNode>(N)->isTruncatingStore(); 620}]>; 621def pre_truncst : PatFrag<(ops node:$val, node:$base, node:$offset), 622 (itruncstore node:$val, node:$base, node:$offset), [{ 623 ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode(); 624 return AM == ISD::PRE_INC || AM == ISD::PRE_DEC; 625}]>; 626def pre_truncsti1 : PatFrag<(ops node:$val, node:$base, node:$offset), 627 (pre_truncst node:$val, node:$base, node:$offset), [{ 628 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i1; 629}]>; 630def pre_truncsti8 : PatFrag<(ops node:$val, node:$base, node:$offset), 631 (pre_truncst node:$val, node:$base, node:$offset), [{ 632 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i8; 633}]>; 634def pre_truncsti16 : PatFrag<(ops node:$val, node:$base, node:$offset), 635 (pre_truncst node:$val, node:$base, node:$offset), [{ 636 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i16; 637}]>; 638def pre_truncsti32 : PatFrag<(ops node:$val, node:$base, node:$offset), 639 (pre_truncst node:$val, node:$base, node:$offset), [{ 640 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i32; 641}]>; 642def pre_truncstf32 : PatFrag<(ops node:$val, node:$base, node:$offset), 643 (pre_truncst node:$val, node:$base, node:$offset), [{ 644 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::f32; 645}]>; 646 647def post_store : PatFrag<(ops node:$val, node:$ptr, node:$offset), 648 (istore node:$val, node:$ptr, node:$offset), [{ 649 ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode(); 650 return AM == ISD::POST_INC || AM == ISD::POST_DEC; 651}]>; 652 653def post_truncst : PatFrag<(ops node:$val, node:$base, node:$offset), 654 (itruncstore node:$val, node:$base, node:$offset), [{ 655 ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode(); 656 return AM == ISD::POST_INC || AM == ISD::POST_DEC; 657}]>; 658def post_truncsti1 : PatFrag<(ops node:$val, node:$base, node:$offset), 659 (post_truncst node:$val, node:$base, node:$offset), [{ 660 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i1; 661}]>; 662def post_truncsti8 : PatFrag<(ops node:$val, node:$base, node:$offset), 663 (post_truncst node:$val, node:$base, node:$offset), [{ 664 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i8; 665}]>; 666def post_truncsti16 : PatFrag<(ops node:$val, node:$base, node:$offset), 667 (post_truncst node:$val, node:$base, node:$offset), [{ 668 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i16; 669}]>; 670def post_truncsti32 : PatFrag<(ops node:$val, node:$base, node:$offset), 671 (post_truncst node:$val, node:$base, node:$offset), [{ 672 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i32; 673}]>; 674def post_truncstf32 : PatFrag<(ops node:$val, node:$base, node:$offset), 675 (post_truncst node:$val, node:$base, node:$offset), [{ 676 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::f32; 677}]>; 678 679// setcc convenience fragments. 680def setoeq : PatFrag<(ops node:$lhs, node:$rhs), 681 (setcc node:$lhs, node:$rhs, SETOEQ)>; 682def setogt : PatFrag<(ops node:$lhs, node:$rhs), 683 (setcc node:$lhs, node:$rhs, SETOGT)>; 684def setoge : PatFrag<(ops node:$lhs, node:$rhs), 685 (setcc node:$lhs, node:$rhs, SETOGE)>; 686def setolt : PatFrag<(ops node:$lhs, node:$rhs), 687 (setcc node:$lhs, node:$rhs, SETOLT)>; 688def setole : PatFrag<(ops node:$lhs, node:$rhs), 689 (setcc node:$lhs, node:$rhs, SETOLE)>; 690def setone : PatFrag<(ops node:$lhs, node:$rhs), 691 (setcc node:$lhs, node:$rhs, SETONE)>; 692def seto : PatFrag<(ops node:$lhs, node:$rhs), 693 (setcc node:$lhs, node:$rhs, SETO)>; 694def setuo : PatFrag<(ops node:$lhs, node:$rhs), 695 (setcc node:$lhs, node:$rhs, SETUO)>; 696def setueq : PatFrag<(ops node:$lhs, node:$rhs), 697 (setcc node:$lhs, node:$rhs, SETUEQ)>; 698def setugt : PatFrag<(ops node:$lhs, node:$rhs), 699 (setcc node:$lhs, node:$rhs, SETUGT)>; 700def setuge : PatFrag<(ops node:$lhs, node:$rhs), 701 (setcc node:$lhs, node:$rhs, SETUGE)>; 702def setult : PatFrag<(ops node:$lhs, node:$rhs), 703 (setcc node:$lhs, node:$rhs, SETULT)>; 704def setule : PatFrag<(ops node:$lhs, node:$rhs), 705 (setcc node:$lhs, node:$rhs, SETULE)>; 706def setune : PatFrag<(ops node:$lhs, node:$rhs), 707 (setcc node:$lhs, node:$rhs, SETUNE)>; 708def seteq : PatFrag<(ops node:$lhs, node:$rhs), 709 (setcc node:$lhs, node:$rhs, SETEQ)>; 710def setgt : PatFrag<(ops node:$lhs, node:$rhs), 711 (setcc node:$lhs, node:$rhs, SETGT)>; 712def setge : PatFrag<(ops node:$lhs, node:$rhs), 713 (setcc node:$lhs, node:$rhs, SETGE)>; 714def setlt : PatFrag<(ops node:$lhs, node:$rhs), 715 (setcc node:$lhs, node:$rhs, SETLT)>; 716def setle : PatFrag<(ops node:$lhs, node:$rhs), 717 (setcc node:$lhs, node:$rhs, SETLE)>; 718def setne : PatFrag<(ops node:$lhs, node:$rhs), 719 (setcc node:$lhs, node:$rhs, SETNE)>; 720 721def atomic_cmp_swap_8 : 722 PatFrag<(ops node:$ptr, node:$cmp, node:$swap), 723 (atomic_cmp_swap node:$ptr, node:$cmp, node:$swap), [{ 724 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i8; 725}]>; 726def atomic_cmp_swap_16 : 727 PatFrag<(ops node:$ptr, node:$cmp, node:$swap), 728 (atomic_cmp_swap node:$ptr, node:$cmp, node:$swap), [{ 729 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i16; 730}]>; 731def atomic_cmp_swap_32 : 732 PatFrag<(ops node:$ptr, node:$cmp, node:$swap), 733 (atomic_cmp_swap node:$ptr, node:$cmp, node:$swap), [{ 734 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i32; 735}]>; 736def atomic_cmp_swap_64 : 737 PatFrag<(ops node:$ptr, node:$cmp, node:$swap), 738 (atomic_cmp_swap node:$ptr, node:$cmp, node:$swap), [{ 739 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i64; 740}]>; 741 742multiclass binary_atomic_op<SDNode atomic_op> { 743 def _8 : PatFrag<(ops node:$ptr, node:$val), 744 (atomic_op node:$ptr, node:$val), [{ 745 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i8; 746 }]>; 747 def _16 : PatFrag<(ops node:$ptr, node:$val), 748 (atomic_op node:$ptr, node:$val), [{ 749 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i16; 750 }]>; 751 def _32 : PatFrag<(ops node:$ptr, node:$val), 752 (atomic_op node:$ptr, node:$val), [{ 753 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i32; 754 }]>; 755 def _64 : PatFrag<(ops node:$ptr, node:$val), 756 (atomic_op node:$ptr, node:$val), [{ 757 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i64; 758 }]>; 759} 760 761defm atomic_load_add : binary_atomic_op<atomic_load_add>; 762defm atomic_swap : binary_atomic_op<atomic_swap>; 763defm atomic_load_sub : binary_atomic_op<atomic_load_sub>; 764defm atomic_load_and : binary_atomic_op<atomic_load_and>; 765defm atomic_load_or : binary_atomic_op<atomic_load_or>; 766defm atomic_load_xor : binary_atomic_op<atomic_load_xor>; 767defm atomic_load_nand : binary_atomic_op<atomic_load_nand>; 768defm atomic_load_min : binary_atomic_op<atomic_load_min>; 769defm atomic_load_max : binary_atomic_op<atomic_load_max>; 770defm atomic_load_umin : binary_atomic_op<atomic_load_umin>; 771defm atomic_load_umax : binary_atomic_op<atomic_load_umax>; 772 773//===----------------------------------------------------------------------===// 774// Selection DAG CONVERT_RNDSAT patterns 775 776def cvtff : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat), 777 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{ 778 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_FF; 779 }]>; 780 781def cvtss : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat), 782 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{ 783 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_SS; 784 }]>; 785 786def cvtsu : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat), 787 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{ 788 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_SU; 789 }]>; 790 791def cvtus : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat), 792 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{ 793 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_US; 794 }]>; 795 796def cvtuu : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat), 797 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{ 798 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_UU; 799 }]>; 800 801def cvtsf : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat), 802 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{ 803 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_SF; 804 }]>; 805 806def cvtuf : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat), 807 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{ 808 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_UF; 809 }]>; 810 811def cvtfs : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat), 812 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{ 813 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_FS; 814 }]>; 815 816def cvtfu : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat), 817 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{ 818 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_FU; 819 }]>; 820 821//===----------------------------------------------------------------------===// 822// Selection DAG Pattern Support. 823// 824// Patterns are what are actually matched against the target-flavored 825// instruction selection DAG. Instructions defined by the target implicitly 826// define patterns in most cases, but patterns can also be explicitly added when 827// an operation is defined by a sequence of instructions (e.g. loading a large 828// immediate value on RISC targets that do not support immediates as large as 829// their GPRs). 830// 831 832class Pattern<dag patternToMatch, list<dag> resultInstrs> { 833 dag PatternToMatch = patternToMatch; 834 list<dag> ResultInstrs = resultInstrs; 835 list<Predicate> Predicates = []; // See class Instruction in Target.td. 836 int AddedComplexity = 0; // See class Instruction in Target.td. 837} 838 839// Pat - A simple (but common) form of a pattern, which produces a simple result 840// not needing a full list. 841class Pat<dag pattern, dag result> : Pattern<pattern, [result]>; 842 843//===----------------------------------------------------------------------===// 844// Complex pattern definitions. 845// 846 847// Complex patterns, e.g. X86 addressing mode, requires pattern matching code 848// in C++. NumOperands is the number of operands returned by the select function; 849// SelectFunc is the name of the function used to pattern match the max. pattern; 850// RootNodes are the list of possible root nodes of the sub-dags to match. 851// e.g. X86 addressing mode - def addr : ComplexPattern<4, "SelectAddr", [add]>; 852// 853class ComplexPattern<ValueType ty, int numops, string fn, 854 list<SDNode> roots = [], list<SDNodeProperty> props = []> { 855 ValueType Ty = ty; 856 int NumOperands = numops; 857 string SelectFunc = fn; 858 list<SDNode> RootNodes = roots; 859 list<SDNodeProperty> Properties = props; 860} 861