TargetSelectionDAG.td revision 204642
1//===- TargetSelectionDAG.td - Common code for DAG isels ---*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines the target-independent interfaces used by SelectionDAG 11// instruction selection generators. 12// 13//===----------------------------------------------------------------------===// 14 15//===----------------------------------------------------------------------===// 16// Selection DAG Type Constraint definitions. 17// 18// Note that the semantics of these constraints are hard coded into tblgen. To 19// modify or add constraints, you have to hack tblgen. 20// 21 22class SDTypeConstraint<int opnum> { 23 int OperandNum = opnum; 24} 25 26// SDTCisVT - The specified operand has exactly this VT. 27class SDTCisVT<int OpNum, ValueType vt> : SDTypeConstraint<OpNum> { 28 ValueType VT = vt; 29} 30 31class SDTCisPtrTy<int OpNum> : SDTypeConstraint<OpNum>; 32 33// SDTCisInt - The specified operand has integer type. 34class SDTCisInt<int OpNum> : SDTypeConstraint<OpNum>; 35 36// SDTCisFP - The specified operand has floating-point type. 37class SDTCisFP<int OpNum> : SDTypeConstraint<OpNum>; 38 39// SDTCisVec - The specified operand has a vector type. 40class SDTCisVec<int OpNum> : SDTypeConstraint<OpNum>; 41 42// SDTCisSameAs - The two specified operands have identical types. 43class SDTCisSameAs<int OpNum, int OtherOp> : SDTypeConstraint<OpNum> { 44 int OtherOperandNum = OtherOp; 45} 46 47// SDTCisVTSmallerThanOp - The specified operand is a VT SDNode, and its type is 48// smaller than the 'Other' operand. 49class SDTCisVTSmallerThanOp<int OpNum, int OtherOp> : SDTypeConstraint<OpNum> { 50 int OtherOperandNum = OtherOp; 51} 52 53class SDTCisOpSmallerThanOp<int SmallOp, int BigOp> : SDTypeConstraint<SmallOp>{ 54 int BigOperandNum = BigOp; 55} 56 57/// SDTCisEltOfVec - This indicates that ThisOp is a scalar type of the same 58/// type as the element type of OtherOp, which is a vector type. 59class SDTCisEltOfVec<int ThisOp, int OtherOp> 60 : SDTypeConstraint<ThisOp> { 61 int OtherOpNum = OtherOp; 62} 63 64//===----------------------------------------------------------------------===// 65// Selection DAG Type Profile definitions. 66// 67// These use the constraints defined above to describe the type requirements of 68// the various nodes. These are not hard coded into tblgen, allowing targets to 69// add their own if needed. 70// 71 72// SDTypeProfile - This profile describes the type requirements of a Selection 73// DAG node. 74class SDTypeProfile<int numresults, int numoperands, 75 list<SDTypeConstraint> constraints> { 76 int NumResults = numresults; 77 int NumOperands = numoperands; 78 list<SDTypeConstraint> Constraints = constraints; 79} 80 81// Builtin profiles. 82def SDTIntLeaf: SDTypeProfile<1, 0, [SDTCisInt<0>]>; // for 'imm'. 83def SDTFPLeaf : SDTypeProfile<1, 0, [SDTCisFP<0>]>; // for 'fpimm'. 84def SDTPtrLeaf: SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>; // for '&g'. 85def SDTOther : SDTypeProfile<1, 0, [SDTCisVT<0, OtherVT>]>; // for 'vt'. 86def SDTUNDEF : SDTypeProfile<1, 0, []>; // for 'undef'. 87def SDTUnaryOp : SDTypeProfile<1, 1, []>; // for bitconvert. 88 89def SDTIntBinOp : SDTypeProfile<1, 2, [ // add, and, or, xor, udiv, etc. 90 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisInt<0> 91]>; 92def SDTIntShiftOp : SDTypeProfile<1, 2, [ // shl, sra, srl 93 SDTCisSameAs<0, 1>, SDTCisInt<0>, SDTCisInt<2> 94]>; 95def SDTFPBinOp : SDTypeProfile<1, 2, [ // fadd, fmul, etc. 96 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisFP<0> 97]>; 98def SDTFPSignOp : SDTypeProfile<1, 2, [ // fcopysign. 99 SDTCisSameAs<0, 1>, SDTCisFP<0>, SDTCisFP<2> 100]>; 101def SDTFPTernaryOp : SDTypeProfile<1, 3, [ // fmadd, fnmsub, etc. 102 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>, SDTCisFP<0> 103]>; 104def SDTIntUnaryOp : SDTypeProfile<1, 1, [ // ctlz 105 SDTCisSameAs<0, 1>, SDTCisInt<0> 106]>; 107def SDTIntExtendOp : SDTypeProfile<1, 1, [ // sext, zext, anyext 108 SDTCisInt<0>, SDTCisInt<1>, SDTCisOpSmallerThanOp<1, 0> 109]>; 110def SDTIntTruncOp : SDTypeProfile<1, 1, [ // trunc 111 SDTCisInt<0>, SDTCisInt<1>, SDTCisOpSmallerThanOp<0, 1> 112]>; 113def SDTFPUnaryOp : SDTypeProfile<1, 1, [ // fneg, fsqrt, etc 114 SDTCisSameAs<0, 1>, SDTCisFP<0> 115]>; 116def SDTFPRoundOp : SDTypeProfile<1, 1, [ // fround 117 SDTCisFP<0>, SDTCisFP<1>, SDTCisOpSmallerThanOp<0, 1> 118]>; 119def SDTFPExtendOp : SDTypeProfile<1, 1, [ // fextend 120 SDTCisFP<0>, SDTCisFP<1>, SDTCisOpSmallerThanOp<1, 0> 121]>; 122def SDTIntToFPOp : SDTypeProfile<1, 1, [ // [su]int_to_fp 123 SDTCisFP<0>, SDTCisInt<1> 124]>; 125def SDTFPToIntOp : SDTypeProfile<1, 1, [ // fp_to_[su]int 126 SDTCisInt<0>, SDTCisFP<1> 127]>; 128def SDTExtInreg : SDTypeProfile<1, 2, [ // sext_inreg 129 SDTCisSameAs<0, 1>, SDTCisInt<0>, SDTCisVT<2, OtherVT>, 130 SDTCisVTSmallerThanOp<2, 1> 131]>; 132 133def SDTSetCC : SDTypeProfile<1, 3, [ // setcc 134 SDTCisInt<0>, SDTCisSameAs<1, 2>, SDTCisVT<3, OtherVT> 135]>; 136 137def SDTSelect : SDTypeProfile<1, 3, [ // select 138 SDTCisInt<1>, SDTCisSameAs<0, 2>, SDTCisSameAs<2, 3> 139]>; 140 141def SDTSelectCC : SDTypeProfile<1, 5, [ // select_cc 142 SDTCisSameAs<1, 2>, SDTCisSameAs<3, 4>, SDTCisSameAs<0, 3>, 143 SDTCisVT<5, OtherVT> 144]>; 145 146def SDTBr : SDTypeProfile<0, 1, [ // br 147 SDTCisVT<0, OtherVT> 148]>; 149 150def SDTBrcond : SDTypeProfile<0, 2, [ // brcond 151 SDTCisInt<0>, SDTCisVT<1, OtherVT> 152]>; 153 154def SDTBrind : SDTypeProfile<0, 1, [ // brind 155 SDTCisPtrTy<0> 156]>; 157 158def SDTNone : SDTypeProfile<0, 0, []>; // ret, trap 159 160def SDTLoad : SDTypeProfile<1, 1, [ // load 161 SDTCisPtrTy<1> 162]>; 163 164def SDTStore : SDTypeProfile<0, 2, [ // store 165 SDTCisPtrTy<1> 166]>; 167 168def SDTIStore : SDTypeProfile<1, 3, [ // indexed store 169 SDTCisSameAs<0, 2>, SDTCisPtrTy<0>, SDTCisPtrTy<3> 170]>; 171 172def SDTVecShuffle : SDTypeProfile<1, 2, [ 173 SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2> 174]>; 175def SDTVecExtract : SDTypeProfile<1, 2, [ // vector extract 176 SDTCisEltOfVec<0, 1>, SDTCisPtrTy<2> 177]>; 178def SDTVecInsert : SDTypeProfile<1, 3, [ // vector insert 179 SDTCisEltOfVec<2, 1>, SDTCisSameAs<0, 1>, SDTCisPtrTy<3> 180]>; 181 182def STDPrefetch : SDTypeProfile<0, 3, [ // prefetch 183 SDTCisPtrTy<0>, SDTCisSameAs<1, 2>, SDTCisInt<1> 184]>; 185 186def STDMemBarrier : SDTypeProfile<0, 5, [ // memory barier 187 SDTCisSameAs<0,1>, SDTCisSameAs<0,2>, SDTCisSameAs<0,3>, SDTCisSameAs<0,4>, 188 SDTCisInt<0> 189]>; 190def STDAtomic3 : SDTypeProfile<1, 3, [ 191 SDTCisSameAs<0,2>, SDTCisSameAs<0,3>, SDTCisInt<0>, SDTCisPtrTy<1> 192]>; 193def STDAtomic2 : SDTypeProfile<1, 2, [ 194 SDTCisSameAs<0,2>, SDTCisInt<0>, SDTCisPtrTy<1> 195]>; 196 197def SDTConvertOp : SDTypeProfile<1, 5, [ //cvtss, su, us, uu, ff, fs, fu, sf, su 198 SDTCisVT<2, OtherVT>, SDTCisVT<3, OtherVT>, SDTCisPtrTy<4>, SDTCisPtrTy<5> 199]>; 200 201class SDCallSeqStart<list<SDTypeConstraint> constraints> : 202 SDTypeProfile<0, 1, constraints>; 203class SDCallSeqEnd<list<SDTypeConstraint> constraints> : 204 SDTypeProfile<0, 2, constraints>; 205 206//===----------------------------------------------------------------------===// 207// Selection DAG Node Properties. 208// 209// Note: These are hard coded into tblgen. 210// 211class SDNodeProperty; 212def SDNPCommutative : SDNodeProperty; // X op Y == Y op X 213def SDNPAssociative : SDNodeProperty; // (X op Y) op Z == X op (Y op Z) 214def SDNPHasChain : SDNodeProperty; // R/W chain operand and result 215def SDNPOutFlag : SDNodeProperty; // Write a flag result 216def SDNPInFlag : SDNodeProperty; // Read a flag operand 217def SDNPOptInFlag : SDNodeProperty; // Optionally read a flag operand 218def SDNPMayStore : SDNodeProperty; // May write to memory, sets 'mayStore'. 219def SDNPMayLoad : SDNodeProperty; // May read memory, sets 'mayLoad'. 220def SDNPSideEffect : SDNodeProperty; // Sets 'HasUnmodelledSideEffects'. 221def SDNPMemOperand : SDNodeProperty; // Touches memory, has assoc MemOperand 222 223//===----------------------------------------------------------------------===// 224// Selection DAG Node definitions. 225// 226class SDNode<string opcode, SDTypeProfile typeprof, 227 list<SDNodeProperty> props = [], string sdclass = "SDNode"> { 228 string Opcode = opcode; 229 string SDClass = sdclass; 230 list<SDNodeProperty> Properties = props; 231 SDTypeProfile TypeProfile = typeprof; 232} 233 234// Special TableGen-recognized dag nodes 235def set; 236def implicit; 237def parallel; 238def node; 239def srcvalue; 240 241def imm : SDNode<"ISD::Constant" , SDTIntLeaf , [], "ConstantSDNode">; 242def timm : SDNode<"ISD::TargetConstant",SDTIntLeaf, [], "ConstantSDNode">; 243def fpimm : SDNode<"ISD::ConstantFP", SDTFPLeaf , [], "ConstantFPSDNode">; 244def vt : SDNode<"ISD::VALUETYPE" , SDTOther , [], "VTSDNode">; 245def bb : SDNode<"ISD::BasicBlock", SDTOther , [], "BasicBlockSDNode">; 246def cond : SDNode<"ISD::CONDCODE" , SDTOther , [], "CondCodeSDNode">; 247def undef : SDNode<"ISD::UNDEF" , SDTUNDEF , []>; 248def globaladdr : SDNode<"ISD::GlobalAddress", SDTPtrLeaf, [], 249 "GlobalAddressSDNode">; 250def tglobaladdr : SDNode<"ISD::TargetGlobalAddress", SDTPtrLeaf, [], 251 "GlobalAddressSDNode">; 252def globaltlsaddr : SDNode<"ISD::GlobalTLSAddress", SDTPtrLeaf, [], 253 "GlobalAddressSDNode">; 254def tglobaltlsaddr : SDNode<"ISD::TargetGlobalTLSAddress", SDTPtrLeaf, [], 255 "GlobalAddressSDNode">; 256def constpool : SDNode<"ISD::ConstantPool", SDTPtrLeaf, [], 257 "ConstantPoolSDNode">; 258def tconstpool : SDNode<"ISD::TargetConstantPool", SDTPtrLeaf, [], 259 "ConstantPoolSDNode">; 260def jumptable : SDNode<"ISD::JumpTable", SDTPtrLeaf, [], 261 "JumpTableSDNode">; 262def tjumptable : SDNode<"ISD::TargetJumpTable", SDTPtrLeaf, [], 263 "JumpTableSDNode">; 264def frameindex : SDNode<"ISD::FrameIndex", SDTPtrLeaf, [], 265 "FrameIndexSDNode">; 266def tframeindex : SDNode<"ISD::TargetFrameIndex", SDTPtrLeaf, [], 267 "FrameIndexSDNode">; 268def externalsym : SDNode<"ISD::ExternalSymbol", SDTPtrLeaf, [], 269 "ExternalSymbolSDNode">; 270def texternalsym: SDNode<"ISD::TargetExternalSymbol", SDTPtrLeaf, [], 271 "ExternalSymbolSDNode">; 272def blockaddress : SDNode<"ISD::BlockAddress", SDTPtrLeaf, [], 273 "BlockAddressSDNode">; 274def tblockaddress: SDNode<"ISD::TargetBlockAddress", SDTPtrLeaf, [], 275 "BlockAddressSDNode">; 276 277def add : SDNode<"ISD::ADD" , SDTIntBinOp , 278 [SDNPCommutative, SDNPAssociative]>; 279def sub : SDNode<"ISD::SUB" , SDTIntBinOp>; 280def mul : SDNode<"ISD::MUL" , SDTIntBinOp, 281 [SDNPCommutative, SDNPAssociative]>; 282def mulhs : SDNode<"ISD::MULHS" , SDTIntBinOp, [SDNPCommutative]>; 283def mulhu : SDNode<"ISD::MULHU" , SDTIntBinOp, [SDNPCommutative]>; 284def sdiv : SDNode<"ISD::SDIV" , SDTIntBinOp>; 285def udiv : SDNode<"ISD::UDIV" , SDTIntBinOp>; 286def srem : SDNode<"ISD::SREM" , SDTIntBinOp>; 287def urem : SDNode<"ISD::UREM" , SDTIntBinOp>; 288def srl : SDNode<"ISD::SRL" , SDTIntShiftOp>; 289def sra : SDNode<"ISD::SRA" , SDTIntShiftOp>; 290def shl : SDNode<"ISD::SHL" , SDTIntShiftOp>; 291def rotl : SDNode<"ISD::ROTL" , SDTIntShiftOp>; 292def rotr : SDNode<"ISD::ROTR" , SDTIntShiftOp>; 293def and : SDNode<"ISD::AND" , SDTIntBinOp, 294 [SDNPCommutative, SDNPAssociative]>; 295def or : SDNode<"ISD::OR" , SDTIntBinOp, 296 [SDNPCommutative, SDNPAssociative]>; 297def xor : SDNode<"ISD::XOR" , SDTIntBinOp, 298 [SDNPCommutative, SDNPAssociative]>; 299def addc : SDNode<"ISD::ADDC" , SDTIntBinOp, 300 [SDNPCommutative, SDNPOutFlag]>; 301def adde : SDNode<"ISD::ADDE" , SDTIntBinOp, 302 [SDNPCommutative, SDNPOutFlag, SDNPInFlag]>; 303def subc : SDNode<"ISD::SUBC" , SDTIntBinOp, 304 [SDNPOutFlag]>; 305def sube : SDNode<"ISD::SUBE" , SDTIntBinOp, 306 [SDNPOutFlag, SDNPInFlag]>; 307 308def sext_inreg : SDNode<"ISD::SIGN_EXTEND_INREG", SDTExtInreg>; 309def bswap : SDNode<"ISD::BSWAP" , SDTIntUnaryOp>; 310def ctlz : SDNode<"ISD::CTLZ" , SDTIntUnaryOp>; 311def cttz : SDNode<"ISD::CTTZ" , SDTIntUnaryOp>; 312def ctpop : SDNode<"ISD::CTPOP" , SDTIntUnaryOp>; 313def sext : SDNode<"ISD::SIGN_EXTEND", SDTIntExtendOp>; 314def zext : SDNode<"ISD::ZERO_EXTEND", SDTIntExtendOp>; 315def anyext : SDNode<"ISD::ANY_EXTEND" , SDTIntExtendOp>; 316def trunc : SDNode<"ISD::TRUNCATE" , SDTIntTruncOp>; 317def bitconvert : SDNode<"ISD::BIT_CONVERT", SDTUnaryOp>; 318def extractelt : SDNode<"ISD::EXTRACT_VECTOR_ELT", SDTVecExtract>; 319def insertelt : SDNode<"ISD::INSERT_VECTOR_ELT", SDTVecInsert>; 320 321 322def fadd : SDNode<"ISD::FADD" , SDTFPBinOp, [SDNPCommutative]>; 323def fsub : SDNode<"ISD::FSUB" , SDTFPBinOp>; 324def fmul : SDNode<"ISD::FMUL" , SDTFPBinOp, [SDNPCommutative]>; 325def fdiv : SDNode<"ISD::FDIV" , SDTFPBinOp>; 326def frem : SDNode<"ISD::FREM" , SDTFPBinOp>; 327def fabs : SDNode<"ISD::FABS" , SDTFPUnaryOp>; 328def fneg : SDNode<"ISD::FNEG" , SDTFPUnaryOp>; 329def fsqrt : SDNode<"ISD::FSQRT" , SDTFPUnaryOp>; 330def fsin : SDNode<"ISD::FSIN" , SDTFPUnaryOp>; 331def fcos : SDNode<"ISD::FCOS" , SDTFPUnaryOp>; 332def fexp2 : SDNode<"ISD::FEXP2" , SDTFPUnaryOp>; 333def flog2 : SDNode<"ISD::FLOG2" , SDTFPUnaryOp>; 334def frint : SDNode<"ISD::FRINT" , SDTFPUnaryOp>; 335def ftrunc : SDNode<"ISD::FTRUNC" , SDTFPUnaryOp>; 336def fceil : SDNode<"ISD::FCEIL" , SDTFPUnaryOp>; 337def ffloor : SDNode<"ISD::FFLOOR" , SDTFPUnaryOp>; 338def fnearbyint : SDNode<"ISD::FNEARBYINT" , SDTFPUnaryOp>; 339 340def fround : SDNode<"ISD::FP_ROUND" , SDTFPRoundOp>; 341def fextend : SDNode<"ISD::FP_EXTEND" , SDTFPExtendOp>; 342def fcopysign : SDNode<"ISD::FCOPYSIGN" , SDTFPSignOp>; 343 344def sint_to_fp : SDNode<"ISD::SINT_TO_FP" , SDTIntToFPOp>; 345def uint_to_fp : SDNode<"ISD::UINT_TO_FP" , SDTIntToFPOp>; 346def fp_to_sint : SDNode<"ISD::FP_TO_SINT" , SDTFPToIntOp>; 347def fp_to_uint : SDNode<"ISD::FP_TO_UINT" , SDTFPToIntOp>; 348 349def setcc : SDNode<"ISD::SETCC" , SDTSetCC>; 350def select : SDNode<"ISD::SELECT" , SDTSelect>; 351def selectcc : SDNode<"ISD::SELECT_CC" , SDTSelectCC>; 352def vsetcc : SDNode<"ISD::VSETCC" , SDTSetCC>; 353 354def brcond : SDNode<"ISD::BRCOND" , SDTBrcond, [SDNPHasChain]>; 355def brind : SDNode<"ISD::BRIND" , SDTBrind, [SDNPHasChain]>; 356def br : SDNode<"ISD::BR" , SDTBr, [SDNPHasChain]>; 357def trap : SDNode<"ISD::TRAP" , SDTNone, 358 [SDNPHasChain, SDNPSideEffect]>; 359 360def prefetch : SDNode<"ISD::PREFETCH" , STDPrefetch, 361 [SDNPHasChain, SDNPMayLoad, SDNPMayStore]>; 362 363def membarrier : SDNode<"ISD::MEMBARRIER" , STDMemBarrier, 364 [SDNPHasChain, SDNPSideEffect]>; 365 366def atomic_cmp_swap : SDNode<"ISD::ATOMIC_CMP_SWAP" , STDAtomic3, 367 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 368def atomic_load_add : SDNode<"ISD::ATOMIC_LOAD_ADD" , STDAtomic2, 369 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 370def atomic_swap : SDNode<"ISD::ATOMIC_SWAP", STDAtomic2, 371 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 372def atomic_load_sub : SDNode<"ISD::ATOMIC_LOAD_SUB" , STDAtomic2, 373 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 374def atomic_load_and : SDNode<"ISD::ATOMIC_LOAD_AND" , STDAtomic2, 375 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 376def atomic_load_or : SDNode<"ISD::ATOMIC_LOAD_OR" , STDAtomic2, 377 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 378def atomic_load_xor : SDNode<"ISD::ATOMIC_LOAD_XOR" , STDAtomic2, 379 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 380def atomic_load_nand: SDNode<"ISD::ATOMIC_LOAD_NAND", STDAtomic2, 381 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 382def atomic_load_min : SDNode<"ISD::ATOMIC_LOAD_MIN", STDAtomic2, 383 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 384def atomic_load_max : SDNode<"ISD::ATOMIC_LOAD_MAX", STDAtomic2, 385 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 386def atomic_load_umin : SDNode<"ISD::ATOMIC_LOAD_UMIN", STDAtomic2, 387 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 388def atomic_load_umax : SDNode<"ISD::ATOMIC_LOAD_UMAX", STDAtomic2, 389 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 390 391// Do not use ld, st directly. Use load, extload, sextload, zextload, store, 392// and truncst (see below). 393def ld : SDNode<"ISD::LOAD" , SDTLoad, 394 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 395def st : SDNode<"ISD::STORE" , SDTStore, 396 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 397def ist : SDNode<"ISD::STORE" , SDTIStore, 398 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 399 400def vector_shuffle : SDNode<"ISD::VECTOR_SHUFFLE", SDTVecShuffle, []>; 401def build_vector : SDNode<"ISD::BUILD_VECTOR", SDTypeProfile<1, -1, []>, []>; 402def scalar_to_vector : SDNode<"ISD::SCALAR_TO_VECTOR", SDTypeProfile<1, 1, []>, 403 []>; 404def vector_extract : SDNode<"ISD::EXTRACT_VECTOR_ELT", 405 SDTypeProfile<1, 2, [SDTCisPtrTy<2>]>, []>; 406def vector_insert : SDNode<"ISD::INSERT_VECTOR_ELT", 407 SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisPtrTy<3>]>, []>; 408 409// Nodes for intrinsics, you should use the intrinsic itself and let tblgen use 410// these internally. Don't reference these directly. 411def intrinsic_void : SDNode<"ISD::INTRINSIC_VOID", 412 SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>, 413 [SDNPHasChain]>; 414def intrinsic_w_chain : SDNode<"ISD::INTRINSIC_W_CHAIN", 415 SDTypeProfile<1, -1, [SDTCisPtrTy<1>]>, 416 [SDNPHasChain]>; 417def intrinsic_wo_chain : SDNode<"ISD::INTRINSIC_WO_CHAIN", 418 SDTypeProfile<1, -1, [SDTCisPtrTy<1>]>, []>; 419 420// Do not use cvt directly. Use cvt forms below 421def cvt : SDNode<"ISD::CONVERT_RNDSAT", SDTConvertOp>; 422 423//===----------------------------------------------------------------------===// 424// Selection DAG Condition Codes 425 426class CondCode; // ISD::CondCode enums 427def SETOEQ : CondCode; def SETOGT : CondCode; 428def SETOGE : CondCode; def SETOLT : CondCode; def SETOLE : CondCode; 429def SETONE : CondCode; def SETO : CondCode; def SETUO : CondCode; 430def SETUEQ : CondCode; def SETUGT : CondCode; def SETUGE : CondCode; 431def SETULT : CondCode; def SETULE : CondCode; def SETUNE : CondCode; 432 433def SETEQ : CondCode; def SETGT : CondCode; def SETGE : CondCode; 434def SETLT : CondCode; def SETLE : CondCode; def SETNE : CondCode; 435 436 437//===----------------------------------------------------------------------===// 438// Selection DAG Node Transformation Functions. 439// 440// This mechanism allows targets to manipulate nodes in the output DAG once a 441// match has been formed. This is typically used to manipulate immediate 442// values. 443// 444class SDNodeXForm<SDNode opc, code xformFunction> { 445 SDNode Opcode = opc; 446 code XFormFunction = xformFunction; 447} 448 449def NOOP_SDNodeXForm : SDNodeXForm<imm, [{}]>; 450 451 452//===----------------------------------------------------------------------===// 453// Selection DAG Pattern Fragments. 454// 455// Pattern fragments are reusable chunks of dags that match specific things. 456// They can take arguments and have C++ predicates that control whether they 457// match. They are intended to make the patterns for common instructions more 458// compact and readable. 459// 460 461/// PatFrag - Represents a pattern fragment. This can match something on the 462/// DAG, frame a single node to multiply nested other fragments. 463/// 464class PatFrag<dag ops, dag frag, code pred = [{}], 465 SDNodeXForm xform = NOOP_SDNodeXForm> { 466 dag Operands = ops; 467 dag Fragment = frag; 468 code Predicate = pred; 469 SDNodeXForm OperandTransform = xform; 470} 471 472// PatLeaf's are pattern fragments that have no operands. This is just a helper 473// to define immediates and other common things concisely. 474class PatLeaf<dag frag, code pred = [{}], SDNodeXForm xform = NOOP_SDNodeXForm> 475 : PatFrag<(ops), frag, pred, xform>; 476 477// Leaf fragments. 478 479def vtInt : PatLeaf<(vt), [{ return N->getVT().isInteger(); }]>; 480def vtFP : PatLeaf<(vt), [{ return N->getVT().isFloatingPoint(); }]>; 481 482def immAllOnesV: PatLeaf<(build_vector), [{ 483 return ISD::isBuildVectorAllOnes(N); 484}]>; 485def immAllOnesV_bc: PatLeaf<(bitconvert), [{ 486 return ISD::isBuildVectorAllOnes(N); 487}]>; 488def immAllZerosV: PatLeaf<(build_vector), [{ 489 return ISD::isBuildVectorAllZeros(N); 490}]>; 491def immAllZerosV_bc: PatLeaf<(bitconvert), [{ 492 return ISD::isBuildVectorAllZeros(N); 493}]>; 494 495 496 497// Other helper fragments. 498def not : PatFrag<(ops node:$in), (xor node:$in, -1)>; 499def vnot : PatFrag<(ops node:$in), (xor node:$in, immAllOnesV)>; 500def vnot_conv : PatFrag<(ops node:$in), (xor node:$in, immAllOnesV_bc)>; 501def ineg : PatFrag<(ops node:$in), (sub 0, node:$in)>; 502 503// load fragments. 504def unindexedload : PatFrag<(ops node:$ptr), (ld node:$ptr), [{ 505 return cast<LoadSDNode>(N)->getAddressingMode() == ISD::UNINDEXED; 506}]>; 507def load : PatFrag<(ops node:$ptr), (unindexedload node:$ptr), [{ 508 return cast<LoadSDNode>(N)->getExtensionType() == ISD::NON_EXTLOAD; 509}]>; 510 511// extending load fragments. 512def extload : PatFrag<(ops node:$ptr), (unindexedload node:$ptr), [{ 513 return cast<LoadSDNode>(N)->getExtensionType() == ISD::EXTLOAD; 514}]>; 515def sextload : PatFrag<(ops node:$ptr), (unindexedload node:$ptr), [{ 516 return cast<LoadSDNode>(N)->getExtensionType() == ISD::SEXTLOAD; 517}]>; 518def zextload : PatFrag<(ops node:$ptr), (unindexedload node:$ptr), [{ 519 return cast<LoadSDNode>(N)->getExtensionType() == ISD::ZEXTLOAD; 520}]>; 521 522def extloadi1 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{ 523 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i1; 524}]>; 525def extloadi8 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{ 526 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i8; 527}]>; 528def extloadi16 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{ 529 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i16; 530}]>; 531def extloadi32 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{ 532 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i32; 533}]>; 534def extloadf32 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{ 535 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::f32; 536}]>; 537def extloadf64 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{ 538 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::f64; 539}]>; 540 541def sextloadi1 : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{ 542 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i1; 543}]>; 544def sextloadi8 : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{ 545 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i8; 546}]>; 547def sextloadi16 : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{ 548 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i16; 549}]>; 550def sextloadi32 : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{ 551 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i32; 552}]>; 553 554def zextloadi1 : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{ 555 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i1; 556}]>; 557def zextloadi8 : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{ 558 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i8; 559}]>; 560def zextloadi16 : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{ 561 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i16; 562}]>; 563def zextloadi32 : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{ 564 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i32; 565}]>; 566 567// store fragments. 568def unindexedstore : PatFrag<(ops node:$val, node:$ptr), 569 (st node:$val, node:$ptr), [{ 570 return cast<StoreSDNode>(N)->getAddressingMode() == ISD::UNINDEXED; 571}]>; 572def store : PatFrag<(ops node:$val, node:$ptr), 573 (unindexedstore node:$val, node:$ptr), [{ 574 return !cast<StoreSDNode>(N)->isTruncatingStore(); 575}]>; 576 577// truncstore fragments. 578def truncstore : PatFrag<(ops node:$val, node:$ptr), 579 (unindexedstore node:$val, node:$ptr), [{ 580 return cast<StoreSDNode>(N)->isTruncatingStore(); 581}]>; 582def truncstorei8 : PatFrag<(ops node:$val, node:$ptr), 583 (truncstore node:$val, node:$ptr), [{ 584 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i8; 585}]>; 586def truncstorei16 : PatFrag<(ops node:$val, node:$ptr), 587 (truncstore node:$val, node:$ptr), [{ 588 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i16; 589}]>; 590def truncstorei32 : PatFrag<(ops node:$val, node:$ptr), 591 (truncstore node:$val, node:$ptr), [{ 592 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i32; 593}]>; 594def truncstoref32 : PatFrag<(ops node:$val, node:$ptr), 595 (truncstore node:$val, node:$ptr), [{ 596 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::f32; 597}]>; 598def truncstoref64 : PatFrag<(ops node:$val, node:$ptr), 599 (truncstore node:$val, node:$ptr), [{ 600 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::f64; 601}]>; 602 603// indexed store fragments. 604def istore : PatFrag<(ops node:$val, node:$base, node:$offset), 605 (ist node:$val, node:$base, node:$offset), [{ 606 return !cast<StoreSDNode>(N)->isTruncatingStore(); 607}]>; 608 609def pre_store : PatFrag<(ops node:$val, node:$base, node:$offset), 610 (istore node:$val, node:$base, node:$offset), [{ 611 ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode(); 612 return AM == ISD::PRE_INC || AM == ISD::PRE_DEC; 613}]>; 614 615def itruncstore : PatFrag<(ops node:$val, node:$base, node:$offset), 616 (ist node:$val, node:$base, node:$offset), [{ 617 return cast<StoreSDNode>(N)->isTruncatingStore(); 618}]>; 619def pre_truncst : PatFrag<(ops node:$val, node:$base, node:$offset), 620 (itruncstore node:$val, node:$base, node:$offset), [{ 621 ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode(); 622 return AM == ISD::PRE_INC || AM == ISD::PRE_DEC; 623}]>; 624def pre_truncsti1 : PatFrag<(ops node:$val, node:$base, node:$offset), 625 (pre_truncst node:$val, node:$base, node:$offset), [{ 626 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i1; 627}]>; 628def pre_truncsti8 : PatFrag<(ops node:$val, node:$base, node:$offset), 629 (pre_truncst node:$val, node:$base, node:$offset), [{ 630 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i8; 631}]>; 632def pre_truncsti16 : PatFrag<(ops node:$val, node:$base, node:$offset), 633 (pre_truncst node:$val, node:$base, node:$offset), [{ 634 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i16; 635}]>; 636def pre_truncsti32 : PatFrag<(ops node:$val, node:$base, node:$offset), 637 (pre_truncst node:$val, node:$base, node:$offset), [{ 638 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i32; 639}]>; 640def pre_truncstf32 : PatFrag<(ops node:$val, node:$base, node:$offset), 641 (pre_truncst node:$val, node:$base, node:$offset), [{ 642 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::f32; 643}]>; 644 645def post_store : PatFrag<(ops node:$val, node:$ptr, node:$offset), 646 (istore node:$val, node:$ptr, node:$offset), [{ 647 ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode(); 648 return AM == ISD::POST_INC || AM == ISD::POST_DEC; 649}]>; 650 651def post_truncst : PatFrag<(ops node:$val, node:$base, node:$offset), 652 (itruncstore node:$val, node:$base, node:$offset), [{ 653 ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode(); 654 return AM == ISD::POST_INC || AM == ISD::POST_DEC; 655}]>; 656def post_truncsti1 : PatFrag<(ops node:$val, node:$base, node:$offset), 657 (post_truncst node:$val, node:$base, node:$offset), [{ 658 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i1; 659}]>; 660def post_truncsti8 : PatFrag<(ops node:$val, node:$base, node:$offset), 661 (post_truncst node:$val, node:$base, node:$offset), [{ 662 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i8; 663}]>; 664def post_truncsti16 : PatFrag<(ops node:$val, node:$base, node:$offset), 665 (post_truncst node:$val, node:$base, node:$offset), [{ 666 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i16; 667}]>; 668def post_truncsti32 : PatFrag<(ops node:$val, node:$base, node:$offset), 669 (post_truncst node:$val, node:$base, node:$offset), [{ 670 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i32; 671}]>; 672def post_truncstf32 : PatFrag<(ops node:$val, node:$base, node:$offset), 673 (post_truncst node:$val, node:$base, node:$offset), [{ 674 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::f32; 675}]>; 676 677// setcc convenience fragments. 678def setoeq : PatFrag<(ops node:$lhs, node:$rhs), 679 (setcc node:$lhs, node:$rhs, SETOEQ)>; 680def setogt : PatFrag<(ops node:$lhs, node:$rhs), 681 (setcc node:$lhs, node:$rhs, SETOGT)>; 682def setoge : PatFrag<(ops node:$lhs, node:$rhs), 683 (setcc node:$lhs, node:$rhs, SETOGE)>; 684def setolt : PatFrag<(ops node:$lhs, node:$rhs), 685 (setcc node:$lhs, node:$rhs, SETOLT)>; 686def setole : PatFrag<(ops node:$lhs, node:$rhs), 687 (setcc node:$lhs, node:$rhs, SETOLE)>; 688def setone : PatFrag<(ops node:$lhs, node:$rhs), 689 (setcc node:$lhs, node:$rhs, SETONE)>; 690def seto : PatFrag<(ops node:$lhs, node:$rhs), 691 (setcc node:$lhs, node:$rhs, SETO)>; 692def setuo : PatFrag<(ops node:$lhs, node:$rhs), 693 (setcc node:$lhs, node:$rhs, SETUO)>; 694def setueq : PatFrag<(ops node:$lhs, node:$rhs), 695 (setcc node:$lhs, node:$rhs, SETUEQ)>; 696def setugt : PatFrag<(ops node:$lhs, node:$rhs), 697 (setcc node:$lhs, node:$rhs, SETUGT)>; 698def setuge : PatFrag<(ops node:$lhs, node:$rhs), 699 (setcc node:$lhs, node:$rhs, SETUGE)>; 700def setult : PatFrag<(ops node:$lhs, node:$rhs), 701 (setcc node:$lhs, node:$rhs, SETULT)>; 702def setule : PatFrag<(ops node:$lhs, node:$rhs), 703 (setcc node:$lhs, node:$rhs, SETULE)>; 704def setune : PatFrag<(ops node:$lhs, node:$rhs), 705 (setcc node:$lhs, node:$rhs, SETUNE)>; 706def seteq : PatFrag<(ops node:$lhs, node:$rhs), 707 (setcc node:$lhs, node:$rhs, SETEQ)>; 708def setgt : PatFrag<(ops node:$lhs, node:$rhs), 709 (setcc node:$lhs, node:$rhs, SETGT)>; 710def setge : PatFrag<(ops node:$lhs, node:$rhs), 711 (setcc node:$lhs, node:$rhs, SETGE)>; 712def setlt : PatFrag<(ops node:$lhs, node:$rhs), 713 (setcc node:$lhs, node:$rhs, SETLT)>; 714def setle : PatFrag<(ops node:$lhs, node:$rhs), 715 (setcc node:$lhs, node:$rhs, SETLE)>; 716def setne : PatFrag<(ops node:$lhs, node:$rhs), 717 (setcc node:$lhs, node:$rhs, SETNE)>; 718 719def atomic_cmp_swap_8 : 720 PatFrag<(ops node:$ptr, node:$cmp, node:$swap), 721 (atomic_cmp_swap node:$ptr, node:$cmp, node:$swap), [{ 722 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i8; 723}]>; 724def atomic_cmp_swap_16 : 725 PatFrag<(ops node:$ptr, node:$cmp, node:$swap), 726 (atomic_cmp_swap node:$ptr, node:$cmp, node:$swap), [{ 727 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i16; 728}]>; 729def atomic_cmp_swap_32 : 730 PatFrag<(ops node:$ptr, node:$cmp, node:$swap), 731 (atomic_cmp_swap node:$ptr, node:$cmp, node:$swap), [{ 732 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i32; 733}]>; 734def atomic_cmp_swap_64 : 735 PatFrag<(ops node:$ptr, node:$cmp, node:$swap), 736 (atomic_cmp_swap node:$ptr, node:$cmp, node:$swap), [{ 737 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i64; 738}]>; 739 740multiclass binary_atomic_op<SDNode atomic_op> { 741 def _8 : PatFrag<(ops node:$ptr, node:$val), 742 (atomic_op node:$ptr, node:$val), [{ 743 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i8; 744 }]>; 745 def _16 : PatFrag<(ops node:$ptr, node:$val), 746 (atomic_op node:$ptr, node:$val), [{ 747 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i16; 748 }]>; 749 def _32 : PatFrag<(ops node:$ptr, node:$val), 750 (atomic_op node:$ptr, node:$val), [{ 751 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i32; 752 }]>; 753 def _64 : PatFrag<(ops node:$ptr, node:$val), 754 (atomic_op node:$ptr, node:$val), [{ 755 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i64; 756 }]>; 757} 758 759defm atomic_load_add : binary_atomic_op<atomic_load_add>; 760defm atomic_swap : binary_atomic_op<atomic_swap>; 761defm atomic_load_sub : binary_atomic_op<atomic_load_sub>; 762defm atomic_load_and : binary_atomic_op<atomic_load_and>; 763defm atomic_load_or : binary_atomic_op<atomic_load_or>; 764defm atomic_load_xor : binary_atomic_op<atomic_load_xor>; 765defm atomic_load_nand : binary_atomic_op<atomic_load_nand>; 766defm atomic_load_min : binary_atomic_op<atomic_load_min>; 767defm atomic_load_max : binary_atomic_op<atomic_load_max>; 768defm atomic_load_umin : binary_atomic_op<atomic_load_umin>; 769defm atomic_load_umax : binary_atomic_op<atomic_load_umax>; 770 771//===----------------------------------------------------------------------===// 772// Selection DAG CONVERT_RNDSAT patterns 773 774def cvtff : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat), 775 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{ 776 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_FF; 777 }]>; 778 779def cvtss : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat), 780 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{ 781 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_SS; 782 }]>; 783 784def cvtsu : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat), 785 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{ 786 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_SU; 787 }]>; 788 789def cvtus : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat), 790 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{ 791 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_US; 792 }]>; 793 794def cvtuu : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat), 795 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{ 796 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_UU; 797 }]>; 798 799def cvtsf : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat), 800 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{ 801 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_SF; 802 }]>; 803 804def cvtuf : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat), 805 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{ 806 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_UF; 807 }]>; 808 809def cvtfs : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat), 810 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{ 811 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_FS; 812 }]>; 813 814def cvtfu : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat), 815 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{ 816 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_FU; 817 }]>; 818 819//===----------------------------------------------------------------------===// 820// Selection DAG Pattern Support. 821// 822// Patterns are what are actually matched against the target-flavored 823// instruction selection DAG. Instructions defined by the target implicitly 824// define patterns in most cases, but patterns can also be explicitly added when 825// an operation is defined by a sequence of instructions (e.g. loading a large 826// immediate value on RISC targets that do not support immediates as large as 827// their GPRs). 828// 829 830class Pattern<dag patternToMatch, list<dag> resultInstrs> { 831 dag PatternToMatch = patternToMatch; 832 list<dag> ResultInstrs = resultInstrs; 833 list<Predicate> Predicates = []; // See class Instruction in Target.td. 834 int AddedComplexity = 0; // See class Instruction in Target.td. 835} 836 837// Pat - A simple (but common) form of a pattern, which produces a simple result 838// not needing a full list. 839class Pat<dag pattern, dag result> : Pattern<pattern, [result]>; 840 841//===----------------------------------------------------------------------===// 842// Complex pattern definitions. 843// 844 845// Complex patterns, e.g. X86 addressing mode, requires pattern matching code 846// in C++. NumOperands is the number of operands returned by the select function; 847// SelectFunc is the name of the function used to pattern match the max. pattern; 848// RootNodes are the list of possible root nodes of the sub-dags to match. 849// e.g. X86 addressing mode - def addr : ComplexPattern<4, "SelectAddr", [add]>; 850// 851class ComplexPattern<ValueType ty, int numops, string fn, 852 list<SDNode> roots = [], list<SDNodeProperty> props = []> { 853 ValueType Ty = ty; 854 int NumOperands = numops; 855 string SelectFunc = fn; 856 list<SDNode> RootNodes = roots; 857 list<SDNodeProperty> Properties = props; 858} 859