1336809Sdim//===--- AMDHSAKernelDescriptor.h -----------------------------*- C++ -*---===// 2336809Sdim// 3353358Sdim// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4353358Sdim// See https://llvm.org/LICENSE.txt for license information. 5353358Sdim// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6336809Sdim// 7336809Sdim//===----------------------------------------------------------------------===// 8336809Sdim// 9336809Sdim/// \file 10336809Sdim/// AMDHSA kernel descriptor definitions. For more information, visit 11336809Sdim/// https://llvm.org/docs/AMDGPUUsage.html#kernel-descriptor 12336809Sdim// 13336809Sdim//===----------------------------------------------------------------------===// 14336809Sdim 15336809Sdim#ifndef LLVM_SUPPORT_AMDHSAKERNELDESCRIPTOR_H 16336809Sdim#define LLVM_SUPPORT_AMDHSAKERNELDESCRIPTOR_H 17336809Sdim 18336809Sdim#include <cstddef> 19336809Sdim#include <cstdint> 20336809Sdim 21336809Sdim// Gets offset of specified member in specified type. 22336809Sdim#ifndef offsetof 23336809Sdim#define offsetof(TYPE, MEMBER) ((size_t)&((TYPE*)0)->MEMBER) 24336809Sdim#endif // offsetof 25336809Sdim 26336809Sdim// Creates enumeration entries used for packing bits into integers. Enumeration 27336809Sdim// entries include bit shift amount, bit width, and bit mask. 28336809Sdim#ifndef AMDHSA_BITS_ENUM_ENTRY 29336809Sdim#define AMDHSA_BITS_ENUM_ENTRY(NAME, SHIFT, WIDTH) \ 30336809Sdim NAME ## _SHIFT = (SHIFT), \ 31336809Sdim NAME ## _WIDTH = (WIDTH), \ 32336809Sdim NAME = (((1 << (WIDTH)) - 1) << (SHIFT)) 33336809Sdim#endif // AMDHSA_BITS_ENUM_ENTRY 34336809Sdim 35336809Sdim// Gets bits for specified bit mask from specified source. 36336809Sdim#ifndef AMDHSA_BITS_GET 37336809Sdim#define AMDHSA_BITS_GET(SRC, MSK) ((SRC & MSK) >> MSK ## _SHIFT) 38336809Sdim#endif // AMDHSA_BITS_GET 39336809Sdim 40336809Sdim// Sets bits for specified bit mask in specified destination. 41336809Sdim#ifndef AMDHSA_BITS_SET 42336809Sdim#define AMDHSA_BITS_SET(DST, MSK, VAL) \ 43336809Sdim DST &= ~MSK; \ 44336809Sdim DST |= ((VAL << MSK ## _SHIFT) & MSK) 45336809Sdim#endif // AMDHSA_BITS_SET 46336809Sdim 47336809Sdimnamespace llvm { 48336809Sdimnamespace amdhsa { 49336809Sdim 50336809Sdim// Floating point rounding modes. Must match hardware definition. 51336809Sdimenum : uint8_t { 52336809Sdim FLOAT_ROUND_MODE_NEAR_EVEN = 0, 53336809Sdim FLOAT_ROUND_MODE_PLUS_INFINITY = 1, 54336809Sdim FLOAT_ROUND_MODE_MINUS_INFINITY = 2, 55336809Sdim FLOAT_ROUND_MODE_ZERO = 3, 56336809Sdim}; 57336809Sdim 58336809Sdim// Floating point denorm modes. Must match hardware definition. 59336809Sdimenum : uint8_t { 60336809Sdim FLOAT_DENORM_MODE_FLUSH_SRC_DST = 0, 61336809Sdim FLOAT_DENORM_MODE_FLUSH_DST = 1, 62336809Sdim FLOAT_DENORM_MODE_FLUSH_SRC = 2, 63336809Sdim FLOAT_DENORM_MODE_FLUSH_NONE = 3, 64336809Sdim}; 65336809Sdim 66336809Sdim// System VGPR workitem IDs. Must match hardware definition. 67336809Sdimenum : uint8_t { 68336809Sdim SYSTEM_VGPR_WORKITEM_ID_X = 0, 69336809Sdim SYSTEM_VGPR_WORKITEM_ID_X_Y = 1, 70336809Sdim SYSTEM_VGPR_WORKITEM_ID_X_Y_Z = 2, 71336809Sdim SYSTEM_VGPR_WORKITEM_ID_UNDEFINED = 3, 72336809Sdim}; 73336809Sdim 74336809Sdim// Compute program resource register 1. Must match hardware definition. 75336809Sdim#define COMPUTE_PGM_RSRC1(NAME, SHIFT, WIDTH) \ 76336809Sdim AMDHSA_BITS_ENUM_ENTRY(COMPUTE_PGM_RSRC1_ ## NAME, SHIFT, WIDTH) 77336809Sdimenum : int32_t { 78336809Sdim COMPUTE_PGM_RSRC1(GRANULATED_WORKITEM_VGPR_COUNT, 0, 6), 79336809Sdim COMPUTE_PGM_RSRC1(GRANULATED_WAVEFRONT_SGPR_COUNT, 6, 4), 80336809Sdim COMPUTE_PGM_RSRC1(PRIORITY, 10, 2), 81336809Sdim COMPUTE_PGM_RSRC1(FLOAT_ROUND_MODE_32, 12, 2), 82336809Sdim COMPUTE_PGM_RSRC1(FLOAT_ROUND_MODE_16_64, 14, 2), 83336809Sdim COMPUTE_PGM_RSRC1(FLOAT_DENORM_MODE_32, 16, 2), 84336809Sdim COMPUTE_PGM_RSRC1(FLOAT_DENORM_MODE_16_64, 18, 2), 85336809Sdim COMPUTE_PGM_RSRC1(PRIV, 20, 1), 86336809Sdim COMPUTE_PGM_RSRC1(ENABLE_DX10_CLAMP, 21, 1), 87336809Sdim COMPUTE_PGM_RSRC1(DEBUG_MODE, 22, 1), 88336809Sdim COMPUTE_PGM_RSRC1(ENABLE_IEEE_MODE, 23, 1), 89336809Sdim COMPUTE_PGM_RSRC1(BULKY, 24, 1), 90336809Sdim COMPUTE_PGM_RSRC1(CDBG_USER, 25, 1), 91353358Sdim COMPUTE_PGM_RSRC1(FP16_OVFL, 26, 1), // GFX9+ 92353358Sdim COMPUTE_PGM_RSRC1(RESERVED0, 27, 2), 93353358Sdim COMPUTE_PGM_RSRC1(WGP_MODE, 29, 1), // GFX10+ 94353358Sdim COMPUTE_PGM_RSRC1(MEM_ORDERED, 30, 1), // GFX10+ 95353358Sdim COMPUTE_PGM_RSRC1(FWD_PROGRESS, 31, 1), // GFX10+ 96336809Sdim}; 97336809Sdim#undef COMPUTE_PGM_RSRC1 98336809Sdim 99336809Sdim// Compute program resource register 2. Must match hardware definition. 100336809Sdim#define COMPUTE_PGM_RSRC2(NAME, SHIFT, WIDTH) \ 101336809Sdim AMDHSA_BITS_ENUM_ENTRY(COMPUTE_PGM_RSRC2_ ## NAME, SHIFT, WIDTH) 102336809Sdimenum : int32_t { 103336809Sdim COMPUTE_PGM_RSRC2(ENABLE_SGPR_PRIVATE_SEGMENT_WAVEFRONT_OFFSET, 0, 1), 104336809Sdim COMPUTE_PGM_RSRC2(USER_SGPR_COUNT, 1, 5), 105336809Sdim COMPUTE_PGM_RSRC2(ENABLE_TRAP_HANDLER, 6, 1), 106336809Sdim COMPUTE_PGM_RSRC2(ENABLE_SGPR_WORKGROUP_ID_X, 7, 1), 107336809Sdim COMPUTE_PGM_RSRC2(ENABLE_SGPR_WORKGROUP_ID_Y, 8, 1), 108336809Sdim COMPUTE_PGM_RSRC2(ENABLE_SGPR_WORKGROUP_ID_Z, 9, 1), 109336809Sdim COMPUTE_PGM_RSRC2(ENABLE_SGPR_WORKGROUP_INFO, 10, 1), 110336809Sdim COMPUTE_PGM_RSRC2(ENABLE_VGPR_WORKITEM_ID, 11, 2), 111336809Sdim COMPUTE_PGM_RSRC2(ENABLE_EXCEPTION_ADDRESS_WATCH, 13, 1), 112336809Sdim COMPUTE_PGM_RSRC2(ENABLE_EXCEPTION_MEMORY, 14, 1), 113336809Sdim COMPUTE_PGM_RSRC2(GRANULATED_LDS_SIZE, 15, 9), 114336809Sdim COMPUTE_PGM_RSRC2(ENABLE_EXCEPTION_IEEE_754_FP_INVALID_OPERATION, 24, 1), 115336809Sdim COMPUTE_PGM_RSRC2(ENABLE_EXCEPTION_FP_DENORMAL_SOURCE, 25, 1), 116336809Sdim COMPUTE_PGM_RSRC2(ENABLE_EXCEPTION_IEEE_754_FP_DIVISION_BY_ZERO, 26, 1), 117336809Sdim COMPUTE_PGM_RSRC2(ENABLE_EXCEPTION_IEEE_754_FP_OVERFLOW, 27, 1), 118336809Sdim COMPUTE_PGM_RSRC2(ENABLE_EXCEPTION_IEEE_754_FP_UNDERFLOW, 28, 1), 119336809Sdim COMPUTE_PGM_RSRC2(ENABLE_EXCEPTION_IEEE_754_FP_INEXACT, 29, 1), 120336809Sdim COMPUTE_PGM_RSRC2(ENABLE_EXCEPTION_INT_DIVIDE_BY_ZERO, 30, 1), 121336809Sdim COMPUTE_PGM_RSRC2(RESERVED0, 31, 1), 122336809Sdim}; 123336809Sdim#undef COMPUTE_PGM_RSRC2 124336809Sdim 125353358Sdim// Compute program resource register 3. Must match hardware definition. 126353358Sdim#define COMPUTE_PGM_RSRC3(NAME, SHIFT, WIDTH) \ 127353358Sdim AMDHSA_BITS_ENUM_ENTRY(COMPUTE_PGM_RSRC3_ ## NAME, SHIFT, WIDTH) 128353358Sdimenum : int32_t { 129353358Sdim COMPUTE_PGM_RSRC3(SHARED_VGPR_COUNT, 0, 4), // GFX10+ 130353358Sdim COMPUTE_PGM_RSRC3(RESERVED0, 4, 28), 131353358Sdim}; 132353358Sdim#undef COMPUTE_PGM_RSRC3 133353358Sdim 134336809Sdim// Kernel code properties. Must be kept backwards compatible. 135336809Sdim#define KERNEL_CODE_PROPERTY(NAME, SHIFT, WIDTH) \ 136336809Sdim AMDHSA_BITS_ENUM_ENTRY(KERNEL_CODE_PROPERTY_ ## NAME, SHIFT, WIDTH) 137336809Sdimenum : int32_t { 138336809Sdim KERNEL_CODE_PROPERTY(ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER, 0, 1), 139336809Sdim KERNEL_CODE_PROPERTY(ENABLE_SGPR_DISPATCH_PTR, 1, 1), 140336809Sdim KERNEL_CODE_PROPERTY(ENABLE_SGPR_QUEUE_PTR, 2, 1), 141336809Sdim KERNEL_CODE_PROPERTY(ENABLE_SGPR_KERNARG_SEGMENT_PTR, 3, 1), 142336809Sdim KERNEL_CODE_PROPERTY(ENABLE_SGPR_DISPATCH_ID, 4, 1), 143336809Sdim KERNEL_CODE_PROPERTY(ENABLE_SGPR_FLAT_SCRATCH_INIT, 5, 1), 144336809Sdim KERNEL_CODE_PROPERTY(ENABLE_SGPR_PRIVATE_SEGMENT_SIZE, 6, 1), 145353358Sdim KERNEL_CODE_PROPERTY(RESERVED0, 7, 3), 146353358Sdim KERNEL_CODE_PROPERTY(ENABLE_WAVEFRONT_SIZE32, 10, 1), // GFX10+ 147353358Sdim KERNEL_CODE_PROPERTY(RESERVED1, 11, 5), 148336809Sdim}; 149336809Sdim#undef KERNEL_CODE_PROPERTY 150336809Sdim 151336809Sdim// Kernel descriptor. Must be kept backwards compatible. 152336809Sdimstruct kernel_descriptor_t { 153336809Sdim uint32_t group_segment_fixed_size; 154336809Sdim uint32_t private_segment_fixed_size; 155336809Sdim uint8_t reserved0[8]; 156336809Sdim int64_t kernel_code_entry_byte_offset; 157353358Sdim uint8_t reserved1[20]; 158353358Sdim uint32_t compute_pgm_rsrc3; // GFX10+ 159336809Sdim uint32_t compute_pgm_rsrc1; 160336809Sdim uint32_t compute_pgm_rsrc2; 161336809Sdim uint16_t kernel_code_properties; 162336809Sdim uint8_t reserved2[6]; 163336809Sdim}; 164336809Sdim 165336809Sdimstatic_assert( 166336809Sdim sizeof(kernel_descriptor_t) == 64, 167336809Sdim "invalid size for kernel_descriptor_t"); 168336809Sdimstatic_assert( 169336809Sdim offsetof(kernel_descriptor_t, group_segment_fixed_size) == 0, 170336809Sdim "invalid offset for group_segment_fixed_size"); 171336809Sdimstatic_assert( 172336809Sdim offsetof(kernel_descriptor_t, private_segment_fixed_size) == 4, 173336809Sdim "invalid offset for private_segment_fixed_size"); 174336809Sdimstatic_assert( 175336809Sdim offsetof(kernel_descriptor_t, reserved0) == 8, 176336809Sdim "invalid offset for reserved0"); 177336809Sdimstatic_assert( 178336809Sdim offsetof(kernel_descriptor_t, kernel_code_entry_byte_offset) == 16, 179336809Sdim "invalid offset for kernel_code_entry_byte_offset"); 180336809Sdimstatic_assert( 181336809Sdim offsetof(kernel_descriptor_t, reserved1) == 24, 182336809Sdim "invalid offset for reserved1"); 183336809Sdimstatic_assert( 184353358Sdim offsetof(kernel_descriptor_t, compute_pgm_rsrc3) == 44, 185353358Sdim "invalid offset for compute_pgm_rsrc3"); 186353358Sdimstatic_assert( 187336809Sdim offsetof(kernel_descriptor_t, compute_pgm_rsrc1) == 48, 188336809Sdim "invalid offset for compute_pgm_rsrc1"); 189336809Sdimstatic_assert( 190336809Sdim offsetof(kernel_descriptor_t, compute_pgm_rsrc2) == 52, 191336809Sdim "invalid offset for compute_pgm_rsrc2"); 192336809Sdimstatic_assert( 193336809Sdim offsetof(kernel_descriptor_t, kernel_code_properties) == 56, 194336809Sdim "invalid offset for kernel_code_properties"); 195336809Sdimstatic_assert( 196336809Sdim offsetof(kernel_descriptor_t, reserved2) == 58, 197336809Sdim "invalid offset for reserved2"); 198336809Sdim 199336809Sdim} // end namespace amdhsa 200336809Sdim} // end namespace llvm 201336809Sdim 202336809Sdim#endif // LLVM_SUPPORT_AMDHSAKERNELDESCRIPTOR_H 203