LiveRegUnits.h revision 360784 
1//===- llvm/CodeGen/LiveRegUnits.h - Register Unit Set ----------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9/// \file
10/// A set of register units. It is intended for register liveness tracking.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef LLVM_CODEGEN_LIVEREGUNITS_H
15#define LLVM_CODEGEN_LIVEREGUNITS_H
16
17#include "llvm/ADT/BitVector.h"
18#include "llvm/CodeGen/MachineRegisterInfo.h"
19#include "llvm/CodeGen/TargetRegisterInfo.h"
20#include "llvm/MC/LaneBitmask.h"
21#include "llvm/MC/MCRegisterInfo.h"
22#include <cstdint>
23
24namespace llvm {
25
26class MachineInstr;
27class MachineBasicBlock;
28
29/// A set of register units used to track register liveness.
30class LiveRegUnits {
31  const TargetRegisterInfo *TRI = nullptr;
32  BitVector Units;
33
34public:
35  /// Constructs a new empty LiveRegUnits set.
36  LiveRegUnits() = default;
37
38  /// Constructs and initialize an empty LiveRegUnits set.
39  LiveRegUnits(const TargetRegisterInfo &TRI) {
40    init(TRI);
41  }
42
43  /// For a machine instruction \p MI, adds all register units used in
44  /// \p UsedRegUnits and defined or clobbered in \p ModifiedRegUnits. This is
45  /// useful when walking over a range of instructions to track registers
46  /// used or defined seperately.
47  static void accumulateUsedDefed(const MachineInstr &MI,
48                                  LiveRegUnits &ModifiedRegUnits,
49                                  LiveRegUnits &UsedRegUnits,
50                                  const TargetRegisterInfo *TRI) {
51    for (ConstMIBundleOperands O(MI); O.isValid(); ++O) {
52      if (O->isRegMask())
53        ModifiedRegUnits.addRegsInMask(O->getRegMask());
54      if (!O->isReg())
55        continue;
56      Register Reg = O->getReg();
57      if (!Reg.isPhysical())
58        continue;
59      if (O->isDef()) {
60        // Some architectures (e.g. AArch64 XZR/WZR) have registers that are
61        // constant and may be used as destinations to indicate the generated
62        // value is discarded. No need to track such case as a def.
63        if (!TRI->isConstantPhysReg(Reg))
64          ModifiedRegUnits.addReg(Reg);
65      } else {
66        assert(O->isUse() && "Reg operand not a def and not a use");
67        UsedRegUnits.addReg(Reg);
68      }
69    }
70    return;
71  }
72
73  /// Initialize and clear the set.
74  void init(const TargetRegisterInfo &TRI) {
75    this->TRI = &TRI;
76    Units.reset();
77    Units.resize(TRI.getNumRegUnits());
78  }
79
80  /// Clears the set.
81  void clear() { Units.reset(); }
82
83  /// Returns true if the set is empty.
84  bool empty() const { return Units.none(); }
85
86  /// Adds register units covered by physical register \p Reg.
87  void addReg(MCPhysReg Reg) {
88    for (MCRegUnitIterator Unit(Reg, TRI); Unit.isValid(); ++Unit)
89      Units.set(*Unit);
90  }
91
92  /// Adds register units covered by physical register \p Reg that are
93  /// part of the lanemask \p Mask.
94  void addRegMasked(MCPhysReg Reg, LaneBitmask Mask) {
95    for (MCRegUnitMaskIterator Unit(Reg, TRI); Unit.isValid(); ++Unit) {
96      LaneBitmask UnitMask = (*Unit).second;
97      if (UnitMask.none() || (UnitMask & Mask).any())
98        Units.set((*Unit).first);
99    }
100  }
101
102  /// Removes all register units covered by physical register \p Reg.
103  void removeReg(MCPhysReg Reg) {
104    for (MCRegUnitIterator Unit(Reg, TRI); Unit.isValid(); ++Unit)
105      Units.reset(*Unit);
106  }
107
108  /// Removes register units not preserved by the regmask \p RegMask.
109  /// The regmask has the same format as the one in the RegMask machine operand.
110  void removeRegsNotPreserved(const uint32_t *RegMask);
111
112  /// Adds register units not preserved by the regmask \p RegMask.
113  /// The regmask has the same format as the one in the RegMask machine operand.
114  void addRegsInMask(const uint32_t *RegMask);
115
116  /// Returns true if no part of physical register \p Reg is live.
117  bool available(MCPhysReg Reg) const {
118    for (MCRegUnitIterator Unit(Reg, TRI); Unit.isValid(); ++Unit) {
119      if (Units.test(*Unit))
120        return false;
121    }
122    return true;
123  }
124
125  /// Updates liveness when stepping backwards over the instruction \p MI.
126  /// This removes all register units defined or clobbered in \p MI and then
127  /// adds the units used (as in use operands) in \p MI.
128  void stepBackward(const MachineInstr &MI);
129
130  /// Adds all register units used, defined or clobbered in \p MI.
131  /// This is useful when walking over a range of instruction to find registers
132  /// unused over the whole range.
133  void accumulate(const MachineInstr &MI);
134
135  /// Adds registers living out of block \p MBB.
136  /// Live out registers are the union of the live-in registers of the successor
137  /// blocks and pristine registers. Live out registers of the end block are the
138  /// callee saved registers.
139  void addLiveOuts(const MachineBasicBlock &MBB);
140
141  /// Adds registers living into block \p MBB.
142  void addLiveIns(const MachineBasicBlock &MBB);
143
144  /// Adds all register units marked in the bitvector \p RegUnits.
145  void addUnits(const BitVector &RegUnits) {
146    Units |= RegUnits;
147  }
148  /// Removes all register units marked in the bitvector \p RegUnits.
149  void removeUnits(const BitVector &RegUnits) {
150    Units.reset(RegUnits);
151  }
152  /// Return the internal bitvector representation of the set.
153  const BitVector &getBitVector() const {
154    return Units;
155  }
156
157private:
158  /// Adds pristine registers. Pristine registers are callee saved registers
159  /// that are unused in the function.
160  void addPristines(const MachineFunction &MF);
161};
162
163/// Returns an iterator range over all physical register and mask operands for
164/// \p MI and bundled instructions. This also skips any debug operands.
165inline iterator_range<filter_iterator<
166    ConstMIBundleOperands, std::function<bool(const MachineOperand &)>>>
167phys_regs_and_masks(const MachineInstr &MI) {
168  std::function<bool(const MachineOperand &)> Pred =
169      [](const MachineOperand &MOP) {
170        return MOP.isRegMask() || (MOP.isReg() && !MOP.isDebug() &&
171                                   Register::isPhysicalRegister(MOP.getReg()));
172      };
173  return make_filter_range(const_mi_bundle_ops(MI), Pred);
174}
175
176} // end namespace llvm
177
178#endif // LLVM_CODEGEN_LIVEREGUNITS_H
179