ISDOpcodes.h revision 355940
1//===-- llvm/CodeGen/ISDOpcodes.h - CodeGen opcodes -------------*- C++ -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file declares codegen opcodes and related utilities. 10// 11//===----------------------------------------------------------------------===// 12 13#ifndef LLVM_CODEGEN_ISDOPCODES_H 14#define LLVM_CODEGEN_ISDOPCODES_H 15 16namespace llvm { 17 18/// ISD namespace - This namespace contains an enum which represents all of the 19/// SelectionDAG node types and value types. 20/// 21namespace ISD { 22 23 //===--------------------------------------------------------------------===// 24 /// ISD::NodeType enum - This enum defines the target-independent operators 25 /// for a SelectionDAG. 26 /// 27 /// Targets may also define target-dependent operator codes for SDNodes. For 28 /// example, on x86, these are the enum values in the X86ISD namespace. 29 /// Targets should aim to use target-independent operators to model their 30 /// instruction sets as much as possible, and only use target-dependent 31 /// operators when they have special requirements. 32 /// 33 /// Finally, during and after selection proper, SNodes may use special 34 /// operator codes that correspond directly with MachineInstr opcodes. These 35 /// are used to represent selected instructions. See the isMachineOpcode() 36 /// and getMachineOpcode() member functions of SDNode. 37 /// 38 enum NodeType { 39 /// DELETED_NODE - This is an illegal value that is used to catch 40 /// errors. This opcode is not a legal opcode for any node. 41 DELETED_NODE, 42 43 /// EntryToken - This is the marker used to indicate the start of a region. 44 EntryToken, 45 46 /// TokenFactor - This node takes multiple tokens as input and produces a 47 /// single token result. This is used to represent the fact that the operand 48 /// operators are independent of each other. 49 TokenFactor, 50 51 /// AssertSext, AssertZext - These nodes record if a register contains a 52 /// value that has already been zero or sign extended from a narrower type. 53 /// These nodes take two operands. The first is the node that has already 54 /// been extended, and the second is a value type node indicating the width 55 /// of the extension 56 AssertSext, AssertZext, 57 58 /// Various leaf nodes. 59 BasicBlock, VALUETYPE, CONDCODE, Register, RegisterMask, 60 Constant, ConstantFP, 61 GlobalAddress, GlobalTLSAddress, FrameIndex, 62 JumpTable, ConstantPool, ExternalSymbol, BlockAddress, 63 64 /// The address of the GOT 65 GLOBAL_OFFSET_TABLE, 66 67 /// FRAMEADDR, RETURNADDR - These nodes represent llvm.frameaddress and 68 /// llvm.returnaddress on the DAG. These nodes take one operand, the index 69 /// of the frame or return address to return. An index of zero corresponds 70 /// to the current function's frame or return address, an index of one to 71 /// the parent's frame or return address, and so on. 72 FRAMEADDR, RETURNADDR, ADDROFRETURNADDR, SPONENTRY, 73 74 /// LOCAL_RECOVER - Represents the llvm.localrecover intrinsic. 75 /// Materializes the offset from the local object pointer of another 76 /// function to a particular local object passed to llvm.localescape. The 77 /// operand is the MCSymbol label used to represent this offset, since 78 /// typically the offset is not known until after code generation of the 79 /// parent. 80 LOCAL_RECOVER, 81 82 /// READ_REGISTER, WRITE_REGISTER - This node represents llvm.register on 83 /// the DAG, which implements the named register global variables extension. 84 READ_REGISTER, 85 WRITE_REGISTER, 86 87 /// FRAME_TO_ARGS_OFFSET - This node represents offset from frame pointer to 88 /// first (possible) on-stack argument. This is needed for correct stack 89 /// adjustment during unwind. 90 FRAME_TO_ARGS_OFFSET, 91 92 /// EH_DWARF_CFA - This node represents the pointer to the DWARF Canonical 93 /// Frame Address (CFA), generally the value of the stack pointer at the 94 /// call site in the previous frame. 95 EH_DWARF_CFA, 96 97 /// OUTCHAIN = EH_RETURN(INCHAIN, OFFSET, HANDLER) - This node represents 98 /// 'eh_return' gcc dwarf builtin, which is used to return from 99 /// exception. The general meaning is: adjust stack by OFFSET and pass 100 /// execution to HANDLER. Many platform-related details also :) 101 EH_RETURN, 102 103 /// RESULT, OUTCHAIN = EH_SJLJ_SETJMP(INCHAIN, buffer) 104 /// This corresponds to the eh.sjlj.setjmp intrinsic. 105 /// It takes an input chain and a pointer to the jump buffer as inputs 106 /// and returns an outchain. 107 EH_SJLJ_SETJMP, 108 109 /// OUTCHAIN = EH_SJLJ_LONGJMP(INCHAIN, buffer) 110 /// This corresponds to the eh.sjlj.longjmp intrinsic. 111 /// It takes an input chain and a pointer to the jump buffer as inputs 112 /// and returns an outchain. 113 EH_SJLJ_LONGJMP, 114 115 /// OUTCHAIN = EH_SJLJ_SETUP_DISPATCH(INCHAIN) 116 /// The target initializes the dispatch table here. 117 EH_SJLJ_SETUP_DISPATCH, 118 119 /// TargetConstant* - Like Constant*, but the DAG does not do any folding, 120 /// simplification, or lowering of the constant. They are used for constants 121 /// which are known to fit in the immediate fields of their users, or for 122 /// carrying magic numbers which are not values which need to be 123 /// materialized in registers. 124 TargetConstant, 125 TargetConstantFP, 126 127 /// TargetGlobalAddress - Like GlobalAddress, but the DAG does no folding or 128 /// anything else with this node, and this is valid in the target-specific 129 /// dag, turning into a GlobalAddress operand. 130 TargetGlobalAddress, 131 TargetGlobalTLSAddress, 132 TargetFrameIndex, 133 TargetJumpTable, 134 TargetConstantPool, 135 TargetExternalSymbol, 136 TargetBlockAddress, 137 138 MCSymbol, 139 140 /// TargetIndex - Like a constant pool entry, but with completely 141 /// target-dependent semantics. Holds target flags, a 32-bit index, and a 142 /// 64-bit index. Targets can use this however they like. 143 TargetIndex, 144 145 /// RESULT = INTRINSIC_WO_CHAIN(INTRINSICID, arg1, arg2, ...) 146 /// This node represents a target intrinsic function with no side effects. 147 /// The first operand is the ID number of the intrinsic from the 148 /// llvm::Intrinsic namespace. The operands to the intrinsic follow. The 149 /// node returns the result of the intrinsic. 150 INTRINSIC_WO_CHAIN, 151 152 /// RESULT,OUTCHAIN = INTRINSIC_W_CHAIN(INCHAIN, INTRINSICID, arg1, ...) 153 /// This node represents a target intrinsic function with side effects that 154 /// returns a result. The first operand is a chain pointer. The second is 155 /// the ID number of the intrinsic from the llvm::Intrinsic namespace. The 156 /// operands to the intrinsic follow. The node has two results, the result 157 /// of the intrinsic and an output chain. 158 INTRINSIC_W_CHAIN, 159 160 /// OUTCHAIN = INTRINSIC_VOID(INCHAIN, INTRINSICID, arg1, arg2, ...) 161 /// This node represents a target intrinsic function with side effects that 162 /// does not return a result. The first operand is a chain pointer. The 163 /// second is the ID number of the intrinsic from the llvm::Intrinsic 164 /// namespace. The operands to the intrinsic follow. 165 INTRINSIC_VOID, 166 167 /// CopyToReg - This node has three operands: a chain, a register number to 168 /// set to this value, and a value. 169 CopyToReg, 170 171 /// CopyFromReg - This node indicates that the input value is a virtual or 172 /// physical register that is defined outside of the scope of this 173 /// SelectionDAG. The register is available from the RegisterSDNode object. 174 CopyFromReg, 175 176 /// UNDEF - An undefined node. 177 UNDEF, 178 179 /// EXTRACT_ELEMENT - This is used to get the lower or upper (determined by 180 /// a Constant, which is required to be operand #1) half of the integer or 181 /// float value specified as operand #0. This is only for use before 182 /// legalization, for values that will be broken into multiple registers. 183 EXTRACT_ELEMENT, 184 185 /// BUILD_PAIR - This is the opposite of EXTRACT_ELEMENT in some ways. 186 /// Given two values of the same integer value type, this produces a value 187 /// twice as big. Like EXTRACT_ELEMENT, this can only be used before 188 /// legalization. The lower part of the composite value should be in 189 /// element 0 and the upper part should be in element 1. 190 BUILD_PAIR, 191 192 /// MERGE_VALUES - This node takes multiple discrete operands and returns 193 /// them all as its individual results. This nodes has exactly the same 194 /// number of inputs and outputs. This node is useful for some pieces of the 195 /// code generator that want to think about a single node with multiple 196 /// results, not multiple nodes. 197 MERGE_VALUES, 198 199 /// Simple integer binary arithmetic operators. 200 ADD, SUB, MUL, SDIV, UDIV, SREM, UREM, 201 202 /// SMUL_LOHI/UMUL_LOHI - Multiply two integers of type iN, producing 203 /// a signed/unsigned value of type i[2*N], and return the full value as 204 /// two results, each of type iN. 205 SMUL_LOHI, UMUL_LOHI, 206 207 /// SDIVREM/UDIVREM - Divide two integers and produce both a quotient and 208 /// remainder result. 209 SDIVREM, UDIVREM, 210 211 /// CARRY_FALSE - This node is used when folding other nodes, 212 /// like ADDC/SUBC, which indicate the carry result is always false. 213 CARRY_FALSE, 214 215 /// Carry-setting nodes for multiple precision addition and subtraction. 216 /// These nodes take two operands of the same value type, and produce two 217 /// results. The first result is the normal add or sub result, the second 218 /// result is the carry flag result. 219 /// FIXME: These nodes are deprecated in favor of ADDCARRY and SUBCARRY. 220 /// They are kept around for now to provide a smooth transition path 221 /// toward the use of ADDCARRY/SUBCARRY and will eventually be removed. 222 ADDC, SUBC, 223 224 /// Carry-using nodes for multiple precision addition and subtraction. These 225 /// nodes take three operands: The first two are the normal lhs and rhs to 226 /// the add or sub, and the third is the input carry flag. These nodes 227 /// produce two results; the normal result of the add or sub, and the output 228 /// carry flag. These nodes both read and write a carry flag to allow them 229 /// to them to be chained together for add and sub of arbitrarily large 230 /// values. 231 ADDE, SUBE, 232 233 /// Carry-using nodes for multiple precision addition and subtraction. 234 /// These nodes take three operands: The first two are the normal lhs and 235 /// rhs to the add or sub, and the third is a boolean indicating if there 236 /// is an incoming carry. These nodes produce two results: the normal 237 /// result of the add or sub, and the output carry so they can be chained 238 /// together. The use of this opcode is preferable to adde/sube if the 239 /// target supports it, as the carry is a regular value rather than a 240 /// glue, which allows further optimisation. 241 ADDCARRY, SUBCARRY, 242 243 /// RESULT, BOOL = [SU]ADDO(LHS, RHS) - Overflow-aware nodes for addition. 244 /// These nodes take two operands: the normal LHS and RHS to the add. They 245 /// produce two results: the normal result of the add, and a boolean that 246 /// indicates if an overflow occurred (*not* a flag, because it may be store 247 /// to memory, etc.). If the type of the boolean is not i1 then the high 248 /// bits conform to getBooleanContents. 249 /// These nodes are generated from llvm.[su]add.with.overflow intrinsics. 250 SADDO, UADDO, 251 252 /// Same for subtraction. 253 SSUBO, USUBO, 254 255 /// Same for multiplication. 256 SMULO, UMULO, 257 258 /// RESULT = [US]ADDSAT(LHS, RHS) - Perform saturation addition on 2 259 /// integers with the same bit width (W). If the true value of LHS + RHS 260 /// exceeds the largest value that can be represented by W bits, the 261 /// resulting value is this maximum value. Otherwise, if this value is less 262 /// than the smallest value that can be represented by W bits, the 263 /// resulting value is this minimum value. 264 SADDSAT, UADDSAT, 265 266 /// RESULT = [US]SUBSAT(LHS, RHS) - Perform saturation subtraction on 2 267 /// integers with the same bit width (W). If the true value of LHS - RHS 268 /// exceeds the largest value that can be represented by W bits, the 269 /// resulting value is this maximum value. Otherwise, if this value is less 270 /// than the smallest value that can be represented by W bits, the 271 /// resulting value is this minimum value. 272 SSUBSAT, USUBSAT, 273 274 /// RESULT = [US]MULFIX(LHS, RHS, SCALE) - Perform fixed point multiplication on 275 /// 2 integers with the same width and scale. SCALE represents the scale of 276 /// both operands as fixed point numbers. This SCALE parameter must be a 277 /// constant integer. A scale of zero is effectively performing 278 /// multiplication on 2 integers. 279 SMULFIX, UMULFIX, 280 281 /// Same as the corresponding unsaturated fixed point instructions, but the 282 /// result is clamped between the min and max values representable by the 283 /// bits of the first 2 operands. 284 SMULFIXSAT, 285 286 /// Simple binary floating point operators. 287 FADD, FSUB, FMUL, FDIV, FREM, 288 289 /// Constrained versions of the binary floating point operators. 290 /// These will be lowered to the simple operators before final selection. 291 /// They are used to limit optimizations while the DAG is being 292 /// optimized. 293 STRICT_FADD, STRICT_FSUB, STRICT_FMUL, STRICT_FDIV, STRICT_FREM, 294 STRICT_FMA, 295 296 /// Constrained versions of libm-equivalent floating point intrinsics. 297 /// These will be lowered to the equivalent non-constrained pseudo-op 298 /// (or expanded to the equivalent library call) before final selection. 299 /// They are used to limit optimizations while the DAG is being optimized. 300 STRICT_FSQRT, STRICT_FPOW, STRICT_FPOWI, STRICT_FSIN, STRICT_FCOS, 301 STRICT_FEXP, STRICT_FEXP2, STRICT_FLOG, STRICT_FLOG10, STRICT_FLOG2, 302 STRICT_FRINT, STRICT_FNEARBYINT, STRICT_FMAXNUM, STRICT_FMINNUM, 303 STRICT_FCEIL, STRICT_FFLOOR, STRICT_FROUND, STRICT_FTRUNC, 304 305 /// X = STRICT_FP_ROUND(Y, TRUNC) - Rounding 'Y' from a larger floating 306 /// point type down to the precision of the destination VT. TRUNC is a 307 /// flag, which is always an integer that is zero or one. If TRUNC is 0, 308 /// this is a normal rounding, if it is 1, this FP_ROUND is known to not 309 /// change the value of Y. 310 /// 311 /// The TRUNC = 1 case is used in cases where we know that the value will 312 /// not be modified by the node, because Y is not using any of the extra 313 /// precision of source type. This allows certain transformations like 314 /// STRICT_FP_EXTEND(STRICT_FP_ROUND(X,1)) -> X which are not safe for 315 /// STRICT_FP_EXTEND(STRICT_FP_ROUND(X,0)) because the extra bits aren't 316 /// removed. 317 /// It is used to limit optimizations while the DAG is being optimized. 318 STRICT_FP_ROUND, 319 320 /// X = STRICT_FP_EXTEND(Y) - Extend a smaller FP type into a larger FP 321 /// type. 322 /// It is used to limit optimizations while the DAG is being optimized. 323 STRICT_FP_EXTEND, 324 325 /// FMA - Perform a * b + c with no intermediate rounding step. 326 FMA, 327 328 /// FMAD - Perform a * b + c, while getting the same result as the 329 /// separately rounded operations. 330 FMAD, 331 332 /// FCOPYSIGN(X, Y) - Return the value of X with the sign of Y. NOTE: This 333 /// DAG node does not require that X and Y have the same type, just that 334 /// they are both floating point. X and the result must have the same type. 335 /// FCOPYSIGN(f32, f64) is allowed. 336 FCOPYSIGN, 337 338 /// INT = FGETSIGN(FP) - Return the sign bit of the specified floating point 339 /// value as an integer 0/1 value. 340 FGETSIGN, 341 342 /// Returns platform specific canonical encoding of a floating point number. 343 FCANONICALIZE, 344 345 /// BUILD_VECTOR(ELT0, ELT1, ELT2, ELT3,...) - Return a vector with the 346 /// specified, possibly variable, elements. The number of elements is 347 /// required to be a power of two. The types of the operands must all be 348 /// the same and must match the vector element type, except that integer 349 /// types are allowed to be larger than the element type, in which case 350 /// the operands are implicitly truncated. 351 BUILD_VECTOR, 352 353 /// INSERT_VECTOR_ELT(VECTOR, VAL, IDX) - Returns VECTOR with the element 354 /// at IDX replaced with VAL. If the type of VAL is larger than the vector 355 /// element type then VAL is truncated before replacement. 356 INSERT_VECTOR_ELT, 357 358 /// EXTRACT_VECTOR_ELT(VECTOR, IDX) - Returns a single element from VECTOR 359 /// identified by the (potentially variable) element number IDX. If the 360 /// return type is an integer type larger than the element type of the 361 /// vector, the result is extended to the width of the return type. In 362 /// that case, the high bits are undefined. 363 EXTRACT_VECTOR_ELT, 364 365 /// CONCAT_VECTORS(VECTOR0, VECTOR1, ...) - Given a number of values of 366 /// vector type with the same length and element type, this produces a 367 /// concatenated vector result value, with length equal to the sum of the 368 /// lengths of the input vectors. 369 CONCAT_VECTORS, 370 371 /// INSERT_SUBVECTOR(VECTOR1, VECTOR2, IDX) - Returns a vector 372 /// with VECTOR2 inserted into VECTOR1 at the (potentially 373 /// variable) element number IDX, which must be a multiple of the 374 /// VECTOR2 vector length. The elements of VECTOR1 starting at 375 /// IDX are overwritten with VECTOR2. Elements IDX through 376 /// vector_length(VECTOR2) must be valid VECTOR1 indices. 377 INSERT_SUBVECTOR, 378 379 /// EXTRACT_SUBVECTOR(VECTOR, IDX) - Returns a subvector from VECTOR (an 380 /// vector value) starting with the element number IDX, which must be a 381 /// constant multiple of the result vector length. 382 EXTRACT_SUBVECTOR, 383 384 /// VECTOR_SHUFFLE(VEC1, VEC2) - Returns a vector, of the same type as 385 /// VEC1/VEC2. A VECTOR_SHUFFLE node also contains an array of constant int 386 /// values that indicate which value (or undef) each result element will 387 /// get. These constant ints are accessible through the 388 /// ShuffleVectorSDNode class. This is quite similar to the Altivec 389 /// 'vperm' instruction, except that the indices must be constants and are 390 /// in terms of the element size of VEC1/VEC2, not in terms of bytes. 391 VECTOR_SHUFFLE, 392 393 /// SCALAR_TO_VECTOR(VAL) - This represents the operation of loading a 394 /// scalar value into element 0 of the resultant vector type. The top 395 /// elements 1 to N-1 of the N-element vector are undefined. The type 396 /// of the operand must match the vector element type, except when they 397 /// are integer types. In this case the operand is allowed to be wider 398 /// than the vector element type, and is implicitly truncated to it. 399 SCALAR_TO_VECTOR, 400 401 /// MULHU/MULHS - Multiply high - Multiply two integers of type iN, 402 /// producing an unsigned/signed value of type i[2*N], then return the top 403 /// part. 404 MULHU, MULHS, 405 406 /// [US]{MIN/MAX} - Binary minimum or maximum or signed or unsigned 407 /// integers. 408 SMIN, SMAX, UMIN, UMAX, 409 410 /// Bitwise operators - logical and, logical or, logical xor. 411 AND, OR, XOR, 412 413 /// ABS - Determine the unsigned absolute value of a signed integer value of 414 /// the same bitwidth. 415 /// Note: A value of INT_MIN will return INT_MIN, no saturation or overflow 416 /// is performed. 417 ABS, 418 419 /// Shift and rotation operations. After legalization, the type of the 420 /// shift amount is known to be TLI.getShiftAmountTy(). Before legalization 421 /// the shift amount can be any type, but care must be taken to ensure it is 422 /// large enough. TLI.getShiftAmountTy() is i8 on some targets, but before 423 /// legalization, types like i1024 can occur and i8 doesn't have enough bits 424 /// to represent the shift amount. 425 /// When the 1st operand is a vector, the shift amount must be in the same 426 /// type. (TLI.getShiftAmountTy() will return the same type when the input 427 /// type is a vector.) 428 /// For rotates and funnel shifts, the shift amount is treated as an unsigned 429 /// amount modulo the element size of the first operand. 430 /// 431 /// Funnel 'double' shifts take 3 operands, 2 inputs and the shift amount. 432 /// fshl(X,Y,Z): (X << (Z % BW)) | (Y >> (BW - (Z % BW))) 433 /// fshr(X,Y,Z): (X << (BW - (Z % BW))) | (Y >> (Z % BW)) 434 SHL, SRA, SRL, ROTL, ROTR, FSHL, FSHR, 435 436 /// Byte Swap and Counting operators. 437 BSWAP, CTTZ, CTLZ, CTPOP, BITREVERSE, 438 439 /// Bit counting operators with an undefined result for zero inputs. 440 CTTZ_ZERO_UNDEF, CTLZ_ZERO_UNDEF, 441 442 /// Select(COND, TRUEVAL, FALSEVAL). If the type of the boolean COND is not 443 /// i1 then the high bits must conform to getBooleanContents. 444 SELECT, 445 446 /// Select with a vector condition (op #0) and two vector operands (ops #1 447 /// and #2), returning a vector result. All vectors have the same length. 448 /// Much like the scalar select and setcc, each bit in the condition selects 449 /// whether the corresponding result element is taken from op #1 or op #2. 450 /// At first, the VSELECT condition is of vXi1 type. Later, targets may 451 /// change the condition type in order to match the VSELECT node using a 452 /// pattern. The condition follows the BooleanContent format of the target. 453 VSELECT, 454 455 /// Select with condition operator - This selects between a true value and 456 /// a false value (ops #2 and #3) based on the boolean result of comparing 457 /// the lhs and rhs (ops #0 and #1) of a conditional expression with the 458 /// condition code in op #4, a CondCodeSDNode. 459 SELECT_CC, 460 461 /// SetCC operator - This evaluates to a true value iff the condition is 462 /// true. If the result value type is not i1 then the high bits conform 463 /// to getBooleanContents. The operands to this are the left and right 464 /// operands to compare (ops #0, and #1) and the condition code to compare 465 /// them with (op #2) as a CondCodeSDNode. If the operands are vector types 466 /// then the result type must also be a vector type. 467 SETCC, 468 469 /// Like SetCC, ops #0 and #1 are the LHS and RHS operands to compare, but 470 /// op #2 is a boolean indicating if there is an incoming carry. This 471 /// operator checks the result of "LHS - RHS - Carry", and can be used to 472 /// compare two wide integers: 473 /// (setcccarry lhshi rhshi (subcarry lhslo rhslo) cc). 474 /// Only valid for integers. 475 SETCCCARRY, 476 477 /// SHL_PARTS/SRA_PARTS/SRL_PARTS - These operators are used for expanded 478 /// integer shift operations. The operation ordering is: 479 /// [Lo,Hi] = op [LoLHS,HiLHS], Amt 480 SHL_PARTS, SRA_PARTS, SRL_PARTS, 481 482 /// Conversion operators. These are all single input single output 483 /// operations. For all of these, the result type must be strictly 484 /// wider or narrower (depending on the operation) than the source 485 /// type. 486 487 /// SIGN_EXTEND - Used for integer types, replicating the sign bit 488 /// into new bits. 489 SIGN_EXTEND, 490 491 /// ZERO_EXTEND - Used for integer types, zeroing the new bits. 492 ZERO_EXTEND, 493 494 /// ANY_EXTEND - Used for integer types. The high bits are undefined. 495 ANY_EXTEND, 496 497 /// TRUNCATE - Completely drop the high bits. 498 TRUNCATE, 499 500 /// [SU]INT_TO_FP - These operators convert integers (whose interpreted sign 501 /// depends on the first letter) to floating point. 502 SINT_TO_FP, 503 UINT_TO_FP, 504 505 /// SIGN_EXTEND_INREG - This operator atomically performs a SHL/SRA pair to 506 /// sign extend a small value in a large integer register (e.g. sign 507 /// extending the low 8 bits of a 32-bit register to fill the top 24 bits 508 /// with the 7th bit). The size of the smaller type is indicated by the 1th 509 /// operand, a ValueType node. 510 SIGN_EXTEND_INREG, 511 512 /// ANY_EXTEND_VECTOR_INREG(Vector) - This operator represents an 513 /// in-register any-extension of the low lanes of an integer vector. The 514 /// result type must have fewer elements than the operand type, and those 515 /// elements must be larger integer types such that the total size of the 516 /// operand type is less than or equal to the size of the result type. Each 517 /// of the low operand elements is any-extended into the corresponding, 518 /// wider result elements with the high bits becoming undef. 519 /// NOTE: The type legalizer prefers to make the operand and result size 520 /// the same to allow expansion to shuffle vector during op legalization. 521 ANY_EXTEND_VECTOR_INREG, 522 523 /// SIGN_EXTEND_VECTOR_INREG(Vector) - This operator represents an 524 /// in-register sign-extension of the low lanes of an integer vector. The 525 /// result type must have fewer elements than the operand type, and those 526 /// elements must be larger integer types such that the total size of the 527 /// operand type is less than or equal to the size of the result type. Each 528 /// of the low operand elements is sign-extended into the corresponding, 529 /// wider result elements. 530 /// NOTE: The type legalizer prefers to make the operand and result size 531 /// the same to allow expansion to shuffle vector during op legalization. 532 SIGN_EXTEND_VECTOR_INREG, 533 534 /// ZERO_EXTEND_VECTOR_INREG(Vector) - This operator represents an 535 /// in-register zero-extension of the low lanes of an integer vector. The 536 /// result type must have fewer elements than the operand type, and those 537 /// elements must be larger integer types such that the total size of the 538 /// operand type is less than or equal to the size of the result type. Each 539 /// of the low operand elements is zero-extended into the corresponding, 540 /// wider result elements. 541 /// NOTE: The type legalizer prefers to make the operand and result size 542 /// the same to allow expansion to shuffle vector during op legalization. 543 ZERO_EXTEND_VECTOR_INREG, 544 545 /// FP_TO_[US]INT - Convert a floating point value to a signed or unsigned 546 /// integer. These have the same semantics as fptosi and fptoui in IR. If 547 /// the FP value cannot fit in the integer type, the results are undefined. 548 FP_TO_SINT, 549 FP_TO_UINT, 550 551 /// X = FP_ROUND(Y, TRUNC) - Rounding 'Y' from a larger floating point type 552 /// down to the precision of the destination VT. TRUNC is a flag, which is 553 /// always an integer that is zero or one. If TRUNC is 0, this is a 554 /// normal rounding, if it is 1, this FP_ROUND is known to not change the 555 /// value of Y. 556 /// 557 /// The TRUNC = 1 case is used in cases where we know that the value will 558 /// not be modified by the node, because Y is not using any of the extra 559 /// precision of source type. This allows certain transformations like 560 /// FP_EXTEND(FP_ROUND(X,1)) -> X which are not safe for 561 /// FP_EXTEND(FP_ROUND(X,0)) because the extra bits aren't removed. 562 FP_ROUND, 563 564 /// FLT_ROUNDS_ - Returns current rounding mode: 565 /// -1 Undefined 566 /// 0 Round to 0 567 /// 1 Round to nearest 568 /// 2 Round to +inf 569 /// 3 Round to -inf 570 FLT_ROUNDS_, 571 572 /// X = FP_ROUND_INREG(Y, VT) - This operator takes an FP register, and 573 /// rounds it to a floating point value. It then promotes it and returns it 574 /// in a register of the same size. This operation effectively just 575 /// discards excess precision. The type to round down to is specified by 576 /// the VT operand, a VTSDNode. 577 FP_ROUND_INREG, 578 579 /// X = FP_EXTEND(Y) - Extend a smaller FP type into a larger FP type. 580 FP_EXTEND, 581 582 /// BITCAST - This operator converts between integer, vector and FP 583 /// values, as if the value was stored to memory with one type and loaded 584 /// from the same address with the other type (or equivalently for vector 585 /// format conversions, etc). The source and result are required to have 586 /// the same bit size (e.g. f32 <-> i32). This can also be used for 587 /// int-to-int or fp-to-fp conversions, but that is a noop, deleted by 588 /// getNode(). 589 /// 590 /// This operator is subtly different from the bitcast instruction from 591 /// LLVM-IR since this node may change the bits in the register. For 592 /// example, this occurs on big-endian NEON and big-endian MSA where the 593 /// layout of the bits in the register depends on the vector type and this 594 /// operator acts as a shuffle operation for some vector type combinations. 595 BITCAST, 596 597 /// ADDRSPACECAST - This operator converts between pointers of different 598 /// address spaces. 599 ADDRSPACECAST, 600 601 /// FP16_TO_FP, FP_TO_FP16 - These operators are used to perform promotions 602 /// and truncation for half-precision (16 bit) floating numbers. These nodes 603 /// form a semi-softened interface for dealing with f16 (as an i16), which 604 /// is often a storage-only type but has native conversions. 605 FP16_TO_FP, FP_TO_FP16, 606 607 /// Perform various unary floating-point operations inspired by libm. For 608 /// FPOWI, the result is undefined if if the integer operand doesn't fit 609 /// into 32 bits. 610 FNEG, FABS, FSQRT, FCBRT, FSIN, FCOS, FPOWI, FPOW, 611 FLOG, FLOG2, FLOG10, FEXP, FEXP2, 612 FCEIL, FTRUNC, FRINT, FNEARBYINT, FROUND, FFLOOR, 613 LROUND, LLROUND, LRINT, LLRINT, 614 615 /// FMINNUM/FMAXNUM - Perform floating-point minimum or maximum on two 616 /// values. 617 // 618 /// In the case where a single input is a NaN (either signaling or quiet), 619 /// the non-NaN input is returned. 620 /// 621 /// The return value of (FMINNUM 0.0, -0.0) could be either 0.0 or -0.0. 622 FMINNUM, FMAXNUM, 623 624 /// FMINNUM_IEEE/FMAXNUM_IEEE - Perform floating-point minimum or maximum on 625 /// two values, following the IEEE-754 2008 definition. This differs from 626 /// FMINNUM/FMAXNUM in the handling of signaling NaNs. If one input is a 627 /// signaling NaN, returns a quiet NaN. 628 FMINNUM_IEEE, FMAXNUM_IEEE, 629 630 /// FMINIMUM/FMAXIMUM - NaN-propagating minimum/maximum that also treat -0.0 631 /// as less than 0.0. While FMINNUM_IEEE/FMAXNUM_IEEE follow IEEE 754-2008 632 /// semantics, FMINIMUM/FMAXIMUM follow IEEE 754-2018 draft semantics. 633 FMINIMUM, FMAXIMUM, 634 635 /// FSINCOS - Compute both fsin and fcos as a single operation. 636 FSINCOS, 637 638 /// LOAD and STORE have token chains as their first operand, then the same 639 /// operands as an LLVM load/store instruction, then an offset node that 640 /// is added / subtracted from the base pointer to form the address (for 641 /// indexed memory ops). 642 LOAD, STORE, 643 644 /// DYNAMIC_STACKALLOC - Allocate some number of bytes on the stack aligned 645 /// to a specified boundary. This node always has two return values: a new 646 /// stack pointer value and a chain. The first operand is the token chain, 647 /// the second is the number of bytes to allocate, and the third is the 648 /// alignment boundary. The size is guaranteed to be a multiple of the 649 /// stack alignment, and the alignment is guaranteed to be bigger than the 650 /// stack alignment (if required) or 0 to get standard stack alignment. 651 DYNAMIC_STACKALLOC, 652 653 /// Control flow instructions. These all have token chains. 654 655 /// BR - Unconditional branch. The first operand is the chain 656 /// operand, the second is the MBB to branch to. 657 BR, 658 659 /// BRIND - Indirect branch. The first operand is the chain, the second 660 /// is the value to branch to, which must be of the same type as the 661 /// target's pointer type. 662 BRIND, 663 664 /// BR_JT - Jumptable branch. The first operand is the chain, the second 665 /// is the jumptable index, the last one is the jumptable entry index. 666 BR_JT, 667 668 /// BRCOND - Conditional branch. The first operand is the chain, the 669 /// second is the condition, the third is the block to branch to if the 670 /// condition is true. If the type of the condition is not i1, then the 671 /// high bits must conform to getBooleanContents. 672 BRCOND, 673 674 /// BR_CC - Conditional branch. The behavior is like that of SELECT_CC, in 675 /// that the condition is represented as condition code, and two nodes to 676 /// compare, rather than as a combined SetCC node. The operands in order 677 /// are chain, cc, lhs, rhs, block to branch to if condition is true. 678 BR_CC, 679 680 /// INLINEASM - Represents an inline asm block. This node always has two 681 /// return values: a chain and a flag result. The inputs are as follows: 682 /// Operand #0 : Input chain. 683 /// Operand #1 : a ExternalSymbolSDNode with a pointer to the asm string. 684 /// Operand #2 : a MDNodeSDNode with the !srcloc metadata. 685 /// Operand #3 : HasSideEffect, IsAlignStack bits. 686 /// After this, it is followed by a list of operands with this format: 687 /// ConstantSDNode: Flags that encode whether it is a mem or not, the 688 /// of operands that follow, etc. See InlineAsm.h. 689 /// ... however many operands ... 690 /// Operand #last: Optional, an incoming flag. 691 /// 692 /// The variable width operands are required to represent target addressing 693 /// modes as a single "operand", even though they may have multiple 694 /// SDOperands. 695 INLINEASM, 696 697 /// INLINEASM_BR - Terminator version of inline asm. Used by asm-goto. 698 INLINEASM_BR, 699 700 /// EH_LABEL - Represents a label in mid basic block used to track 701 /// locations needed for debug and exception handling tables. These nodes 702 /// take a chain as input and return a chain. 703 EH_LABEL, 704 705 /// ANNOTATION_LABEL - Represents a mid basic block label used by 706 /// annotations. This should remain within the basic block and be ordered 707 /// with respect to other call instructions, but loads and stores may float 708 /// past it. 709 ANNOTATION_LABEL, 710 711 /// CATCHPAD - Represents a catchpad instruction. 712 CATCHPAD, 713 714 /// CATCHRET - Represents a return from a catch block funclet. Used for 715 /// MSVC compatible exception handling. Takes a chain operand and a 716 /// destination basic block operand. 717 CATCHRET, 718 719 /// CLEANUPRET - Represents a return from a cleanup block funclet. Used for 720 /// MSVC compatible exception handling. Takes only a chain operand. 721 CLEANUPRET, 722 723 /// STACKSAVE - STACKSAVE has one operand, an input chain. It produces a 724 /// value, the same type as the pointer type for the system, and an output 725 /// chain. 726 STACKSAVE, 727 728 /// STACKRESTORE has two operands, an input chain and a pointer to restore 729 /// to it returns an output chain. 730 STACKRESTORE, 731 732 /// CALLSEQ_START/CALLSEQ_END - These operators mark the beginning and end 733 /// of a call sequence, and carry arbitrary information that target might 734 /// want to know. The first operand is a chain, the rest are specified by 735 /// the target and not touched by the DAG optimizers. 736 /// Targets that may use stack to pass call arguments define additional 737 /// operands: 738 /// - size of the call frame part that must be set up within the 739 /// CALLSEQ_START..CALLSEQ_END pair, 740 /// - part of the call frame prepared prior to CALLSEQ_START. 741 /// Both these parameters must be constants, their sum is the total call 742 /// frame size. 743 /// CALLSEQ_START..CALLSEQ_END pairs may not be nested. 744 CALLSEQ_START, // Beginning of a call sequence 745 CALLSEQ_END, // End of a call sequence 746 747 /// VAARG - VAARG has four operands: an input chain, a pointer, a SRCVALUE, 748 /// and the alignment. It returns a pair of values: the vaarg value and a 749 /// new chain. 750 VAARG, 751 752 /// VACOPY - VACOPY has 5 operands: an input chain, a destination pointer, 753 /// a source pointer, a SRCVALUE for the destination, and a SRCVALUE for the 754 /// source. 755 VACOPY, 756 757 /// VAEND, VASTART - VAEND and VASTART have three operands: an input chain, 758 /// pointer, and a SRCVALUE. 759 VAEND, VASTART, 760 761 /// SRCVALUE - This is a node type that holds a Value* that is used to 762 /// make reference to a value in the LLVM IR. 763 SRCVALUE, 764 765 /// MDNODE_SDNODE - This is a node that holdes an MDNode*, which is used to 766 /// reference metadata in the IR. 767 MDNODE_SDNODE, 768 769 /// PCMARKER - This corresponds to the pcmarker intrinsic. 770 PCMARKER, 771 772 /// READCYCLECOUNTER - This corresponds to the readcyclecounter intrinsic. 773 /// It produces a chain and one i64 value. The only operand is a chain. 774 /// If i64 is not legal, the result will be expanded into smaller values. 775 /// Still, it returns an i64, so targets should set legality for i64. 776 /// The result is the content of the architecture-specific cycle 777 /// counter-like register (or other high accuracy low latency clock source). 778 READCYCLECOUNTER, 779 780 /// HANDLENODE node - Used as a handle for various purposes. 781 HANDLENODE, 782 783 /// INIT_TRAMPOLINE - This corresponds to the init_trampoline intrinsic. It 784 /// takes as input a token chain, the pointer to the trampoline, the pointer 785 /// to the nested function, the pointer to pass for the 'nest' parameter, a 786 /// SRCVALUE for the trampoline and another for the nested function 787 /// (allowing targets to access the original Function*). 788 /// It produces a token chain as output. 789 INIT_TRAMPOLINE, 790 791 /// ADJUST_TRAMPOLINE - This corresponds to the adjust_trampoline intrinsic. 792 /// It takes a pointer to the trampoline and produces a (possibly) new 793 /// pointer to the same trampoline with platform-specific adjustments 794 /// applied. The pointer it returns points to an executable block of code. 795 ADJUST_TRAMPOLINE, 796 797 /// TRAP - Trapping instruction 798 TRAP, 799 800 /// DEBUGTRAP - Trap intended to get the attention of a debugger. 801 DEBUGTRAP, 802 803 /// PREFETCH - This corresponds to a prefetch intrinsic. The first operand 804 /// is the chain. The other operands are the address to prefetch, 805 /// read / write specifier, locality specifier and instruction / data cache 806 /// specifier. 807 PREFETCH, 808 809 /// OUTCHAIN = ATOMIC_FENCE(INCHAIN, ordering, scope) 810 /// This corresponds to the fence instruction. It takes an input chain, and 811 /// two integer constants: an AtomicOrdering and a SynchronizationScope. 812 ATOMIC_FENCE, 813 814 /// Val, OUTCHAIN = ATOMIC_LOAD(INCHAIN, ptr) 815 /// This corresponds to "load atomic" instruction. 816 ATOMIC_LOAD, 817 818 /// OUTCHAIN = ATOMIC_STORE(INCHAIN, ptr, val) 819 /// This corresponds to "store atomic" instruction. 820 ATOMIC_STORE, 821 822 /// Val, OUTCHAIN = ATOMIC_CMP_SWAP(INCHAIN, ptr, cmp, swap) 823 /// For double-word atomic operations: 824 /// ValLo, ValHi, OUTCHAIN = ATOMIC_CMP_SWAP(INCHAIN, ptr, cmpLo, cmpHi, 825 /// swapLo, swapHi) 826 /// This corresponds to the cmpxchg instruction. 827 ATOMIC_CMP_SWAP, 828 829 /// Val, Success, OUTCHAIN 830 /// = ATOMIC_CMP_SWAP_WITH_SUCCESS(INCHAIN, ptr, cmp, swap) 831 /// N.b. this is still a strong cmpxchg operation, so 832 /// Success == "Val == cmp". 833 ATOMIC_CMP_SWAP_WITH_SUCCESS, 834 835 /// Val, OUTCHAIN = ATOMIC_SWAP(INCHAIN, ptr, amt) 836 /// Val, OUTCHAIN = ATOMIC_LOAD_[OpName](INCHAIN, ptr, amt) 837 /// For double-word atomic operations: 838 /// ValLo, ValHi, OUTCHAIN = ATOMIC_SWAP(INCHAIN, ptr, amtLo, amtHi) 839 /// ValLo, ValHi, OUTCHAIN = ATOMIC_LOAD_[OpName](INCHAIN, ptr, amtLo, amtHi) 840 /// These correspond to the atomicrmw instruction. 841 ATOMIC_SWAP, 842 ATOMIC_LOAD_ADD, 843 ATOMIC_LOAD_SUB, 844 ATOMIC_LOAD_AND, 845 ATOMIC_LOAD_CLR, 846 ATOMIC_LOAD_OR, 847 ATOMIC_LOAD_XOR, 848 ATOMIC_LOAD_NAND, 849 ATOMIC_LOAD_MIN, 850 ATOMIC_LOAD_MAX, 851 ATOMIC_LOAD_UMIN, 852 ATOMIC_LOAD_UMAX, 853 ATOMIC_LOAD_FADD, 854 ATOMIC_LOAD_FSUB, 855 856 // Masked load and store - consecutive vector load and store operations 857 // with additional mask operand that prevents memory accesses to the 858 // masked-off lanes. 859 // 860 // Val, OutChain = MLOAD(BasePtr, Mask, PassThru) 861 // OutChain = MSTORE(Value, BasePtr, Mask) 862 MLOAD, MSTORE, 863 864 // Masked gather and scatter - load and store operations for a vector of 865 // random addresses with additional mask operand that prevents memory 866 // accesses to the masked-off lanes. 867 // 868 // Val, OutChain = GATHER(InChain, PassThru, Mask, BasePtr, Index, Scale) 869 // OutChain = SCATTER(InChain, Value, Mask, BasePtr, Index, Scale) 870 // 871 // The Index operand can have more vector elements than the other operands 872 // due to type legalization. The extra elements are ignored. 873 MGATHER, MSCATTER, 874 875 /// This corresponds to the llvm.lifetime.* intrinsics. The first operand 876 /// is the chain and the second operand is the alloca pointer. 877 LIFETIME_START, LIFETIME_END, 878 879 /// GC_TRANSITION_START/GC_TRANSITION_END - These operators mark the 880 /// beginning and end of GC transition sequence, and carry arbitrary 881 /// information that target might need for lowering. The first operand is 882 /// a chain, the rest are specified by the target and not touched by the DAG 883 /// optimizers. GC_TRANSITION_START..GC_TRANSITION_END pairs may not be 884 /// nested. 885 GC_TRANSITION_START, 886 GC_TRANSITION_END, 887 888 /// GET_DYNAMIC_AREA_OFFSET - get offset from native SP to the address of 889 /// the most recent dynamic alloca. For most targets that would be 0, but 890 /// for some others (e.g. PowerPC, PowerPC64) that would be compile-time 891 /// known nonzero constant. The only operand here is the chain. 892 GET_DYNAMIC_AREA_OFFSET, 893 894 /// Generic reduction nodes. These nodes represent horizontal vector 895 /// reduction operations, producing a scalar result. 896 /// The STRICT variants perform reductions in sequential order. The first 897 /// operand is an initial scalar accumulator value, and the second operand 898 /// is the vector to reduce. 899 VECREDUCE_STRICT_FADD, VECREDUCE_STRICT_FMUL, 900 /// These reductions are non-strict, and have a single vector operand. 901 VECREDUCE_FADD, VECREDUCE_FMUL, 902 /// FMIN/FMAX nodes can have flags, for NaN/NoNaN variants. 903 VECREDUCE_FMAX, VECREDUCE_FMIN, 904 /// Integer reductions may have a result type larger than the vector element 905 /// type. However, the reduction is performed using the vector element type 906 /// and the value in the top bits is unspecified. 907 VECREDUCE_ADD, VECREDUCE_MUL, 908 VECREDUCE_AND, VECREDUCE_OR, VECREDUCE_XOR, 909 VECREDUCE_SMAX, VECREDUCE_SMIN, VECREDUCE_UMAX, VECREDUCE_UMIN, 910 911 /// BUILTIN_OP_END - This must be the last enum value in this list. 912 /// The target-specific pre-isel opcode values start here. 913 BUILTIN_OP_END 914 }; 915 916 /// FIRST_TARGET_MEMORY_OPCODE - Target-specific pre-isel operations 917 /// which do not reference a specific memory location should be less than 918 /// this value. Those that do must not be less than this value, and can 919 /// be used with SelectionDAG::getMemIntrinsicNode. 920 static const int FIRST_TARGET_MEMORY_OPCODE = BUILTIN_OP_END+400; 921 922 //===--------------------------------------------------------------------===// 923 /// MemIndexedMode enum - This enum defines the load / store indexed 924 /// addressing modes. 925 /// 926 /// UNINDEXED "Normal" load / store. The effective address is already 927 /// computed and is available in the base pointer. The offset 928 /// operand is always undefined. In addition to producing a 929 /// chain, an unindexed load produces one value (result of the 930 /// load); an unindexed store does not produce a value. 931 /// 932 /// PRE_INC Similar to the unindexed mode where the effective address is 933 /// PRE_DEC the value of the base pointer add / subtract the offset. 934 /// It considers the computation as being folded into the load / 935 /// store operation (i.e. the load / store does the address 936 /// computation as well as performing the memory transaction). 937 /// The base operand is always undefined. In addition to 938 /// producing a chain, pre-indexed load produces two values 939 /// (result of the load and the result of the address 940 /// computation); a pre-indexed store produces one value (result 941 /// of the address computation). 942 /// 943 /// POST_INC The effective address is the value of the base pointer. The 944 /// POST_DEC value of the offset operand is then added to / subtracted 945 /// from the base after memory transaction. In addition to 946 /// producing a chain, post-indexed load produces two values 947 /// (the result of the load and the result of the base +/- offset 948 /// computation); a post-indexed store produces one value (the 949 /// the result of the base +/- offset computation). 950 enum MemIndexedMode { 951 UNINDEXED = 0, 952 PRE_INC, 953 PRE_DEC, 954 POST_INC, 955 POST_DEC 956 }; 957 958 static const int LAST_INDEXED_MODE = POST_DEC + 1; 959 960 //===--------------------------------------------------------------------===// 961 /// LoadExtType enum - This enum defines the three variants of LOADEXT 962 /// (load with extension). 963 /// 964 /// SEXTLOAD loads the integer operand and sign extends it to a larger 965 /// integer result type. 966 /// ZEXTLOAD loads the integer operand and zero extends it to a larger 967 /// integer result type. 968 /// EXTLOAD is used for two things: floating point extending loads and 969 /// integer extending loads [the top bits are undefined]. 970 enum LoadExtType { 971 NON_EXTLOAD = 0, 972 EXTLOAD, 973 SEXTLOAD, 974 ZEXTLOAD 975 }; 976 977 static const int LAST_LOADEXT_TYPE = ZEXTLOAD + 1; 978 979 NodeType getExtForLoadExtType(bool IsFP, LoadExtType); 980 981 //===--------------------------------------------------------------------===// 982 /// ISD::CondCode enum - These are ordered carefully to make the bitfields 983 /// below work out, when considering SETFALSE (something that never exists 984 /// dynamically) as 0. "U" -> Unsigned (for integer operands) or Unordered 985 /// (for floating point), "L" -> Less than, "G" -> Greater than, "E" -> Equal 986 /// to. If the "N" column is 1, the result of the comparison is undefined if 987 /// the input is a NAN. 988 /// 989 /// All of these (except for the 'always folded ops') should be handled for 990 /// floating point. For integer, only the SETEQ,SETNE,SETLT,SETLE,SETGT, 991 /// SETGE,SETULT,SETULE,SETUGT, and SETUGE opcodes are used. 992 /// 993 /// Note that these are laid out in a specific order to allow bit-twiddling 994 /// to transform conditions. 995 enum CondCode { 996 // Opcode N U L G E Intuitive operation 997 SETFALSE, // 0 0 0 0 Always false (always folded) 998 SETOEQ, // 0 0 0 1 True if ordered and equal 999 SETOGT, // 0 0 1 0 True if ordered and greater than 1000 SETOGE, // 0 0 1 1 True if ordered and greater than or equal 1001 SETOLT, // 0 1 0 0 True if ordered and less than 1002 SETOLE, // 0 1 0 1 True if ordered and less than or equal 1003 SETONE, // 0 1 1 0 True if ordered and operands are unequal 1004 SETO, // 0 1 1 1 True if ordered (no nans) 1005 SETUO, // 1 0 0 0 True if unordered: isnan(X) | isnan(Y) 1006 SETUEQ, // 1 0 0 1 True if unordered or equal 1007 SETUGT, // 1 0 1 0 True if unordered or greater than 1008 SETUGE, // 1 0 1 1 True if unordered, greater than, or equal 1009 SETULT, // 1 1 0 0 True if unordered or less than 1010 SETULE, // 1 1 0 1 True if unordered, less than, or equal 1011 SETUNE, // 1 1 1 0 True if unordered or not equal 1012 SETTRUE, // 1 1 1 1 Always true (always folded) 1013 // Don't care operations: undefined if the input is a nan. 1014 SETFALSE2, // 1 X 0 0 0 Always false (always folded) 1015 SETEQ, // 1 X 0 0 1 True if equal 1016 SETGT, // 1 X 0 1 0 True if greater than 1017 SETGE, // 1 X 0 1 1 True if greater than or equal 1018 SETLT, // 1 X 1 0 0 True if less than 1019 SETLE, // 1 X 1 0 1 True if less than or equal 1020 SETNE, // 1 X 1 1 0 True if not equal 1021 SETTRUE2, // 1 X 1 1 1 Always true (always folded) 1022 1023 SETCC_INVALID // Marker value. 1024 }; 1025 1026 /// Return true if this is a setcc instruction that performs a signed 1027 /// comparison when used with integer operands. 1028 inline bool isSignedIntSetCC(CondCode Code) { 1029 return Code == SETGT || Code == SETGE || Code == SETLT || Code == SETLE; 1030 } 1031 1032 /// Return true if this is a setcc instruction that performs an unsigned 1033 /// comparison when used with integer operands. 1034 inline bool isUnsignedIntSetCC(CondCode Code) { 1035 return Code == SETUGT || Code == SETUGE || Code == SETULT || Code == SETULE; 1036 } 1037 1038 /// Return true if the specified condition returns true if the two operands to 1039 /// the condition are equal. Note that if one of the two operands is a NaN, 1040 /// this value is meaningless. 1041 inline bool isTrueWhenEqual(CondCode Cond) { 1042 return ((int)Cond & 1) != 0; 1043 } 1044 1045 /// This function returns 0 if the condition is always false if an operand is 1046 /// a NaN, 1 if the condition is always true if the operand is a NaN, and 2 if 1047 /// the condition is undefined if the operand is a NaN. 1048 inline unsigned getUnorderedFlavor(CondCode Cond) { 1049 return ((int)Cond >> 3) & 3; 1050 } 1051 1052 /// Return the operation corresponding to !(X op Y), where 'op' is a valid 1053 /// SetCC operation. 1054 CondCode getSetCCInverse(CondCode Operation, bool isInteger); 1055 1056 /// Return the operation corresponding to (Y op X) when given the operation 1057 /// for (X op Y). 1058 CondCode getSetCCSwappedOperands(CondCode Operation); 1059 1060 /// Return the result of a logical OR between different comparisons of 1061 /// identical values: ((X op1 Y) | (X op2 Y)). This function returns 1062 /// SETCC_INVALID if it is not possible to represent the resultant comparison. 1063 CondCode getSetCCOrOperation(CondCode Op1, CondCode Op2, bool isInteger); 1064 1065 /// Return the result of a logical AND between different comparisons of 1066 /// identical values: ((X op1 Y) & (X op2 Y)). This function returns 1067 /// SETCC_INVALID if it is not possible to represent the resultant comparison. 1068 CondCode getSetCCAndOperation(CondCode Op1, CondCode Op2, bool isInteger); 1069 1070} // end llvm::ISD namespace 1071 1072} // end llvm namespace 1073 1074#endif 1075