ISDOpcodes.h revision 321369
1//===-- llvm/CodeGen/ISDOpcodes.h - CodeGen opcodes -------------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file declares codegen opcodes and related utilities. 11// 12//===----------------------------------------------------------------------===// 13 14#ifndef LLVM_CODEGEN_ISDOPCODES_H 15#define LLVM_CODEGEN_ISDOPCODES_H 16 17namespace llvm { 18 19/// ISD namespace - This namespace contains an enum which represents all of the 20/// SelectionDAG node types and value types. 21/// 22namespace ISD { 23 24 //===--------------------------------------------------------------------===// 25 /// ISD::NodeType enum - This enum defines the target-independent operators 26 /// for a SelectionDAG. 27 /// 28 /// Targets may also define target-dependent operator codes for SDNodes. For 29 /// example, on x86, these are the enum values in the X86ISD namespace. 30 /// Targets should aim to use target-independent operators to model their 31 /// instruction sets as much as possible, and only use target-dependent 32 /// operators when they have special requirements. 33 /// 34 /// Finally, during and after selection proper, SNodes may use special 35 /// operator codes that correspond directly with MachineInstr opcodes. These 36 /// are used to represent selected instructions. See the isMachineOpcode() 37 /// and getMachineOpcode() member functions of SDNode. 38 /// 39 enum NodeType { 40 /// DELETED_NODE - This is an illegal value that is used to catch 41 /// errors. This opcode is not a legal opcode for any node. 42 DELETED_NODE, 43 44 /// EntryToken - This is the marker used to indicate the start of a region. 45 EntryToken, 46 47 /// TokenFactor - This node takes multiple tokens as input and produces a 48 /// single token result. This is used to represent the fact that the operand 49 /// operators are independent of each other. 50 TokenFactor, 51 52 /// AssertSext, AssertZext - These nodes record if a register contains a 53 /// value that has already been zero or sign extended from a narrower type. 54 /// These nodes take two operands. The first is the node that has already 55 /// been extended, and the second is a value type node indicating the width 56 /// of the extension 57 AssertSext, AssertZext, 58 59 /// Various leaf nodes. 60 BasicBlock, VALUETYPE, CONDCODE, Register, RegisterMask, 61 Constant, ConstantFP, 62 GlobalAddress, GlobalTLSAddress, FrameIndex, 63 JumpTable, ConstantPool, ExternalSymbol, BlockAddress, 64 65 /// The address of the GOT 66 GLOBAL_OFFSET_TABLE, 67 68 /// FRAMEADDR, RETURNADDR - These nodes represent llvm.frameaddress and 69 /// llvm.returnaddress on the DAG. These nodes take one operand, the index 70 /// of the frame or return address to return. An index of zero corresponds 71 /// to the current function's frame or return address, an index of one to 72 /// the parent's frame or return address, and so on. 73 FRAMEADDR, RETURNADDR, ADDROFRETURNADDR, 74 75 /// LOCAL_RECOVER - Represents the llvm.localrecover intrinsic. 76 /// Materializes the offset from the local object pointer of another 77 /// function to a particular local object passed to llvm.localescape. The 78 /// operand is the MCSymbol label used to represent this offset, since 79 /// typically the offset is not known until after code generation of the 80 /// parent. 81 LOCAL_RECOVER, 82 83 /// READ_REGISTER, WRITE_REGISTER - This node represents llvm.register on 84 /// the DAG, which implements the named register global variables extension. 85 READ_REGISTER, 86 WRITE_REGISTER, 87 88 /// FRAME_TO_ARGS_OFFSET - This node represents offset from frame pointer to 89 /// first (possible) on-stack argument. This is needed for correct stack 90 /// adjustment during unwind. 91 FRAME_TO_ARGS_OFFSET, 92 93 /// EH_DWARF_CFA - This node represents the pointer to the DWARF Canonical 94 /// Frame Address (CFA), generally the value of the stack pointer at the 95 /// call site in the previous frame. 96 EH_DWARF_CFA, 97 98 /// OUTCHAIN = EH_RETURN(INCHAIN, OFFSET, HANDLER) - This node represents 99 /// 'eh_return' gcc dwarf builtin, which is used to return from 100 /// exception. The general meaning is: adjust stack by OFFSET and pass 101 /// execution to HANDLER. Many platform-related details also :) 102 EH_RETURN, 103 104 /// RESULT, OUTCHAIN = EH_SJLJ_SETJMP(INCHAIN, buffer) 105 /// This corresponds to the eh.sjlj.setjmp intrinsic. 106 /// It takes an input chain and a pointer to the jump buffer as inputs 107 /// and returns an outchain. 108 EH_SJLJ_SETJMP, 109 110 /// OUTCHAIN = EH_SJLJ_LONGJMP(INCHAIN, buffer) 111 /// This corresponds to the eh.sjlj.longjmp intrinsic. 112 /// It takes an input chain and a pointer to the jump buffer as inputs 113 /// and returns an outchain. 114 EH_SJLJ_LONGJMP, 115 116 /// OUTCHAIN = EH_SJLJ_SETUP_DISPATCH(INCHAIN) 117 /// The target initializes the dispatch table here. 118 EH_SJLJ_SETUP_DISPATCH, 119 120 /// TargetConstant* - Like Constant*, but the DAG does not do any folding, 121 /// simplification, or lowering of the constant. They are used for constants 122 /// which are known to fit in the immediate fields of their users, or for 123 /// carrying magic numbers which are not values which need to be 124 /// materialized in registers. 125 TargetConstant, 126 TargetConstantFP, 127 128 /// TargetGlobalAddress - Like GlobalAddress, but the DAG does no folding or 129 /// anything else with this node, and this is valid in the target-specific 130 /// dag, turning into a GlobalAddress operand. 131 TargetGlobalAddress, 132 TargetGlobalTLSAddress, 133 TargetFrameIndex, 134 TargetJumpTable, 135 TargetConstantPool, 136 TargetExternalSymbol, 137 TargetBlockAddress, 138 139 MCSymbol, 140 141 /// TargetIndex - Like a constant pool entry, but with completely 142 /// target-dependent semantics. Holds target flags, a 32-bit index, and a 143 /// 64-bit index. Targets can use this however they like. 144 TargetIndex, 145 146 /// RESULT = INTRINSIC_WO_CHAIN(INTRINSICID, arg1, arg2, ...) 147 /// This node represents a target intrinsic function with no side effects. 148 /// The first operand is the ID number of the intrinsic from the 149 /// llvm::Intrinsic namespace. The operands to the intrinsic follow. The 150 /// node returns the result of the intrinsic. 151 INTRINSIC_WO_CHAIN, 152 153 /// RESULT,OUTCHAIN = INTRINSIC_W_CHAIN(INCHAIN, INTRINSICID, arg1, ...) 154 /// This node represents a target intrinsic function with side effects that 155 /// returns a result. The first operand is a chain pointer. The second is 156 /// the ID number of the intrinsic from the llvm::Intrinsic namespace. The 157 /// operands to the intrinsic follow. The node has two results, the result 158 /// of the intrinsic and an output chain. 159 INTRINSIC_W_CHAIN, 160 161 /// OUTCHAIN = INTRINSIC_VOID(INCHAIN, INTRINSICID, arg1, arg2, ...) 162 /// This node represents a target intrinsic function with side effects that 163 /// does not return a result. The first operand is a chain pointer. The 164 /// second is the ID number of the intrinsic from the llvm::Intrinsic 165 /// namespace. The operands to the intrinsic follow. 166 INTRINSIC_VOID, 167 168 /// CopyToReg - This node has three operands: a chain, a register number to 169 /// set to this value, and a value. 170 CopyToReg, 171 172 /// CopyFromReg - This node indicates that the input value is a virtual or 173 /// physical register that is defined outside of the scope of this 174 /// SelectionDAG. The register is available from the RegisterSDNode object. 175 CopyFromReg, 176 177 /// UNDEF - An undefined node. 178 UNDEF, 179 180 /// EXTRACT_ELEMENT - This is used to get the lower or upper (determined by 181 /// a Constant, which is required to be operand #1) half of the integer or 182 /// float value specified as operand #0. This is only for use before 183 /// legalization, for values that will be broken into multiple registers. 184 EXTRACT_ELEMENT, 185 186 /// BUILD_PAIR - This is the opposite of EXTRACT_ELEMENT in some ways. 187 /// Given two values of the same integer value type, this produces a value 188 /// twice as big. Like EXTRACT_ELEMENT, this can only be used before 189 /// legalization. 190 BUILD_PAIR, 191 192 /// MERGE_VALUES - This node takes multiple discrete operands and returns 193 /// them all as its individual results. This nodes has exactly the same 194 /// number of inputs and outputs. This node is useful for some pieces of the 195 /// code generator that want to think about a single node with multiple 196 /// results, not multiple nodes. 197 MERGE_VALUES, 198 199 /// Simple integer binary arithmetic operators. 200 ADD, SUB, MUL, SDIV, UDIV, SREM, UREM, 201 202 /// SMUL_LOHI/UMUL_LOHI - Multiply two integers of type iN, producing 203 /// a signed/unsigned value of type i[2*N], and return the full value as 204 /// two results, each of type iN. 205 SMUL_LOHI, UMUL_LOHI, 206 207 /// SDIVREM/UDIVREM - Divide two integers and produce both a quotient and 208 /// remainder result. 209 SDIVREM, UDIVREM, 210 211 /// CARRY_FALSE - This node is used when folding other nodes, 212 /// like ADDC/SUBC, which indicate the carry result is always false. 213 CARRY_FALSE, 214 215 /// Carry-setting nodes for multiple precision addition and subtraction. 216 /// These nodes take two operands of the same value type, and produce two 217 /// results. The first result is the normal add or sub result, the second 218 /// result is the carry flag result. 219 /// FIXME: These nodes are deprecated in favor of ADDCARRY and SUBCARRY. 220 /// They are kept around for now to provide a smooth transition path 221 /// toward the use of ADDCARRY/SUBCARRY and will eventually be removed. 222 ADDC, SUBC, 223 224 /// Carry-using nodes for multiple precision addition and subtraction. These 225 /// nodes take three operands: The first two are the normal lhs and rhs to 226 /// the add or sub, and the third is the input carry flag. These nodes 227 /// produce two results; the normal result of the add or sub, and the output 228 /// carry flag. These nodes both read and write a carry flag to allow them 229 /// to them to be chained together for add and sub of arbitrarily large 230 /// values. 231 ADDE, SUBE, 232 233 /// Carry-using nodes for multiple precision addition and subtraction. 234 /// These nodes take three operands: The first two are the normal lhs and 235 /// rhs to the add or sub, and the third is a boolean indicating if there 236 /// is an incoming carry. These nodes produce two results: the normal 237 /// result of the add or sub, and the output carry so they can be chained 238 /// together. The use of this opcode is preferable to adde/sube if the 239 /// target supports it, as the carry is a regular value rather than a 240 /// glue, which allows further optimisation. 241 ADDCARRY, SUBCARRY, 242 243 /// RESULT, BOOL = [SU]ADDO(LHS, RHS) - Overflow-aware nodes for addition. 244 /// These nodes take two operands: the normal LHS and RHS to the add. They 245 /// produce two results: the normal result of the add, and a boolean that 246 /// indicates if an overflow occurred (*not* a flag, because it may be store 247 /// to memory, etc.). If the type of the boolean is not i1 then the high 248 /// bits conform to getBooleanContents. 249 /// These nodes are generated from llvm.[su]add.with.overflow intrinsics. 250 SADDO, UADDO, 251 252 /// Same for subtraction. 253 SSUBO, USUBO, 254 255 /// Same for multiplication. 256 SMULO, UMULO, 257 258 /// Simple binary floating point operators. 259 FADD, FSUB, FMUL, FDIV, FREM, 260 261 /// Constrained versions of the binary floating point operators. 262 /// These will be lowered to the simple operators before final selection. 263 /// They are used to limit optimizations while the DAG is being 264 /// optimized. 265 STRICT_FADD, STRICT_FSUB, STRICT_FMUL, STRICT_FDIV, STRICT_FREM, 266 267 /// Constrained versions of libm-equivalent floating point intrinsics. 268 /// These will be lowered to the equivalent non-constrained pseudo-op 269 /// (or expanded to the equivalent library call) before final selection. 270 /// They are used to limit optimizations while the DAG is being optimized. 271 STRICT_FSQRT, STRICT_FPOW, STRICT_FPOWI, STRICT_FSIN, STRICT_FCOS, 272 STRICT_FEXP, STRICT_FEXP2, STRICT_FLOG, STRICT_FLOG10, STRICT_FLOG2, 273 STRICT_FRINT, STRICT_FNEARBYINT, 274 275 /// FMA - Perform a * b + c with no intermediate rounding step. 276 FMA, 277 278 /// FMAD - Perform a * b + c, while getting the same result as the 279 /// separately rounded operations. 280 FMAD, 281 282 /// FCOPYSIGN(X, Y) - Return the value of X with the sign of Y. NOTE: This 283 /// DAG node does not require that X and Y have the same type, just that 284 /// they are both floating point. X and the result must have the same type. 285 /// FCOPYSIGN(f32, f64) is allowed. 286 FCOPYSIGN, 287 288 /// INT = FGETSIGN(FP) - Return the sign bit of the specified floating point 289 /// value as an integer 0/1 value. 290 FGETSIGN, 291 292 /// Returns platform specific canonical encoding of a floating point number. 293 FCANONICALIZE, 294 295 /// BUILD_VECTOR(ELT0, ELT1, ELT2, ELT3,...) - Return a vector with the 296 /// specified, possibly variable, elements. The number of elements is 297 /// required to be a power of two. The types of the operands must all be 298 /// the same and must match the vector element type, except that integer 299 /// types are allowed to be larger than the element type, in which case 300 /// the operands are implicitly truncated. 301 BUILD_VECTOR, 302 303 /// INSERT_VECTOR_ELT(VECTOR, VAL, IDX) - Returns VECTOR with the element 304 /// at IDX replaced with VAL. If the type of VAL is larger than the vector 305 /// element type then VAL is truncated before replacement. 306 INSERT_VECTOR_ELT, 307 308 /// EXTRACT_VECTOR_ELT(VECTOR, IDX) - Returns a single element from VECTOR 309 /// identified by the (potentially variable) element number IDX. If the 310 /// return type is an integer type larger than the element type of the 311 /// vector, the result is extended to the width of the return type. In 312 /// that case, the high bits are undefined. 313 EXTRACT_VECTOR_ELT, 314 315 /// CONCAT_VECTORS(VECTOR0, VECTOR1, ...) - Given a number of values of 316 /// vector type with the same length and element type, this produces a 317 /// concatenated vector result value, with length equal to the sum of the 318 /// lengths of the input vectors. 319 CONCAT_VECTORS, 320 321 /// INSERT_SUBVECTOR(VECTOR1, VECTOR2, IDX) - Returns a vector 322 /// with VECTOR2 inserted into VECTOR1 at the (potentially 323 /// variable) element number IDX, which must be a multiple of the 324 /// VECTOR2 vector length. The elements of VECTOR1 starting at 325 /// IDX are overwritten with VECTOR2. Elements IDX through 326 /// vector_length(VECTOR2) must be valid VECTOR1 indices. 327 INSERT_SUBVECTOR, 328 329 /// EXTRACT_SUBVECTOR(VECTOR, IDX) - Returns a subvector from VECTOR (an 330 /// vector value) starting with the element number IDX, which must be a 331 /// constant multiple of the result vector length. 332 EXTRACT_SUBVECTOR, 333 334 /// VECTOR_SHUFFLE(VEC1, VEC2) - Returns a vector, of the same type as 335 /// VEC1/VEC2. A VECTOR_SHUFFLE node also contains an array of constant int 336 /// values that indicate which value (or undef) each result element will 337 /// get. These constant ints are accessible through the 338 /// ShuffleVectorSDNode class. This is quite similar to the Altivec 339 /// 'vperm' instruction, except that the indices must be constants and are 340 /// in terms of the element size of VEC1/VEC2, not in terms of bytes. 341 VECTOR_SHUFFLE, 342 343 /// SCALAR_TO_VECTOR(VAL) - This represents the operation of loading a 344 /// scalar value into element 0 of the resultant vector type. The top 345 /// elements 1 to N-1 of the N-element vector are undefined. The type 346 /// of the operand must match the vector element type, except when they 347 /// are integer types. In this case the operand is allowed to be wider 348 /// than the vector element type, and is implicitly truncated to it. 349 SCALAR_TO_VECTOR, 350 351 /// MULHU/MULHS - Multiply high - Multiply two integers of type iN, 352 /// producing an unsigned/signed value of type i[2*N], then return the top 353 /// part. 354 MULHU, MULHS, 355 356 /// [US]{MIN/MAX} - Binary minimum or maximum or signed or unsigned 357 /// integers. 358 SMIN, SMAX, UMIN, UMAX, 359 360 /// Bitwise operators - logical and, logical or, logical xor. 361 AND, OR, XOR, 362 363 /// ABS - Determine the unsigned absolute value of a signed integer value of 364 /// the same bitwidth. 365 /// Note: A value of INT_MIN will return INT_MIN, no saturation or overflow 366 /// is performed. 367 ABS, 368 369 /// Shift and rotation operations. After legalization, the type of the 370 /// shift amount is known to be TLI.getShiftAmountTy(). Before legalization 371 /// the shift amount can be any type, but care must be taken to ensure it is 372 /// large enough. TLI.getShiftAmountTy() is i8 on some targets, but before 373 /// legalization, types like i1024 can occur and i8 doesn't have enough bits 374 /// to represent the shift amount. 375 /// When the 1st operand is a vector, the shift amount must be in the same 376 /// type. (TLI.getShiftAmountTy() will return the same type when the input 377 /// type is a vector.) 378 SHL, SRA, SRL, ROTL, ROTR, 379 380 /// Byte Swap and Counting operators. 381 BSWAP, CTTZ, CTLZ, CTPOP, BITREVERSE, 382 383 /// Bit counting operators with an undefined result for zero inputs. 384 CTTZ_ZERO_UNDEF, CTLZ_ZERO_UNDEF, 385 386 /// Select(COND, TRUEVAL, FALSEVAL). If the type of the boolean COND is not 387 /// i1 then the high bits must conform to getBooleanContents. 388 SELECT, 389 390 /// Select with a vector condition (op #0) and two vector operands (ops #1 391 /// and #2), returning a vector result. All vectors have the same length. 392 /// Much like the scalar select and setcc, each bit in the condition selects 393 /// whether the corresponding result element is taken from op #1 or op #2. 394 /// At first, the VSELECT condition is of vXi1 type. Later, targets may 395 /// change the condition type in order to match the VSELECT node using a 396 /// pattern. The condition follows the BooleanContent format of the target. 397 VSELECT, 398 399 /// Select with condition operator - This selects between a true value and 400 /// a false value (ops #2 and #3) based on the boolean result of comparing 401 /// the lhs and rhs (ops #0 and #1) of a conditional expression with the 402 /// condition code in op #4, a CondCodeSDNode. 403 SELECT_CC, 404 405 /// SetCC operator - This evaluates to a true value iff the condition is 406 /// true. If the result value type is not i1 then the high bits conform 407 /// to getBooleanContents. The operands to this are the left and right 408 /// operands to compare (ops #0, and #1) and the condition code to compare 409 /// them with (op #2) as a CondCodeSDNode. If the operands are vector types 410 /// then the result type must also be a vector type. 411 SETCC, 412 413 /// Like SetCC, ops #0 and #1 are the LHS and RHS operands to compare, and 414 /// op #2 is a *carry value*. This operator checks the result of 415 /// "LHS - RHS - Carry", and can be used to compare two wide integers: 416 /// (setcce lhshi rhshi (subc lhslo rhslo) cc). Only valid for integers. 417 /// FIXME: This node is deprecated in favor of SETCCCARRY. 418 /// It is kept around for now to provide a smooth transition path 419 /// toward the use of SETCCCARRY and will eventually be removed. 420 SETCCE, 421 422 /// Like SetCC, ops #0 and #1 are the LHS and RHS operands to compare, but 423 /// op #2 is a boolean indicating if there is an incoming carry. This 424 /// operator checks the result of "LHS - RHS - Carry", and can be used to 425 /// compare two wide integers: (setcce lhshi rhshi (subc lhslo rhslo) cc). 426 /// Only valid for integers. 427 SETCCCARRY, 428 429 /// SHL_PARTS/SRA_PARTS/SRL_PARTS - These operators are used for expanded 430 /// integer shift operations. The operation ordering is: 431 /// [Lo,Hi] = op [LoLHS,HiLHS], Amt 432 SHL_PARTS, SRA_PARTS, SRL_PARTS, 433 434 /// Conversion operators. These are all single input single output 435 /// operations. For all of these, the result type must be strictly 436 /// wider or narrower (depending on the operation) than the source 437 /// type. 438 439 /// SIGN_EXTEND - Used for integer types, replicating the sign bit 440 /// into new bits. 441 SIGN_EXTEND, 442 443 /// ZERO_EXTEND - Used for integer types, zeroing the new bits. 444 ZERO_EXTEND, 445 446 /// ANY_EXTEND - Used for integer types. The high bits are undefined. 447 ANY_EXTEND, 448 449 /// TRUNCATE - Completely drop the high bits. 450 TRUNCATE, 451 452 /// [SU]INT_TO_FP - These operators convert integers (whose interpreted sign 453 /// depends on the first letter) to floating point. 454 SINT_TO_FP, 455 UINT_TO_FP, 456 457 /// SIGN_EXTEND_INREG - This operator atomically performs a SHL/SRA pair to 458 /// sign extend a small value in a large integer register (e.g. sign 459 /// extending the low 8 bits of a 32-bit register to fill the top 24 bits 460 /// with the 7th bit). The size of the smaller type is indicated by the 1th 461 /// operand, a ValueType node. 462 SIGN_EXTEND_INREG, 463 464 /// ANY_EXTEND_VECTOR_INREG(Vector) - This operator represents an 465 /// in-register any-extension of the low lanes of an integer vector. The 466 /// result type must have fewer elements than the operand type, and those 467 /// elements must be larger integer types such that the total size of the 468 /// operand type and the result type match. Each of the low operand 469 /// elements is any-extended into the corresponding, wider result 470 /// elements with the high bits becoming undef. 471 ANY_EXTEND_VECTOR_INREG, 472 473 /// SIGN_EXTEND_VECTOR_INREG(Vector) - This operator represents an 474 /// in-register sign-extension of the low lanes of an integer vector. The 475 /// result type must have fewer elements than the operand type, and those 476 /// elements must be larger integer types such that the total size of the 477 /// operand type and the result type match. Each of the low operand 478 /// elements is sign-extended into the corresponding, wider result 479 /// elements. 480 // FIXME: The SIGN_EXTEND_INREG node isn't specifically limited to 481 // scalars, but it also doesn't handle vectors well. Either it should be 482 // restricted to scalars or this node (and its handling) should be merged 483 // into it. 484 SIGN_EXTEND_VECTOR_INREG, 485 486 /// ZERO_EXTEND_VECTOR_INREG(Vector) - This operator represents an 487 /// in-register zero-extension of the low lanes of an integer vector. The 488 /// result type must have fewer elements than the operand type, and those 489 /// elements must be larger integer types such that the total size of the 490 /// operand type and the result type match. Each of the low operand 491 /// elements is zero-extended into the corresponding, wider result 492 /// elements. 493 ZERO_EXTEND_VECTOR_INREG, 494 495 /// FP_TO_[US]INT - Convert a floating point value to a signed or unsigned 496 /// integer. 497 FP_TO_SINT, 498 FP_TO_UINT, 499 500 /// X = FP_ROUND(Y, TRUNC) - Rounding 'Y' from a larger floating point type 501 /// down to the precision of the destination VT. TRUNC is a flag, which is 502 /// always an integer that is zero or one. If TRUNC is 0, this is a 503 /// normal rounding, if it is 1, this FP_ROUND is known to not change the 504 /// value of Y. 505 /// 506 /// The TRUNC = 1 case is used in cases where we know that the value will 507 /// not be modified by the node, because Y is not using any of the extra 508 /// precision of source type. This allows certain transformations like 509 /// FP_EXTEND(FP_ROUND(X,1)) -> X which are not safe for 510 /// FP_EXTEND(FP_ROUND(X,0)) because the extra bits aren't removed. 511 FP_ROUND, 512 513 /// FLT_ROUNDS_ - Returns current rounding mode: 514 /// -1 Undefined 515 /// 0 Round to 0 516 /// 1 Round to nearest 517 /// 2 Round to +inf 518 /// 3 Round to -inf 519 FLT_ROUNDS_, 520 521 /// X = FP_ROUND_INREG(Y, VT) - This operator takes an FP register, and 522 /// rounds it to a floating point value. It then promotes it and returns it 523 /// in a register of the same size. This operation effectively just 524 /// discards excess precision. The type to round down to is specified by 525 /// the VT operand, a VTSDNode. 526 FP_ROUND_INREG, 527 528 /// X = FP_EXTEND(Y) - Extend a smaller FP type into a larger FP type. 529 FP_EXTEND, 530 531 /// BITCAST - This operator converts between integer, vector and FP 532 /// values, as if the value was stored to memory with one type and loaded 533 /// from the same address with the other type (or equivalently for vector 534 /// format conversions, etc). The source and result are required to have 535 /// the same bit size (e.g. f32 <-> i32). This can also be used for 536 /// int-to-int or fp-to-fp conversions, but that is a noop, deleted by 537 /// getNode(). 538 /// 539 /// This operator is subtly different from the bitcast instruction from 540 /// LLVM-IR since this node may change the bits in the register. For 541 /// example, this occurs on big-endian NEON and big-endian MSA where the 542 /// layout of the bits in the register depends on the vector type and this 543 /// operator acts as a shuffle operation for some vector type combinations. 544 BITCAST, 545 546 /// ADDRSPACECAST - This operator converts between pointers of different 547 /// address spaces. 548 ADDRSPACECAST, 549 550 /// FP16_TO_FP, FP_TO_FP16 - These operators are used to perform promotions 551 /// and truncation for half-precision (16 bit) floating numbers. These nodes 552 /// form a semi-softened interface for dealing with f16 (as an i16), which 553 /// is often a storage-only type but has native conversions. 554 FP16_TO_FP, FP_TO_FP16, 555 556 /// FNEG, FABS, FSQRT, FSIN, FCOS, FPOWI, FPOW, 557 /// FLOG, FLOG2, FLOG10, FEXP, FEXP2, 558 /// FCEIL, FTRUNC, FRINT, FNEARBYINT, FROUND, FFLOOR - Perform various unary 559 /// floating point operations. These are inspired by libm. 560 FNEG, FABS, FSQRT, FSIN, FCOS, FPOWI, FPOW, 561 FLOG, FLOG2, FLOG10, FEXP, FEXP2, 562 FCEIL, FTRUNC, FRINT, FNEARBYINT, FROUND, FFLOOR, 563 /// FMINNUM/FMAXNUM - Perform floating-point minimum or maximum on two 564 /// values. 565 /// In the case where a single input is NaN, the non-NaN input is returned. 566 /// 567 /// The return value of (FMINNUM 0.0, -0.0) could be either 0.0 or -0.0. 568 FMINNUM, FMAXNUM, 569 /// FMINNAN/FMAXNAN - Behave identically to FMINNUM/FMAXNUM, except that 570 /// when a single input is NaN, NaN is returned. 571 FMINNAN, FMAXNAN, 572 573 /// FSINCOS - Compute both fsin and fcos as a single operation. 574 FSINCOS, 575 576 /// LOAD and STORE have token chains as their first operand, then the same 577 /// operands as an LLVM load/store instruction, then an offset node that 578 /// is added / subtracted from the base pointer to form the address (for 579 /// indexed memory ops). 580 LOAD, STORE, 581 582 /// DYNAMIC_STACKALLOC - Allocate some number of bytes on the stack aligned 583 /// to a specified boundary. This node always has two return values: a new 584 /// stack pointer value and a chain. The first operand is the token chain, 585 /// the second is the number of bytes to allocate, and the third is the 586 /// alignment boundary. The size is guaranteed to be a multiple of the 587 /// stack alignment, and the alignment is guaranteed to be bigger than the 588 /// stack alignment (if required) or 0 to get standard stack alignment. 589 DYNAMIC_STACKALLOC, 590 591 /// Control flow instructions. These all have token chains. 592 593 /// BR - Unconditional branch. The first operand is the chain 594 /// operand, the second is the MBB to branch to. 595 BR, 596 597 /// BRIND - Indirect branch. The first operand is the chain, the second 598 /// is the value to branch to, which must be of the same type as the 599 /// target's pointer type. 600 BRIND, 601 602 /// BR_JT - Jumptable branch. The first operand is the chain, the second 603 /// is the jumptable index, the last one is the jumptable entry index. 604 BR_JT, 605 606 /// BRCOND - Conditional branch. The first operand is the chain, the 607 /// second is the condition, the third is the block to branch to if the 608 /// condition is true. If the type of the condition is not i1, then the 609 /// high bits must conform to getBooleanContents. 610 BRCOND, 611 612 /// BR_CC - Conditional branch. The behavior is like that of SELECT_CC, in 613 /// that the condition is represented as condition code, and two nodes to 614 /// compare, rather than as a combined SetCC node. The operands in order 615 /// are chain, cc, lhs, rhs, block to branch to if condition is true. 616 BR_CC, 617 618 /// INLINEASM - Represents an inline asm block. This node always has two 619 /// return values: a chain and a flag result. The inputs are as follows: 620 /// Operand #0 : Input chain. 621 /// Operand #1 : a ExternalSymbolSDNode with a pointer to the asm string. 622 /// Operand #2 : a MDNodeSDNode with the !srcloc metadata. 623 /// Operand #3 : HasSideEffect, IsAlignStack bits. 624 /// After this, it is followed by a list of operands with this format: 625 /// ConstantSDNode: Flags that encode whether it is a mem or not, the 626 /// of operands that follow, etc. See InlineAsm.h. 627 /// ... however many operands ... 628 /// Operand #last: Optional, an incoming flag. 629 /// 630 /// The variable width operands are required to represent target addressing 631 /// modes as a single "operand", even though they may have multiple 632 /// SDOperands. 633 INLINEASM, 634 635 /// EH_LABEL - Represents a label in mid basic block used to track 636 /// locations needed for debug and exception handling tables. These nodes 637 /// take a chain as input and return a chain. 638 EH_LABEL, 639 640 /// CATCHPAD - Represents a catchpad instruction. 641 CATCHPAD, 642 643 /// CATCHRET - Represents a return from a catch block funclet. Used for 644 /// MSVC compatible exception handling. Takes a chain operand and a 645 /// destination basic block operand. 646 CATCHRET, 647 648 /// CLEANUPRET - Represents a return from a cleanup block funclet. Used for 649 /// MSVC compatible exception handling. Takes only a chain operand. 650 CLEANUPRET, 651 652 /// STACKSAVE - STACKSAVE has one operand, an input chain. It produces a 653 /// value, the same type as the pointer type for the system, and an output 654 /// chain. 655 STACKSAVE, 656 657 /// STACKRESTORE has two operands, an input chain and a pointer to restore 658 /// to it returns an output chain. 659 STACKRESTORE, 660 661 /// CALLSEQ_START/CALLSEQ_END - These operators mark the beginning and end 662 /// of a call sequence, and carry arbitrary information that target might 663 /// want to know. The first operand is a chain, the rest are specified by 664 /// the target and not touched by the DAG optimizers. 665 /// Targets that may use stack to pass call arguments define additional 666 /// operands: 667 /// - size of the call frame part that must be set up within the 668 /// CALLSEQ_START..CALLSEQ_END pair, 669 /// - part of the call frame prepared prior to CALLSEQ_START. 670 /// Both these parameters must be constants, their sum is the total call 671 /// frame size. 672 /// CALLSEQ_START..CALLSEQ_END pairs may not be nested. 673 CALLSEQ_START, // Beginning of a call sequence 674 CALLSEQ_END, // End of a call sequence 675 676 /// VAARG - VAARG has four operands: an input chain, a pointer, a SRCVALUE, 677 /// and the alignment. It returns a pair of values: the vaarg value and a 678 /// new chain. 679 VAARG, 680 681 /// VACOPY - VACOPY has 5 operands: an input chain, a destination pointer, 682 /// a source pointer, a SRCVALUE for the destination, and a SRCVALUE for the 683 /// source. 684 VACOPY, 685 686 /// VAEND, VASTART - VAEND and VASTART have three operands: an input chain, 687 /// pointer, and a SRCVALUE. 688 VAEND, VASTART, 689 690 /// SRCVALUE - This is a node type that holds a Value* that is used to 691 /// make reference to a value in the LLVM IR. 692 SRCVALUE, 693 694 /// MDNODE_SDNODE - This is a node that holdes an MDNode*, which is used to 695 /// reference metadata in the IR. 696 MDNODE_SDNODE, 697 698 /// PCMARKER - This corresponds to the pcmarker intrinsic. 699 PCMARKER, 700 701 /// READCYCLECOUNTER - This corresponds to the readcyclecounter intrinsic. 702 /// It produces a chain and one i64 value. The only operand is a chain. 703 /// If i64 is not legal, the result will be expanded into smaller values. 704 /// Still, it returns an i64, so targets should set legality for i64. 705 /// The result is the content of the architecture-specific cycle 706 /// counter-like register (or other high accuracy low latency clock source). 707 READCYCLECOUNTER, 708 709 /// HANDLENODE node - Used as a handle for various purposes. 710 HANDLENODE, 711 712 /// INIT_TRAMPOLINE - This corresponds to the init_trampoline intrinsic. It 713 /// takes as input a token chain, the pointer to the trampoline, the pointer 714 /// to the nested function, the pointer to pass for the 'nest' parameter, a 715 /// SRCVALUE for the trampoline and another for the nested function 716 /// (allowing targets to access the original Function*). 717 /// It produces a token chain as output. 718 INIT_TRAMPOLINE, 719 720 /// ADJUST_TRAMPOLINE - This corresponds to the adjust_trampoline intrinsic. 721 /// It takes a pointer to the trampoline and produces a (possibly) new 722 /// pointer to the same trampoline with platform-specific adjustments 723 /// applied. The pointer it returns points to an executable block of code. 724 ADJUST_TRAMPOLINE, 725 726 /// TRAP - Trapping instruction 727 TRAP, 728 729 /// DEBUGTRAP - Trap intended to get the attention of a debugger. 730 DEBUGTRAP, 731 732 /// PREFETCH - This corresponds to a prefetch intrinsic. The first operand 733 /// is the chain. The other operands are the address to prefetch, 734 /// read / write specifier, locality specifier and instruction / data cache 735 /// specifier. 736 PREFETCH, 737 738 /// OUTCHAIN = ATOMIC_FENCE(INCHAIN, ordering, scope) 739 /// This corresponds to the fence instruction. It takes an input chain, and 740 /// two integer constants: an AtomicOrdering and a SynchronizationScope. 741 ATOMIC_FENCE, 742 743 /// Val, OUTCHAIN = ATOMIC_LOAD(INCHAIN, ptr) 744 /// This corresponds to "load atomic" instruction. 745 ATOMIC_LOAD, 746 747 /// OUTCHAIN = ATOMIC_STORE(INCHAIN, ptr, val) 748 /// This corresponds to "store atomic" instruction. 749 ATOMIC_STORE, 750 751 /// Val, OUTCHAIN = ATOMIC_CMP_SWAP(INCHAIN, ptr, cmp, swap) 752 /// For double-word atomic operations: 753 /// ValLo, ValHi, OUTCHAIN = ATOMIC_CMP_SWAP(INCHAIN, ptr, cmpLo, cmpHi, 754 /// swapLo, swapHi) 755 /// This corresponds to the cmpxchg instruction. 756 ATOMIC_CMP_SWAP, 757 758 /// Val, Success, OUTCHAIN 759 /// = ATOMIC_CMP_SWAP_WITH_SUCCESS(INCHAIN, ptr, cmp, swap) 760 /// N.b. this is still a strong cmpxchg operation, so 761 /// Success == "Val == cmp". 762 ATOMIC_CMP_SWAP_WITH_SUCCESS, 763 764 /// Val, OUTCHAIN = ATOMIC_SWAP(INCHAIN, ptr, amt) 765 /// Val, OUTCHAIN = ATOMIC_LOAD_[OpName](INCHAIN, ptr, amt) 766 /// For double-word atomic operations: 767 /// ValLo, ValHi, OUTCHAIN = ATOMIC_SWAP(INCHAIN, ptr, amtLo, amtHi) 768 /// ValLo, ValHi, OUTCHAIN = ATOMIC_LOAD_[OpName](INCHAIN, ptr, amtLo, amtHi) 769 /// These correspond to the atomicrmw instruction. 770 ATOMIC_SWAP, 771 ATOMIC_LOAD_ADD, 772 ATOMIC_LOAD_SUB, 773 ATOMIC_LOAD_AND, 774 ATOMIC_LOAD_OR, 775 ATOMIC_LOAD_XOR, 776 ATOMIC_LOAD_NAND, 777 ATOMIC_LOAD_MIN, 778 ATOMIC_LOAD_MAX, 779 ATOMIC_LOAD_UMIN, 780 ATOMIC_LOAD_UMAX, 781 782 // Masked load and store - consecutive vector load and store operations 783 // with additional mask operand that prevents memory accesses to the 784 // masked-off lanes. 785 MLOAD, MSTORE, 786 787 // Masked gather and scatter - load and store operations for a vector of 788 // random addresses with additional mask operand that prevents memory 789 // accesses to the masked-off lanes. 790 MGATHER, MSCATTER, 791 792 /// This corresponds to the llvm.lifetime.* intrinsics. The first operand 793 /// is the chain and the second operand is the alloca pointer. 794 LIFETIME_START, LIFETIME_END, 795 796 /// GC_TRANSITION_START/GC_TRANSITION_END - These operators mark the 797 /// beginning and end of GC transition sequence, and carry arbitrary 798 /// information that target might need for lowering. The first operand is 799 /// a chain, the rest are specified by the target and not touched by the DAG 800 /// optimizers. GC_TRANSITION_START..GC_TRANSITION_END pairs may not be 801 /// nested. 802 GC_TRANSITION_START, 803 GC_TRANSITION_END, 804 805 /// GET_DYNAMIC_AREA_OFFSET - get offset from native SP to the address of 806 /// the most recent dynamic alloca. For most targets that would be 0, but 807 /// for some others (e.g. PowerPC, PowerPC64) that would be compile-time 808 /// known nonzero constant. The only operand here is the chain. 809 GET_DYNAMIC_AREA_OFFSET, 810 811 /// Generic reduction nodes. These nodes represent horizontal vector 812 /// reduction operations, producing a scalar result. 813 /// The STRICT variants perform reductions in sequential order. The first 814 /// operand is an initial scalar accumulator value, and the second operand 815 /// is the vector to reduce. 816 VECREDUCE_STRICT_FADD, VECREDUCE_STRICT_FMUL, 817 /// These reductions are non-strict, and have a single vector operand. 818 VECREDUCE_FADD, VECREDUCE_FMUL, 819 VECREDUCE_ADD, VECREDUCE_MUL, 820 VECREDUCE_AND, VECREDUCE_OR, VECREDUCE_XOR, 821 VECREDUCE_SMAX, VECREDUCE_SMIN, VECREDUCE_UMAX, VECREDUCE_UMIN, 822 /// FMIN/FMAX nodes can have flags, for NaN/NoNaN variants. 823 VECREDUCE_FMAX, VECREDUCE_FMIN, 824 825 /// BUILTIN_OP_END - This must be the last enum value in this list. 826 /// The target-specific pre-isel opcode values start here. 827 BUILTIN_OP_END 828 }; 829 830 /// FIRST_TARGET_MEMORY_OPCODE - Target-specific pre-isel operations 831 /// which do not reference a specific memory location should be less than 832 /// this value. Those that do must not be less than this value, and can 833 /// be used with SelectionDAG::getMemIntrinsicNode. 834 static const int FIRST_TARGET_MEMORY_OPCODE = BUILTIN_OP_END+300; 835 836 //===--------------------------------------------------------------------===// 837 /// MemIndexedMode enum - This enum defines the load / store indexed 838 /// addressing modes. 839 /// 840 /// UNINDEXED "Normal" load / store. The effective address is already 841 /// computed and is available in the base pointer. The offset 842 /// operand is always undefined. In addition to producing a 843 /// chain, an unindexed load produces one value (result of the 844 /// load); an unindexed store does not produce a value. 845 /// 846 /// PRE_INC Similar to the unindexed mode where the effective address is 847 /// PRE_DEC the value of the base pointer add / subtract the offset. 848 /// It considers the computation as being folded into the load / 849 /// store operation (i.e. the load / store does the address 850 /// computation as well as performing the memory transaction). 851 /// The base operand is always undefined. In addition to 852 /// producing a chain, pre-indexed load produces two values 853 /// (result of the load and the result of the address 854 /// computation); a pre-indexed store produces one value (result 855 /// of the address computation). 856 /// 857 /// POST_INC The effective address is the value of the base pointer. The 858 /// POST_DEC value of the offset operand is then added to / subtracted 859 /// from the base after memory transaction. In addition to 860 /// producing a chain, post-indexed load produces two values 861 /// (the result of the load and the result of the base +/- offset 862 /// computation); a post-indexed store produces one value (the 863 /// the result of the base +/- offset computation). 864 enum MemIndexedMode { 865 UNINDEXED = 0, 866 PRE_INC, 867 PRE_DEC, 868 POST_INC, 869 POST_DEC 870 }; 871 872 static const int LAST_INDEXED_MODE = POST_DEC + 1; 873 874 //===--------------------------------------------------------------------===// 875 /// LoadExtType enum - This enum defines the three variants of LOADEXT 876 /// (load with extension). 877 /// 878 /// SEXTLOAD loads the integer operand and sign extends it to a larger 879 /// integer result type. 880 /// ZEXTLOAD loads the integer operand and zero extends it to a larger 881 /// integer result type. 882 /// EXTLOAD is used for two things: floating point extending loads and 883 /// integer extending loads [the top bits are undefined]. 884 enum LoadExtType { 885 NON_EXTLOAD = 0, 886 EXTLOAD, 887 SEXTLOAD, 888 ZEXTLOAD 889 }; 890 891 static const int LAST_LOADEXT_TYPE = ZEXTLOAD + 1; 892 893 NodeType getExtForLoadExtType(bool IsFP, LoadExtType); 894 895 //===--------------------------------------------------------------------===// 896 /// ISD::CondCode enum - These are ordered carefully to make the bitfields 897 /// below work out, when considering SETFALSE (something that never exists 898 /// dynamically) as 0. "U" -> Unsigned (for integer operands) or Unordered 899 /// (for floating point), "L" -> Less than, "G" -> Greater than, "E" -> Equal 900 /// to. If the "N" column is 1, the result of the comparison is undefined if 901 /// the input is a NAN. 902 /// 903 /// All of these (except for the 'always folded ops') should be handled for 904 /// floating point. For integer, only the SETEQ,SETNE,SETLT,SETLE,SETGT, 905 /// SETGE,SETULT,SETULE,SETUGT, and SETUGE opcodes are used. 906 /// 907 /// Note that these are laid out in a specific order to allow bit-twiddling 908 /// to transform conditions. 909 enum CondCode { 910 // Opcode N U L G E Intuitive operation 911 SETFALSE, // 0 0 0 0 Always false (always folded) 912 SETOEQ, // 0 0 0 1 True if ordered and equal 913 SETOGT, // 0 0 1 0 True if ordered and greater than 914 SETOGE, // 0 0 1 1 True if ordered and greater than or equal 915 SETOLT, // 0 1 0 0 True if ordered and less than 916 SETOLE, // 0 1 0 1 True if ordered and less than or equal 917 SETONE, // 0 1 1 0 True if ordered and operands are unequal 918 SETO, // 0 1 1 1 True if ordered (no nans) 919 SETUO, // 1 0 0 0 True if unordered: isnan(X) | isnan(Y) 920 SETUEQ, // 1 0 0 1 True if unordered or equal 921 SETUGT, // 1 0 1 0 True if unordered or greater than 922 SETUGE, // 1 0 1 1 True if unordered, greater than, or equal 923 SETULT, // 1 1 0 0 True if unordered or less than 924 SETULE, // 1 1 0 1 True if unordered, less than, or equal 925 SETUNE, // 1 1 1 0 True if unordered or not equal 926 SETTRUE, // 1 1 1 1 Always true (always folded) 927 // Don't care operations: undefined if the input is a nan. 928 SETFALSE2, // 1 X 0 0 0 Always false (always folded) 929 SETEQ, // 1 X 0 0 1 True if equal 930 SETGT, // 1 X 0 1 0 True if greater than 931 SETGE, // 1 X 0 1 1 True if greater than or equal 932 SETLT, // 1 X 1 0 0 True if less than 933 SETLE, // 1 X 1 0 1 True if less than or equal 934 SETNE, // 1 X 1 1 0 True if not equal 935 SETTRUE2, // 1 X 1 1 1 Always true (always folded) 936 937 SETCC_INVALID // Marker value. 938 }; 939 940 /// Return true if this is a setcc instruction that performs a signed 941 /// comparison when used with integer operands. 942 inline bool isSignedIntSetCC(CondCode Code) { 943 return Code == SETGT || Code == SETGE || Code == SETLT || Code == SETLE; 944 } 945 946 /// Return true if this is a setcc instruction that performs an unsigned 947 /// comparison when used with integer operands. 948 inline bool isUnsignedIntSetCC(CondCode Code) { 949 return Code == SETUGT || Code == SETUGE || Code == SETULT || Code == SETULE; 950 } 951 952 /// Return true if the specified condition returns true if the two operands to 953 /// the condition are equal. Note that if one of the two operands is a NaN, 954 /// this value is meaningless. 955 inline bool isTrueWhenEqual(CondCode Cond) { 956 return ((int)Cond & 1) != 0; 957 } 958 959 /// This function returns 0 if the condition is always false if an operand is 960 /// a NaN, 1 if the condition is always true if the operand is a NaN, and 2 if 961 /// the condition is undefined if the operand is a NaN. 962 inline unsigned getUnorderedFlavor(CondCode Cond) { 963 return ((int)Cond >> 3) & 3; 964 } 965 966 /// Return the operation corresponding to !(X op Y), where 'op' is a valid 967 /// SetCC operation. 968 CondCode getSetCCInverse(CondCode Operation, bool isInteger); 969 970 /// Return the operation corresponding to (Y op X) when given the operation 971 /// for (X op Y). 972 CondCode getSetCCSwappedOperands(CondCode Operation); 973 974 /// Return the result of a logical OR between different comparisons of 975 /// identical values: ((X op1 Y) | (X op2 Y)). This function returns 976 /// SETCC_INVALID if it is not possible to represent the resultant comparison. 977 CondCode getSetCCOrOperation(CondCode Op1, CondCode Op2, bool isInteger); 978 979 /// Return the result of a logical AND between different comparisons of 980 /// identical values: ((X op1 Y) & (X op2 Y)). This function returns 981 /// SETCC_INVALID if it is not possible to represent the resultant comparison. 982 CondCode getSetCCAndOperation(CondCode Op1, CondCode Op2, bool isInteger); 983 984} // end llvm::ISD namespace 985 986} // end llvm namespace 987 988#endif 989