ISDOpcodes.h revision 309124
1//===-- llvm/CodeGen/ISDOpcodes.h - CodeGen opcodes -------------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file declares codegen opcodes and related utilities. 11// 12//===----------------------------------------------------------------------===// 13 14#ifndef LLVM_CODEGEN_ISDOPCODES_H 15#define LLVM_CODEGEN_ISDOPCODES_H 16 17namespace llvm { 18 19/// ISD namespace - This namespace contains an enum which represents all of the 20/// SelectionDAG node types and value types. 21/// 22namespace ISD { 23 24 //===--------------------------------------------------------------------===// 25 /// ISD::NodeType enum - This enum defines the target-independent operators 26 /// for a SelectionDAG. 27 /// 28 /// Targets may also define target-dependent operator codes for SDNodes. For 29 /// example, on x86, these are the enum values in the X86ISD namespace. 30 /// Targets should aim to use target-independent operators to model their 31 /// instruction sets as much as possible, and only use target-dependent 32 /// operators when they have special requirements. 33 /// 34 /// Finally, during and after selection proper, SNodes may use special 35 /// operator codes that correspond directly with MachineInstr opcodes. These 36 /// are used to represent selected instructions. See the isMachineOpcode() 37 /// and getMachineOpcode() member functions of SDNode. 38 /// 39 enum NodeType { 40 /// DELETED_NODE - This is an illegal value that is used to catch 41 /// errors. This opcode is not a legal opcode for any node. 42 DELETED_NODE, 43 44 /// EntryToken - This is the marker used to indicate the start of a region. 45 EntryToken, 46 47 /// TokenFactor - This node takes multiple tokens as input and produces a 48 /// single token result. This is used to represent the fact that the operand 49 /// operators are independent of each other. 50 TokenFactor, 51 52 /// AssertSext, AssertZext - These nodes record if a register contains a 53 /// value that has already been zero or sign extended from a narrower type. 54 /// These nodes take two operands. The first is the node that has already 55 /// been extended, and the second is a value type node indicating the width 56 /// of the extension 57 AssertSext, AssertZext, 58 59 /// Various leaf nodes. 60 BasicBlock, VALUETYPE, CONDCODE, Register, RegisterMask, 61 Constant, ConstantFP, 62 GlobalAddress, GlobalTLSAddress, FrameIndex, 63 JumpTable, ConstantPool, ExternalSymbol, BlockAddress, 64 65 /// The address of the GOT 66 GLOBAL_OFFSET_TABLE, 67 68 /// FRAMEADDR, RETURNADDR - These nodes represent llvm.frameaddress and 69 /// llvm.returnaddress on the DAG. These nodes take one operand, the index 70 /// of the frame or return address to return. An index of zero corresponds 71 /// to the current function's frame or return address, an index of one to 72 /// the parent's frame or return address, and so on. 73 FRAMEADDR, RETURNADDR, 74 75 /// LOCAL_RECOVER - Represents the llvm.localrecover intrinsic. 76 /// Materializes the offset from the local object pointer of another 77 /// function to a particular local object passed to llvm.localescape. The 78 /// operand is the MCSymbol label used to represent this offset, since 79 /// typically the offset is not known until after code generation of the 80 /// parent. 81 LOCAL_RECOVER, 82 83 /// READ_REGISTER, WRITE_REGISTER - This node represents llvm.register on 84 /// the DAG, which implements the named register global variables extension. 85 READ_REGISTER, 86 WRITE_REGISTER, 87 88 /// FRAME_TO_ARGS_OFFSET - This node represents offset from frame pointer to 89 /// first (possible) on-stack argument. This is needed for correct stack 90 /// adjustment during unwind. 91 FRAME_TO_ARGS_OFFSET, 92 93 /// EH_DWARF_CFA - This node represents the pointer to the DWARF Canonical 94 /// Frame Address (CFA), generally the value of the stack pointer at the 95 /// call site in the previous frame. 96 EH_DWARF_CFA, 97 98 /// OUTCHAIN = EH_RETURN(INCHAIN, OFFSET, HANDLER) - This node represents 99 /// 'eh_return' gcc dwarf builtin, which is used to return from 100 /// exception. The general meaning is: adjust stack by OFFSET and pass 101 /// execution to HANDLER. Many platform-related details also :) 102 EH_RETURN, 103 104 /// RESULT, OUTCHAIN = EH_SJLJ_SETJMP(INCHAIN, buffer) 105 /// This corresponds to the eh.sjlj.setjmp intrinsic. 106 /// It takes an input chain and a pointer to the jump buffer as inputs 107 /// and returns an outchain. 108 EH_SJLJ_SETJMP, 109 110 /// OUTCHAIN = EH_SJLJ_LONGJMP(INCHAIN, buffer) 111 /// This corresponds to the eh.sjlj.longjmp intrinsic. 112 /// It takes an input chain and a pointer to the jump buffer as inputs 113 /// and returns an outchain. 114 EH_SJLJ_LONGJMP, 115 116 /// OUTCHAIN = EH_SJLJ_SETUP_DISPATCH(INCHAIN) 117 /// The target initializes the dispatch table here. 118 EH_SJLJ_SETUP_DISPATCH, 119 120 /// TargetConstant* - Like Constant*, but the DAG does not do any folding, 121 /// simplification, or lowering of the constant. They are used for constants 122 /// which are known to fit in the immediate fields of their users, or for 123 /// carrying magic numbers which are not values which need to be 124 /// materialized in registers. 125 TargetConstant, 126 TargetConstantFP, 127 128 /// TargetGlobalAddress - Like GlobalAddress, but the DAG does no folding or 129 /// anything else with this node, and this is valid in the target-specific 130 /// dag, turning into a GlobalAddress operand. 131 TargetGlobalAddress, 132 TargetGlobalTLSAddress, 133 TargetFrameIndex, 134 TargetJumpTable, 135 TargetConstantPool, 136 TargetExternalSymbol, 137 TargetBlockAddress, 138 139 MCSymbol, 140 141 /// TargetIndex - Like a constant pool entry, but with completely 142 /// target-dependent semantics. Holds target flags, a 32-bit index, and a 143 /// 64-bit index. Targets can use this however they like. 144 TargetIndex, 145 146 /// RESULT = INTRINSIC_WO_CHAIN(INTRINSICID, arg1, arg2, ...) 147 /// This node represents a target intrinsic function with no side effects. 148 /// The first operand is the ID number of the intrinsic from the 149 /// llvm::Intrinsic namespace. The operands to the intrinsic follow. The 150 /// node returns the result of the intrinsic. 151 INTRINSIC_WO_CHAIN, 152 153 /// RESULT,OUTCHAIN = INTRINSIC_W_CHAIN(INCHAIN, INTRINSICID, arg1, ...) 154 /// This node represents a target intrinsic function with side effects that 155 /// returns a result. The first operand is a chain pointer. The second is 156 /// the ID number of the intrinsic from the llvm::Intrinsic namespace. The 157 /// operands to the intrinsic follow. The node has two results, the result 158 /// of the intrinsic and an output chain. 159 INTRINSIC_W_CHAIN, 160 161 /// OUTCHAIN = INTRINSIC_VOID(INCHAIN, INTRINSICID, arg1, arg2, ...) 162 /// This node represents a target intrinsic function with side effects that 163 /// does not return a result. The first operand is a chain pointer. The 164 /// second is the ID number of the intrinsic from the llvm::Intrinsic 165 /// namespace. The operands to the intrinsic follow. 166 INTRINSIC_VOID, 167 168 /// CopyToReg - This node has three operands: a chain, a register number to 169 /// set to this value, and a value. 170 CopyToReg, 171 172 /// CopyFromReg - This node indicates that the input value is a virtual or 173 /// physical register that is defined outside of the scope of this 174 /// SelectionDAG. The register is available from the RegisterSDNode object. 175 CopyFromReg, 176 177 /// UNDEF - An undefined node. 178 UNDEF, 179 180 /// EXTRACT_ELEMENT - This is used to get the lower or upper (determined by 181 /// a Constant, which is required to be operand #1) half of the integer or 182 /// float value specified as operand #0. This is only for use before 183 /// legalization, for values that will be broken into multiple registers. 184 EXTRACT_ELEMENT, 185 186 /// BUILD_PAIR - This is the opposite of EXTRACT_ELEMENT in some ways. 187 /// Given two values of the same integer value type, this produces a value 188 /// twice as big. Like EXTRACT_ELEMENT, this can only be used before 189 /// legalization. 190 BUILD_PAIR, 191 192 /// MERGE_VALUES - This node takes multiple discrete operands and returns 193 /// them all as its individual results. This nodes has exactly the same 194 /// number of inputs and outputs. This node is useful for some pieces of the 195 /// code generator that want to think about a single node with multiple 196 /// results, not multiple nodes. 197 MERGE_VALUES, 198 199 /// Simple integer binary arithmetic operators. 200 ADD, SUB, MUL, SDIV, UDIV, SREM, UREM, 201 202 /// SMUL_LOHI/UMUL_LOHI - Multiply two integers of type iN, producing 203 /// a signed/unsigned value of type i[2*N], and return the full value as 204 /// two results, each of type iN. 205 SMUL_LOHI, UMUL_LOHI, 206 207 /// SDIVREM/UDIVREM - Divide two integers and produce both a quotient and 208 /// remainder result. 209 SDIVREM, UDIVREM, 210 211 /// CARRY_FALSE - This node is used when folding other nodes, 212 /// like ADDC/SUBC, which indicate the carry result is always false. 213 CARRY_FALSE, 214 215 /// Carry-setting nodes for multiple precision addition and subtraction. 216 /// These nodes take two operands of the same value type, and produce two 217 /// results. The first result is the normal add or sub result, the second 218 /// result is the carry flag result. 219 ADDC, SUBC, 220 221 /// Carry-using nodes for multiple precision addition and subtraction. These 222 /// nodes take three operands: The first two are the normal lhs and rhs to 223 /// the add or sub, and the third is the input carry flag. These nodes 224 /// produce two results; the normal result of the add or sub, and the output 225 /// carry flag. These nodes both read and write a carry flag to allow them 226 /// to them to be chained together for add and sub of arbitrarily large 227 /// values. 228 ADDE, SUBE, 229 230 /// RESULT, BOOL = [SU]ADDO(LHS, RHS) - Overflow-aware nodes for addition. 231 /// These nodes take two operands: the normal LHS and RHS to the add. They 232 /// produce two results: the normal result of the add, and a boolean that 233 /// indicates if an overflow occurred (*not* a flag, because it may be store 234 /// to memory, etc.). If the type of the boolean is not i1 then the high 235 /// bits conform to getBooleanContents. 236 /// These nodes are generated from llvm.[su]add.with.overflow intrinsics. 237 SADDO, UADDO, 238 239 /// Same for subtraction. 240 SSUBO, USUBO, 241 242 /// Same for multiplication. 243 SMULO, UMULO, 244 245 /// Simple binary floating point operators. 246 FADD, FSUB, FMUL, FDIV, FREM, 247 248 /// FMA - Perform a * b + c with no intermediate rounding step. 249 FMA, 250 251 /// FMAD - Perform a * b + c, while getting the same result as the 252 /// separately rounded operations. 253 FMAD, 254 255 /// FCOPYSIGN(X, Y) - Return the value of X with the sign of Y. NOTE: This 256 /// DAG node does not require that X and Y have the same type, just that 257 /// they are both floating point. X and the result must have the same type. 258 /// FCOPYSIGN(f32, f64) is allowed. 259 FCOPYSIGN, 260 261 /// INT = FGETSIGN(FP) - Return the sign bit of the specified floating point 262 /// value as an integer 0/1 value. 263 FGETSIGN, 264 265 /// Returns platform specific canonical encoding of a floating point number. 266 FCANONICALIZE, 267 268 /// BUILD_VECTOR(ELT0, ELT1, ELT2, ELT3,...) - Return a vector with the 269 /// specified, possibly variable, elements. The number of elements is 270 /// required to be a power of two. The types of the operands must all be 271 /// the same and must match the vector element type, except that integer 272 /// types are allowed to be larger than the element type, in which case 273 /// the operands are implicitly truncated. 274 BUILD_VECTOR, 275 276 /// INSERT_VECTOR_ELT(VECTOR, VAL, IDX) - Returns VECTOR with the element 277 /// at IDX replaced with VAL. If the type of VAL is larger than the vector 278 /// element type then VAL is truncated before replacement. 279 INSERT_VECTOR_ELT, 280 281 /// EXTRACT_VECTOR_ELT(VECTOR, IDX) - Returns a single element from VECTOR 282 /// identified by the (potentially variable) element number IDX. If the 283 /// return type is an integer type larger than the element type of the 284 /// vector, the result is extended to the width of the return type. 285 EXTRACT_VECTOR_ELT, 286 287 /// CONCAT_VECTORS(VECTOR0, VECTOR1, ...) - Given a number of values of 288 /// vector type with the same length and element type, this produces a 289 /// concatenated vector result value, with length equal to the sum of the 290 /// lengths of the input vectors. 291 CONCAT_VECTORS, 292 293 /// INSERT_SUBVECTOR(VECTOR1, VECTOR2, IDX) - Returns a vector 294 /// with VECTOR2 inserted into VECTOR1 at the (potentially 295 /// variable) element number IDX, which must be a multiple of the 296 /// VECTOR2 vector length. The elements of VECTOR1 starting at 297 /// IDX are overwritten with VECTOR2. Elements IDX through 298 /// vector_length(VECTOR2) must be valid VECTOR1 indices. 299 INSERT_SUBVECTOR, 300 301 /// EXTRACT_SUBVECTOR(VECTOR, IDX) - Returns a subvector from VECTOR (an 302 /// vector value) starting with the element number IDX, which must be a 303 /// constant multiple of the result vector length. 304 EXTRACT_SUBVECTOR, 305 306 /// VECTOR_SHUFFLE(VEC1, VEC2) - Returns a vector, of the same type as 307 /// VEC1/VEC2. A VECTOR_SHUFFLE node also contains an array of constant int 308 /// values that indicate which value (or undef) each result element will 309 /// get. These constant ints are accessible through the 310 /// ShuffleVectorSDNode class. This is quite similar to the Altivec 311 /// 'vperm' instruction, except that the indices must be constants and are 312 /// in terms of the element size of VEC1/VEC2, not in terms of bytes. 313 VECTOR_SHUFFLE, 314 315 /// SCALAR_TO_VECTOR(VAL) - This represents the operation of loading a 316 /// scalar value into element 0 of the resultant vector type. The top 317 /// elements 1 to N-1 of the N-element vector are undefined. The type 318 /// of the operand must match the vector element type, except when they 319 /// are integer types. In this case the operand is allowed to be wider 320 /// than the vector element type, and is implicitly truncated to it. 321 SCALAR_TO_VECTOR, 322 323 /// MULHU/MULHS - Multiply high - Multiply two integers of type iN, 324 /// producing an unsigned/signed value of type i[2*N], then return the top 325 /// part. 326 MULHU, MULHS, 327 328 /// [US]{MIN/MAX} - Binary minimum or maximum or signed or unsigned 329 /// integers. 330 SMIN, SMAX, UMIN, UMAX, 331 332 /// Bitwise operators - logical and, logical or, logical xor. 333 AND, OR, XOR, 334 335 /// Shift and rotation operations. After legalization, the type of the 336 /// shift amount is known to be TLI.getShiftAmountTy(). Before legalization 337 /// the shift amount can be any type, but care must be taken to ensure it is 338 /// large enough. TLI.getShiftAmountTy() is i8 on some targets, but before 339 /// legalization, types like i1024 can occur and i8 doesn't have enough bits 340 /// to represent the shift amount. 341 /// When the 1st operand is a vector, the shift amount must be in the same 342 /// type. (TLI.getShiftAmountTy() will return the same type when the input 343 /// type is a vector.) 344 SHL, SRA, SRL, ROTL, ROTR, 345 346 /// Byte Swap and Counting operators. 347 BSWAP, CTTZ, CTLZ, CTPOP, BITREVERSE, 348 349 /// Bit counting operators with an undefined result for zero inputs. 350 CTTZ_ZERO_UNDEF, CTLZ_ZERO_UNDEF, 351 352 /// Select(COND, TRUEVAL, FALSEVAL). If the type of the boolean COND is not 353 /// i1 then the high bits must conform to getBooleanContents. 354 SELECT, 355 356 /// Select with a vector condition (op #0) and two vector operands (ops #1 357 /// and #2), returning a vector result. All vectors have the same length. 358 /// Much like the scalar select and setcc, each bit in the condition selects 359 /// whether the corresponding result element is taken from op #1 or op #2. 360 /// At first, the VSELECT condition is of vXi1 type. Later, targets may 361 /// change the condition type in order to match the VSELECT node using a 362 /// pattern. The condition follows the BooleanContent format of the target. 363 VSELECT, 364 365 /// Select with condition operator - This selects between a true value and 366 /// a false value (ops #2 and #3) based on the boolean result of comparing 367 /// the lhs and rhs (ops #0 and #1) of a conditional expression with the 368 /// condition code in op #4, a CondCodeSDNode. 369 SELECT_CC, 370 371 /// SetCC operator - This evaluates to a true value iff the condition is 372 /// true. If the result value type is not i1 then the high bits conform 373 /// to getBooleanContents. The operands to this are the left and right 374 /// operands to compare (ops #0, and #1) and the condition code to compare 375 /// them with (op #2) as a CondCodeSDNode. If the operands are vector types 376 /// then the result type must also be a vector type. 377 SETCC, 378 379 /// Like SetCC, ops #0 and #1 are the LHS and RHS operands to compare, but 380 /// op #2 is a *carry value*. This operator checks the result of 381 /// "LHS - RHS - Carry", and can be used to compare two wide integers: 382 /// (setcce lhshi rhshi (subc lhslo rhslo) cc). Only valid for integers. 383 SETCCE, 384 385 /// SHL_PARTS/SRA_PARTS/SRL_PARTS - These operators are used for expanded 386 /// integer shift operations. The operation ordering is: 387 /// [Lo,Hi] = op [LoLHS,HiLHS], Amt 388 SHL_PARTS, SRA_PARTS, SRL_PARTS, 389 390 /// Conversion operators. These are all single input single output 391 /// operations. For all of these, the result type must be strictly 392 /// wider or narrower (depending on the operation) than the source 393 /// type. 394 395 /// SIGN_EXTEND - Used for integer types, replicating the sign bit 396 /// into new bits. 397 SIGN_EXTEND, 398 399 /// ZERO_EXTEND - Used for integer types, zeroing the new bits. 400 ZERO_EXTEND, 401 402 /// ANY_EXTEND - Used for integer types. The high bits are undefined. 403 ANY_EXTEND, 404 405 /// TRUNCATE - Completely drop the high bits. 406 TRUNCATE, 407 408 /// [SU]INT_TO_FP - These operators convert integers (whose interpreted sign 409 /// depends on the first letter) to floating point. 410 SINT_TO_FP, 411 UINT_TO_FP, 412 413 /// SIGN_EXTEND_INREG - This operator atomically performs a SHL/SRA pair to 414 /// sign extend a small value in a large integer register (e.g. sign 415 /// extending the low 8 bits of a 32-bit register to fill the top 24 bits 416 /// with the 7th bit). The size of the smaller type is indicated by the 1th 417 /// operand, a ValueType node. 418 SIGN_EXTEND_INREG, 419 420 /// ANY_EXTEND_VECTOR_INREG(Vector) - This operator represents an 421 /// in-register any-extension of the low lanes of an integer vector. The 422 /// result type must have fewer elements than the operand type, and those 423 /// elements must be larger integer types such that the total size of the 424 /// operand type and the result type match. Each of the low operand 425 /// elements is any-extended into the corresponding, wider result 426 /// elements with the high bits becoming undef. 427 ANY_EXTEND_VECTOR_INREG, 428 429 /// SIGN_EXTEND_VECTOR_INREG(Vector) - This operator represents an 430 /// in-register sign-extension of the low lanes of an integer vector. The 431 /// result type must have fewer elements than the operand type, and those 432 /// elements must be larger integer types such that the total size of the 433 /// operand type and the result type match. Each of the low operand 434 /// elements is sign-extended into the corresponding, wider result 435 /// elements. 436 // FIXME: The SIGN_EXTEND_INREG node isn't specifically limited to 437 // scalars, but it also doesn't handle vectors well. Either it should be 438 // restricted to scalars or this node (and its handling) should be merged 439 // into it. 440 SIGN_EXTEND_VECTOR_INREG, 441 442 /// ZERO_EXTEND_VECTOR_INREG(Vector) - This operator represents an 443 /// in-register zero-extension of the low lanes of an integer vector. The 444 /// result type must have fewer elements than the operand type, and those 445 /// elements must be larger integer types such that the total size of the 446 /// operand type and the result type match. Each of the low operand 447 /// elements is zero-extended into the corresponding, wider result 448 /// elements. 449 ZERO_EXTEND_VECTOR_INREG, 450 451 /// FP_TO_[US]INT - Convert a floating point value to a signed or unsigned 452 /// integer. 453 FP_TO_SINT, 454 FP_TO_UINT, 455 456 /// X = FP_ROUND(Y, TRUNC) - Rounding 'Y' from a larger floating point type 457 /// down to the precision of the destination VT. TRUNC is a flag, which is 458 /// always an integer that is zero or one. If TRUNC is 0, this is a 459 /// normal rounding, if it is 1, this FP_ROUND is known to not change the 460 /// value of Y. 461 /// 462 /// The TRUNC = 1 case is used in cases where we know that the value will 463 /// not be modified by the node, because Y is not using any of the extra 464 /// precision of source type. This allows certain transformations like 465 /// FP_EXTEND(FP_ROUND(X,1)) -> X which are not safe for 466 /// FP_EXTEND(FP_ROUND(X,0)) because the extra bits aren't removed. 467 FP_ROUND, 468 469 /// FLT_ROUNDS_ - Returns current rounding mode: 470 /// -1 Undefined 471 /// 0 Round to 0 472 /// 1 Round to nearest 473 /// 2 Round to +inf 474 /// 3 Round to -inf 475 FLT_ROUNDS_, 476 477 /// X = FP_ROUND_INREG(Y, VT) - This operator takes an FP register, and 478 /// rounds it to a floating point value. It then promotes it and returns it 479 /// in a register of the same size. This operation effectively just 480 /// discards excess precision. The type to round down to is specified by 481 /// the VT operand, a VTSDNode. 482 FP_ROUND_INREG, 483 484 /// X = FP_EXTEND(Y) - Extend a smaller FP type into a larger FP type. 485 FP_EXTEND, 486 487 /// BITCAST - This operator converts between integer, vector and FP 488 /// values, as if the value was stored to memory with one type and loaded 489 /// from the same address with the other type (or equivalently for vector 490 /// format conversions, etc). The source and result are required to have 491 /// the same bit size (e.g. f32 <-> i32). This can also be used for 492 /// int-to-int or fp-to-fp conversions, but that is a noop, deleted by 493 /// getNode(). 494 /// 495 /// This operator is subtly different from the bitcast instruction from 496 /// LLVM-IR since this node may change the bits in the register. For 497 /// example, this occurs on big-endian NEON and big-endian MSA where the 498 /// layout of the bits in the register depends on the vector type and this 499 /// operator acts as a shuffle operation for some vector type combinations. 500 BITCAST, 501 502 /// ADDRSPACECAST - This operator converts between pointers of different 503 /// address spaces. 504 ADDRSPACECAST, 505 506 /// CONVERT_RNDSAT - This operator is used to support various conversions 507 /// between various types (float, signed, unsigned and vectors of those 508 /// types) with rounding and saturation. NOTE: Avoid using this operator as 509 /// most target don't support it and the operator might be removed in the 510 /// future. It takes the following arguments: 511 /// 0) value 512 /// 1) dest type (type to convert to) 513 /// 2) src type (type to convert from) 514 /// 3) rounding imm 515 /// 4) saturation imm 516 /// 5) ISD::CvtCode indicating the type of conversion to do 517 CONVERT_RNDSAT, 518 519 /// FP16_TO_FP, FP_TO_FP16 - These operators are used to perform promotions 520 /// and truncation for half-precision (16 bit) floating numbers. These nodes 521 /// form a semi-softened interface for dealing with f16 (as an i16), which 522 /// is often a storage-only type but has native conversions. 523 FP16_TO_FP, FP_TO_FP16, 524 525 /// FNEG, FABS, FSQRT, FSIN, FCOS, FPOWI, FPOW, 526 /// FLOG, FLOG2, FLOG10, FEXP, FEXP2, 527 /// FCEIL, FTRUNC, FRINT, FNEARBYINT, FROUND, FFLOOR - Perform various unary 528 /// floating point operations. These are inspired by libm. 529 FNEG, FABS, FSQRT, FSIN, FCOS, FPOWI, FPOW, 530 FLOG, FLOG2, FLOG10, FEXP, FEXP2, 531 FCEIL, FTRUNC, FRINT, FNEARBYINT, FROUND, FFLOOR, 532 /// FMINNUM/FMAXNUM - Perform floating-point minimum or maximum on two 533 /// values. 534 /// In the case where a single input is NaN, the non-NaN input is returned. 535 /// 536 /// The return value of (FMINNUM 0.0, -0.0) could be either 0.0 or -0.0. 537 FMINNUM, FMAXNUM, 538 /// FMINNAN/FMAXNAN - Behave identically to FMINNUM/FMAXNUM, except that 539 /// when a single input is NaN, NaN is returned. 540 FMINNAN, FMAXNAN, 541 542 /// FSINCOS - Compute both fsin and fcos as a single operation. 543 FSINCOS, 544 545 /// LOAD and STORE have token chains as their first operand, then the same 546 /// operands as an LLVM load/store instruction, then an offset node that 547 /// is added / subtracted from the base pointer to form the address (for 548 /// indexed memory ops). 549 LOAD, STORE, 550 551 /// DYNAMIC_STACKALLOC - Allocate some number of bytes on the stack aligned 552 /// to a specified boundary. This node always has two return values: a new 553 /// stack pointer value and a chain. The first operand is the token chain, 554 /// the second is the number of bytes to allocate, and the third is the 555 /// alignment boundary. The size is guaranteed to be a multiple of the 556 /// stack alignment, and the alignment is guaranteed to be bigger than the 557 /// stack alignment (if required) or 0 to get standard stack alignment. 558 DYNAMIC_STACKALLOC, 559 560 /// Control flow instructions. These all have token chains. 561 562 /// BR - Unconditional branch. The first operand is the chain 563 /// operand, the second is the MBB to branch to. 564 BR, 565 566 /// BRIND - Indirect branch. The first operand is the chain, the second 567 /// is the value to branch to, which must be of the same type as the 568 /// target's pointer type. 569 BRIND, 570 571 /// BR_JT - Jumptable branch. The first operand is the chain, the second 572 /// is the jumptable index, the last one is the jumptable entry index. 573 BR_JT, 574 575 /// BRCOND - Conditional branch. The first operand is the chain, the 576 /// second is the condition, the third is the block to branch to if the 577 /// condition is true. If the type of the condition is not i1, then the 578 /// high bits must conform to getBooleanContents. 579 BRCOND, 580 581 /// BR_CC - Conditional branch. The behavior is like that of SELECT_CC, in 582 /// that the condition is represented as condition code, and two nodes to 583 /// compare, rather than as a combined SetCC node. The operands in order 584 /// are chain, cc, lhs, rhs, block to branch to if condition is true. 585 BR_CC, 586 587 /// INLINEASM - Represents an inline asm block. This node always has two 588 /// return values: a chain and a flag result. The inputs are as follows: 589 /// Operand #0 : Input chain. 590 /// Operand #1 : a ExternalSymbolSDNode with a pointer to the asm string. 591 /// Operand #2 : a MDNodeSDNode with the !srcloc metadata. 592 /// Operand #3 : HasSideEffect, IsAlignStack bits. 593 /// After this, it is followed by a list of operands with this format: 594 /// ConstantSDNode: Flags that encode whether it is a mem or not, the 595 /// of operands that follow, etc. See InlineAsm.h. 596 /// ... however many operands ... 597 /// Operand #last: Optional, an incoming flag. 598 /// 599 /// The variable width operands are required to represent target addressing 600 /// modes as a single "operand", even though they may have multiple 601 /// SDOperands. 602 INLINEASM, 603 604 /// EH_LABEL - Represents a label in mid basic block used to track 605 /// locations needed for debug and exception handling tables. These nodes 606 /// take a chain as input and return a chain. 607 EH_LABEL, 608 609 /// CATCHPAD - Represents a catchpad instruction. 610 CATCHPAD, 611 612 /// CATCHRET - Represents a return from a catch block funclet. Used for 613 /// MSVC compatible exception handling. Takes a chain operand and a 614 /// destination basic block operand. 615 CATCHRET, 616 617 /// CLEANUPRET - Represents a return from a cleanup block funclet. Used for 618 /// MSVC compatible exception handling. Takes only a chain operand. 619 CLEANUPRET, 620 621 /// STACKSAVE - STACKSAVE has one operand, an input chain. It produces a 622 /// value, the same type as the pointer type for the system, and an output 623 /// chain. 624 STACKSAVE, 625 626 /// STACKRESTORE has two operands, an input chain and a pointer to restore 627 /// to it returns an output chain. 628 STACKRESTORE, 629 630 /// CALLSEQ_START/CALLSEQ_END - These operators mark the beginning and end 631 /// of a call sequence, and carry arbitrary information that target might 632 /// want to know. The first operand is a chain, the rest are specified by 633 /// the target and not touched by the DAG optimizers. 634 /// CALLSEQ_START..CALLSEQ_END pairs may not be nested. 635 CALLSEQ_START, // Beginning of a call sequence 636 CALLSEQ_END, // End of a call sequence 637 638 /// VAARG - VAARG has four operands: an input chain, a pointer, a SRCVALUE, 639 /// and the alignment. It returns a pair of values: the vaarg value and a 640 /// new chain. 641 VAARG, 642 643 /// VACOPY - VACOPY has 5 operands: an input chain, a destination pointer, 644 /// a source pointer, a SRCVALUE for the destination, and a SRCVALUE for the 645 /// source. 646 VACOPY, 647 648 /// VAEND, VASTART - VAEND and VASTART have three operands: an input chain, 649 /// pointer, and a SRCVALUE. 650 VAEND, VASTART, 651 652 /// SRCVALUE - This is a node type that holds a Value* that is used to 653 /// make reference to a value in the LLVM IR. 654 SRCVALUE, 655 656 /// MDNODE_SDNODE - This is a node that holdes an MDNode*, which is used to 657 /// reference metadata in the IR. 658 MDNODE_SDNODE, 659 660 /// PCMARKER - This corresponds to the pcmarker intrinsic. 661 PCMARKER, 662 663 /// READCYCLECOUNTER - This corresponds to the readcyclecounter intrinsic. 664 /// It produces a chain and one i64 value. The only operand is a chain. 665 /// If i64 is not legal, the result will be expanded into smaller values. 666 /// Still, it returns an i64, so targets should set legality for i64. 667 /// The result is the content of the architecture-specific cycle 668 /// counter-like register (or other high accuracy low latency clock source). 669 READCYCLECOUNTER, 670 671 /// HANDLENODE node - Used as a handle for various purposes. 672 HANDLENODE, 673 674 /// INIT_TRAMPOLINE - This corresponds to the init_trampoline intrinsic. It 675 /// takes as input a token chain, the pointer to the trampoline, the pointer 676 /// to the nested function, the pointer to pass for the 'nest' parameter, a 677 /// SRCVALUE for the trampoline and another for the nested function 678 /// (allowing targets to access the original Function*). 679 /// It produces a token chain as output. 680 INIT_TRAMPOLINE, 681 682 /// ADJUST_TRAMPOLINE - This corresponds to the adjust_trampoline intrinsic. 683 /// It takes a pointer to the trampoline and produces a (possibly) new 684 /// pointer to the same trampoline with platform-specific adjustments 685 /// applied. The pointer it returns points to an executable block of code. 686 ADJUST_TRAMPOLINE, 687 688 /// TRAP - Trapping instruction 689 TRAP, 690 691 /// DEBUGTRAP - Trap intended to get the attention of a debugger. 692 DEBUGTRAP, 693 694 /// PREFETCH - This corresponds to a prefetch intrinsic. The first operand 695 /// is the chain. The other operands are the address to prefetch, 696 /// read / write specifier, locality specifier and instruction / data cache 697 /// specifier. 698 PREFETCH, 699 700 /// OUTCHAIN = ATOMIC_FENCE(INCHAIN, ordering, scope) 701 /// This corresponds to the fence instruction. It takes an input chain, and 702 /// two integer constants: an AtomicOrdering and a SynchronizationScope. 703 ATOMIC_FENCE, 704 705 /// Val, OUTCHAIN = ATOMIC_LOAD(INCHAIN, ptr) 706 /// This corresponds to "load atomic" instruction. 707 ATOMIC_LOAD, 708 709 /// OUTCHAIN = ATOMIC_STORE(INCHAIN, ptr, val) 710 /// This corresponds to "store atomic" instruction. 711 ATOMIC_STORE, 712 713 /// Val, OUTCHAIN = ATOMIC_CMP_SWAP(INCHAIN, ptr, cmp, swap) 714 /// For double-word atomic operations: 715 /// ValLo, ValHi, OUTCHAIN = ATOMIC_CMP_SWAP(INCHAIN, ptr, cmpLo, cmpHi, 716 /// swapLo, swapHi) 717 /// This corresponds to the cmpxchg instruction. 718 ATOMIC_CMP_SWAP, 719 720 /// Val, Success, OUTCHAIN 721 /// = ATOMIC_CMP_SWAP_WITH_SUCCESS(INCHAIN, ptr, cmp, swap) 722 /// N.b. this is still a strong cmpxchg operation, so 723 /// Success == "Val == cmp". 724 ATOMIC_CMP_SWAP_WITH_SUCCESS, 725 726 /// Val, OUTCHAIN = ATOMIC_SWAP(INCHAIN, ptr, amt) 727 /// Val, OUTCHAIN = ATOMIC_LOAD_[OpName](INCHAIN, ptr, amt) 728 /// For double-word atomic operations: 729 /// ValLo, ValHi, OUTCHAIN = ATOMIC_SWAP(INCHAIN, ptr, amtLo, amtHi) 730 /// ValLo, ValHi, OUTCHAIN = ATOMIC_LOAD_[OpName](INCHAIN, ptr, amtLo, amtHi) 731 /// These correspond to the atomicrmw instruction. 732 ATOMIC_SWAP, 733 ATOMIC_LOAD_ADD, 734 ATOMIC_LOAD_SUB, 735 ATOMIC_LOAD_AND, 736 ATOMIC_LOAD_OR, 737 ATOMIC_LOAD_XOR, 738 ATOMIC_LOAD_NAND, 739 ATOMIC_LOAD_MIN, 740 ATOMIC_LOAD_MAX, 741 ATOMIC_LOAD_UMIN, 742 ATOMIC_LOAD_UMAX, 743 744 // Masked load and store - consecutive vector load and store operations 745 // with additional mask operand that prevents memory accesses to the 746 // masked-off lanes. 747 MLOAD, MSTORE, 748 749 // Masked gather and scatter - load and store operations for a vector of 750 // random addresses with additional mask operand that prevents memory 751 // accesses to the masked-off lanes. 752 MGATHER, MSCATTER, 753 754 /// This corresponds to the llvm.lifetime.* intrinsics. The first operand 755 /// is the chain and the second operand is the alloca pointer. 756 LIFETIME_START, LIFETIME_END, 757 758 /// GC_TRANSITION_START/GC_TRANSITION_END - These operators mark the 759 /// beginning and end of GC transition sequence, and carry arbitrary 760 /// information that target might need for lowering. The first operand is 761 /// a chain, the rest are specified by the target and not touched by the DAG 762 /// optimizers. GC_TRANSITION_START..GC_TRANSITION_END pairs may not be 763 /// nested. 764 GC_TRANSITION_START, 765 GC_TRANSITION_END, 766 767 /// GET_DYNAMIC_AREA_OFFSET - get offset from native SP to the address of 768 /// the most recent dynamic alloca. For most targets that would be 0, but 769 /// for some others (e.g. PowerPC, PowerPC64) that would be compile-time 770 /// known nonzero constant. The only operand here is the chain. 771 GET_DYNAMIC_AREA_OFFSET, 772 773 /// BUILTIN_OP_END - This must be the last enum value in this list. 774 /// The target-specific pre-isel opcode values start here. 775 BUILTIN_OP_END 776 }; 777 778 /// FIRST_TARGET_MEMORY_OPCODE - Target-specific pre-isel operations 779 /// which do not reference a specific memory location should be less than 780 /// this value. Those that do must not be less than this value, and can 781 /// be used with SelectionDAG::getMemIntrinsicNode. 782 static const int FIRST_TARGET_MEMORY_OPCODE = BUILTIN_OP_END+300; 783 784 //===--------------------------------------------------------------------===// 785 /// MemIndexedMode enum - This enum defines the load / store indexed 786 /// addressing modes. 787 /// 788 /// UNINDEXED "Normal" load / store. The effective address is already 789 /// computed and is available in the base pointer. The offset 790 /// operand is always undefined. In addition to producing a 791 /// chain, an unindexed load produces one value (result of the 792 /// load); an unindexed store does not produce a value. 793 /// 794 /// PRE_INC Similar to the unindexed mode where the effective address is 795 /// PRE_DEC the value of the base pointer add / subtract the offset. 796 /// It considers the computation as being folded into the load / 797 /// store operation (i.e. the load / store does the address 798 /// computation as well as performing the memory transaction). 799 /// The base operand is always undefined. In addition to 800 /// producing a chain, pre-indexed load produces two values 801 /// (result of the load and the result of the address 802 /// computation); a pre-indexed store produces one value (result 803 /// of the address computation). 804 /// 805 /// POST_INC The effective address is the value of the base pointer. The 806 /// POST_DEC value of the offset operand is then added to / subtracted 807 /// from the base after memory transaction. In addition to 808 /// producing a chain, post-indexed load produces two values 809 /// (the result of the load and the result of the base +/- offset 810 /// computation); a post-indexed store produces one value (the 811 /// the result of the base +/- offset computation). 812 enum MemIndexedMode { 813 UNINDEXED = 0, 814 PRE_INC, 815 PRE_DEC, 816 POST_INC, 817 POST_DEC, 818 LAST_INDEXED_MODE 819 }; 820 821 //===--------------------------------------------------------------------===// 822 /// LoadExtType enum - This enum defines the three variants of LOADEXT 823 /// (load with extension). 824 /// 825 /// SEXTLOAD loads the integer operand and sign extends it to a larger 826 /// integer result type. 827 /// ZEXTLOAD loads the integer operand and zero extends it to a larger 828 /// integer result type. 829 /// EXTLOAD is used for two things: floating point extending loads and 830 /// integer extending loads [the top bits are undefined]. 831 enum LoadExtType { 832 NON_EXTLOAD = 0, 833 EXTLOAD, 834 SEXTLOAD, 835 ZEXTLOAD, 836 LAST_LOADEXT_TYPE 837 }; 838 839 NodeType getExtForLoadExtType(bool IsFP, LoadExtType); 840 841 //===--------------------------------------------------------------------===// 842 /// ISD::CondCode enum - These are ordered carefully to make the bitfields 843 /// below work out, when considering SETFALSE (something that never exists 844 /// dynamically) as 0. "U" -> Unsigned (for integer operands) or Unordered 845 /// (for floating point), "L" -> Less than, "G" -> Greater than, "E" -> Equal 846 /// to. If the "N" column is 1, the result of the comparison is undefined if 847 /// the input is a NAN. 848 /// 849 /// All of these (except for the 'always folded ops') should be handled for 850 /// floating point. For integer, only the SETEQ,SETNE,SETLT,SETLE,SETGT, 851 /// SETGE,SETULT,SETULE,SETUGT, and SETUGE opcodes are used. 852 /// 853 /// Note that these are laid out in a specific order to allow bit-twiddling 854 /// to transform conditions. 855 enum CondCode { 856 // Opcode N U L G E Intuitive operation 857 SETFALSE, // 0 0 0 0 Always false (always folded) 858 SETOEQ, // 0 0 0 1 True if ordered and equal 859 SETOGT, // 0 0 1 0 True if ordered and greater than 860 SETOGE, // 0 0 1 1 True if ordered and greater than or equal 861 SETOLT, // 0 1 0 0 True if ordered and less than 862 SETOLE, // 0 1 0 1 True if ordered and less than or equal 863 SETONE, // 0 1 1 0 True if ordered and operands are unequal 864 SETO, // 0 1 1 1 True if ordered (no nans) 865 SETUO, // 1 0 0 0 True if unordered: isnan(X) | isnan(Y) 866 SETUEQ, // 1 0 0 1 True if unordered or equal 867 SETUGT, // 1 0 1 0 True if unordered or greater than 868 SETUGE, // 1 0 1 1 True if unordered, greater than, or equal 869 SETULT, // 1 1 0 0 True if unordered or less than 870 SETULE, // 1 1 0 1 True if unordered, less than, or equal 871 SETUNE, // 1 1 1 0 True if unordered or not equal 872 SETTRUE, // 1 1 1 1 Always true (always folded) 873 // Don't care operations: undefined if the input is a nan. 874 SETFALSE2, // 1 X 0 0 0 Always false (always folded) 875 SETEQ, // 1 X 0 0 1 True if equal 876 SETGT, // 1 X 0 1 0 True if greater than 877 SETGE, // 1 X 0 1 1 True if greater than or equal 878 SETLT, // 1 X 1 0 0 True if less than 879 SETLE, // 1 X 1 0 1 True if less than or equal 880 SETNE, // 1 X 1 1 0 True if not equal 881 SETTRUE2, // 1 X 1 1 1 Always true (always folded) 882 883 SETCC_INVALID // Marker value. 884 }; 885 886 /// Return true if this is a setcc instruction that performs a signed 887 /// comparison when used with integer operands. 888 inline bool isSignedIntSetCC(CondCode Code) { 889 return Code == SETGT || Code == SETGE || Code == SETLT || Code == SETLE; 890 } 891 892 /// Return true if this is a setcc instruction that performs an unsigned 893 /// comparison when used with integer operands. 894 inline bool isUnsignedIntSetCC(CondCode Code) { 895 return Code == SETUGT || Code == SETUGE || Code == SETULT || Code == SETULE; 896 } 897 898 /// Return true if the specified condition returns true if the two operands to 899 /// the condition are equal. Note that if one of the two operands is a NaN, 900 /// this value is meaningless. 901 inline bool isTrueWhenEqual(CondCode Cond) { 902 return ((int)Cond & 1) != 0; 903 } 904 905 /// This function returns 0 if the condition is always false if an operand is 906 /// a NaN, 1 if the condition is always true if the operand is a NaN, and 2 if 907 /// the condition is undefined if the operand is a NaN. 908 inline unsigned getUnorderedFlavor(CondCode Cond) { 909 return ((int)Cond >> 3) & 3; 910 } 911 912 /// Return the operation corresponding to !(X op Y), where 'op' is a valid 913 /// SetCC operation. 914 CondCode getSetCCInverse(CondCode Operation, bool isInteger); 915 916 /// Return the operation corresponding to (Y op X) when given the operation 917 /// for (X op Y). 918 CondCode getSetCCSwappedOperands(CondCode Operation); 919 920 /// Return the result of a logical OR between different comparisons of 921 /// identical values: ((X op1 Y) | (X op2 Y)). This function returns 922 /// SETCC_INVALID if it is not possible to represent the resultant comparison. 923 CondCode getSetCCOrOperation(CondCode Op1, CondCode Op2, bool isInteger); 924 925 /// Return the result of a logical AND between different comparisons of 926 /// identical values: ((X op1 Y) & (X op2 Y)). This function returns 927 /// SETCC_INVALID if it is not possible to represent the resultant comparison. 928 CondCode getSetCCAndOperation(CondCode Op1, CondCode Op2, bool isInteger); 929 930 //===--------------------------------------------------------------------===// 931 /// This enum defines the various converts CONVERT_RNDSAT supports. 932 enum CvtCode { 933 CVT_FF, /// Float from Float 934 CVT_FS, /// Float from Signed 935 CVT_FU, /// Float from Unsigned 936 CVT_SF, /// Signed from Float 937 CVT_UF, /// Unsigned from Float 938 CVT_SS, /// Signed from Signed 939 CVT_SU, /// Signed from Unsigned 940 CVT_US, /// Unsigned from Signed 941 CVT_UU, /// Unsigned from Unsigned 942 CVT_INVALID /// Marker - Invalid opcode 943 }; 944 945} // end llvm::ISD namespace 946 947} // end llvm namespace 948 949#endif 950