1344779Sdim//===- FunctionLoweringInfo.h - Lower functions from LLVM IR ---*- C++ -*--===// 2210006Srdivacky// 3353358Sdim// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4353358Sdim// See https://llvm.org/LICENSE.txt for license information. 5353358Sdim// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6210006Srdivacky// 7210006Srdivacky//===----------------------------------------------------------------------===// 8210006Srdivacky// 9210006Srdivacky// This implements routines for translating functions from LLVM IR into 10210006Srdivacky// Machine IR. 11210006Srdivacky// 12210006Srdivacky//===----------------------------------------------------------------------===// 13210006Srdivacky 14210006Srdivacky#ifndef LLVM_CODEGEN_FUNCTIONLOWERINGINFO_H 15210006Srdivacky#define LLVM_CODEGEN_FUNCTIONLOWERINGINFO_H 16210006Srdivacky#include "llvm/ADT/APInt.h" 17353358Sdim#include "llvm/ADT/BitVector.h" 18210006Srdivacky#include "llvm/ADT/DenseMap.h" 19218893Sdim#include "llvm/ADT/IndexedMap.h" 20288943Sdim#include "llvm/ADT/Optional.h" 21234353Sdim#include "llvm/ADT/SmallPtrSet.h" 22210006Srdivacky#include "llvm/ADT/SmallVector.h" 23280031Sdim#include "llvm/CodeGen/ISDOpcodes.h" 24249423Sdim#include "llvm/CodeGen/MachineBasicBlock.h" 25327952Sdim#include "llvm/CodeGen/TargetRegisterInfo.h" 26249423Sdim#include "llvm/IR/Instructions.h" 27321369Sdim#include "llvm/IR/Type.h" 28321369Sdim#include "llvm/IR/Value.h" 29321369Sdim#include "llvm/Support/KnownBits.h" 30321369Sdim#include <cassert> 31321369Sdim#include <utility> 32210006Srdivacky#include <vector> 33210006Srdivacky 34210006Srdivackynamespace llvm { 35210006Srdivacky 36321369Sdimclass Argument; 37210006Srdivackyclass BasicBlock; 38249423Sdimclass BranchProbabilityInfo; 39360784Sdimclass LegacyDivergenceAnalysis; 40210006Srdivackyclass Function; 41210006Srdivackyclass Instruction; 42321369Sdimclass MachineFunction; 43210006Srdivackyclass MachineInstr; 44210006Srdivackyclass MachineRegisterInfo; 45321369Sdimclass MVT; 46263312Sdimclass SelectionDAG; 47210006Srdivackyclass TargetLowering; 48210006Srdivacky 49210006Srdivacky//===--------------------------------------------------------------------===// 50210006Srdivacky/// FunctionLoweringInfo - This contains information that is global to a 51210006Srdivacky/// function that is used when lowering a region of the function. 52210006Srdivacky/// 53210006Srdivackyclass FunctionLoweringInfo { 54210006Srdivackypublic: 55210006Srdivacky const Function *Fn; 56210006Srdivacky MachineFunction *MF; 57280031Sdim const TargetLowering *TLI; 58210006Srdivacky MachineRegisterInfo *RegInfo; 59224145Sdim BranchProbabilityInfo *BPI; 60353358Sdim const LegacyDivergenceAnalysis *DA; 61210006Srdivacky /// CanLowerReturn - true iff the function's return value can be lowered to 62210006Srdivacky /// registers. 63210006Srdivacky bool CanLowerReturn; 64210006Srdivacky 65296417Sdim /// True if part of the CSRs will be handled via explicit copies. 66296417Sdim bool SplitCSR; 67296417Sdim 68210006Srdivacky /// DemoteRegister - if CanLowerReturn is false, DemoteRegister is a vreg 69210006Srdivacky /// allocated to hold a pointer to the hidden sret parameter. 70210006Srdivacky unsigned DemoteRegister; 71210006Srdivacky 72210006Srdivacky /// MBBMap - A mapping from LLVM basic blocks to their machine code entry. 73210006Srdivacky DenseMap<const BasicBlock*, MachineBasicBlock *> MBBMap; 74210006Srdivacky 75210006Srdivacky /// ValueMap - Since we emit code for the function a basic block at a time, 76210006Srdivacky /// we must remember which virtual registers hold the values for 77210006Srdivacky /// cross-basic-block values. 78296417Sdim DenseMap<const Value *, unsigned> ValueMap; 79210006Srdivacky 80341825Sdim /// VirtReg2Value map is needed by the Divergence Analysis driven 81341825Sdim /// instruction selection. It is reverted ValueMap. It is computed 82341825Sdim /// in lazy style - on demand. It is used to get the Value corresponding 83341825Sdim /// to the live in virtual register and is called from the 84341825Sdim /// TargetLowerinInfo::isSDNodeSourceOfDivergence. 85341825Sdim DenseMap<unsigned, const Value*> VirtReg2Value; 86341825Sdim 87341825Sdim /// This method is called from TargetLowerinInfo::isSDNodeSourceOfDivergence 88341825Sdim /// to get the Value corresponding to the live-in virtual register. 89341825Sdim const Value * getValueFromVirtualReg(unsigned Vreg); 90341825Sdim 91296417Sdim /// Track virtual registers created for exception pointers. 92296417Sdim DenseMap<const Value *, unsigned> CatchPadExceptionPointers; 93296417Sdim 94309124Sdim /// Keep track of frame indices allocated for statepoints as they could be 95309124Sdim /// used across basic block boundaries. This struct is more complex than a 96309124Sdim /// simple map because the stateopint lowering code de-duplicates gc pointers 97309124Sdim /// based on their SDValue (so %p and (bitcast %p to T) will get the same 98309124Sdim /// slot), and we track that here. 99288943Sdim 100309124Sdim struct StatepointSpillMap { 101321369Sdim using SlotMapTy = DenseMap<const Value *, Optional<int>>; 102309124Sdim 103309124Sdim /// Maps uniqued llvm IR values to the slots they were spilled in. If a 104309124Sdim /// value is mapped to None it means we visited the value but didn't spill 105309124Sdim /// it (because it was a constant, for instance). 106309124Sdim SlotMapTy SlotMap; 107309124Sdim 108309124Sdim /// Maps llvm IR values to the values they were de-duplicated to. 109309124Sdim DenseMap<const Value *, const Value *> DuplicateMap; 110309124Sdim 111309124Sdim SlotMapTy::const_iterator find(const Value *V) const { 112309124Sdim auto DuplIt = DuplicateMap.find(V); 113309124Sdim if (DuplIt != DuplicateMap.end()) 114309124Sdim V = DuplIt->second; 115309124Sdim return SlotMap.find(V); 116309124Sdim } 117309124Sdim 118309124Sdim SlotMapTy::const_iterator end() const { return SlotMap.end(); } 119309124Sdim }; 120309124Sdim 121309124Sdim /// Maps gc.statepoint instructions to their corresponding StatepointSpillMap 122309124Sdim /// instances. 123309124Sdim DenseMap<const Instruction *, StatepointSpillMap> StatepointSpillMaps; 124309124Sdim 125210006Srdivacky /// StaticAllocaMap - Keep track of frame indices for fixed sized allocas in 126210006Srdivacky /// the entry block. This allows the allocas to be efficiently referenced 127210006Srdivacky /// anywhere in the function. 128210006Srdivacky DenseMap<const AllocaInst*, int> StaticAllocaMap; 129210006Srdivacky 130212904Sdim /// ByValArgFrameIndexMap - Keep track of frame indices for byval arguments. 131212904Sdim DenseMap<const Argument*, int> ByValArgFrameIndexMap; 132212904Sdim 133210006Srdivacky /// ArgDbgValues - A list of DBG_VALUE instructions created during isel for 134210006Srdivacky /// function arguments that are inserted after scheduling is completed. 135210006Srdivacky SmallVector<MachineInstr*, 8> ArgDbgValues; 136210006Srdivacky 137353358Sdim /// Bitvector with a bit set if corresponding argument is described in 138353358Sdim /// ArgDbgValues. Using arg numbers according to Argument numbering. 139353358Sdim BitVector DescribedArgs; 140353358Sdim 141210006Srdivacky /// RegFixups - Registers which need to be replaced after isel is done. 142210006Srdivacky DenseMap<unsigned, unsigned> RegFixups; 143210006Srdivacky 144341825Sdim DenseSet<unsigned> RegsWithFixups; 145341825Sdim 146296417Sdim /// StatepointStackSlots - A list of temporary stack slots (frame indices) 147280031Sdim /// used to spill values at a statepoint. We store them here to enable 148280031Sdim /// reuse of the same stack slots across different statepoints in different 149280031Sdim /// basic blocks. 150280031Sdim SmallVector<unsigned, 50> StatepointStackSlots; 151280031Sdim 152210006Srdivacky /// MBB - The current block. 153210006Srdivacky MachineBasicBlock *MBB; 154210006Srdivacky 155210006Srdivacky /// MBB - The current insert position inside the current block. 156210006Srdivacky MachineBasicBlock::iterator InsertPt; 157210006Srdivacky 158210006Srdivacky struct LiveOutInfo { 159219077Sdim unsigned NumSignBits : 31; 160309124Sdim unsigned IsValid : 1; 161321369Sdim KnownBits Known = 1; 162321369Sdim 163321369Sdim LiveOutInfo() : NumSignBits(0), IsValid(true) {} 164210006Srdivacky }; 165210006Srdivacky 166280031Sdim /// Record the preferred extend type (ISD::SIGN_EXTEND or ISD::ZERO_EXTEND) 167280031Sdim /// for a value. 168280031Sdim DenseMap<const Value *, ISD::NodeType> PreferredExtendType; 169280031Sdim 170219077Sdim /// VisitedBBs - The set of basic blocks visited thus far by instruction 171219077Sdim /// selection. 172234353Sdim SmallPtrSet<const BasicBlock*, 4> VisitedBBs; 173219077Sdim 174210006Srdivacky /// PHINodesToUpdate - A list of phi instructions whose operand list will 175210006Srdivacky /// be updated after processing the current basic block. 176210006Srdivacky /// TODO: This isn't per-function state, it's per-basic-block state. But 177210006Srdivacky /// there's no other convenient place for it to live right now. 178210006Srdivacky std::vector<std::pair<MachineInstr*, unsigned> > PHINodesToUpdate; 179280031Sdim unsigned OrigNumPHINodesToUpdate; 180210006Srdivacky 181252720Sdim /// If the current MBB is a landing pad, the exception pointer and exception 182252720Sdim /// selector registers are copied into these virtual registers by 183252720Sdim /// SelectionDAGISel::PrepareEHLandingPad(). 184252720Sdim unsigned ExceptionPointerVirtReg, ExceptionSelectorVirtReg; 185252720Sdim 186210006Srdivacky /// set - Initialize this FunctionLoweringInfo with the given Function 187210006Srdivacky /// and its associated MachineFunction. 188210006Srdivacky /// 189263312Sdim void set(const Function &Fn, MachineFunction &MF, SelectionDAG *DAG); 190210006Srdivacky 191210006Srdivacky /// clear - Clear out all the function-specific state. This returns this 192210006Srdivacky /// FunctionLoweringInfo to an empty state, ready to be used for a 193210006Srdivacky /// different function. 194210006Srdivacky void clear(); 195210006Srdivacky 196210006Srdivacky /// isExportedInst - Return true if the specified value is an instruction 197210006Srdivacky /// exported from its block. 198360784Sdim bool isExportedInst(const Value *V) const { 199210006Srdivacky return ValueMap.count(V); 200210006Srdivacky } 201210006Srdivacky 202353358Sdim unsigned CreateReg(MVT VT, bool isDivergent = false); 203296417Sdim 204353358Sdim unsigned CreateRegs(const Value *V); 205296417Sdim 206353358Sdim unsigned CreateRegs(Type *Ty, bool isDivergent = false); 207353358Sdim 208210006Srdivacky unsigned InitializeRegForValue(const Value *V) { 209296417Sdim // Tokens never live in vregs. 210296417Sdim if (V->getType()->isTokenTy()) 211296417Sdim return 0; 212210006Srdivacky unsigned &R = ValueMap[V]; 213210006Srdivacky assert(R == 0 && "Already initialized this value register!"); 214344779Sdim assert(VirtReg2Value.empty()); 215353358Sdim return R = CreateRegs(V); 216210006Srdivacky } 217212904Sdim 218219077Sdim /// GetLiveOutRegInfo - Gets LiveOutInfo for a register, returning NULL if the 219219077Sdim /// register is a PHI destination and the PHI's LiveOutInfo is not valid. 220219077Sdim const LiveOutInfo *GetLiveOutRegInfo(unsigned Reg) { 221219077Sdim if (!LiveOutRegInfo.inBounds(Reg)) 222276479Sdim return nullptr; 223219077Sdim 224219077Sdim const LiveOutInfo *LOI = &LiveOutRegInfo[Reg]; 225219077Sdim if (!LOI->IsValid) 226276479Sdim return nullptr; 227219077Sdim 228219077Sdim return LOI; 229219077Sdim } 230219077Sdim 231219077Sdim /// GetLiveOutRegInfo - Gets LiveOutInfo for a register, returning NULL if the 232219077Sdim /// register is a PHI destination and the PHI's LiveOutInfo is not valid. If 233219077Sdim /// the register's LiveOutInfo is for a smaller bit width, it is extended to 234219077Sdim /// the larger bit width by zero extension. The bit width must be no smaller 235219077Sdim /// than the LiveOutInfo's existing bit width. 236219077Sdim const LiveOutInfo *GetLiveOutRegInfo(unsigned Reg, unsigned BitWidth); 237219077Sdim 238219077Sdim /// AddLiveOutRegInfo - Adds LiveOutInfo for a register. 239219077Sdim void AddLiveOutRegInfo(unsigned Reg, unsigned NumSignBits, 240321369Sdim const KnownBits &Known) { 241219077Sdim // Only install this information if it tells us something. 242321369Sdim if (NumSignBits == 1 && Known.isUnknown()) 243219077Sdim return; 244219077Sdim 245219077Sdim LiveOutRegInfo.grow(Reg); 246219077Sdim LiveOutInfo &LOI = LiveOutRegInfo[Reg]; 247219077Sdim LOI.NumSignBits = NumSignBits; 248321369Sdim LOI.Known.One = Known.One; 249321369Sdim LOI.Known.Zero = Known.Zero; 250219077Sdim } 251219077Sdim 252219077Sdim /// ComputePHILiveOutRegInfo - Compute LiveOutInfo for a PHI's destination 253219077Sdim /// register based on the LiveOutInfo of its operands. 254219077Sdim void ComputePHILiveOutRegInfo(const PHINode*); 255219077Sdim 256219077Sdim /// InvalidatePHILiveOutRegInfo - Invalidates a PHI's LiveOutInfo, to be 257219077Sdim /// called when a block is visited before all of its predecessors. 258219077Sdim void InvalidatePHILiveOutRegInfo(const PHINode *PN) { 259221345Sdim // PHIs with no uses have no ValueMap entry. 260221345Sdim DenseMap<const Value*, unsigned>::const_iterator It = ValueMap.find(PN); 261221345Sdim if (It == ValueMap.end()) 262221345Sdim return; 263221345Sdim 264221345Sdim unsigned Reg = It->second; 265280031Sdim if (Reg == 0) 266280031Sdim return; 267280031Sdim 268219077Sdim LiveOutRegInfo.grow(Reg); 269219077Sdim LiveOutRegInfo[Reg].IsValid = false; 270219077Sdim } 271219077Sdim 272226633Sdim /// setArgumentFrameIndex - Record frame index for the byval 273212904Sdim /// argument. 274226633Sdim void setArgumentFrameIndex(const Argument *A, int FI); 275234353Sdim 276226633Sdim /// getArgumentFrameIndex - Get frame index for the byval argument. 277226633Sdim int getArgumentFrameIndex(const Argument *A); 278219077Sdim 279296417Sdim unsigned getCatchPadExceptionPointerVReg(const Value *CPI, 280296417Sdim const TargetRegisterClass *RC); 281296417Sdim 282219077Sdimprivate: 283288943Sdim void addSEHHandlersForLPads(ArrayRef<const LandingPadInst *> LPads); 284288943Sdim 285219077Sdim /// LiveOutRegInfo - Information about live out vregs. 286219077Sdim IndexedMap<LiveOutInfo, VirtReg2IndexFunctor> LiveOutRegInfo; 287210006Srdivacky}; 288210006Srdivacky 289210006Srdivacky} // end namespace llvm 290210006Srdivacky 291321369Sdim#endif // LLVM_CODEGEN_FUNCTIONLOWERINGINFO_H 292