ArchSpec.cpp revision 360784
1//===-- ArchSpec.cpp --------------------------------------------*- C++ -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8 9#include "lldb/Utility/ArchSpec.h" 10 11#include "lldb/Utility/Log.h" 12#include "lldb/Utility/StringList.h" 13#include "lldb/lldb-defines.h" 14#include "llvm/ADT/STLExtras.h" 15#include "llvm/BinaryFormat/COFF.h" 16#include "llvm/BinaryFormat/ELF.h" 17#include "llvm/BinaryFormat/MachO.h" 18#include "llvm/Support/Compiler.h" 19 20using namespace lldb; 21using namespace lldb_private; 22 23static bool cores_match(const ArchSpec::Core core1, const ArchSpec::Core core2, 24 bool try_inverse, bool enforce_exact_match); 25 26namespace lldb_private { 27 28struct CoreDefinition { 29 ByteOrder default_byte_order; 30 uint32_t addr_byte_size; 31 uint32_t min_opcode_byte_size; 32 uint32_t max_opcode_byte_size; 33 llvm::Triple::ArchType machine; 34 ArchSpec::Core core; 35 const char *const name; 36}; 37 38} // namespace lldb_private 39 40// This core information can be looked using the ArchSpec::Core as the index 41static const CoreDefinition g_core_definitions[] = { 42 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_generic, 43 "arm"}, 44 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv4, 45 "armv4"}, 46 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv4t, 47 "armv4t"}, 48 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv5, 49 "armv5"}, 50 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv5e, 51 "armv5e"}, 52 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv5t, 53 "armv5t"}, 54 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv6, 55 "armv6"}, 56 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv6m, 57 "armv6m"}, 58 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7, 59 "armv7"}, 60 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7l, 61 "armv7l"}, 62 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7f, 63 "armv7f"}, 64 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7s, 65 "armv7s"}, 66 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7k, 67 "armv7k"}, 68 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7m, 69 "armv7m"}, 70 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7em, 71 "armv7em"}, 72 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_xscale, 73 "xscale"}, 74 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumb, 75 "thumb"}, 76 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv4t, 77 "thumbv4t"}, 78 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv5, 79 "thumbv5"}, 80 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv5e, 81 "thumbv5e"}, 82 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv6, 83 "thumbv6"}, 84 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv6m, 85 "thumbv6m"}, 86 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv7, 87 "thumbv7"}, 88 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv7f, 89 "thumbv7f"}, 90 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv7s, 91 "thumbv7s"}, 92 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv7k, 93 "thumbv7k"}, 94 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv7m, 95 "thumbv7m"}, 96 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv7em, 97 "thumbv7em"}, 98 {eByteOrderLittle, 8, 4, 4, llvm::Triple::aarch64, 99 ArchSpec::eCore_arm_arm64, "arm64"}, 100 {eByteOrderLittle, 8, 4, 4, llvm::Triple::aarch64, 101 ArchSpec::eCore_arm_armv8, "armv8"}, 102 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, 103 ArchSpec::eCore_arm_armv8l, "armv8l"}, 104 {eByteOrderLittle, 4, 4, 4, llvm::Triple::aarch64_32, 105 ArchSpec::eCore_arm_arm64_32, "arm64_32"}, 106 {eByteOrderLittle, 8, 4, 4, llvm::Triple::aarch64, 107 ArchSpec::eCore_arm_aarch64, "aarch64"}, 108 109 // mips32, mips32r2, mips32r3, mips32r5, mips32r6 110 {eByteOrderBig, 4, 2, 4, llvm::Triple::mips, ArchSpec::eCore_mips32, 111 "mips"}, 112 {eByteOrderBig, 4, 2, 4, llvm::Triple::mips, ArchSpec::eCore_mips32r2, 113 "mipsr2"}, 114 {eByteOrderBig, 4, 2, 4, llvm::Triple::mips, ArchSpec::eCore_mips32r3, 115 "mipsr3"}, 116 {eByteOrderBig, 4, 2, 4, llvm::Triple::mips, ArchSpec::eCore_mips32r5, 117 "mipsr5"}, 118 {eByteOrderBig, 4, 2, 4, llvm::Triple::mips, ArchSpec::eCore_mips32r6, 119 "mipsr6"}, 120 {eByteOrderLittle, 4, 2, 4, llvm::Triple::mipsel, ArchSpec::eCore_mips32el, 121 "mipsel"}, 122 {eByteOrderLittle, 4, 2, 4, llvm::Triple::mipsel, 123 ArchSpec::eCore_mips32r2el, "mipsr2el"}, 124 {eByteOrderLittle, 4, 2, 4, llvm::Triple::mipsel, 125 ArchSpec::eCore_mips32r3el, "mipsr3el"}, 126 {eByteOrderLittle, 4, 2, 4, llvm::Triple::mipsel, 127 ArchSpec::eCore_mips32r5el, "mipsr5el"}, 128 {eByteOrderLittle, 4, 2, 4, llvm::Triple::mipsel, 129 ArchSpec::eCore_mips32r6el, "mipsr6el"}, 130 131 // mips64, mips64r2, mips64r3, mips64r5, mips64r6 132 {eByteOrderBig, 8, 2, 4, llvm::Triple::mips64, ArchSpec::eCore_mips64, 133 "mips64"}, 134 {eByteOrderBig, 8, 2, 4, llvm::Triple::mips64, ArchSpec::eCore_mips64r2, 135 "mips64r2"}, 136 {eByteOrderBig, 8, 2, 4, llvm::Triple::mips64, ArchSpec::eCore_mips64r3, 137 "mips64r3"}, 138 {eByteOrderBig, 8, 2, 4, llvm::Triple::mips64, ArchSpec::eCore_mips64r5, 139 "mips64r5"}, 140 {eByteOrderBig, 8, 2, 4, llvm::Triple::mips64, ArchSpec::eCore_mips64r6, 141 "mips64r6"}, 142 {eByteOrderLittle, 8, 2, 4, llvm::Triple::mips64el, 143 ArchSpec::eCore_mips64el, "mips64el"}, 144 {eByteOrderLittle, 8, 2, 4, llvm::Triple::mips64el, 145 ArchSpec::eCore_mips64r2el, "mips64r2el"}, 146 {eByteOrderLittle, 8, 2, 4, llvm::Triple::mips64el, 147 ArchSpec::eCore_mips64r3el, "mips64r3el"}, 148 {eByteOrderLittle, 8, 2, 4, llvm::Triple::mips64el, 149 ArchSpec::eCore_mips64r5el, "mips64r5el"}, 150 {eByteOrderLittle, 8, 2, 4, llvm::Triple::mips64el, 151 ArchSpec::eCore_mips64r6el, "mips64r6el"}, 152 153 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_generic, 154 "powerpc"}, 155 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc601, 156 "ppc601"}, 157 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc602, 158 "ppc602"}, 159 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc603, 160 "ppc603"}, 161 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc603e, 162 "ppc603e"}, 163 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc603ev, 164 "ppc603ev"}, 165 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc604, 166 "ppc604"}, 167 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc604e, 168 "ppc604e"}, 169 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc620, 170 "ppc620"}, 171 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc750, 172 "ppc750"}, 173 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc7400, 174 "ppc7400"}, 175 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc7450, 176 "ppc7450"}, 177 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc970, 178 "ppc970"}, 179 180 {eByteOrderLittle, 8, 4, 4, llvm::Triple::ppc64le, 181 ArchSpec::eCore_ppc64le_generic, "powerpc64le"}, 182 {eByteOrderBig, 8, 4, 4, llvm::Triple::ppc64, ArchSpec::eCore_ppc64_generic, 183 "powerpc64"}, 184 {eByteOrderBig, 8, 4, 4, llvm::Triple::ppc64, 185 ArchSpec::eCore_ppc64_ppc970_64, "ppc970-64"}, 186 187 {eByteOrderBig, 8, 2, 6, llvm::Triple::systemz, 188 ArchSpec::eCore_s390x_generic, "s390x"}, 189 190 {eByteOrderLittle, 4, 4, 4, llvm::Triple::sparc, 191 ArchSpec::eCore_sparc_generic, "sparc"}, 192 {eByteOrderLittle, 8, 4, 4, llvm::Triple::sparcv9, 193 ArchSpec::eCore_sparc9_generic, "sparcv9"}, 194 195 {eByteOrderLittle, 4, 1, 15, llvm::Triple::x86, ArchSpec::eCore_x86_32_i386, 196 "i386"}, 197 {eByteOrderLittle, 4, 1, 15, llvm::Triple::x86, ArchSpec::eCore_x86_32_i486, 198 "i486"}, 199 {eByteOrderLittle, 4, 1, 15, llvm::Triple::x86, 200 ArchSpec::eCore_x86_32_i486sx, "i486sx"}, 201 {eByteOrderLittle, 4, 1, 15, llvm::Triple::x86, ArchSpec::eCore_x86_32_i686, 202 "i686"}, 203 204 {eByteOrderLittle, 8, 1, 15, llvm::Triple::x86_64, 205 ArchSpec::eCore_x86_64_x86_64, "x86_64"}, 206 {eByteOrderLittle, 8, 1, 15, llvm::Triple::x86_64, 207 ArchSpec::eCore_x86_64_x86_64h, "x86_64h"}, 208 {eByteOrderLittle, 4, 4, 4, llvm::Triple::hexagon, 209 ArchSpec::eCore_hexagon_generic, "hexagon"}, 210 {eByteOrderLittle, 4, 4, 4, llvm::Triple::hexagon, 211 ArchSpec::eCore_hexagon_hexagonv4, "hexagonv4"}, 212 {eByteOrderLittle, 4, 4, 4, llvm::Triple::hexagon, 213 ArchSpec::eCore_hexagon_hexagonv5, "hexagonv5"}, 214 215 {eByteOrderLittle, 4, 4, 4, llvm::Triple::UnknownArch, 216 ArchSpec::eCore_uknownMach32, "unknown-mach-32"}, 217 {eByteOrderLittle, 8, 4, 4, llvm::Triple::UnknownArch, 218 ArchSpec::eCore_uknownMach64, "unknown-mach-64"}, 219 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arc, ArchSpec::eCore_arc, "arc"} 220}; 221 222// Ensure that we have an entry in the g_core_definitions for each core. If you 223// comment out an entry above, you will need to comment out the corresponding 224// ArchSpec::Core enumeration. 225static_assert(sizeof(g_core_definitions) / sizeof(CoreDefinition) == 226 ArchSpec::kNumCores, 227 "make sure we have one core definition for each core"); 228 229struct ArchDefinitionEntry { 230 ArchSpec::Core core; 231 uint32_t cpu; 232 uint32_t sub; 233 uint32_t cpu_mask; 234 uint32_t sub_mask; 235}; 236 237struct ArchDefinition { 238 ArchitectureType type; 239 size_t num_entries; 240 const ArchDefinitionEntry *entries; 241 const char *name; 242}; 243 244void ArchSpec::ListSupportedArchNames(StringList &list) { 245 for (uint32_t i = 0; i < llvm::array_lengthof(g_core_definitions); ++i) 246 list.AppendString(g_core_definitions[i].name); 247} 248 249void ArchSpec::AutoComplete(CompletionRequest &request) { 250 for (uint32_t i = 0; i < llvm::array_lengthof(g_core_definitions); ++i) 251 request.TryCompleteCurrentArg(g_core_definitions[i].name); 252} 253 254#define CPU_ANY (UINT32_MAX) 255 256//===----------------------------------------------------------------------===// 257// A table that gets searched linearly for matches. This table is used to 258// convert cpu type and subtypes to architecture names, and to convert 259// architecture names to cpu types and subtypes. The ordering is important and 260// allows the precedence to be set when the table is built. 261#define SUBTYPE_MASK 0x00FFFFFFu 262 263static const ArchDefinitionEntry g_macho_arch_entries[] = { 264 {ArchSpec::eCore_arm_generic, llvm::MachO::CPU_TYPE_ARM, CPU_ANY, 265 UINT32_MAX, UINT32_MAX}, 266 {ArchSpec::eCore_arm_generic, llvm::MachO::CPU_TYPE_ARM, 0, UINT32_MAX, 267 SUBTYPE_MASK}, 268 {ArchSpec::eCore_arm_armv4, llvm::MachO::CPU_TYPE_ARM, 5, UINT32_MAX, 269 SUBTYPE_MASK}, 270 {ArchSpec::eCore_arm_armv4t, llvm::MachO::CPU_TYPE_ARM, 5, UINT32_MAX, 271 SUBTYPE_MASK}, 272 {ArchSpec::eCore_arm_armv6, llvm::MachO::CPU_TYPE_ARM, 6, UINT32_MAX, 273 SUBTYPE_MASK}, 274 {ArchSpec::eCore_arm_armv6m, llvm::MachO::CPU_TYPE_ARM, 14, UINT32_MAX, 275 SUBTYPE_MASK}, 276 {ArchSpec::eCore_arm_armv5, llvm::MachO::CPU_TYPE_ARM, 7, UINT32_MAX, 277 SUBTYPE_MASK}, 278 {ArchSpec::eCore_arm_armv5e, llvm::MachO::CPU_TYPE_ARM, 7, UINT32_MAX, 279 SUBTYPE_MASK}, 280 {ArchSpec::eCore_arm_armv5t, llvm::MachO::CPU_TYPE_ARM, 7, UINT32_MAX, 281 SUBTYPE_MASK}, 282 {ArchSpec::eCore_arm_xscale, llvm::MachO::CPU_TYPE_ARM, 8, UINT32_MAX, 283 SUBTYPE_MASK}, 284 {ArchSpec::eCore_arm_armv7, llvm::MachO::CPU_TYPE_ARM, 9, UINT32_MAX, 285 SUBTYPE_MASK}, 286 {ArchSpec::eCore_arm_armv7f, llvm::MachO::CPU_TYPE_ARM, 10, UINT32_MAX, 287 SUBTYPE_MASK}, 288 {ArchSpec::eCore_arm_armv7s, llvm::MachO::CPU_TYPE_ARM, 11, UINT32_MAX, 289 SUBTYPE_MASK}, 290 {ArchSpec::eCore_arm_armv7k, llvm::MachO::CPU_TYPE_ARM, 12, UINT32_MAX, 291 SUBTYPE_MASK}, 292 {ArchSpec::eCore_arm_armv7m, llvm::MachO::CPU_TYPE_ARM, 15, UINT32_MAX, 293 SUBTYPE_MASK}, 294 {ArchSpec::eCore_arm_armv7em, llvm::MachO::CPU_TYPE_ARM, 16, UINT32_MAX, 295 SUBTYPE_MASK}, 296 {ArchSpec::eCore_arm_arm64, llvm::MachO::CPU_TYPE_ARM64, 1, UINT32_MAX, 297 SUBTYPE_MASK}, 298 {ArchSpec::eCore_arm_arm64, llvm::MachO::CPU_TYPE_ARM64, 0, UINT32_MAX, 299 SUBTYPE_MASK}, 300 {ArchSpec::eCore_arm_arm64, llvm::MachO::CPU_TYPE_ARM64, 13, UINT32_MAX, 301 SUBTYPE_MASK}, 302 {ArchSpec::eCore_arm_arm64_32, llvm::MachO::CPU_TYPE_ARM64_32, 0, 303 UINT32_MAX, SUBTYPE_MASK}, 304 {ArchSpec::eCore_arm_arm64_32, llvm::MachO::CPU_TYPE_ARM64_32, 1, 305 UINT32_MAX, SUBTYPE_MASK}, 306 {ArchSpec::eCore_arm_arm64, llvm::MachO::CPU_TYPE_ARM64, CPU_ANY, 307 UINT32_MAX, SUBTYPE_MASK}, 308 {ArchSpec::eCore_thumb, llvm::MachO::CPU_TYPE_ARM, 0, UINT32_MAX, 309 SUBTYPE_MASK}, 310 {ArchSpec::eCore_thumbv4t, llvm::MachO::CPU_TYPE_ARM, 5, UINT32_MAX, 311 SUBTYPE_MASK}, 312 {ArchSpec::eCore_thumbv5, llvm::MachO::CPU_TYPE_ARM, 7, UINT32_MAX, 313 SUBTYPE_MASK}, 314 {ArchSpec::eCore_thumbv5e, llvm::MachO::CPU_TYPE_ARM, 7, UINT32_MAX, 315 SUBTYPE_MASK}, 316 {ArchSpec::eCore_thumbv6, llvm::MachO::CPU_TYPE_ARM, 6, UINT32_MAX, 317 SUBTYPE_MASK}, 318 {ArchSpec::eCore_thumbv6m, llvm::MachO::CPU_TYPE_ARM, 14, UINT32_MAX, 319 SUBTYPE_MASK}, 320 {ArchSpec::eCore_thumbv7, llvm::MachO::CPU_TYPE_ARM, 9, UINT32_MAX, 321 SUBTYPE_MASK}, 322 {ArchSpec::eCore_thumbv7f, llvm::MachO::CPU_TYPE_ARM, 10, UINT32_MAX, 323 SUBTYPE_MASK}, 324 {ArchSpec::eCore_thumbv7s, llvm::MachO::CPU_TYPE_ARM, 11, UINT32_MAX, 325 SUBTYPE_MASK}, 326 {ArchSpec::eCore_thumbv7k, llvm::MachO::CPU_TYPE_ARM, 12, UINT32_MAX, 327 SUBTYPE_MASK}, 328 {ArchSpec::eCore_thumbv7m, llvm::MachO::CPU_TYPE_ARM, 15, UINT32_MAX, 329 SUBTYPE_MASK}, 330 {ArchSpec::eCore_thumbv7em, llvm::MachO::CPU_TYPE_ARM, 16, UINT32_MAX, 331 SUBTYPE_MASK}, 332 {ArchSpec::eCore_ppc_generic, llvm::MachO::CPU_TYPE_POWERPC, CPU_ANY, 333 UINT32_MAX, UINT32_MAX}, 334 {ArchSpec::eCore_ppc_generic, llvm::MachO::CPU_TYPE_POWERPC, 0, UINT32_MAX, 335 SUBTYPE_MASK}, 336 {ArchSpec::eCore_ppc_ppc601, llvm::MachO::CPU_TYPE_POWERPC, 1, UINT32_MAX, 337 SUBTYPE_MASK}, 338 {ArchSpec::eCore_ppc_ppc602, llvm::MachO::CPU_TYPE_POWERPC, 2, UINT32_MAX, 339 SUBTYPE_MASK}, 340 {ArchSpec::eCore_ppc_ppc603, llvm::MachO::CPU_TYPE_POWERPC, 3, UINT32_MAX, 341 SUBTYPE_MASK}, 342 {ArchSpec::eCore_ppc_ppc603e, llvm::MachO::CPU_TYPE_POWERPC, 4, UINT32_MAX, 343 SUBTYPE_MASK}, 344 {ArchSpec::eCore_ppc_ppc603ev, llvm::MachO::CPU_TYPE_POWERPC, 5, UINT32_MAX, 345 SUBTYPE_MASK}, 346 {ArchSpec::eCore_ppc_ppc604, llvm::MachO::CPU_TYPE_POWERPC, 6, UINT32_MAX, 347 SUBTYPE_MASK}, 348 {ArchSpec::eCore_ppc_ppc604e, llvm::MachO::CPU_TYPE_POWERPC, 7, UINT32_MAX, 349 SUBTYPE_MASK}, 350 {ArchSpec::eCore_ppc_ppc620, llvm::MachO::CPU_TYPE_POWERPC, 8, UINT32_MAX, 351 SUBTYPE_MASK}, 352 {ArchSpec::eCore_ppc_ppc750, llvm::MachO::CPU_TYPE_POWERPC, 9, UINT32_MAX, 353 SUBTYPE_MASK}, 354 {ArchSpec::eCore_ppc_ppc7400, llvm::MachO::CPU_TYPE_POWERPC, 10, UINT32_MAX, 355 SUBTYPE_MASK}, 356 {ArchSpec::eCore_ppc_ppc7450, llvm::MachO::CPU_TYPE_POWERPC, 11, UINT32_MAX, 357 SUBTYPE_MASK}, 358 {ArchSpec::eCore_ppc_ppc970, llvm::MachO::CPU_TYPE_POWERPC, 100, UINT32_MAX, 359 SUBTYPE_MASK}, 360 {ArchSpec::eCore_ppc64_generic, llvm::MachO::CPU_TYPE_POWERPC64, 0, 361 UINT32_MAX, SUBTYPE_MASK}, 362 {ArchSpec::eCore_ppc64le_generic, llvm::MachO::CPU_TYPE_POWERPC64, CPU_ANY, 363 UINT32_MAX, SUBTYPE_MASK}, 364 {ArchSpec::eCore_ppc64_ppc970_64, llvm::MachO::CPU_TYPE_POWERPC64, 100, 365 UINT32_MAX, SUBTYPE_MASK}, 366 {ArchSpec::eCore_x86_32_i386, llvm::MachO::CPU_TYPE_I386, 3, UINT32_MAX, 367 SUBTYPE_MASK}, 368 {ArchSpec::eCore_x86_32_i486, llvm::MachO::CPU_TYPE_I386, 4, UINT32_MAX, 369 SUBTYPE_MASK}, 370 {ArchSpec::eCore_x86_32_i486sx, llvm::MachO::CPU_TYPE_I386, 0x84, 371 UINT32_MAX, SUBTYPE_MASK}, 372 {ArchSpec::eCore_x86_32_i386, llvm::MachO::CPU_TYPE_I386, CPU_ANY, 373 UINT32_MAX, UINT32_MAX}, 374 {ArchSpec::eCore_x86_64_x86_64, llvm::MachO::CPU_TYPE_X86_64, 3, UINT32_MAX, 375 SUBTYPE_MASK}, 376 {ArchSpec::eCore_x86_64_x86_64, llvm::MachO::CPU_TYPE_X86_64, 4, UINT32_MAX, 377 SUBTYPE_MASK}, 378 {ArchSpec::eCore_x86_64_x86_64h, llvm::MachO::CPU_TYPE_X86_64, 8, 379 UINT32_MAX, SUBTYPE_MASK}, 380 {ArchSpec::eCore_x86_64_x86_64, llvm::MachO::CPU_TYPE_X86_64, CPU_ANY, 381 UINT32_MAX, UINT32_MAX}, 382 // Catch any unknown mach architectures so we can always use the object and 383 // symbol mach-o files 384 {ArchSpec::eCore_uknownMach32, 0, 0, 0xFF000000u, 0x00000000u}, 385 {ArchSpec::eCore_uknownMach64, llvm::MachO::CPU_ARCH_ABI64, 0, 0xFF000000u, 386 0x00000000u}}; 387 388static const ArchDefinition g_macho_arch_def = { 389 eArchTypeMachO, llvm::array_lengthof(g_macho_arch_entries), 390 g_macho_arch_entries, "mach-o"}; 391 392//===----------------------------------------------------------------------===// 393// A table that gets searched linearly for matches. This table is used to 394// convert cpu type and subtypes to architecture names, and to convert 395// architecture names to cpu types and subtypes. The ordering is important and 396// allows the precedence to be set when the table is built. 397static const ArchDefinitionEntry g_elf_arch_entries[] = { 398 {ArchSpec::eCore_sparc_generic, llvm::ELF::EM_SPARC, LLDB_INVALID_CPUTYPE, 399 0xFFFFFFFFu, 0xFFFFFFFFu}, // Sparc 400 {ArchSpec::eCore_x86_32_i386, llvm::ELF::EM_386, LLDB_INVALID_CPUTYPE, 401 0xFFFFFFFFu, 0xFFFFFFFFu}, // Intel 80386 402 {ArchSpec::eCore_x86_32_i486, llvm::ELF::EM_IAMCU, LLDB_INVALID_CPUTYPE, 403 0xFFFFFFFFu, 0xFFFFFFFFu}, // Intel MCU // FIXME: is this correct? 404 {ArchSpec::eCore_ppc_generic, llvm::ELF::EM_PPC, LLDB_INVALID_CPUTYPE, 405 0xFFFFFFFFu, 0xFFFFFFFFu}, // PowerPC 406 {ArchSpec::eCore_ppc64le_generic, llvm::ELF::EM_PPC64, LLDB_INVALID_CPUTYPE, 407 0xFFFFFFFFu, 0xFFFFFFFFu}, // PowerPC64le 408 {ArchSpec::eCore_ppc64_generic, llvm::ELF::EM_PPC64, LLDB_INVALID_CPUTYPE, 409 0xFFFFFFFFu, 0xFFFFFFFFu}, // PowerPC64 410 {ArchSpec::eCore_arm_generic, llvm::ELF::EM_ARM, LLDB_INVALID_CPUTYPE, 411 0xFFFFFFFFu, 0xFFFFFFFFu}, // ARM 412 {ArchSpec::eCore_arm_aarch64, llvm::ELF::EM_AARCH64, LLDB_INVALID_CPUTYPE, 413 0xFFFFFFFFu, 0xFFFFFFFFu}, // ARM64 414 {ArchSpec::eCore_s390x_generic, llvm::ELF::EM_S390, LLDB_INVALID_CPUTYPE, 415 0xFFFFFFFFu, 0xFFFFFFFFu}, // SystemZ 416 {ArchSpec::eCore_sparc9_generic, llvm::ELF::EM_SPARCV9, 417 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // SPARC V9 418 {ArchSpec::eCore_x86_64_x86_64, llvm::ELF::EM_X86_64, LLDB_INVALID_CPUTYPE, 419 0xFFFFFFFFu, 0xFFFFFFFFu}, // AMD64 420 {ArchSpec::eCore_mips32, llvm::ELF::EM_MIPS, ArchSpec::eMIPSSubType_mips32, 421 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips32 422 {ArchSpec::eCore_mips32r2, llvm::ELF::EM_MIPS, 423 ArchSpec::eMIPSSubType_mips32r2, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips32r2 424 {ArchSpec::eCore_mips32r6, llvm::ELF::EM_MIPS, 425 ArchSpec::eMIPSSubType_mips32r6, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips32r6 426 {ArchSpec::eCore_mips32el, llvm::ELF::EM_MIPS, 427 ArchSpec::eMIPSSubType_mips32el, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips32el 428 {ArchSpec::eCore_mips32r2el, llvm::ELF::EM_MIPS, 429 ArchSpec::eMIPSSubType_mips32r2el, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips32r2el 430 {ArchSpec::eCore_mips32r6el, llvm::ELF::EM_MIPS, 431 ArchSpec::eMIPSSubType_mips32r6el, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips32r6el 432 {ArchSpec::eCore_mips64, llvm::ELF::EM_MIPS, ArchSpec::eMIPSSubType_mips64, 433 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips64 434 {ArchSpec::eCore_mips64r2, llvm::ELF::EM_MIPS, 435 ArchSpec::eMIPSSubType_mips64r2, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips64r2 436 {ArchSpec::eCore_mips64r6, llvm::ELF::EM_MIPS, 437 ArchSpec::eMIPSSubType_mips64r6, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips64r6 438 {ArchSpec::eCore_mips64el, llvm::ELF::EM_MIPS, 439 ArchSpec::eMIPSSubType_mips64el, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips64el 440 {ArchSpec::eCore_mips64r2el, llvm::ELF::EM_MIPS, 441 ArchSpec::eMIPSSubType_mips64r2el, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips64r2el 442 {ArchSpec::eCore_mips64r6el, llvm::ELF::EM_MIPS, 443 ArchSpec::eMIPSSubType_mips64r6el, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips64r6el 444 {ArchSpec::eCore_hexagon_generic, llvm::ELF::EM_HEXAGON, 445 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // HEXAGON 446 {ArchSpec::eCore_arc, llvm::ELF::EM_ARC_COMPACT2, LLDB_INVALID_CPUTYPE, 447 0xFFFFFFFFu, 0xFFFFFFFFu}, // ARC 448}; 449 450static const ArchDefinition g_elf_arch_def = { 451 eArchTypeELF, 452 llvm::array_lengthof(g_elf_arch_entries), 453 g_elf_arch_entries, 454 "elf", 455}; 456 457static const ArchDefinitionEntry g_coff_arch_entries[] = { 458 {ArchSpec::eCore_x86_32_i386, llvm::COFF::IMAGE_FILE_MACHINE_I386, 459 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // Intel 80x86 460 {ArchSpec::eCore_ppc_generic, llvm::COFF::IMAGE_FILE_MACHINE_POWERPC, 461 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // PowerPC 462 {ArchSpec::eCore_ppc_generic, llvm::COFF::IMAGE_FILE_MACHINE_POWERPCFP, 463 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // PowerPC (with FPU) 464 {ArchSpec::eCore_arm_generic, llvm::COFF::IMAGE_FILE_MACHINE_ARM, 465 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // ARM 466 {ArchSpec::eCore_arm_armv7, llvm::COFF::IMAGE_FILE_MACHINE_ARMNT, 467 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // ARMv7 468 {ArchSpec::eCore_thumb, llvm::COFF::IMAGE_FILE_MACHINE_THUMB, 469 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // ARMv7 470 {ArchSpec::eCore_x86_64_x86_64, llvm::COFF::IMAGE_FILE_MACHINE_AMD64, 471 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // AMD64 472 {ArchSpec::eCore_arm_arm64, llvm::COFF::IMAGE_FILE_MACHINE_ARM64, 473 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu} // ARM64 474}; 475 476static const ArchDefinition g_coff_arch_def = { 477 eArchTypeCOFF, 478 llvm::array_lengthof(g_coff_arch_entries), 479 g_coff_arch_entries, 480 "pe-coff", 481}; 482 483//===----------------------------------------------------------------------===// 484// Table of all ArchDefinitions 485static const ArchDefinition *g_arch_definitions[] = { 486 &g_macho_arch_def, &g_elf_arch_def, &g_coff_arch_def}; 487 488static const size_t k_num_arch_definitions = 489 llvm::array_lengthof(g_arch_definitions); 490 491//===----------------------------------------------------------------------===// 492// Static helper functions. 493 494// Get the architecture definition for a given object type. 495static const ArchDefinition *FindArchDefinition(ArchitectureType arch_type) { 496 for (unsigned int i = 0; i < k_num_arch_definitions; ++i) { 497 const ArchDefinition *def = g_arch_definitions[i]; 498 if (def->type == arch_type) 499 return def; 500 } 501 return nullptr; 502} 503 504// Get an architecture definition by name. 505static const CoreDefinition *FindCoreDefinition(llvm::StringRef name) { 506 for (unsigned int i = 0; i < llvm::array_lengthof(g_core_definitions); ++i) { 507 if (name.equals_lower(g_core_definitions[i].name)) 508 return &g_core_definitions[i]; 509 } 510 return nullptr; 511} 512 513static inline const CoreDefinition *FindCoreDefinition(ArchSpec::Core core) { 514 if (core < llvm::array_lengthof(g_core_definitions)) 515 return &g_core_definitions[core]; 516 return nullptr; 517} 518 519// Get a definition entry by cpu type and subtype. 520static const ArchDefinitionEntry * 521FindArchDefinitionEntry(const ArchDefinition *def, uint32_t cpu, uint32_t sub) { 522 if (def == nullptr) 523 return nullptr; 524 525 const ArchDefinitionEntry *entries = def->entries; 526 for (size_t i = 0; i < def->num_entries; ++i) { 527 if (entries[i].cpu == (cpu & entries[i].cpu_mask)) 528 if (entries[i].sub == (sub & entries[i].sub_mask)) 529 return &entries[i]; 530 } 531 return nullptr; 532} 533 534static const ArchDefinitionEntry * 535FindArchDefinitionEntry(const ArchDefinition *def, ArchSpec::Core core) { 536 if (def == nullptr) 537 return nullptr; 538 539 const ArchDefinitionEntry *entries = def->entries; 540 for (size_t i = 0; i < def->num_entries; ++i) { 541 if (entries[i].core == core) 542 return &entries[i]; 543 } 544 return nullptr; 545} 546 547//===----------------------------------------------------------------------===// 548// Constructors and destructors. 549 550ArchSpec::ArchSpec() {} 551 552ArchSpec::ArchSpec(const char *triple_cstr) { 553 if (triple_cstr) 554 SetTriple(triple_cstr); 555} 556 557ArchSpec::ArchSpec(llvm::StringRef triple_str) { SetTriple(triple_str); } 558 559ArchSpec::ArchSpec(const llvm::Triple &triple) { SetTriple(triple); } 560 561ArchSpec::ArchSpec(ArchitectureType arch_type, uint32_t cpu, uint32_t subtype) { 562 SetArchitecture(arch_type, cpu, subtype); 563} 564 565ArchSpec::~ArchSpec() = default; 566 567void ArchSpec::Clear() { 568 m_triple = llvm::Triple(); 569 m_core = kCore_invalid; 570 m_byte_order = eByteOrderInvalid; 571 m_distribution_id.Clear(); 572 m_flags = 0; 573} 574 575//===----------------------------------------------------------------------===// 576// Predicates. 577 578const char *ArchSpec::GetArchitectureName() const { 579 const CoreDefinition *core_def = FindCoreDefinition(m_core); 580 if (core_def) 581 return core_def->name; 582 return "unknown"; 583} 584 585bool ArchSpec::IsMIPS() const { return GetTriple().isMIPS(); } 586 587std::string ArchSpec::GetTargetABI() const { 588 589 std::string abi; 590 591 if (IsMIPS()) { 592 switch (GetFlags() & ArchSpec::eMIPSABI_mask) { 593 case ArchSpec::eMIPSABI_N64: 594 abi = "n64"; 595 return abi; 596 case ArchSpec::eMIPSABI_N32: 597 abi = "n32"; 598 return abi; 599 case ArchSpec::eMIPSABI_O32: 600 abi = "o32"; 601 return abi; 602 default: 603 return abi; 604 } 605 } 606 return abi; 607} 608 609void ArchSpec::SetFlags(std::string elf_abi) { 610 611 uint32_t flag = GetFlags(); 612 if (IsMIPS()) { 613 if (elf_abi == "n64") 614 flag |= ArchSpec::eMIPSABI_N64; 615 else if (elf_abi == "n32") 616 flag |= ArchSpec::eMIPSABI_N32; 617 else if (elf_abi == "o32") 618 flag |= ArchSpec::eMIPSABI_O32; 619 } 620 SetFlags(flag); 621} 622 623std::string ArchSpec::GetClangTargetCPU() const { 624 std::string cpu; 625 626 if (IsMIPS()) { 627 switch (m_core) { 628 case ArchSpec::eCore_mips32: 629 case ArchSpec::eCore_mips32el: 630 cpu = "mips32"; 631 break; 632 case ArchSpec::eCore_mips32r2: 633 case ArchSpec::eCore_mips32r2el: 634 cpu = "mips32r2"; 635 break; 636 case ArchSpec::eCore_mips32r3: 637 case ArchSpec::eCore_mips32r3el: 638 cpu = "mips32r3"; 639 break; 640 case ArchSpec::eCore_mips32r5: 641 case ArchSpec::eCore_mips32r5el: 642 cpu = "mips32r5"; 643 break; 644 case ArchSpec::eCore_mips32r6: 645 case ArchSpec::eCore_mips32r6el: 646 cpu = "mips32r6"; 647 break; 648 case ArchSpec::eCore_mips64: 649 case ArchSpec::eCore_mips64el: 650 cpu = "mips64"; 651 break; 652 case ArchSpec::eCore_mips64r2: 653 case ArchSpec::eCore_mips64r2el: 654 cpu = "mips64r2"; 655 break; 656 case ArchSpec::eCore_mips64r3: 657 case ArchSpec::eCore_mips64r3el: 658 cpu = "mips64r3"; 659 break; 660 case ArchSpec::eCore_mips64r5: 661 case ArchSpec::eCore_mips64r5el: 662 cpu = "mips64r5"; 663 break; 664 case ArchSpec::eCore_mips64r6: 665 case ArchSpec::eCore_mips64r6el: 666 cpu = "mips64r6"; 667 break; 668 default: 669 break; 670 } 671 } 672 return cpu; 673} 674 675uint32_t ArchSpec::GetMachOCPUType() const { 676 const CoreDefinition *core_def = FindCoreDefinition(m_core); 677 if (core_def) { 678 const ArchDefinitionEntry *arch_def = 679 FindArchDefinitionEntry(&g_macho_arch_def, core_def->core); 680 if (arch_def) { 681 return arch_def->cpu; 682 } 683 } 684 return LLDB_INVALID_CPUTYPE; 685} 686 687uint32_t ArchSpec::GetMachOCPUSubType() const { 688 const CoreDefinition *core_def = FindCoreDefinition(m_core); 689 if (core_def) { 690 const ArchDefinitionEntry *arch_def = 691 FindArchDefinitionEntry(&g_macho_arch_def, core_def->core); 692 if (arch_def) { 693 return arch_def->sub; 694 } 695 } 696 return LLDB_INVALID_CPUTYPE; 697} 698 699uint32_t ArchSpec::GetDataByteSize() const { 700 return 1; 701} 702 703uint32_t ArchSpec::GetCodeByteSize() const { 704 return 1; 705} 706 707llvm::Triple::ArchType ArchSpec::GetMachine() const { 708 const CoreDefinition *core_def = FindCoreDefinition(m_core); 709 if (core_def) 710 return core_def->machine; 711 712 return llvm::Triple::UnknownArch; 713} 714 715ConstString ArchSpec::GetDistributionId() const { 716 return m_distribution_id; 717} 718 719void ArchSpec::SetDistributionId(const char *distribution_id) { 720 m_distribution_id.SetCString(distribution_id); 721} 722 723uint32_t ArchSpec::GetAddressByteSize() const { 724 const CoreDefinition *core_def = FindCoreDefinition(m_core); 725 if (core_def) { 726 if (core_def->machine == llvm::Triple::mips64 || 727 core_def->machine == llvm::Triple::mips64el) { 728 // For N32/O32 applications Address size is 4 bytes. 729 if (m_flags & (eMIPSABI_N32 | eMIPSABI_O32)) 730 return 4; 731 } 732 return core_def->addr_byte_size; 733 } 734 return 0; 735} 736 737ByteOrder ArchSpec::GetDefaultEndian() const { 738 const CoreDefinition *core_def = FindCoreDefinition(m_core); 739 if (core_def) 740 return core_def->default_byte_order; 741 return eByteOrderInvalid; 742} 743 744bool ArchSpec::CharIsSignedByDefault() const { 745 switch (m_triple.getArch()) { 746 default: 747 return true; 748 749 case llvm::Triple::aarch64: 750 case llvm::Triple::aarch64_32: 751 case llvm::Triple::aarch64_be: 752 case llvm::Triple::arm: 753 case llvm::Triple::armeb: 754 case llvm::Triple::thumb: 755 case llvm::Triple::thumbeb: 756 return m_triple.isOSDarwin() || m_triple.isOSWindows(); 757 758 case llvm::Triple::ppc: 759 case llvm::Triple::ppc64: 760 return m_triple.isOSDarwin(); 761 762 case llvm::Triple::ppc64le: 763 case llvm::Triple::systemz: 764 case llvm::Triple::xcore: 765 case llvm::Triple::arc: 766 return false; 767 } 768} 769 770lldb::ByteOrder ArchSpec::GetByteOrder() const { 771 if (m_byte_order == eByteOrderInvalid) 772 return GetDefaultEndian(); 773 return m_byte_order; 774} 775 776//===----------------------------------------------------------------------===// 777// Mutators. 778 779bool ArchSpec::SetTriple(const llvm::Triple &triple) { 780 m_triple = triple; 781 UpdateCore(); 782 return IsValid(); 783} 784 785bool lldb_private::ParseMachCPUDashSubtypeTriple(llvm::StringRef triple_str, 786 ArchSpec &arch) { 787 // Accept "12-10" or "12.10" as cpu type/subtype 788 if (triple_str.empty()) 789 return false; 790 791 size_t pos = triple_str.find_first_of("-."); 792 if (pos == llvm::StringRef::npos) 793 return false; 794 795 llvm::StringRef cpu_str = triple_str.substr(0, pos); 796 llvm::StringRef remainder = triple_str.substr(pos + 1); 797 if (cpu_str.empty() || remainder.empty()) 798 return false; 799 800 llvm::StringRef sub_str; 801 llvm::StringRef vendor; 802 llvm::StringRef os; 803 std::tie(sub_str, remainder) = remainder.split('-'); 804 std::tie(vendor, os) = remainder.split('-'); 805 806 uint32_t cpu = 0; 807 uint32_t sub = 0; 808 if (cpu_str.getAsInteger(10, cpu) || sub_str.getAsInteger(10, sub)) 809 return false; 810 811 if (!arch.SetArchitecture(eArchTypeMachO, cpu, sub)) 812 return false; 813 if (!vendor.empty() && !os.empty()) { 814 arch.GetTriple().setVendorName(vendor); 815 arch.GetTriple().setOSName(os); 816 } 817 818 return true; 819} 820 821bool ArchSpec::SetTriple(llvm::StringRef triple) { 822 if (triple.empty()) { 823 Clear(); 824 return false; 825 } 826 827 if (ParseMachCPUDashSubtypeTriple(triple, *this)) 828 return true; 829 830 SetTriple(llvm::Triple(llvm::Triple::normalize(triple))); 831 return IsValid(); 832} 833 834bool ArchSpec::ContainsOnlyArch(const llvm::Triple &normalized_triple) { 835 return !normalized_triple.getArchName().empty() && 836 normalized_triple.getOSName().empty() && 837 normalized_triple.getVendorName().empty() && 838 normalized_triple.getEnvironmentName().empty(); 839} 840 841void ArchSpec::MergeFrom(const ArchSpec &other) { 842 if (!TripleVendorWasSpecified() && other.TripleVendorWasSpecified()) 843 GetTriple().setVendor(other.GetTriple().getVendor()); 844 if (!TripleOSWasSpecified() && other.TripleOSWasSpecified()) 845 GetTriple().setOS(other.GetTriple().getOS()); 846 if (GetTriple().getArch() == llvm::Triple::UnknownArch) { 847 GetTriple().setArch(other.GetTriple().getArch()); 848 849 // MachO unknown64 isn't really invalid as the debugger can still obtain 850 // information from the binary, e.g. line tables. As such, we don't update 851 // the core here. 852 if (other.GetCore() != eCore_uknownMach64) 853 UpdateCore(); 854 } 855 if (!TripleEnvironmentWasSpecified() && 856 other.TripleEnvironmentWasSpecified()) { 857 GetTriple().setEnvironment(other.GetTriple().getEnvironment()); 858 } 859 // If this and other are both arm ArchSpecs and this ArchSpec is a generic 860 // "some kind of arm" spec but the other ArchSpec is a specific arm core, 861 // adopt the specific arm core. 862 if (GetTriple().getArch() == llvm::Triple::arm && 863 other.GetTriple().getArch() == llvm::Triple::arm && 864 IsCompatibleMatch(other) && GetCore() == ArchSpec::eCore_arm_generic && 865 other.GetCore() != ArchSpec::eCore_arm_generic) { 866 m_core = other.GetCore(); 867 CoreUpdated(false); 868 } 869 if (GetFlags() == 0) { 870 SetFlags(other.GetFlags()); 871 } 872} 873 874bool ArchSpec::SetArchitecture(ArchitectureType arch_type, uint32_t cpu, 875 uint32_t sub, uint32_t os) { 876 m_core = kCore_invalid; 877 bool update_triple = true; 878 const ArchDefinition *arch_def = FindArchDefinition(arch_type); 879 if (arch_def) { 880 const ArchDefinitionEntry *arch_def_entry = 881 FindArchDefinitionEntry(arch_def, cpu, sub); 882 if (arch_def_entry) { 883 const CoreDefinition *core_def = FindCoreDefinition(arch_def_entry->core); 884 if (core_def) { 885 m_core = core_def->core; 886 update_triple = false; 887 // Always use the architecture name because it might be more 888 // descriptive than the architecture enum ("armv7" -> 889 // llvm::Triple::arm). 890 m_triple.setArchName(llvm::StringRef(core_def->name)); 891 if (arch_type == eArchTypeMachO) { 892 m_triple.setVendor(llvm::Triple::Apple); 893 894 // Don't set the OS. It could be simulator, macosx, ios, watchos, 895 // tvos, bridgeos. We could get close with the cpu type - but we 896 // can't get it right all of the time. Better to leave this unset 897 // so other sections of code will set it when they have more 898 // information. NB: don't call m_triple.setOS 899 // (llvm::Triple::UnknownOS). That sets the OSName to "unknown" and 900 // the ArchSpec::TripleVendorWasSpecified() method says that any 901 // OSName setting means it was specified. 902 } else if (arch_type == eArchTypeELF) { 903 switch (os) { 904 case llvm::ELF::ELFOSABI_AIX: 905 m_triple.setOS(llvm::Triple::OSType::AIX); 906 break; 907 case llvm::ELF::ELFOSABI_FREEBSD: 908 m_triple.setOS(llvm::Triple::OSType::FreeBSD); 909 break; 910 case llvm::ELF::ELFOSABI_GNU: 911 m_triple.setOS(llvm::Triple::OSType::Linux); 912 break; 913 case llvm::ELF::ELFOSABI_NETBSD: 914 m_triple.setOS(llvm::Triple::OSType::NetBSD); 915 break; 916 case llvm::ELF::ELFOSABI_OPENBSD: 917 m_triple.setOS(llvm::Triple::OSType::OpenBSD); 918 break; 919 case llvm::ELF::ELFOSABI_SOLARIS: 920 m_triple.setOS(llvm::Triple::OSType::Solaris); 921 break; 922 } 923 } else if (arch_type == eArchTypeCOFF && os == llvm::Triple::Win32) { 924 m_triple.setVendor(llvm::Triple::PC); 925 m_triple.setOS(llvm::Triple::Win32); 926 } else { 927 m_triple.setVendor(llvm::Triple::UnknownVendor); 928 m_triple.setOS(llvm::Triple::UnknownOS); 929 } 930 // Fall back onto setting the machine type if the arch by name 931 // failed... 932 if (m_triple.getArch() == llvm::Triple::UnknownArch) 933 m_triple.setArch(core_def->machine); 934 } 935 } else { 936 Log *log(lldb_private::GetLogIfAnyCategoriesSet(LIBLLDB_LOG_TARGET | LIBLLDB_LOG_PROCESS | LIBLLDB_LOG_PLATFORM)); 937 LLDB_LOGF(log, 938 "Unable to find a core definition for cpu 0x%" PRIx32 939 " sub %" PRId32, 940 cpu, sub); 941 } 942 } 943 CoreUpdated(update_triple); 944 return IsValid(); 945} 946 947uint32_t ArchSpec::GetMinimumOpcodeByteSize() const { 948 const CoreDefinition *core_def = FindCoreDefinition(m_core); 949 if (core_def) 950 return core_def->min_opcode_byte_size; 951 return 0; 952} 953 954uint32_t ArchSpec::GetMaximumOpcodeByteSize() const { 955 const CoreDefinition *core_def = FindCoreDefinition(m_core); 956 if (core_def) 957 return core_def->max_opcode_byte_size; 958 return 0; 959} 960 961bool ArchSpec::IsExactMatch(const ArchSpec &rhs) const { 962 return IsEqualTo(rhs, true); 963} 964 965bool ArchSpec::IsCompatibleMatch(const ArchSpec &rhs) const { 966 return IsEqualTo(rhs, false); 967} 968 969static bool IsCompatibleEnvironment(llvm::Triple::EnvironmentType lhs, 970 llvm::Triple::EnvironmentType rhs) { 971 if (lhs == rhs) 972 return true; 973 974 // If any of the environment is unknown then they are compatible 975 if (lhs == llvm::Triple::UnknownEnvironment || 976 rhs == llvm::Triple::UnknownEnvironment) 977 return true; 978 979 // If one of the environment is Android and the other one is EABI then they 980 // are considered to be compatible. This is required as a workaround for 981 // shared libraries compiled for Android without the NOTE section indicating 982 // that they are using the Android ABI. 983 if ((lhs == llvm::Triple::Android && rhs == llvm::Triple::EABI) || 984 (rhs == llvm::Triple::Android && lhs == llvm::Triple::EABI) || 985 (lhs == llvm::Triple::GNUEABI && rhs == llvm::Triple::EABI) || 986 (rhs == llvm::Triple::GNUEABI && lhs == llvm::Triple::EABI) || 987 (lhs == llvm::Triple::GNUEABIHF && rhs == llvm::Triple::EABIHF) || 988 (rhs == llvm::Triple::GNUEABIHF && lhs == llvm::Triple::EABIHF)) 989 return true; 990 991 return false; 992} 993 994bool ArchSpec::IsEqualTo(const ArchSpec &rhs, bool exact_match) const { 995 // explicitly ignoring m_distribution_id in this method. 996 997 if (GetByteOrder() != rhs.GetByteOrder()) 998 return false; 999 1000 const ArchSpec::Core lhs_core = GetCore(); 1001 const ArchSpec::Core rhs_core = rhs.GetCore(); 1002 1003 const bool core_match = cores_match(lhs_core, rhs_core, true, exact_match); 1004 1005 if (core_match) { 1006 const llvm::Triple &lhs_triple = GetTriple(); 1007 const llvm::Triple &rhs_triple = rhs.GetTriple(); 1008 1009 const llvm::Triple::VendorType lhs_triple_vendor = lhs_triple.getVendor(); 1010 const llvm::Triple::VendorType rhs_triple_vendor = rhs_triple.getVendor(); 1011 if (lhs_triple_vendor != rhs_triple_vendor) { 1012 const bool rhs_vendor_specified = rhs.TripleVendorWasSpecified(); 1013 const bool lhs_vendor_specified = TripleVendorWasSpecified(); 1014 // Both architectures had the vendor specified, so if they aren't equal 1015 // then we return false 1016 if (rhs_vendor_specified && lhs_vendor_specified) 1017 return false; 1018 1019 // Only fail if both vendor types are not unknown 1020 if (lhs_triple_vendor != llvm::Triple::UnknownVendor && 1021 rhs_triple_vendor != llvm::Triple::UnknownVendor) 1022 return false; 1023 } 1024 1025 const llvm::Triple::OSType lhs_triple_os = lhs_triple.getOS(); 1026 const llvm::Triple::OSType rhs_triple_os = rhs_triple.getOS(); 1027 if (lhs_triple_os != rhs_triple_os) { 1028 const bool rhs_os_specified = rhs.TripleOSWasSpecified(); 1029 const bool lhs_os_specified = TripleOSWasSpecified(); 1030 // Both architectures had the OS specified, so if they aren't equal then 1031 // we return false 1032 if (rhs_os_specified && lhs_os_specified) 1033 return false; 1034 1035 // Only fail if both os types are not unknown 1036 if (lhs_triple_os != llvm::Triple::UnknownOS && 1037 rhs_triple_os != llvm::Triple::UnknownOS) 1038 return false; 1039 } 1040 1041 const llvm::Triple::EnvironmentType lhs_triple_env = 1042 lhs_triple.getEnvironment(); 1043 const llvm::Triple::EnvironmentType rhs_triple_env = 1044 rhs_triple.getEnvironment(); 1045 1046 return IsCompatibleEnvironment(lhs_triple_env, rhs_triple_env); 1047 } 1048 return false; 1049} 1050 1051void ArchSpec::UpdateCore() { 1052 llvm::StringRef arch_name(m_triple.getArchName()); 1053 const CoreDefinition *core_def = FindCoreDefinition(arch_name); 1054 if (core_def) { 1055 m_core = core_def->core; 1056 // Set the byte order to the default byte order for an architecture. This 1057 // can be modified if needed for cases when cores handle both big and 1058 // little endian 1059 m_byte_order = core_def->default_byte_order; 1060 } else { 1061 Clear(); 1062 } 1063} 1064 1065//===----------------------------------------------------------------------===// 1066// Helper methods. 1067 1068void ArchSpec::CoreUpdated(bool update_triple) { 1069 const CoreDefinition *core_def = FindCoreDefinition(m_core); 1070 if (core_def) { 1071 if (update_triple) 1072 m_triple = llvm::Triple(core_def->name, "unknown", "unknown"); 1073 m_byte_order = core_def->default_byte_order; 1074 } else { 1075 if (update_triple) 1076 m_triple = llvm::Triple(); 1077 m_byte_order = eByteOrderInvalid; 1078 } 1079} 1080 1081//===----------------------------------------------------------------------===// 1082// Operators. 1083 1084static bool cores_match(const ArchSpec::Core core1, const ArchSpec::Core core2, 1085 bool try_inverse, bool enforce_exact_match) { 1086 if (core1 == core2) 1087 return true; 1088 1089 switch (core1) { 1090 case ArchSpec::kCore_any: 1091 return true; 1092 1093 case ArchSpec::eCore_arm_generic: 1094 if (enforce_exact_match) 1095 break; 1096 LLVM_FALLTHROUGH; 1097 case ArchSpec::kCore_arm_any: 1098 if (core2 >= ArchSpec::kCore_arm_first && core2 <= ArchSpec::kCore_arm_last) 1099 return true; 1100 if (core2 >= ArchSpec::kCore_thumb_first && 1101 core2 <= ArchSpec::kCore_thumb_last) 1102 return true; 1103 if (core2 == ArchSpec::kCore_arm_any) 1104 return true; 1105 break; 1106 1107 case ArchSpec::kCore_x86_32_any: 1108 if ((core2 >= ArchSpec::kCore_x86_32_first && 1109 core2 <= ArchSpec::kCore_x86_32_last) || 1110 (core2 == ArchSpec::kCore_x86_32_any)) 1111 return true; 1112 break; 1113 1114 case ArchSpec::kCore_x86_64_any: 1115 if ((core2 >= ArchSpec::kCore_x86_64_first && 1116 core2 <= ArchSpec::kCore_x86_64_last) || 1117 (core2 == ArchSpec::kCore_x86_64_any)) 1118 return true; 1119 break; 1120 1121 case ArchSpec::kCore_ppc_any: 1122 if ((core2 >= ArchSpec::kCore_ppc_first && 1123 core2 <= ArchSpec::kCore_ppc_last) || 1124 (core2 == ArchSpec::kCore_ppc_any)) 1125 return true; 1126 break; 1127 1128 case ArchSpec::kCore_ppc64_any: 1129 if ((core2 >= ArchSpec::kCore_ppc64_first && 1130 core2 <= ArchSpec::kCore_ppc64_last) || 1131 (core2 == ArchSpec::kCore_ppc64_any)) 1132 return true; 1133 break; 1134 1135 case ArchSpec::eCore_arm_armv6m: 1136 if (!enforce_exact_match) { 1137 if (core2 == ArchSpec::eCore_arm_generic) 1138 return true; 1139 try_inverse = false; 1140 if (core2 == ArchSpec::eCore_arm_armv7) 1141 return true; 1142 if (core2 == ArchSpec::eCore_arm_armv6m) 1143 return true; 1144 } 1145 break; 1146 1147 case ArchSpec::kCore_hexagon_any: 1148 if ((core2 >= ArchSpec::kCore_hexagon_first && 1149 core2 <= ArchSpec::kCore_hexagon_last) || 1150 (core2 == ArchSpec::kCore_hexagon_any)) 1151 return true; 1152 break; 1153 1154 // v. https://en.wikipedia.org/wiki/ARM_Cortex-M#Silicon_customization 1155 // Cortex-M0 - ARMv6-M - armv6m Cortex-M3 - ARMv7-M - armv7m Cortex-M4 - 1156 // ARMv7E-M - armv7em 1157 case ArchSpec::eCore_arm_armv7em: 1158 if (!enforce_exact_match) { 1159 if (core2 == ArchSpec::eCore_arm_generic) 1160 return true; 1161 if (core2 == ArchSpec::eCore_arm_armv7m) 1162 return true; 1163 if (core2 == ArchSpec::eCore_arm_armv6m) 1164 return true; 1165 if (core2 == ArchSpec::eCore_arm_armv7) 1166 return true; 1167 try_inverse = true; 1168 } 1169 break; 1170 1171 // v. https://en.wikipedia.org/wiki/ARM_Cortex-M#Silicon_customization 1172 // Cortex-M0 - ARMv6-M - armv6m Cortex-M3 - ARMv7-M - armv7m Cortex-M4 - 1173 // ARMv7E-M - armv7em 1174 case ArchSpec::eCore_arm_armv7m: 1175 if (!enforce_exact_match) { 1176 if (core2 == ArchSpec::eCore_arm_generic) 1177 return true; 1178 if (core2 == ArchSpec::eCore_arm_armv6m) 1179 return true; 1180 if (core2 == ArchSpec::eCore_arm_armv7) 1181 return true; 1182 if (core2 == ArchSpec::eCore_arm_armv7em) 1183 return true; 1184 try_inverse = true; 1185 } 1186 break; 1187 1188 case ArchSpec::eCore_arm_armv7f: 1189 case ArchSpec::eCore_arm_armv7k: 1190 case ArchSpec::eCore_arm_armv7s: 1191 case ArchSpec::eCore_arm_armv7l: 1192 case ArchSpec::eCore_arm_armv8l: 1193 if (!enforce_exact_match) { 1194 if (core2 == ArchSpec::eCore_arm_generic) 1195 return true; 1196 if (core2 == ArchSpec::eCore_arm_armv7) 1197 return true; 1198 try_inverse = false; 1199 } 1200 break; 1201 1202 case ArchSpec::eCore_x86_64_x86_64h: 1203 if (!enforce_exact_match) { 1204 try_inverse = false; 1205 if (core2 == ArchSpec::eCore_x86_64_x86_64) 1206 return true; 1207 } 1208 break; 1209 1210 case ArchSpec::eCore_arm_armv8: 1211 if (!enforce_exact_match) { 1212 if (core2 == ArchSpec::eCore_arm_arm64) 1213 return true; 1214 if (core2 == ArchSpec::eCore_arm_aarch64) 1215 return true; 1216 try_inverse = false; 1217 } 1218 break; 1219 1220 case ArchSpec::eCore_arm_aarch64: 1221 if (!enforce_exact_match) { 1222 if (core2 == ArchSpec::eCore_arm_arm64) 1223 return true; 1224 if (core2 == ArchSpec::eCore_arm_armv8) 1225 return true; 1226 try_inverse = false; 1227 } 1228 break; 1229 1230 case ArchSpec::eCore_arm_arm64: 1231 if (!enforce_exact_match) { 1232 if (core2 == ArchSpec::eCore_arm_aarch64) 1233 return true; 1234 if (core2 == ArchSpec::eCore_arm_armv8) 1235 return true; 1236 try_inverse = false; 1237 } 1238 break; 1239 1240 case ArchSpec::eCore_arm_arm64_32: 1241 if (!enforce_exact_match) { 1242 if (core2 == ArchSpec::eCore_arm_generic) 1243 return true; 1244 try_inverse = false; 1245 } 1246 break; 1247 1248 case ArchSpec::eCore_mips32: 1249 if (!enforce_exact_match) { 1250 if (core2 >= ArchSpec::kCore_mips32_first && 1251 core2 <= ArchSpec::kCore_mips32_last) 1252 return true; 1253 try_inverse = false; 1254 } 1255 break; 1256 1257 case ArchSpec::eCore_mips32el: 1258 if (!enforce_exact_match) { 1259 if (core2 >= ArchSpec::kCore_mips32el_first && 1260 core2 <= ArchSpec::kCore_mips32el_last) 1261 return true; 1262 try_inverse = true; 1263 } 1264 break; 1265 1266 case ArchSpec::eCore_mips64: 1267 if (!enforce_exact_match) { 1268 if (core2 >= ArchSpec::kCore_mips32_first && 1269 core2 <= ArchSpec::kCore_mips32_last) 1270 return true; 1271 if (core2 >= ArchSpec::kCore_mips64_first && 1272 core2 <= ArchSpec::kCore_mips64_last) 1273 return true; 1274 try_inverse = false; 1275 } 1276 break; 1277 1278 case ArchSpec::eCore_mips64el: 1279 if (!enforce_exact_match) { 1280 if (core2 >= ArchSpec::kCore_mips32el_first && 1281 core2 <= ArchSpec::kCore_mips32el_last) 1282 return true; 1283 if (core2 >= ArchSpec::kCore_mips64el_first && 1284 core2 <= ArchSpec::kCore_mips64el_last) 1285 return true; 1286 try_inverse = false; 1287 } 1288 break; 1289 1290 case ArchSpec::eCore_mips64r2: 1291 case ArchSpec::eCore_mips64r3: 1292 case ArchSpec::eCore_mips64r5: 1293 if (!enforce_exact_match) { 1294 if (core2 >= ArchSpec::kCore_mips32_first && core2 <= (core1 - 10)) 1295 return true; 1296 if (core2 >= ArchSpec::kCore_mips64_first && core2 <= (core1 - 1)) 1297 return true; 1298 try_inverse = false; 1299 } 1300 break; 1301 1302 case ArchSpec::eCore_mips64r2el: 1303 case ArchSpec::eCore_mips64r3el: 1304 case ArchSpec::eCore_mips64r5el: 1305 if (!enforce_exact_match) { 1306 if (core2 >= ArchSpec::kCore_mips32el_first && core2 <= (core1 - 10)) 1307 return true; 1308 if (core2 >= ArchSpec::kCore_mips64el_first && core2 <= (core1 - 1)) 1309 return true; 1310 try_inverse = false; 1311 } 1312 break; 1313 1314 case ArchSpec::eCore_mips32r2: 1315 case ArchSpec::eCore_mips32r3: 1316 case ArchSpec::eCore_mips32r5: 1317 if (!enforce_exact_match) { 1318 if (core2 >= ArchSpec::kCore_mips32_first && core2 <= core1) 1319 return true; 1320 } 1321 break; 1322 1323 case ArchSpec::eCore_mips32r2el: 1324 case ArchSpec::eCore_mips32r3el: 1325 case ArchSpec::eCore_mips32r5el: 1326 if (!enforce_exact_match) { 1327 if (core2 >= ArchSpec::kCore_mips32el_first && core2 <= core1) 1328 return true; 1329 } 1330 break; 1331 1332 case ArchSpec::eCore_mips32r6: 1333 if (!enforce_exact_match) { 1334 if (core2 == ArchSpec::eCore_mips32 || core2 == ArchSpec::eCore_mips32r6) 1335 return true; 1336 } 1337 break; 1338 1339 case ArchSpec::eCore_mips32r6el: 1340 if (!enforce_exact_match) { 1341 if (core2 == ArchSpec::eCore_mips32el || 1342 core2 == ArchSpec::eCore_mips32r6el) 1343 return true; 1344 } 1345 break; 1346 1347 case ArchSpec::eCore_mips64r6: 1348 if (!enforce_exact_match) { 1349 if (core2 == ArchSpec::eCore_mips32 || core2 == ArchSpec::eCore_mips32r6) 1350 return true; 1351 if (core2 == ArchSpec::eCore_mips64 || core2 == ArchSpec::eCore_mips64r6) 1352 return true; 1353 } 1354 break; 1355 1356 case ArchSpec::eCore_mips64r6el: 1357 if (!enforce_exact_match) { 1358 if (core2 == ArchSpec::eCore_mips32el || 1359 core2 == ArchSpec::eCore_mips32r6el) 1360 return true; 1361 if (core2 == ArchSpec::eCore_mips64el || 1362 core2 == ArchSpec::eCore_mips64r6el) 1363 return true; 1364 } 1365 break; 1366 1367 default: 1368 break; 1369 } 1370 if (try_inverse) 1371 return cores_match(core2, core1, false, enforce_exact_match); 1372 return false; 1373} 1374 1375bool lldb_private::operator<(const ArchSpec &lhs, const ArchSpec &rhs) { 1376 const ArchSpec::Core lhs_core = lhs.GetCore(); 1377 const ArchSpec::Core rhs_core = rhs.GetCore(); 1378 return lhs_core < rhs_core; 1379} 1380 1381 1382bool lldb_private::operator==(const ArchSpec &lhs, const ArchSpec &rhs) { 1383 return lhs.GetCore() == rhs.GetCore(); 1384} 1385 1386bool ArchSpec::IsFullySpecifiedTriple() const { 1387 const auto &user_specified_triple = GetTriple(); 1388 1389 bool user_triple_fully_specified = false; 1390 1391 if ((user_specified_triple.getOS() != llvm::Triple::UnknownOS) || 1392 TripleOSWasSpecified()) { 1393 if ((user_specified_triple.getVendor() != llvm::Triple::UnknownVendor) || 1394 TripleVendorWasSpecified()) { 1395 const unsigned unspecified = 0; 1396 if (user_specified_triple.getOSMajorVersion() != unspecified) { 1397 user_triple_fully_specified = true; 1398 } 1399 } 1400 } 1401 1402 return user_triple_fully_specified; 1403} 1404 1405void ArchSpec::PiecewiseTripleCompare( 1406 const ArchSpec &other, bool &arch_different, bool &vendor_different, 1407 bool &os_different, bool &os_version_different, bool &env_different) const { 1408 const llvm::Triple &me(GetTriple()); 1409 const llvm::Triple &them(other.GetTriple()); 1410 1411 arch_different = (me.getArch() != them.getArch()); 1412 1413 vendor_different = (me.getVendor() != them.getVendor()); 1414 1415 os_different = (me.getOS() != them.getOS()); 1416 1417 os_version_different = (me.getOSMajorVersion() != them.getOSMajorVersion()); 1418 1419 env_different = (me.getEnvironment() != them.getEnvironment()); 1420} 1421 1422bool ArchSpec::IsAlwaysThumbInstructions() const { 1423 std::string Status; 1424 if (GetTriple().getArch() == llvm::Triple::arm || 1425 GetTriple().getArch() == llvm::Triple::thumb) { 1426 // v. https://en.wikipedia.org/wiki/ARM_Cortex-M 1427 // 1428 // Cortex-M0 through Cortex-M7 are ARM processor cores which can only 1429 // execute thumb instructions. We map the cores to arch names like this: 1430 // 1431 // Cortex-M0, Cortex-M0+, Cortex-M1: armv6m Cortex-M3: armv7m Cortex-M4, 1432 // Cortex-M7: armv7em 1433 1434 if (GetCore() == ArchSpec::Core::eCore_arm_armv7m || 1435 GetCore() == ArchSpec::Core::eCore_arm_armv7em || 1436 GetCore() == ArchSpec::Core::eCore_arm_armv6m || 1437 GetCore() == ArchSpec::Core::eCore_thumbv7m || 1438 GetCore() == ArchSpec::Core::eCore_thumbv7em || 1439 GetCore() == ArchSpec::Core::eCore_thumbv6m) { 1440 return true; 1441 } 1442 // Windows on ARM is always thumb. 1443 if (GetTriple().isOSWindows()) 1444 return true; 1445 } 1446 return false; 1447} 1448 1449void ArchSpec::DumpTriple(llvm::raw_ostream &s) const { 1450 const llvm::Triple &triple = GetTriple(); 1451 llvm::StringRef arch_str = triple.getArchName(); 1452 llvm::StringRef vendor_str = triple.getVendorName(); 1453 llvm::StringRef os_str = triple.getOSName(); 1454 llvm::StringRef environ_str = triple.getEnvironmentName(); 1455 1456 s << llvm::formatv("{0}-{1}-{2}", arch_str.empty() ? "*" : arch_str, 1457 vendor_str.empty() ? "*" : vendor_str, 1458 os_str.empty() ? "*" : os_str); 1459 1460 if (!environ_str.empty()) 1461 s << "-" << environ_str; 1462} 1463