RegisterInfos_arm64.h revision 314564
178064Sume//===-- RegisterInfos_arm64.h -----------------------------------*- C++ -*-===// 262638Skris// 355505Sshin// The LLVM Compiler Infrastructure 455505Sshin// 555505Sshin// This file is distributed under the University of Illinois Open Source 655505Sshin// License. See LICENSE.TXT for details. 755505Sshin// 855505Sshin//===----------------------------------------------------------------------===// 955505Sshin 1055505Sshin#ifdef DECLARE_REGISTER_INFOS_ARM64_STRUCT 1155505Sshin 1255505Sshin// C Includes 1355505Sshin#include <stddef.h> 1455505Sshin 1555505Sshin// C++ Includes 1655505Sshin// Other libraries and framework includes 1755505Sshin// Project includes 1855505Sshin#include "lldb/lldb-defines.h" 1955505Sshin#include "lldb/lldb-enumerations.h" 2055505Sshin#include "lldb/lldb-private.h" 2155505Sshin 2255505Sshin#include "Utility/ARM64_DWARF_Registers.h" 2355505Sshin#include "Utility/ARM64_ehframe_Registers.h" 2455505Sshin 2555505Sshin#ifndef GPR_OFFSET 2655505Sshin#error GPR_OFFSET must be defined before including this header file 2755505Sshin#endif 2855505Sshin 2955505Sshin#ifndef GPR_OFFSET_NAME 3055505Sshin#error GPR_OFFSET_NAME must be defined before including this header file 3155505Sshin#endif 3255505Sshin 3355505Sshin#ifndef FPU_OFFSET 3455505Sshin#error FPU_OFFSET must be defined before including this header file 3555505Sshin#endif 3655505Sshin 3755505Sshin#ifndef FPU_OFFSET_NAME 3855505Sshin#error FPU_OFFSET_NAME must be defined before including this header file 3955505Sshin#endif 4055505Sshin 4155505Sshin#ifndef EXC_OFFSET_NAME 4255505Sshin#error EXC_OFFSET_NAME must be defined before including this header file 4355505Sshin#endif 4455505Sshin 4555505Sshin#ifndef DBG_OFFSET_NAME 4655505Sshin#error DBG_OFFSET_NAME must be defined before including this header file 4755505Sshin#endif 4855505Sshin 4962638Skris#ifndef DEFINE_DBG 5062638Skris#error DEFINE_DBG must be defined before including this header file 5155505Sshin#endif 52171135Sgnn 5355505Sshin// Offsets for a little-endian layout of the register context 5455505Sshin#define GPR_W_PSEUDO_REG_ENDIAN_OFFSET 0 5555505Sshin#define FPU_S_PSEUDO_REG_ENDIAN_OFFSET 0 5662638Skris#define FPU_D_PSEUDO_REG_ENDIAN_OFFSET 0 5755505Sshin 5855505Sshinenum { 5955505Sshin gpr_x0 = 0, 6055505Sshin gpr_x1, 6155505Sshin gpr_x2, 6255505Sshin gpr_x3, 6355505Sshin gpr_x4, 6462638Skris gpr_x5, 6562638Skris gpr_x6, 6655505Sshin gpr_x7, 6778064Sume gpr_x8, 6878064Sume gpr_x9, 6955505Sshin gpr_x10, 7062638Skris gpr_x11, 7155505Sshin gpr_x12, 7255505Sshin gpr_x13, 7355505Sshin gpr_x14, 7455505Sshin gpr_x15, 7555505Sshin gpr_x16, 7662638Skris gpr_x17, 7762638Skris gpr_x18, 7855505Sshin gpr_x19, 7955505Sshin gpr_x20, 8062638Skris gpr_x21, 8162638Skris gpr_x22, 8262638Skris gpr_x23, 8362638Skris gpr_x24, 8455505Sshin gpr_x25, 8555505Sshin gpr_x26, 8655505Sshin gpr_x27, 8755505Sshin gpr_x28, 8862638Skris gpr_x29 = 29, 8962638Skris gpr_fp = gpr_x29, 9062638Skris gpr_x30 = 30, 9162638Skris gpr_lr = gpr_x30, 9255505Sshin gpr_ra = gpr_x30, 9362638Skris gpr_x31 = 31, 9462638Skris gpr_sp = gpr_x31, 9562638Skris gpr_pc = 32, 9662638Skris gpr_cpsr, 9755505Sshin 98173412Skevlo gpr_w0, 9955505Sshin gpr_w1, 100173412Skevlo gpr_w2, 101173412Skevlo gpr_w3, 10278064Sume gpr_w4, 103173412Skevlo gpr_w5, 10478064Sume gpr_w6, 105173412Skevlo gpr_w7, 106173412Skevlo gpr_w8, 10778064Sume gpr_w9, 108173412Skevlo gpr_w10, 109173412Skevlo gpr_w11, 11078064Sume gpr_w12, 111173412Skevlo gpr_w13, 112173412Skevlo gpr_w14, 11378064Sume gpr_w15, 114173412Skevlo gpr_w16, 115173412Skevlo gpr_w17, 11678064Sume gpr_w18, 117173412Skevlo gpr_w19, 11878064Sume gpr_w20, 119173412Skevlo gpr_w21, 120173412Skevlo gpr_w22, 12178064Sume gpr_w23, 12278064Sume gpr_w24, 12355505Sshin gpr_w25, 12455505Sshin gpr_w26, 12555505Sshin gpr_w27, 12655505Sshin gpr_w28, 12755505Sshin 12855505Sshin fpu_v0, 12955505Sshin fpu_v1, 13055505Sshin fpu_v2, 13162638Skris fpu_v3, 13262638Skris fpu_v4, 13355505Sshin fpu_v5, 13455505Sshin fpu_v6, 13555505Sshin fpu_v7, 13655505Sshin fpu_v8, 13755505Sshin fpu_v9, 13855505Sshin fpu_v10, 13978064Sume fpu_v11, 14055505Sshin fpu_v12, 14155505Sshin fpu_v13, 14255505Sshin fpu_v14, 14355505Sshin fpu_v15, 14455505Sshin fpu_v16, 14555505Sshin fpu_v17, 14655505Sshin fpu_v18, 14755505Sshin fpu_v19, 14855505Sshin fpu_v20, 14962638Skris fpu_v21, 15078064Sume fpu_v22, 15162638Skris fpu_v23, 15262638Skris fpu_v24, 15362638Skris fpu_v25, 15462638Skris fpu_v26, 15562638Skris fpu_v27, 15662638Skris fpu_v28, 15762638Skris fpu_v29, 158136057Sstefanf fpu_v30, 15962638Skris fpu_v31, 16062638Skris 16162638Skris fpu_s0, 16262638Skris fpu_s1, 16362638Skris fpu_s2, 16462638Skris fpu_s3, 165136057Sstefanf fpu_s4, 16662638Skris fpu_s5, 16762638Skris fpu_s6, 16862638Skris fpu_s7, 16962638Skris fpu_s8, 17062638Skris fpu_s9, 17162638Skris fpu_s10, 172136057Sstefanf fpu_s11, 17362638Skris fpu_s12, 17462638Skris fpu_s13, 17562638Skris fpu_s14, 17662638Skris fpu_s15, 17762638Skris fpu_s16, 17862638Skris fpu_s17, 17978064Sume fpu_s18, 18055505Sshin fpu_s19, 18155505Sshin fpu_s20, 18255505Sshin fpu_s21, 18355505Sshin fpu_s22, 18462638Skris fpu_s23, 18562638Skris fpu_s24, 18662638Skris fpu_s25, 18755505Sshin fpu_s26, 18855505Sshin fpu_s27, 18955505Sshin fpu_s28, 19055505Sshin fpu_s29, 19155505Sshin fpu_s30, 19255505Sshin fpu_s31, 19355505Sshin 19455505Sshin fpu_d0, 19555505Sshin fpu_d1, 19655505Sshin fpu_d2, 19762638Skris fpu_d3, 19862638Skris fpu_d4, 19962638Skris fpu_d5, 20062638Skris fpu_d6, 201136057Sstefanf fpu_d7, 20262638Skris fpu_d8, 20362638Skris fpu_d9, 20455505Sshin fpu_d10, 20562638Skris fpu_d11, 20655505Sshin fpu_d12, 20755505Sshin fpu_d13, 20855505Sshin fpu_d14, 20955505Sshin fpu_d15, 21062638Skris fpu_d16, 21162638Skris fpu_d17, 21262638Skris fpu_d18, 21362638Skris fpu_d19, 214136057Sstefanf fpu_d20, 21562638Skris fpu_d21, 21662638Skris fpu_d22, 21755505Sshin fpu_d23, 21862638Skris fpu_d24, 21955505Sshin fpu_d25, 22055505Sshin fpu_d26, 22178064Sume fpu_d27, 22255505Sshin fpu_d28, 22355505Sshin fpu_d29, 22455505Sshin fpu_d30, 22555505Sshin fpu_d31, 22655505Sshin 22755505Sshin fpu_fpsr, 22855505Sshin fpu_fpcr, 22955505Sshin 230136057Sstefanf exc_far, 23155505Sshin exc_esr, 23255505Sshin exc_exception, 23355505Sshin 23455505Sshin dbg_bvr0, 23555505Sshin dbg_bvr1, 23655505Sshin dbg_bvr2, 23755505Sshin dbg_bvr3, 23855505Sshin dbg_bvr4, 23955505Sshin dbg_bvr5, 24055505Sshin dbg_bvr6, 24155505Sshin dbg_bvr7, 24255505Sshin dbg_bvr8, 24355505Sshin dbg_bvr9, 24455505Sshin dbg_bvr10, 24555505Sshin dbg_bvr11, 24655505Sshin dbg_bvr12, 24755505Sshin dbg_bvr13, 24855505Sshin dbg_bvr14, 24955505Sshin dbg_bvr15, 25055505Sshin 25155505Sshin dbg_bcr0, 25255505Sshin dbg_bcr1, 25355505Sshin dbg_bcr2, 25455505Sshin dbg_bcr3, 25555505Sshin dbg_bcr4, 25655505Sshin dbg_bcr5, 25755505Sshin dbg_bcr6, 25855505Sshin dbg_bcr7, 25955505Sshin dbg_bcr8, 26055505Sshin dbg_bcr9, 26155505Sshin dbg_bcr10, 26255505Sshin dbg_bcr11, 26355505Sshin dbg_bcr12, 26478064Sume dbg_bcr13, 26555505Sshin dbg_bcr14, 26655505Sshin dbg_bcr15, 26755505Sshin 26855505Sshin dbg_wvr0, 26955505Sshin dbg_wvr1, 27055505Sshin dbg_wvr2, 27155505Sshin dbg_wvr3, 27262638Skris dbg_wvr4, 27362638Skris dbg_wvr5, 27462638Skris dbg_wvr6, 27562638Skris dbg_wvr7, 27662638Skris dbg_wvr8, 27762638Skris dbg_wvr9, 27855505Sshin dbg_wvr10, 27955505Sshin dbg_wvr11, 28055505Sshin dbg_wvr12, 28155505Sshin dbg_wvr13, 28255505Sshin dbg_wvr14, 283136057Sstefanf dbg_wvr15, 28455505Sshin 28555505Sshin dbg_wcr0, 28655505Sshin dbg_wcr1, 28755505Sshin dbg_wcr2, 28862638Skris dbg_wcr3, 28962638Skris dbg_wcr4, 29062638Skris dbg_wcr5, 29162638Skris dbg_wcr6, 29262638Skris dbg_wcr7, 29362638Skris dbg_wcr8, 29462638Skris dbg_wcr9, 29555505Sshin dbg_wcr10, 29655505Sshin dbg_wcr11, 29755505Sshin dbg_wcr12, 29855505Sshin dbg_wcr13, 29955505Sshin dbg_wcr14, 30055505Sshin dbg_wcr15, 30155505Sshin 302136057Sstefanf k_num_registers 30355505Sshin}; 30455505Sshin 30555505Sshinstatic uint32_t g_contained_x0[] = {gpr_x0, LLDB_INVALID_REGNUM}; 30655505Sshinstatic uint32_t g_contained_x1[] = {gpr_x1, LLDB_INVALID_REGNUM}; 30755505Sshinstatic uint32_t g_contained_x2[] = {gpr_x2, LLDB_INVALID_REGNUM}; 308121561Sumestatic uint32_t g_contained_x3[] = {gpr_x3, LLDB_INVALID_REGNUM}; 30955505Sshinstatic uint32_t g_contained_x4[] = {gpr_x4, LLDB_INVALID_REGNUM}; 310121568Sumestatic uint32_t g_contained_x5[] = {gpr_x5, LLDB_INVALID_REGNUM}; 311136057Sstefanfstatic uint32_t g_contained_x6[] = {gpr_x6, LLDB_INVALID_REGNUM}; 31255505Sshinstatic uint32_t g_contained_x7[] = {gpr_x7, LLDB_INVALID_REGNUM}; 31355505Sshinstatic uint32_t g_contained_x8[] = {gpr_x8, LLDB_INVALID_REGNUM}; 31455505Sshinstatic uint32_t g_contained_x9[] = {gpr_x9, LLDB_INVALID_REGNUM}; 31555505Sshinstatic uint32_t g_contained_x10[] = {gpr_x10, LLDB_INVALID_REGNUM}; 31655505Sshinstatic uint32_t g_contained_x11[] = {gpr_x11, LLDB_INVALID_REGNUM}; 31755505Sshinstatic uint32_t g_contained_x12[] = {gpr_x12, LLDB_INVALID_REGNUM}; 31855505Sshinstatic uint32_t g_contained_x13[] = {gpr_x13, LLDB_INVALID_REGNUM}; 31955505Sshinstatic uint32_t g_contained_x14[] = {gpr_x14, LLDB_INVALID_REGNUM}; 32055505Sshinstatic uint32_t g_contained_x15[] = {gpr_x15, LLDB_INVALID_REGNUM}; 32168905Skrisstatic uint32_t g_contained_x16[] = {gpr_x16, LLDB_INVALID_REGNUM}; 32255505Sshinstatic uint32_t g_contained_x17[] = {gpr_x17, LLDB_INVALID_REGNUM}; 32355505Sshinstatic uint32_t g_contained_x18[] = {gpr_x18, LLDB_INVALID_REGNUM}; 32455505Sshinstatic uint32_t g_contained_x19[] = {gpr_x19, LLDB_INVALID_REGNUM}; 32578064Sumestatic uint32_t g_contained_x20[] = {gpr_x20, LLDB_INVALID_REGNUM}; 32655505Sshinstatic uint32_t g_contained_x21[] = {gpr_x21, LLDB_INVALID_REGNUM}; 32755505Sshinstatic uint32_t g_contained_x22[] = {gpr_x22, LLDB_INVALID_REGNUM}; 32862638Skrisstatic uint32_t g_contained_x23[] = {gpr_x23, LLDB_INVALID_REGNUM}; 32962638Skrisstatic uint32_t g_contained_x24[] = {gpr_x24, LLDB_INVALID_REGNUM}; 33062638Skrisstatic uint32_t g_contained_x25[] = {gpr_x25, LLDB_INVALID_REGNUM}; 33162638Skrisstatic uint32_t g_contained_x26[] = {gpr_x26, LLDB_INVALID_REGNUM}; 33262638Skrisstatic uint32_t g_contained_x27[] = {gpr_x27, LLDB_INVALID_REGNUM}; 33362638Skrisstatic uint32_t g_contained_x28[] = {gpr_x28, LLDB_INVALID_REGNUM}; 334136057Sstefanf 33562638Skrisstatic uint32_t g_w0_invalidates[] = {gpr_x0, LLDB_INVALID_REGNUM}; 33662638Skrisstatic uint32_t g_w1_invalidates[] = {gpr_x1, LLDB_INVALID_REGNUM}; 33762638Skrisstatic uint32_t g_w2_invalidates[] = {gpr_x2, LLDB_INVALID_REGNUM}; 33862638Skrisstatic uint32_t g_w3_invalidates[] = {gpr_x3, LLDB_INVALID_REGNUM}; 33962638Skrisstatic uint32_t g_w4_invalidates[] = {gpr_x4, LLDB_INVALID_REGNUM}; 34062638Skrisstatic uint32_t g_w5_invalidates[] = {gpr_x5, LLDB_INVALID_REGNUM}; 34162638Skrisstatic uint32_t g_w6_invalidates[] = {gpr_x6, LLDB_INVALID_REGNUM}; 34262638Skrisstatic uint32_t g_w7_invalidates[] = {gpr_x7, LLDB_INVALID_REGNUM}; 343136057Sstefanfstatic uint32_t g_w8_invalidates[] = {gpr_x8, LLDB_INVALID_REGNUM}; 34462638Skrisstatic uint32_t g_w9_invalidates[] = {gpr_x9, LLDB_INVALID_REGNUM}; 34562638Skrisstatic uint32_t g_w10_invalidates[] = {gpr_x10, LLDB_INVALID_REGNUM}; 34662638Skrisstatic uint32_t g_w11_invalidates[] = {gpr_x11, LLDB_INVALID_REGNUM}; 34755505Sshinstatic uint32_t g_w12_invalidates[] = {gpr_x12, LLDB_INVALID_REGNUM}; 34855505Sshinstatic uint32_t g_w13_invalidates[] = {gpr_x13, LLDB_INVALID_REGNUM}; 34955505Sshinstatic uint32_t g_w14_invalidates[] = {gpr_x14, LLDB_INVALID_REGNUM}; 35055505Sshinstatic uint32_t g_w15_invalidates[] = {gpr_x15, LLDB_INVALID_REGNUM}; 35155505Sshinstatic uint32_t g_w16_invalidates[] = {gpr_x16, LLDB_INVALID_REGNUM}; 35255505Sshinstatic uint32_t g_w17_invalidates[] = {gpr_x17, LLDB_INVALID_REGNUM}; 35378064Sumestatic uint32_t g_w18_invalidates[] = {gpr_x18, LLDB_INVALID_REGNUM}; 35462638Skrisstatic uint32_t g_w19_invalidates[] = {gpr_x19, LLDB_INVALID_REGNUM}; 35562638Skrisstatic uint32_t g_w20_invalidates[] = {gpr_x20, LLDB_INVALID_REGNUM}; 35662638Skrisstatic uint32_t g_w21_invalidates[] = {gpr_x21, LLDB_INVALID_REGNUM}; 35762638Skrisstatic uint32_t g_w22_invalidates[] = {gpr_x22, LLDB_INVALID_REGNUM}; 35862638Skrisstatic uint32_t g_w23_invalidates[] = {gpr_x23, LLDB_INVALID_REGNUM}; 35962638Skrisstatic uint32_t g_w24_invalidates[] = {gpr_x24, LLDB_INVALID_REGNUM}; 36062638Skrisstatic uint32_t g_w25_invalidates[] = {gpr_x25, LLDB_INVALID_REGNUM}; 36162638Skrisstatic uint32_t g_w26_invalidates[] = {gpr_x26, LLDB_INVALID_REGNUM}; 36262638Skrisstatic uint32_t g_w27_invalidates[] = {gpr_x27, LLDB_INVALID_REGNUM}; 36362638Skrisstatic uint32_t g_w28_invalidates[] = {gpr_x28, LLDB_INVALID_REGNUM}; 36462638Skris 36562638Skrisstatic uint32_t g_contained_v0[] = {fpu_v0, LLDB_INVALID_REGNUM}; 36662638Skrisstatic uint32_t g_contained_v1[] = {fpu_v1, LLDB_INVALID_REGNUM}; 36762638Skrisstatic uint32_t g_contained_v2[] = {fpu_v2, LLDB_INVALID_REGNUM}; 36862638Skrisstatic uint32_t g_contained_v3[] = {fpu_v3, LLDB_INVALID_REGNUM}; 369136057Sstefanfstatic uint32_t g_contained_v4[] = {fpu_v4, LLDB_INVALID_REGNUM}; 37062638Skrisstatic uint32_t g_contained_v5[] = {fpu_v5, LLDB_INVALID_REGNUM}; 37162638Skrisstatic uint32_t g_contained_v6[] = {fpu_v6, LLDB_INVALID_REGNUM}; 37262638Skrisstatic uint32_t g_contained_v7[] = {fpu_v7, LLDB_INVALID_REGNUM}; 37362638Skrisstatic uint32_t g_contained_v8[] = {fpu_v8, LLDB_INVALID_REGNUM}; 37462638Skrisstatic uint32_t g_contained_v9[] = {fpu_v9, LLDB_INVALID_REGNUM}; 37562638Skrisstatic uint32_t g_contained_v10[] = {fpu_v10, LLDB_INVALID_REGNUM}; 37662638Skrisstatic uint32_t g_contained_v11[] = {fpu_v11, LLDB_INVALID_REGNUM}; 37762638Skrisstatic uint32_t g_contained_v12[] = {fpu_v12, LLDB_INVALID_REGNUM}; 37862638Skrisstatic uint32_t g_contained_v13[] = {fpu_v13, LLDB_INVALID_REGNUM}; 37962638Skrisstatic uint32_t g_contained_v14[] = {fpu_v14, LLDB_INVALID_REGNUM}; 38062638Skrisstatic uint32_t g_contained_v15[] = {fpu_v15, LLDB_INVALID_REGNUM}; 38162638Skrisstatic uint32_t g_contained_v16[] = {fpu_v16, LLDB_INVALID_REGNUM}; 38262638Skrisstatic uint32_t g_contained_v17[] = {fpu_v17, LLDB_INVALID_REGNUM}; 38362638Skrisstatic uint32_t g_contained_v18[] = {fpu_v18, LLDB_INVALID_REGNUM}; 38462638Skrisstatic uint32_t g_contained_v19[] = {fpu_v19, LLDB_INVALID_REGNUM}; 38562638Skrisstatic uint32_t g_contained_v20[] = {fpu_v20, LLDB_INVALID_REGNUM}; 38662638Skrisstatic uint32_t g_contained_v21[] = {fpu_v21, LLDB_INVALID_REGNUM}; 38768905Skrisstatic uint32_t g_contained_v22[] = {fpu_v22, LLDB_INVALID_REGNUM}; 38862638Skrisstatic uint32_t g_contained_v23[] = {fpu_v23, LLDB_INVALID_REGNUM}; 38962638Skrisstatic uint32_t g_contained_v24[] = {fpu_v24, LLDB_INVALID_REGNUM}; 39062638Skrisstatic uint32_t g_contained_v25[] = {fpu_v25, LLDB_INVALID_REGNUM}; 39178064Sumestatic uint32_t g_contained_v26[] = {fpu_v26, LLDB_INVALID_REGNUM}; 39262638Skrisstatic uint32_t g_contained_v27[] = {fpu_v27, LLDB_INVALID_REGNUM}; 39362638Skrisstatic uint32_t g_contained_v28[] = {fpu_v28, LLDB_INVALID_REGNUM}; 39462638Skrisstatic uint32_t g_contained_v29[] = {fpu_v29, LLDB_INVALID_REGNUM}; 39562638Skrisstatic uint32_t g_contained_v30[] = {fpu_v30, LLDB_INVALID_REGNUM}; 39662638Skrisstatic uint32_t g_contained_v31[] = {fpu_v31, LLDB_INVALID_REGNUM}; 39762638Skris 39862638Skrisstatic uint32_t g_s0_invalidates[] = {fpu_v0, fpu_d0, LLDB_INVALID_REGNUM}; 39962638Skrisstatic uint32_t g_s1_invalidates[] = {fpu_v1, fpu_d1, LLDB_INVALID_REGNUM}; 400136057Sstefanfstatic uint32_t g_s2_invalidates[] = {fpu_v2, fpu_d2, LLDB_INVALID_REGNUM}; 40162638Skrisstatic uint32_t g_s3_invalidates[] = {fpu_v3, fpu_d3, LLDB_INVALID_REGNUM}; 40262638Skrisstatic uint32_t g_s4_invalidates[] = {fpu_v4, fpu_d4, LLDB_INVALID_REGNUM}; 40362638Skrisstatic uint32_t g_s5_invalidates[] = {fpu_v5, fpu_d5, LLDB_INVALID_REGNUM}; 40462638Skrisstatic uint32_t g_s6_invalidates[] = {fpu_v6, fpu_d6, LLDB_INVALID_REGNUM}; 40562638Skrisstatic uint32_t g_s7_invalidates[] = {fpu_v7, fpu_d7, LLDB_INVALID_REGNUM}; 40662638Skrisstatic uint32_t g_s8_invalidates[] = {fpu_v8, fpu_d8, LLDB_INVALID_REGNUM}; 40762638Skrisstatic uint32_t g_s9_invalidates[] = {fpu_v9, fpu_d9, LLDB_INVALID_REGNUM}; 40862638Skrisstatic uint32_t g_s10_invalidates[] = {fpu_v10, fpu_d10, LLDB_INVALID_REGNUM}; 409136057Sstefanfstatic uint32_t g_s11_invalidates[] = {fpu_v11, fpu_d11, LLDB_INVALID_REGNUM}; 41062638Skrisstatic uint32_t g_s12_invalidates[] = {fpu_v12, fpu_d12, LLDB_INVALID_REGNUM}; 41162638Skrisstatic uint32_t g_s13_invalidates[] = {fpu_v13, fpu_d13, LLDB_INVALID_REGNUM}; 41262638Skrisstatic uint32_t g_s14_invalidates[] = {fpu_v14, fpu_d14, LLDB_INVALID_REGNUM}; 41362638Skrisstatic uint32_t g_s15_invalidates[] = {fpu_v15, fpu_d15, LLDB_INVALID_REGNUM}; 41462638Skrisstatic uint32_t g_s16_invalidates[] = {fpu_v16, fpu_d16, LLDB_INVALID_REGNUM}; 41562638Skrisstatic uint32_t g_s17_invalidates[] = {fpu_v17, fpu_d17, LLDB_INVALID_REGNUM}; 41662638Skrisstatic uint32_t g_s18_invalidates[] = {fpu_v18, fpu_d18, LLDB_INVALID_REGNUM}; 41762638Skrisstatic uint32_t g_s19_invalidates[] = {fpu_v19, fpu_d19, LLDB_INVALID_REGNUM}; 41862638Skrisstatic uint32_t g_s20_invalidates[] = {fpu_v20, fpu_d20, LLDB_INVALID_REGNUM}; 41978064Sumestatic uint32_t g_s21_invalidates[] = {fpu_v21, fpu_d21, LLDB_INVALID_REGNUM}; 42055505Sshinstatic uint32_t g_s22_invalidates[] = {fpu_v22, fpu_d22, LLDB_INVALID_REGNUM}; 42155505Sshinstatic uint32_t g_s23_invalidates[] = {fpu_v23, fpu_d23, LLDB_INVALID_REGNUM}; 42255505Sshinstatic uint32_t g_s24_invalidates[] = {fpu_v24, fpu_d24, LLDB_INVALID_REGNUM}; 42355505Sshinstatic uint32_t g_s25_invalidates[] = {fpu_v25, fpu_d25, LLDB_INVALID_REGNUM}; 42455505Sshinstatic uint32_t g_s26_invalidates[] = {fpu_v26, fpu_d26, LLDB_INVALID_REGNUM}; 42555505Sshinstatic uint32_t g_s27_invalidates[] = {fpu_v27, fpu_d27, LLDB_INVALID_REGNUM}; 42655505Sshinstatic uint32_t g_s28_invalidates[] = {fpu_v28, fpu_d28, LLDB_INVALID_REGNUM}; 42755505Sshinstatic uint32_t g_s29_invalidates[] = {fpu_v29, fpu_d29, LLDB_INVALID_REGNUM}; 42855505Sshinstatic uint32_t g_s30_invalidates[] = {fpu_v30, fpu_d30, LLDB_INVALID_REGNUM}; 42955505Sshinstatic uint32_t g_s31_invalidates[] = {fpu_v31, fpu_d31, LLDB_INVALID_REGNUM}; 43055505Sshin 43155505Sshinstatic uint32_t g_d0_invalidates[] = {fpu_v0, fpu_s0, LLDB_INVALID_REGNUM}; 43278064Sumestatic uint32_t g_d1_invalidates[] = {fpu_v1, fpu_s1, LLDB_INVALID_REGNUM}; 43378064Sumestatic uint32_t g_d2_invalidates[] = {fpu_v2, fpu_s2, LLDB_INVALID_REGNUM}; 43455505Sshinstatic uint32_t g_d3_invalidates[] = {fpu_v3, fpu_s3, LLDB_INVALID_REGNUM}; 43555505Sshinstatic uint32_t g_d4_invalidates[] = {fpu_v4, fpu_s4, LLDB_INVALID_REGNUM}; 43655505Sshinstatic uint32_t g_d5_invalidates[] = {fpu_v5, fpu_s5, LLDB_INVALID_REGNUM}; 43755505Sshinstatic uint32_t g_d6_invalidates[] = {fpu_v6, fpu_s6, LLDB_INVALID_REGNUM}; 43855505Sshinstatic uint32_t g_d7_invalidates[] = {fpu_v7, fpu_s7, LLDB_INVALID_REGNUM}; 43955505Sshinstatic uint32_t g_d8_invalidates[] = {fpu_v8, fpu_s8, LLDB_INVALID_REGNUM}; 44055505Sshinstatic uint32_t g_d9_invalidates[] = {fpu_v9, fpu_s9, LLDB_INVALID_REGNUM}; 44155505Sshinstatic uint32_t g_d10_invalidates[] = {fpu_v10, fpu_s10, LLDB_INVALID_REGNUM}; 44255505Sshinstatic uint32_t g_d11_invalidates[] = {fpu_v11, fpu_s11, LLDB_INVALID_REGNUM}; 44362638Skrisstatic uint32_t g_d12_invalidates[] = {fpu_v12, fpu_s12, LLDB_INVALID_REGNUM}; 44455505Sshinstatic uint32_t g_d13_invalidates[] = {fpu_v13, fpu_s13, LLDB_INVALID_REGNUM}; 44555505Sshinstatic uint32_t g_d14_invalidates[] = {fpu_v14, fpu_s14, LLDB_INVALID_REGNUM}; 44655505Sshinstatic uint32_t g_d15_invalidates[] = {fpu_v15, fpu_s15, LLDB_INVALID_REGNUM}; 44755505Sshinstatic uint32_t g_d16_invalidates[] = {fpu_v16, fpu_s16, LLDB_INVALID_REGNUM}; 44855505Sshinstatic uint32_t g_d17_invalidates[] = {fpu_v17, fpu_s17, LLDB_INVALID_REGNUM}; 44955505Sshinstatic uint32_t g_d18_invalidates[] = {fpu_v18, fpu_s18, LLDB_INVALID_REGNUM}; 45055505Sshinstatic uint32_t g_d19_invalidates[] = {fpu_v19, fpu_s19, LLDB_INVALID_REGNUM}; 45155505Sshinstatic uint32_t g_d20_invalidates[] = {fpu_v20, fpu_s20, LLDB_INVALID_REGNUM}; 45262638Skrisstatic uint32_t g_d21_invalidates[] = {fpu_v21, fpu_s21, LLDB_INVALID_REGNUM}; 45355505Sshinstatic uint32_t g_d22_invalidates[] = {fpu_v22, fpu_s22, LLDB_INVALID_REGNUM}; 45455505Sshinstatic uint32_t g_d23_invalidates[] = {fpu_v23, fpu_s23, LLDB_INVALID_REGNUM}; 45555505Sshinstatic uint32_t g_d24_invalidates[] = {fpu_v24, fpu_s24, LLDB_INVALID_REGNUM}; 45655505Sshinstatic uint32_t g_d25_invalidates[] = {fpu_v25, fpu_s25, LLDB_INVALID_REGNUM}; 45755505Sshinstatic uint32_t g_d26_invalidates[] = {fpu_v26, fpu_s26, LLDB_INVALID_REGNUM}; 45855505Sshinstatic uint32_t g_d27_invalidates[] = {fpu_v27, fpu_s27, LLDB_INVALID_REGNUM}; 45962638Skrisstatic uint32_t g_d28_invalidates[] = {fpu_v28, fpu_s28, LLDB_INVALID_REGNUM}; 46055505Sshinstatic uint32_t g_d29_invalidates[] = {fpu_v29, fpu_s29, LLDB_INVALID_REGNUM}; 46155505Sshinstatic uint32_t g_d30_invalidates[] = {fpu_v30, fpu_s30, LLDB_INVALID_REGNUM}; 462136057Sstefanfstatic uint32_t g_d31_invalidates[] = {fpu_v31, fpu_s31, LLDB_INVALID_REGNUM}; 46355505Sshin 46455505Sshinstatic lldb_private::RegisterInfo g_register_infos_arm64_le[] = { 46555505Sshin // clang-format off 46678064Sume // General purpose registers 46755505Sshin // NAME ALT SZ OFFSET ENCODING FORMAT EH_FRAME DWARF GENERIC PROCESS PLUGIN LLDB VALUE REGS INVAL DYNEXPR SZ 46855505Sshin // ===== ======= == ============= =================== ================ ================= =============== ======================== =================== ====== ============== ======= ======= == 46955505Sshin {"x0", nullptr, 8, GPR_OFFSET(0), lldb::eEncodingUint, lldb::eFormatHex, {arm64_ehframe::x0, arm64_dwarf::x0, LLDB_REGNUM_GENERIC_ARG1, LLDB_INVALID_REGNUM, gpr_x0}, nullptr, nullptr, nullptr, 0}, 47055505Sshin {"x1", nullptr, 8, GPR_OFFSET(1), lldb::eEncodingUint, lldb::eFormatHex, {arm64_ehframe::x1, arm64_dwarf::x1, LLDB_REGNUM_GENERIC_ARG2, LLDB_INVALID_REGNUM, gpr_x1}, nullptr, nullptr, nullptr, 0}, 47155505Sshin {"x2", nullptr, 8, GPR_OFFSET(2), lldb::eEncodingUint, lldb::eFormatHex, {arm64_ehframe::x2, arm64_dwarf::x2, LLDB_REGNUM_GENERIC_ARG3, LLDB_INVALID_REGNUM, gpr_x2}, nullptr, nullptr, nullptr, 0}, 47255505Sshin {"x3", nullptr, 8, GPR_OFFSET(3), lldb::eEncodingUint, lldb::eFormatHex, {arm64_ehframe::x3, arm64_dwarf::x3, LLDB_REGNUM_GENERIC_ARG4, LLDB_INVALID_REGNUM, gpr_x3}, nullptr, nullptr, nullptr, 0}, 47355505Sshin {"x4", nullptr, 8, GPR_OFFSET(4), lldb::eEncodingUint, lldb::eFormatHex, {arm64_ehframe::x4, arm64_dwarf::x4, LLDB_REGNUM_GENERIC_ARG5, LLDB_INVALID_REGNUM, gpr_x4}, nullptr, nullptr, nullptr, 0}, 47455505Sshin {"x5", nullptr, 8, GPR_OFFSET(5), lldb::eEncodingUint, lldb::eFormatHex, {arm64_ehframe::x5, arm64_dwarf::x5, LLDB_REGNUM_GENERIC_ARG6, LLDB_INVALID_REGNUM, gpr_x5}, nullptr, nullptr, nullptr, 0}, 47555505Sshin {"x6", nullptr, 8, GPR_OFFSET(6), lldb::eEncodingUint, lldb::eFormatHex, {arm64_ehframe::x6, arm64_dwarf::x6, LLDB_REGNUM_GENERIC_ARG7, LLDB_INVALID_REGNUM, gpr_x6}, nullptr, nullptr, nullptr, 0}, 47678064Sume {"x7", nullptr, 8, GPR_OFFSET(7), lldb::eEncodingUint, lldb::eFormatHex, {arm64_ehframe::x7, arm64_dwarf::x7, LLDB_REGNUM_GENERIC_ARG8, LLDB_INVALID_REGNUM, gpr_x7}, nullptr, nullptr, nullptr, 0}, 47778064Sume {"x8", nullptr, 8, GPR_OFFSET(8), lldb::eEncodingUint, lldb::eFormatHex, {arm64_ehframe::x8, arm64_dwarf::x8, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, gpr_x8}, nullptr, nullptr, nullptr, 0}, 47855505Sshin {"x9", nullptr, 8, GPR_OFFSET(9), lldb::eEncodingUint, lldb::eFormatHex, {arm64_ehframe::x9, arm64_dwarf::x9, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, gpr_x9}, nullptr, nullptr, nullptr, 0}, 47955505Sshin {"x10", nullptr, 8, GPR_OFFSET(10), lldb::eEncodingUint, lldb::eFormatHex, {arm64_ehframe::x10, arm64_dwarf::x10, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, gpr_x10}, nullptr, nullptr, nullptr, 0}, 48055505Sshin {"x11", nullptr, 8, GPR_OFFSET(11), lldb::eEncodingUint, lldb::eFormatHex, {arm64_ehframe::x11, arm64_dwarf::x11, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, gpr_x11}, nullptr, nullptr, nullptr, 0}, 48155505Sshin {"x12", nullptr, 8, GPR_OFFSET(12), lldb::eEncodingUint, lldb::eFormatHex, {arm64_ehframe::x12, arm64_dwarf::x12, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, gpr_x12}, nullptr, nullptr, nullptr, 0}, 48255505Sshin {"x13", nullptr, 8, GPR_OFFSET(13), lldb::eEncodingUint, lldb::eFormatHex, {arm64_ehframe::x13, arm64_dwarf::x13, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, gpr_x13}, nullptr, nullptr, nullptr, 0}, 48355505Sshin {"x14", nullptr, 8, GPR_OFFSET(14), lldb::eEncodingUint, lldb::eFormatHex, {arm64_ehframe::x14, arm64_dwarf::x14, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, gpr_x14}, nullptr, nullptr, nullptr, 0}, 48455505Sshin {"x15", nullptr, 8, GPR_OFFSET(15), lldb::eEncodingUint, lldb::eFormatHex, {arm64_ehframe::x15, arm64_dwarf::x15, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, gpr_x15}, nullptr, nullptr, nullptr, 0}, 48555505Sshin {"x16", nullptr, 8, GPR_OFFSET(16), lldb::eEncodingUint, lldb::eFormatHex, {arm64_ehframe::x16, arm64_dwarf::x16, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, gpr_x16}, nullptr, nullptr, nullptr, 0}, 48678064Sume {"x17", nullptr, 8, GPR_OFFSET(17), lldb::eEncodingUint, lldb::eFormatHex, {arm64_ehframe::x17, arm64_dwarf::x17, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, gpr_x17}, nullptr, nullptr, nullptr, 0}, 48755505Sshin {"x18", nullptr, 8, GPR_OFFSET(18), lldb::eEncodingUint, lldb::eFormatHex, {arm64_ehframe::x18, arm64_dwarf::x18, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, gpr_x18}, nullptr, nullptr, nullptr, 0}, 48878064Sume {"x19", nullptr, 8, GPR_OFFSET(19), lldb::eEncodingUint, lldb::eFormatHex, {arm64_ehframe::x19, arm64_dwarf::x19, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, gpr_x19}, nullptr, nullptr, nullptr, 0}, 48955505Sshin {"x20", nullptr, 8, GPR_OFFSET(20), lldb::eEncodingUint, lldb::eFormatHex, {arm64_ehframe::x20, arm64_dwarf::x20, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, gpr_x20}, nullptr, nullptr, nullptr, 0}, 49055505Sshin {"x21", nullptr, 8, GPR_OFFSET(21), lldb::eEncodingUint, lldb::eFormatHex, {arm64_ehframe::x21, arm64_dwarf::x21, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, gpr_x21}, nullptr, nullptr, nullptr, 0}, 49155505Sshin {"x22", nullptr, 8, GPR_OFFSET(22), lldb::eEncodingUint, lldb::eFormatHex, {arm64_ehframe::x22, arm64_dwarf::x22, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, gpr_x22}, nullptr, nullptr, nullptr, 0}, 49255505Sshin {"x23", nullptr, 8, GPR_OFFSET(23), lldb::eEncodingUint, lldb::eFormatHex, {arm64_ehframe::x23, arm64_dwarf::x23, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, gpr_x23}, nullptr, nullptr, nullptr, 0}, 49355505Sshin {"x24", nullptr, 8, GPR_OFFSET(24), lldb::eEncodingUint, lldb::eFormatHex, {arm64_ehframe::x24, arm64_dwarf::x24, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, gpr_x24}, nullptr, nullptr, nullptr, 0}, 49455505Sshin {"x25", nullptr, 8, GPR_OFFSET(25), lldb::eEncodingUint, lldb::eFormatHex, {arm64_ehframe::x25, arm64_dwarf::x25, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, gpr_x25}, nullptr, nullptr, nullptr, 0}, 49555505Sshin {"x26", nullptr, 8, GPR_OFFSET(26), lldb::eEncodingUint, lldb::eFormatHex, {arm64_ehframe::x26, arm64_dwarf::x26, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, gpr_x26}, nullptr, nullptr, nullptr, 0}, 496136057Sstefanf {"x27", nullptr, 8, GPR_OFFSET(27), lldb::eEncodingUint, lldb::eFormatHex, {arm64_ehframe::x27, arm64_dwarf::x27, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, gpr_x27}, nullptr, nullptr, nullptr, 0}, 49755505Sshin {"x28", nullptr, 8, GPR_OFFSET(28), lldb::eEncodingUint, lldb::eFormatHex, {arm64_ehframe::x28, arm64_dwarf::x28, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, gpr_x28}, nullptr, nullptr, nullptr, 0}, 49855505Sshin {"fp", "x29", 8, GPR_OFFSET(29), lldb::eEncodingUint, lldb::eFormatHex, {arm64_ehframe::fp, arm64_dwarf::fp, LLDB_REGNUM_GENERIC_FP, LLDB_INVALID_REGNUM, gpr_fp}, nullptr, nullptr, nullptr, 0}, 49955505Sshin {"lr", "x30", 8, GPR_OFFSET(30), lldb::eEncodingUint, lldb::eFormatHex, {arm64_ehframe::lr, arm64_dwarf::lr, LLDB_REGNUM_GENERIC_RA, LLDB_INVALID_REGNUM, gpr_lr}, nullptr, nullptr, nullptr, 0}, 50062638Skris {"sp", "x31", 8, GPR_OFFSET(31), lldb::eEncodingUint, lldb::eFormatHex, {arm64_ehframe::sp, arm64_dwarf::sp, LLDB_REGNUM_GENERIC_SP, LLDB_INVALID_REGNUM, gpr_sp}, nullptr, nullptr, nullptr, 0}, 50162638Skris {"pc", nullptr, 8, GPR_OFFSET(32), lldb::eEncodingUint, lldb::eFormatHex, {arm64_ehframe::pc, arm64_dwarf::pc, LLDB_REGNUM_GENERIC_PC, LLDB_INVALID_REGNUM, gpr_pc}, nullptr, nullptr, nullptr, 0}, 50255505Sshin 50355505Sshin {"cpsr",nullptr, 4, GPR_OFFSET_NAME(cpsr), lldb::eEncodingUint, lldb::eFormatHex, {arm64_ehframe::cpsr, arm64_dwarf::cpsr, LLDB_REGNUM_GENERIC_FLAGS, LLDB_INVALID_REGNUM, gpr_cpsr}, nullptr, nullptr, nullptr, 0}, 504136057Sstefanf 50555505Sshin // NAME ALT SZ OFFSET ENCODING FORMAT EH_FRAME DWARF GENERIC PROCESS PLUGIN LLDB VALUE INVALIDATES DYNEXPR SZ 50655505Sshin // ===== ======= == ============================================== =================== ================ ================= =============== =================== =================== ====== =============== ================= ======= == 50762638Skris {"w0", nullptr, 4, GPR_OFFSET(0) + GPR_W_PSEUDO_REG_ENDIAN_OFFSET, lldb::eEncodingUint, lldb::eFormatHex, {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, gpr_w0}, g_contained_x0, g_w0_invalidates, nullptr, 0}, 50862638Skris {"w1", nullptr, 4, GPR_OFFSET(1) + GPR_W_PSEUDO_REG_ENDIAN_OFFSET, lldb::eEncodingUint, lldb::eFormatHex, {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, gpr_w1}, g_contained_x1, g_w1_invalidates, nullptr, 0}, 50955505Sshin {"w2", nullptr, 4, GPR_OFFSET(2) + GPR_W_PSEUDO_REG_ENDIAN_OFFSET, lldb::eEncodingUint, lldb::eFormatHex, {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, gpr_w2}, g_contained_x2, g_w2_invalidates, nullptr, 0}, 51062638Skris {"w3", nullptr, 4, GPR_OFFSET(3) + GPR_W_PSEUDO_REG_ENDIAN_OFFSET, lldb::eEncodingUint, lldb::eFormatHex, {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, gpr_w3}, g_contained_x3, g_w3_invalidates, nullptr, 0}, 51162638Skris {"w4", nullptr, 4, GPR_OFFSET(4) + GPR_W_PSEUDO_REG_ENDIAN_OFFSET, lldb::eEncodingUint, lldb::eFormatHex, {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, gpr_w4}, g_contained_x4, g_w4_invalidates, nullptr, 0}, 51262638Skris {"w5", nullptr, 4, GPR_OFFSET(5) + GPR_W_PSEUDO_REG_ENDIAN_OFFSET, lldb::eEncodingUint, lldb::eFormatHex, {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, gpr_w5}, g_contained_x5, g_w5_invalidates, nullptr, 0}, 51362638Skris {"w6", nullptr, 4, GPR_OFFSET(6) + GPR_W_PSEUDO_REG_ENDIAN_OFFSET, lldb::eEncodingUint, lldb::eFormatHex, {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, gpr_w6}, g_contained_x6, g_w6_invalidates, nullptr, 0}, 51455505Sshin {"w7", nullptr, 4, GPR_OFFSET(7) + GPR_W_PSEUDO_REG_ENDIAN_OFFSET, lldb::eEncodingUint, lldb::eFormatHex, {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, gpr_w7}, g_contained_x7, g_w7_invalidates, nullptr, 0}, 51555505Sshin {"w8", nullptr, 4, GPR_OFFSET(8) + GPR_W_PSEUDO_REG_ENDIAN_OFFSET, lldb::eEncodingUint, lldb::eFormatHex, {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, gpr_w8}, g_contained_x8, g_w8_invalidates, nullptr, 0}, 51655505Sshin {"w9", nullptr, 4, GPR_OFFSET(9) + GPR_W_PSEUDO_REG_ENDIAN_OFFSET, lldb::eEncodingUint, lldb::eFormatHex, {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, gpr_w9}, g_contained_x9, g_w9_invalidates, nullptr, 0}, 51755505Sshin {"w10", nullptr, 4, GPR_OFFSET(10) + GPR_W_PSEUDO_REG_ENDIAN_OFFSET, lldb::eEncodingUint, lldb::eFormatHex, {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, gpr_w10}, g_contained_x10, g_w10_invalidates, nullptr, 0}, 51855505Sshin {"w11", nullptr, 4, GPR_OFFSET(11) + GPR_W_PSEUDO_REG_ENDIAN_OFFSET, lldb::eEncodingUint, lldb::eFormatHex, {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, gpr_w11}, g_contained_x11, g_w11_invalidates, nullptr, 0}, 51955505Sshin {"w12", nullptr, 4, GPR_OFFSET(12) + GPR_W_PSEUDO_REG_ENDIAN_OFFSET, lldb::eEncodingUint, lldb::eFormatHex, {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, gpr_w12}, g_contained_x12, g_w12_invalidates, nullptr, 0}, 52055505Sshin {"w13", nullptr, 4, GPR_OFFSET(13) + GPR_W_PSEUDO_REG_ENDIAN_OFFSET, lldb::eEncodingUint, lldb::eFormatHex, {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, gpr_w13}, g_contained_x13, g_w13_invalidates, nullptr, 0}, 52155505Sshin {"w14", nullptr, 4, GPR_OFFSET(14) + GPR_W_PSEUDO_REG_ENDIAN_OFFSET, lldb::eEncodingUint, lldb::eFormatHex, {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, gpr_w14}, g_contained_x14, g_w14_invalidates, nullptr, 0}, 52262638Skris {"w15", nullptr, 4, GPR_OFFSET(15) + GPR_W_PSEUDO_REG_ENDIAN_OFFSET, lldb::eEncodingUint, lldb::eFormatHex, {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, gpr_w15}, g_contained_x15, g_w15_invalidates, nullptr, 0}, 523136057Sstefanf {"w16", nullptr, 4, GPR_OFFSET(16) + GPR_W_PSEUDO_REG_ENDIAN_OFFSET, lldb::eEncodingUint, lldb::eFormatHex, {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, gpr_w16}, g_contained_x16, g_w16_invalidates, nullptr, 0}, 52455505Sshin {"w17", nullptr, 4, GPR_OFFSET(17) + GPR_W_PSEUDO_REG_ENDIAN_OFFSET, lldb::eEncodingUint, lldb::eFormatHex, {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, gpr_w17}, g_contained_x17, g_w17_invalidates, nullptr, 0}, 52555505Sshin {"w18", nullptr, 4, GPR_OFFSET(18) + GPR_W_PSEUDO_REG_ENDIAN_OFFSET, lldb::eEncodingUint, lldb::eFormatHex, {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, gpr_w18}, g_contained_x18, g_w18_invalidates, nullptr, 0}, 52655505Sshin {"w19", nullptr, 4, GPR_OFFSET(19) + GPR_W_PSEUDO_REG_ENDIAN_OFFSET, lldb::eEncodingUint, lldb::eFormatHex, {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, gpr_w19}, g_contained_x19, g_w19_invalidates, nullptr, 0}, 52755505Sshin {"w20", nullptr, 4, GPR_OFFSET(20) + GPR_W_PSEUDO_REG_ENDIAN_OFFSET, lldb::eEncodingUint, lldb::eFormatHex, {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, gpr_w20}, g_contained_x20, g_w20_invalidates, nullptr, 0}, 52855505Sshin {"w21", nullptr, 4, GPR_OFFSET(21) + GPR_W_PSEUDO_REG_ENDIAN_OFFSET, lldb::eEncodingUint, lldb::eFormatHex, {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, gpr_w21}, g_contained_x21, g_w21_invalidates, nullptr, 0}, 52955505Sshin {"w22", nullptr, 4, GPR_OFFSET(22) + GPR_W_PSEUDO_REG_ENDIAN_OFFSET, lldb::eEncodingUint, lldb::eFormatHex, {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, gpr_w22}, g_contained_x22, g_w22_invalidates, nullptr, 0}, 53055505Sshin {"w23", nullptr, 4, GPR_OFFSET(23) + GPR_W_PSEUDO_REG_ENDIAN_OFFSET, lldb::eEncodingUint, lldb::eFormatHex, {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, gpr_w23}, g_contained_x23, g_w23_invalidates, nullptr, 0}, 53155505Sshin {"w24", nullptr, 4, GPR_OFFSET(24) + GPR_W_PSEUDO_REG_ENDIAN_OFFSET, lldb::eEncodingUint, lldb::eFormatHex, {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, gpr_w24}, g_contained_x24, g_w24_invalidates, nullptr, 0}, 53255505Sshin {"w25", nullptr, 4, GPR_OFFSET(25) + GPR_W_PSEUDO_REG_ENDIAN_OFFSET, lldb::eEncodingUint, lldb::eFormatHex, {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, gpr_w25}, g_contained_x25, g_w25_invalidates, nullptr, 0}, 53355505Sshin {"w26", nullptr, 4, GPR_OFFSET(26) + GPR_W_PSEUDO_REG_ENDIAN_OFFSET, lldb::eEncodingUint, lldb::eFormatHex, {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, gpr_w26}, g_contained_x26, g_w26_invalidates, nullptr, 0}, 53455505Sshin {"w27", nullptr, 4, GPR_OFFSET(27) + GPR_W_PSEUDO_REG_ENDIAN_OFFSET, lldb::eEncodingUint, lldb::eFormatHex, {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, gpr_w27}, g_contained_x27, g_w27_invalidates, nullptr, 0}, 53555505Sshin {"w28", nullptr, 4, GPR_OFFSET(28) + GPR_W_PSEUDO_REG_ENDIAN_OFFSET, lldb::eEncodingUint, lldb::eFormatHex, {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, gpr_w28}, g_contained_x28, g_w28_invalidates, nullptr, 0}, 53655505Sshin 53755505Sshin // NAME ALT SZ OFFSET ENCODING FORMAT EH_FRAME DWARF GENERIC PROCESS PLUGIN LLDB VALUE REGS INVAL DYNEXPR SZ 53855505Sshin // ===== ======= == ============= =================== ================ ================= =============== =================== =================== ====== ============== ======= ======= == 53955505Sshin {"v0", nullptr, 16, FPU_OFFSET(0), lldb::eEncodingVector, lldb::eFormatVectorOfUInt8, {LLDB_INVALID_REGNUM, arm64_dwarf::v0, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, fpu_v0}, nullptr, nullptr, nullptr, 0}, 54055505Sshin {"v1", nullptr, 16, FPU_OFFSET(1), lldb::eEncodingVector, lldb::eFormatVectorOfUInt8, {LLDB_INVALID_REGNUM, arm64_dwarf::v1, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, fpu_v1}, nullptr, nullptr, nullptr, 0}, 54155505Sshin {"v2", nullptr, 16, FPU_OFFSET(2), lldb::eEncodingVector, lldb::eFormatVectorOfUInt8, {LLDB_INVALID_REGNUM, arm64_dwarf::v2, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, fpu_v2}, nullptr, nullptr, nullptr, 0}, 54262638Skris {"v3", nullptr, 16, FPU_OFFSET(3), lldb::eEncodingVector, lldb::eFormatVectorOfUInt8, {LLDB_INVALID_REGNUM, arm64_dwarf::v3, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, fpu_v3}, nullptr, nullptr, nullptr, 0}, 54355505Sshin {"v4", nullptr, 16, FPU_OFFSET(4), lldb::eEncodingVector, lldb::eFormatVectorOfUInt8, {LLDB_INVALID_REGNUM, arm64_dwarf::v4, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, fpu_v4}, nullptr, nullptr, nullptr, 0}, 54455505Sshin {"v5", nullptr, 16, FPU_OFFSET(5), lldb::eEncodingVector, lldb::eFormatVectorOfUInt8, {LLDB_INVALID_REGNUM, arm64_dwarf::v5, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, fpu_v5}, nullptr, nullptr, nullptr, 0}, 54555505Sshin {"v6", nullptr, 16, FPU_OFFSET(6), lldb::eEncodingVector, lldb::eFormatVectorOfUInt8, {LLDB_INVALID_REGNUM, arm64_dwarf::v6, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, fpu_v6}, nullptr, nullptr, nullptr, 0}, 54655505Sshin {"v7", nullptr, 16, FPU_OFFSET(7), lldb::eEncodingVector, lldb::eFormatVectorOfUInt8, {LLDB_INVALID_REGNUM, arm64_dwarf::v7, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, fpu_v7}, nullptr, nullptr, nullptr, 0}, 54755505Sshin {"v8", nullptr, 16, FPU_OFFSET(8), lldb::eEncodingVector, lldb::eFormatVectorOfUInt8, {LLDB_INVALID_REGNUM, arm64_dwarf::v8, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, fpu_v8}, nullptr, nullptr, nullptr, 0}, 54879101Sume {"v9", nullptr, 16, FPU_OFFSET(9), lldb::eEncodingVector, lldb::eFormatVectorOfUInt8, {LLDB_INVALID_REGNUM, arm64_dwarf::v9, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, fpu_v9}, nullptr, nullptr, nullptr, 0}, 54962638Skris {"v10", nullptr, 16, FPU_OFFSET(10), lldb::eEncodingVector, lldb::eFormatVectorOfUInt8, {LLDB_INVALID_REGNUM, arm64_dwarf::v10, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, fpu_v10}, nullptr, nullptr, nullptr, 0}, 55062638Skris {"v11", nullptr, 16, FPU_OFFSET(11), lldb::eEncodingVector, lldb::eFormatVectorOfUInt8, {LLDB_INVALID_REGNUM, arm64_dwarf::v11, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, fpu_v11}, nullptr, nullptr, nullptr, 0}, 55155505Sshin {"v12", nullptr, 16, FPU_OFFSET(12), lldb::eEncodingVector, lldb::eFormatVectorOfUInt8, {LLDB_INVALID_REGNUM, arm64_dwarf::v12, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, fpu_v12}, nullptr, nullptr, nullptr, 0}, 55255505Sshin {"v13", nullptr, 16, FPU_OFFSET(13), lldb::eEncodingVector, lldb::eFormatVectorOfUInt8, {LLDB_INVALID_REGNUM, arm64_dwarf::v13, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, fpu_v13}, nullptr, nullptr, nullptr, 0}, 55355505Sshin {"v14", nullptr, 16, FPU_OFFSET(14), lldb::eEncodingVector, lldb::eFormatVectorOfUInt8, {LLDB_INVALID_REGNUM, arm64_dwarf::v14, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, fpu_v14}, nullptr, nullptr, nullptr, 0}, 55455505Sshin {"v15", nullptr, 16, FPU_OFFSET(15), lldb::eEncodingVector, lldb::eFormatVectorOfUInt8, {LLDB_INVALID_REGNUM, arm64_dwarf::v15, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, fpu_v15}, nullptr, nullptr, nullptr, 0}, 55555505Sshin {"v16", nullptr, 16, FPU_OFFSET(16), lldb::eEncodingVector, lldb::eFormatVectorOfUInt8, {LLDB_INVALID_REGNUM, arm64_dwarf::v16, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, fpu_v16}, nullptr, nullptr, nullptr, 0}, 55655505Sshin {"v17", nullptr, 16, FPU_OFFSET(17), lldb::eEncodingVector, lldb::eFormatVectorOfUInt8, {LLDB_INVALID_REGNUM, arm64_dwarf::v17, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, fpu_v17}, nullptr, nullptr, nullptr, 0}, 55755505Sshin {"v18", nullptr, 16, FPU_OFFSET(18), lldb::eEncodingVector, lldb::eFormatVectorOfUInt8, {LLDB_INVALID_REGNUM, arm64_dwarf::v18, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, fpu_v18}, nullptr, nullptr, nullptr, 0}, 55855505Sshin {"v19", nullptr, 16, FPU_OFFSET(19), lldb::eEncodingVector, lldb::eFormatVectorOfUInt8, {LLDB_INVALID_REGNUM, arm64_dwarf::v19, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, fpu_v19}, nullptr, nullptr, nullptr, 0}, 559136057Sstefanf {"v20", nullptr, 16, FPU_OFFSET(20), lldb::eEncodingVector, lldb::eFormatVectorOfUInt8, {LLDB_INVALID_REGNUM, arm64_dwarf::v20, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, fpu_v20}, nullptr, nullptr, nullptr, 0}, 56055505Sshin {"v21", nullptr, 16, FPU_OFFSET(21), lldb::eEncodingVector, lldb::eFormatVectorOfUInt8, {LLDB_INVALID_REGNUM, arm64_dwarf::v21, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, fpu_v21}, nullptr, nullptr, nullptr, 0}, 56155505Sshin {"v22", nullptr, 16, FPU_OFFSET(22), lldb::eEncodingVector, lldb::eFormatVectorOfUInt8, {LLDB_INVALID_REGNUM, arm64_dwarf::v22, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, fpu_v22}, nullptr, nullptr, nullptr, 0}, 56255505Sshin {"v23", nullptr, 16, FPU_OFFSET(23), lldb::eEncodingVector, lldb::eFormatVectorOfUInt8, {LLDB_INVALID_REGNUM, arm64_dwarf::v23, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, fpu_v23}, nullptr, nullptr, nullptr, 0}, 56355505Sshin {"v24", nullptr, 16, FPU_OFFSET(24), lldb::eEncodingVector, lldb::eFormatVectorOfUInt8, {LLDB_INVALID_REGNUM, arm64_dwarf::v24, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, fpu_v24}, nullptr, nullptr, nullptr, 0}, 56455505Sshin {"v25", nullptr, 16, FPU_OFFSET(25), lldb::eEncodingVector, lldb::eFormatVectorOfUInt8, {LLDB_INVALID_REGNUM, arm64_dwarf::v25, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, fpu_v25}, nullptr, nullptr, nullptr, 0}, 56555505Sshin {"v26", nullptr, 16, FPU_OFFSET(26), lldb::eEncodingVector, lldb::eFormatVectorOfUInt8, {LLDB_INVALID_REGNUM, arm64_dwarf::v26, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, fpu_v26}, nullptr, nullptr, nullptr, 0}, 56655505Sshin {"v27", nullptr, 16, FPU_OFFSET(27), lldb::eEncodingVector, lldb::eFormatVectorOfUInt8, {LLDB_INVALID_REGNUM, arm64_dwarf::v27, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, fpu_v27}, nullptr, nullptr, nullptr, 0}, 56755505Sshin {"v28", nullptr, 16, FPU_OFFSET(28), lldb::eEncodingVector, lldb::eFormatVectorOfUInt8, {LLDB_INVALID_REGNUM, arm64_dwarf::v28, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, fpu_v28}, nullptr, nullptr, nullptr, 0}, 56855505Sshin {"v29", nullptr, 16, FPU_OFFSET(29), lldb::eEncodingVector, lldb::eFormatVectorOfUInt8, {LLDB_INVALID_REGNUM, arm64_dwarf::v29, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, fpu_v29}, nullptr, nullptr, nullptr, 0}, 56955505Sshin {"v30", nullptr, 16, FPU_OFFSET(30), lldb::eEncodingVector, lldb::eFormatVectorOfUInt8, {LLDB_INVALID_REGNUM, arm64_dwarf::v30, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, fpu_v30}, nullptr, nullptr, nullptr, 0}, 57055505Sshin {"v31", nullptr, 16, FPU_OFFSET(31), lldb::eEncodingVector, lldb::eFormatVectorOfUInt8, {LLDB_INVALID_REGNUM, arm64_dwarf::v31, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, fpu_v31}, nullptr, nullptr, nullptr, 0}, 57155505Sshin 57255505Sshin // NAME ALT SZ OFFSET ENCODING FORMAT EH_FRAME DWARF GENERIC PROCESS PLUGIN LLDB VALUE REGS INVALIDATES DYNEXPR SZ 57355505Sshin // ===== ======= == ============================================== =================== ================ ================= =============== =================== =================== ====== =============== ================= ======= == 57455505Sshin {"s0", nullptr, 4, FPU_OFFSET(0) + FPU_S_PSEUDO_REG_ENDIAN_OFFSET, lldb::eEncodingIEEE754, lldb::eFormatFloat, {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, fpu_s0}, g_contained_v0, g_s0_invalidates, nullptr, 0}, 57555505Sshin {"s1", nullptr, 4, FPU_OFFSET(1) + FPU_S_PSEUDO_REG_ENDIAN_OFFSET, lldb::eEncodingIEEE754, lldb::eFormatFloat, {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, fpu_s1}, g_contained_v1, g_s1_invalidates, nullptr, 0}, 57655505Sshin {"s2", nullptr, 4, FPU_OFFSET(2) + FPU_S_PSEUDO_REG_ENDIAN_OFFSET, lldb::eEncodingIEEE754, lldb::eFormatFloat, {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, fpu_s2}, g_contained_v2, g_s2_invalidates, nullptr, 0}, 57755505Sshin {"s3", nullptr, 4, FPU_OFFSET(3) + FPU_S_PSEUDO_REG_ENDIAN_OFFSET, lldb::eEncodingIEEE754, lldb::eFormatFloat, {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, fpu_s3}, g_contained_v3, g_s3_invalidates, nullptr, 0}, 57862638Skris {"s4", nullptr, 4, FPU_OFFSET(4) + FPU_S_PSEUDO_REG_ENDIAN_OFFSET, lldb::eEncodingIEEE754, lldb::eFormatFloat, {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, fpu_s4}, g_contained_v4, g_s4_invalidates, nullptr, 0}, 57962638Skris {"s5", nullptr, 4, FPU_OFFSET(5) + FPU_S_PSEUDO_REG_ENDIAN_OFFSET, lldb::eEncodingIEEE754, lldb::eFormatFloat, {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, fpu_s5}, g_contained_v5, g_s5_invalidates, nullptr, 0}, 58062638Skris {"s6", nullptr, 4, FPU_OFFSET(6) + FPU_S_PSEUDO_REG_ENDIAN_OFFSET, lldb::eEncodingIEEE754, lldb::eFormatFloat, {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, fpu_s6}, g_contained_v6, g_s6_invalidates, nullptr, 0}, 58162638Skris {"s7", nullptr, 4, FPU_OFFSET(7) + FPU_S_PSEUDO_REG_ENDIAN_OFFSET, lldb::eEncodingIEEE754, lldb::eFormatFloat, {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, fpu_s7}, g_contained_v7, g_s7_invalidates, nullptr, 0}, 58262638Skris {"s8", nullptr, 4, FPU_OFFSET(8) + FPU_S_PSEUDO_REG_ENDIAN_OFFSET, lldb::eEncodingIEEE754, lldb::eFormatFloat, {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, fpu_s8}, g_contained_v8, g_s8_invalidates, nullptr, 0}, 58362638Skris {"s9", nullptr, 4, FPU_OFFSET(9) + FPU_S_PSEUDO_REG_ENDIAN_OFFSET, lldb::eEncodingIEEE754, lldb::eFormatFloat, {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, fpu_s9}, g_contained_v9, g_s9_invalidates, nullptr, 0}, 58462638Skris {"s10", nullptr, 4, FPU_OFFSET(10) + FPU_S_PSEUDO_REG_ENDIAN_OFFSET, lldb::eEncodingIEEE754, lldb::eFormatFloat, {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, fpu_s10}, g_contained_v10, g_s10_invalidates, nullptr, 0}, 58555505Sshin {"s11", nullptr, 4, FPU_OFFSET(11) + FPU_S_PSEUDO_REG_ENDIAN_OFFSET, lldb::eEncodingIEEE754, lldb::eFormatFloat, {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, fpu_s11}, g_contained_v11, g_s11_invalidates, nullptr, 0}, 58655505Sshin {"s12", nullptr, 4, FPU_OFFSET(12) + FPU_S_PSEUDO_REG_ENDIAN_OFFSET, lldb::eEncodingIEEE754, lldb::eFormatFloat, {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, fpu_s12}, g_contained_v12, g_s12_invalidates, nullptr, 0}, 58755505Sshin {"s13", nullptr, 4, FPU_OFFSET(13) + FPU_S_PSEUDO_REG_ENDIAN_OFFSET, lldb::eEncodingIEEE754, lldb::eFormatFloat, {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, fpu_s13}, g_contained_v13, g_s13_invalidates, nullptr, 0}, 58855505Sshin {"s14", nullptr, 4, FPU_OFFSET(14) + FPU_S_PSEUDO_REG_ENDIAN_OFFSET, lldb::eEncodingIEEE754, lldb::eFormatFloat, {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, fpu_s14}, g_contained_v14, g_s14_invalidates, nullptr, 0}, 58955505Sshin {"s15", nullptr, 4, FPU_OFFSET(15) + FPU_S_PSEUDO_REG_ENDIAN_OFFSET, lldb::eEncodingIEEE754, lldb::eFormatFloat, {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, fpu_s15}, g_contained_v15, g_s15_invalidates, nullptr, 0}, 59055505Sshin {"s16", nullptr, 4, FPU_OFFSET(16) + FPU_S_PSEUDO_REG_ENDIAN_OFFSET, lldb::eEncodingIEEE754, lldb::eFormatFloat, {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, fpu_s16}, g_contained_v16, g_s16_invalidates, nullptr, 0}, 59155505Sshin {"s17", nullptr, 4, FPU_OFFSET(17) + FPU_S_PSEUDO_REG_ENDIAN_OFFSET, lldb::eEncodingIEEE754, lldb::eFormatFloat, {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, fpu_s17}, g_contained_v17, g_s17_invalidates, nullptr, 0}, 59255505Sshin {"s18", nullptr, 4, FPU_OFFSET(18) + FPU_S_PSEUDO_REG_ENDIAN_OFFSET, lldb::eEncodingIEEE754, lldb::eFormatFloat, {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, fpu_s18}, g_contained_v18, g_s18_invalidates, nullptr, 0}, 59355505Sshin {"s19", nullptr, 4, FPU_OFFSET(19) + FPU_S_PSEUDO_REG_ENDIAN_OFFSET, lldb::eEncodingIEEE754, lldb::eFormatFloat, {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, fpu_s19}, g_contained_v19, g_s19_invalidates, nullptr, 0}, 59455505Sshin {"s20", nullptr, 4, FPU_OFFSET(20) + FPU_S_PSEUDO_REG_ENDIAN_OFFSET, lldb::eEncodingIEEE754, lldb::eFormatFloat, {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, fpu_s20}, g_contained_v20, g_s20_invalidates, nullptr, 0}, 59555505Sshin {"s21", nullptr, 4, FPU_OFFSET(21) + FPU_S_PSEUDO_REG_ENDIAN_OFFSET, lldb::eEncodingIEEE754, lldb::eFormatFloat, {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, fpu_s21}, g_contained_v21, g_s21_invalidates, nullptr, 0}, 59655505Sshin {"s22", nullptr, 4, FPU_OFFSET(22) + FPU_S_PSEUDO_REG_ENDIAN_OFFSET, lldb::eEncodingIEEE754, lldb::eFormatFloat, {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, fpu_s22}, g_contained_v22, g_s22_invalidates, nullptr, 0}, 59755505Sshin {"s23", nullptr, 4, FPU_OFFSET(23) + FPU_S_PSEUDO_REG_ENDIAN_OFFSET, lldb::eEncodingIEEE754, lldb::eFormatFloat, {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, fpu_s23}, g_contained_v23, g_s23_invalidates, nullptr, 0}, 59855505Sshin {"s24", nullptr, 4, FPU_OFFSET(24) + FPU_S_PSEUDO_REG_ENDIAN_OFFSET, lldb::eEncodingIEEE754, lldb::eFormatFloat, {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, fpu_s24}, g_contained_v24, g_s24_invalidates, nullptr, 0}, 59955505Sshin {"s25", nullptr, 4, FPU_OFFSET(25) + FPU_S_PSEUDO_REG_ENDIAN_OFFSET, lldb::eEncodingIEEE754, lldb::eFormatFloat, {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, fpu_s25}, g_contained_v25, g_s25_invalidates, nullptr, 0}, 60055505Sshin {"s26", nullptr, 4, FPU_OFFSET(26) + FPU_S_PSEUDO_REG_ENDIAN_OFFSET, lldb::eEncodingIEEE754, lldb::eFormatFloat, {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, fpu_s26}, g_contained_v26, g_s26_invalidates, nullptr, 0}, 60155505Sshin {"s27", nullptr, 4, FPU_OFFSET(27) + FPU_S_PSEUDO_REG_ENDIAN_OFFSET, lldb::eEncodingIEEE754, lldb::eFormatFloat, {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, fpu_s27}, g_contained_v27, g_s27_invalidates, nullptr, 0}, 60255505Sshin {"s28", nullptr, 4, FPU_OFFSET(28) + FPU_S_PSEUDO_REG_ENDIAN_OFFSET, lldb::eEncodingIEEE754, lldb::eFormatFloat, {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, fpu_s28}, g_contained_v28, g_s28_invalidates, nullptr, 0}, 60355505Sshin {"s29", nullptr, 4, FPU_OFFSET(29) + FPU_S_PSEUDO_REG_ENDIAN_OFFSET, lldb::eEncodingIEEE754, lldb::eFormatFloat, {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, fpu_s29}, g_contained_v29, g_s29_invalidates, nullptr, 0}, 60455505Sshin {"s30", nullptr, 4, FPU_OFFSET(30) + FPU_S_PSEUDO_REG_ENDIAN_OFFSET, lldb::eEncodingIEEE754, lldb::eFormatFloat, {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, fpu_s30}, g_contained_v30, g_s30_invalidates, nullptr, 0}, 60555505Sshin {"s31", nullptr, 4, FPU_OFFSET(31) + FPU_S_PSEUDO_REG_ENDIAN_OFFSET, lldb::eEncodingIEEE754, lldb::eFormatFloat, {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, fpu_s31}, g_contained_v31, g_s31_invalidates, nullptr, 0}, 60655505Sshin 60755505Sshin {"d0", nullptr, 8, FPU_OFFSET(0) + FPU_D_PSEUDO_REG_ENDIAN_OFFSET, lldb::eEncodingIEEE754, lldb::eFormatFloat, {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, fpu_d0}, g_contained_v0, g_d0_invalidates, nullptr, 0}, 60855505Sshin {"d1", nullptr, 8, FPU_OFFSET(1) + FPU_D_PSEUDO_REG_ENDIAN_OFFSET, lldb::eEncodingIEEE754, lldb::eFormatFloat, {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, fpu_d1}, g_contained_v1, g_d1_invalidates, nullptr, 0}, 60955505Sshin {"d2", nullptr, 8, FPU_OFFSET(2) + FPU_D_PSEUDO_REG_ENDIAN_OFFSET, lldb::eEncodingIEEE754, lldb::eFormatFloat, {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, fpu_d2}, g_contained_v2, g_d2_invalidates, nullptr, 0}, 61062638Skris {"d3", nullptr, 8, FPU_OFFSET(3) + FPU_D_PSEUDO_REG_ENDIAN_OFFSET, lldb::eEncodingIEEE754, lldb::eFormatFloat, {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, fpu_d3}, g_contained_v3, g_d3_invalidates, nullptr, 0}, 61162638Skris {"d4", nullptr, 8, FPU_OFFSET(4) + FPU_D_PSEUDO_REG_ENDIAN_OFFSET, lldb::eEncodingIEEE754, lldb::eFormatFloat, {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, fpu_d4}, g_contained_v4, g_d4_invalidates, nullptr, 0}, 61262638Skris {"d5", nullptr, 8, FPU_OFFSET(5) + FPU_D_PSEUDO_REG_ENDIAN_OFFSET, lldb::eEncodingIEEE754, lldb::eFormatFloat, {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, fpu_d5}, g_contained_v5, g_d5_invalidates, nullptr, 0}, 61362638Skris {"d6", nullptr, 8, FPU_OFFSET(6) + FPU_D_PSEUDO_REG_ENDIAN_OFFSET, lldb::eEncodingIEEE754, lldb::eFormatFloat, {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, fpu_d6}, g_contained_v6, g_d6_invalidates, nullptr, 0}, 61462638Skris {"d7", nullptr, 8, FPU_OFFSET(7) + FPU_D_PSEUDO_REG_ENDIAN_OFFSET, lldb::eEncodingIEEE754, lldb::eFormatFloat, {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, fpu_d7}, g_contained_v7, g_d7_invalidates, nullptr, 0}, 61555505Sshin {"d8", nullptr, 8, FPU_OFFSET(8) + FPU_D_PSEUDO_REG_ENDIAN_OFFSET, lldb::eEncodingIEEE754, lldb::eFormatFloat, {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, fpu_d8}, g_contained_v8, g_d8_invalidates, nullptr, 0}, 61655505Sshin {"d9", nullptr, 8, FPU_OFFSET(9) + FPU_D_PSEUDO_REG_ENDIAN_OFFSET, lldb::eEncodingIEEE754, lldb::eFormatFloat, {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, fpu_d9}, g_contained_v9, g_d9_invalidates, nullptr, 0}, 61755505Sshin {"d10", nullptr, 8, FPU_OFFSET(10) + FPU_D_PSEUDO_REG_ENDIAN_OFFSET, lldb::eEncodingIEEE754, lldb::eFormatFloat, {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, fpu_d10}, g_contained_v10, g_d10_invalidates, nullptr, 0}, 61855505Sshin {"d11", nullptr, 8, FPU_OFFSET(11) + FPU_D_PSEUDO_REG_ENDIAN_OFFSET, lldb::eEncodingIEEE754, lldb::eFormatFloat, {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, fpu_d11}, g_contained_v11, g_d11_invalidates, nullptr, 0}, 61955505Sshin {"d12", nullptr, 8, FPU_OFFSET(12) + FPU_D_PSEUDO_REG_ENDIAN_OFFSET, lldb::eEncodingIEEE754, lldb::eFormatFloat, {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, fpu_d12}, g_contained_v12, g_d12_invalidates, nullptr, 0}, 62055505Sshin {"d13", nullptr, 8, FPU_OFFSET(13) + FPU_D_PSEUDO_REG_ENDIAN_OFFSET, lldb::eEncodingIEEE754, lldb::eFormatFloat, {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, fpu_d13}, g_contained_v13, g_d13_invalidates, nullptr, 0}, 62155505Sshin {"d14", nullptr, 8, FPU_OFFSET(14) + FPU_D_PSEUDO_REG_ENDIAN_OFFSET, lldb::eEncodingIEEE754, lldb::eFormatFloat, {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, fpu_d14}, g_contained_v14, g_d14_invalidates, nullptr, 0}, 62255505Sshin {"d15", nullptr, 8, FPU_OFFSET(15) + FPU_D_PSEUDO_REG_ENDIAN_OFFSET, lldb::eEncodingIEEE754, lldb::eFormatFloat, {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, fpu_d15}, g_contained_v15, g_d15_invalidates, nullptr, 0}, 62355505Sshin {"d16", nullptr, 8, FPU_OFFSET(16) + FPU_D_PSEUDO_REG_ENDIAN_OFFSET, lldb::eEncodingIEEE754, lldb::eFormatFloat, {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, fpu_d16}, g_contained_v16, g_d16_invalidates, nullptr, 0}, 62455505Sshin {"d17", nullptr, 8, FPU_OFFSET(17) + FPU_D_PSEUDO_REG_ENDIAN_OFFSET, lldb::eEncodingIEEE754, lldb::eFormatFloat, {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, fpu_d17}, g_contained_v17, g_d17_invalidates, nullptr, 0}, 62562638Skris {"d18", nullptr, 8, FPU_OFFSET(18) + FPU_D_PSEUDO_REG_ENDIAN_OFFSET, lldb::eEncodingIEEE754, lldb::eFormatFloat, {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, fpu_d18}, g_contained_v18, g_d18_invalidates, nullptr, 0}, 62662638Skris {"d19", nullptr, 8, FPU_OFFSET(19) + FPU_D_PSEUDO_REG_ENDIAN_OFFSET, lldb::eEncodingIEEE754, lldb::eFormatFloat, {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, fpu_d19}, g_contained_v19, g_d19_invalidates, nullptr, 0}, 62762638Skris {"d20", nullptr, 8, FPU_OFFSET(20) + FPU_D_PSEUDO_REG_ENDIAN_OFFSET, lldb::eEncodingIEEE754, lldb::eFormatFloat, {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, fpu_d20}, g_contained_v20, g_d20_invalidates, nullptr, 0}, 62862638Skris {"d21", nullptr, 8, FPU_OFFSET(21) + FPU_D_PSEUDO_REG_ENDIAN_OFFSET, lldb::eEncodingIEEE754, lldb::eFormatFloat, {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, fpu_d21}, g_contained_v21, g_d21_invalidates, nullptr, 0}, 62962638Skris {"d22", nullptr, 8, FPU_OFFSET(22) + FPU_D_PSEUDO_REG_ENDIAN_OFFSET, lldb::eEncodingIEEE754, lldb::eFormatFloat, {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, fpu_d22}, g_contained_v22, g_d22_invalidates, nullptr, 0}, 63055505Sshin {"d23", nullptr, 8, FPU_OFFSET(23) + FPU_D_PSEUDO_REG_ENDIAN_OFFSET, lldb::eEncodingIEEE754, lldb::eFormatFloat, {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, fpu_d23}, g_contained_v23, g_d23_invalidates, nullptr, 0}, 63155505Sshin {"d24", nullptr, 8, FPU_OFFSET(24) + FPU_D_PSEUDO_REG_ENDIAN_OFFSET, lldb::eEncodingIEEE754, lldb::eFormatFloat, {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, fpu_d24}, g_contained_v24, g_d24_invalidates, nullptr, 0}, 63255505Sshin {"d25", nullptr, 8, FPU_OFFSET(25) + FPU_D_PSEUDO_REG_ENDIAN_OFFSET, lldb::eEncodingIEEE754, lldb::eFormatFloat, {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, fpu_d25}, g_contained_v25, g_d25_invalidates, nullptr, 0}, 63355505Sshin {"d26", nullptr, 8, FPU_OFFSET(26) + FPU_D_PSEUDO_REG_ENDIAN_OFFSET, lldb::eEncodingIEEE754, lldb::eFormatFloat, {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, fpu_d26}, g_contained_v26, g_d26_invalidates, nullptr, 0}, 63478064Sume {"d27", nullptr, 8, FPU_OFFSET(27) + FPU_D_PSEUDO_REG_ENDIAN_OFFSET, lldb::eEncodingIEEE754, lldb::eFormatFloat, {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, fpu_d27}, g_contained_v27, g_d27_invalidates, nullptr, 0}, 63555505Sshin {"d28", nullptr, 8, FPU_OFFSET(28) + FPU_D_PSEUDO_REG_ENDIAN_OFFSET, lldb::eEncodingIEEE754, lldb::eFormatFloat, {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, fpu_d28}, g_contained_v28, g_d28_invalidates, nullptr, 0}, 63655505Sshin {"d29", nullptr, 8, FPU_OFFSET(29) + FPU_D_PSEUDO_REG_ENDIAN_OFFSET, lldb::eEncodingIEEE754, lldb::eFormatFloat, {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, fpu_d29}, g_contained_v29, g_d29_invalidates, nullptr, 0}, 63755505Sshin {"d30", nullptr, 8, FPU_OFFSET(30) + FPU_D_PSEUDO_REG_ENDIAN_OFFSET, lldb::eEncodingIEEE754, lldb::eFormatFloat, {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, fpu_d30}, g_contained_v30, g_d30_invalidates, nullptr, 0}, 63855505Sshin {"d31", nullptr, 8, FPU_OFFSET(31) + FPU_D_PSEUDO_REG_ENDIAN_OFFSET, lldb::eEncodingIEEE754, lldb::eFormatFloat, {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, fpu_d31}, g_contained_v31, g_d31_invalidates, nullptr, 0}, 63955505Sshin 64055505Sshin {"fpsr", nullptr, 4, FPU_OFFSET_NAME(fpsr), lldb::eEncodingUint, lldb::eFormatHex, {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, fpu_fpsr}, nullptr, nullptr, nullptr, 0}, 64155505Sshin {"fpcr", nullptr, 4, FPU_OFFSET_NAME(fpcr), lldb::eEncodingUint, lldb::eFormatHex, {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, fpu_fpcr}, nullptr, nullptr, nullptr, 0}, 64255505Sshin 643136057Sstefanf {"far", nullptr, 8, EXC_OFFSET_NAME(far), lldb::eEncodingUint, lldb::eFormatHex, {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, exc_far}, nullptr, nullptr, nullptr, 0}, 64455505Sshin {"esr", nullptr, 4, EXC_OFFSET_NAME(esr), lldb::eEncodingUint, lldb::eFormatHex, {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, exc_esr}, nullptr, nullptr, nullptr, 0}, 64555505Sshin {"exception", nullptr, 4, EXC_OFFSET_NAME(exception), lldb::eEncodingUint, lldb::eFormatHex, {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, exc_exception}, nullptr, nullptr, nullptr, 0}, 64655505Sshin 64755505Sshin {DEFINE_DBG(bvr, 0)}, 64855505Sshin {DEFINE_DBG(bvr, 1)}, 64955505Sshin {DEFINE_DBG(bvr, 2)}, 65055505Sshin {DEFINE_DBG(bvr, 3)}, 65178064Sume {DEFINE_DBG(bvr, 4)}, 65255505Sshin {DEFINE_DBG(bvr, 5)}, 65378064Sume {DEFINE_DBG(bvr, 6)}, 65455505Sshin {DEFINE_DBG(bvr, 7)}, 65555505Sshin {DEFINE_DBG(bvr, 8)}, 65655505Sshin {DEFINE_DBG(bvr, 9)}, 65755505Sshin {DEFINE_DBG(bvr, 10)}, 65862638Skris {DEFINE_DBG(bvr, 11)}, 65962638Skris {DEFINE_DBG(bvr, 12)}, 66055505Sshin {DEFINE_DBG(bvr, 13)}, 66155505Sshin {DEFINE_DBG(bvr, 14)}, 66255505Sshin {DEFINE_DBG(bvr, 15)}, 66355505Sshin 664 {DEFINE_DBG(bcr, 0)}, 665 {DEFINE_DBG(bcr, 1)}, 666 {DEFINE_DBG(bcr, 2)}, 667 {DEFINE_DBG(bcr, 3)}, 668 {DEFINE_DBG(bcr, 4)}, 669 {DEFINE_DBG(bcr, 5)}, 670 {DEFINE_DBG(bcr, 6)}, 671 {DEFINE_DBG(bcr, 7)}, 672 {DEFINE_DBG(bcr, 8)}, 673 {DEFINE_DBG(bcr, 9)}, 674 {DEFINE_DBG(bcr, 10)}, 675 {DEFINE_DBG(bcr, 11)}, 676 {DEFINE_DBG(bcr, 12)}, 677 {DEFINE_DBG(bcr, 13)}, 678 {DEFINE_DBG(bcr, 14)}, 679 {DEFINE_DBG(bcr, 15)}, 680 681 {DEFINE_DBG(wvr, 0)}, 682 {DEFINE_DBG(wvr, 1)}, 683 {DEFINE_DBG(wvr, 2)}, 684 {DEFINE_DBG(wvr, 3)}, 685 {DEFINE_DBG(wvr, 4)}, 686 {DEFINE_DBG(wvr, 5)}, 687 {DEFINE_DBG(wvr, 6)}, 688 {DEFINE_DBG(wvr, 7)}, 689 {DEFINE_DBG(wvr, 8)}, 690 {DEFINE_DBG(wvr, 9)}, 691 {DEFINE_DBG(wvr, 10)}, 692 {DEFINE_DBG(wvr, 11)}, 693 {DEFINE_DBG(wvr, 12)}, 694 {DEFINE_DBG(wvr, 13)}, 695 {DEFINE_DBG(wvr, 14)}, 696 {DEFINE_DBG(wvr, 15)}, 697 698 {DEFINE_DBG(wcr, 0)}, 699 {DEFINE_DBG(wcr, 1)}, 700 {DEFINE_DBG(wcr, 2)}, 701 {DEFINE_DBG(wcr, 3)}, 702 {DEFINE_DBG(wcr, 4)}, 703 {DEFINE_DBG(wcr, 5)}, 704 {DEFINE_DBG(wcr, 6)}, 705 {DEFINE_DBG(wcr, 7)}, 706 {DEFINE_DBG(wcr, 8)}, 707 {DEFINE_DBG(wcr, 9)}, 708 {DEFINE_DBG(wcr, 10)}, 709 {DEFINE_DBG(wcr, 11)}, 710 {DEFINE_DBG(wcr, 12)}, 711 {DEFINE_DBG(wcr, 13)}, 712 {DEFINE_DBG(wcr, 14)}, 713 {DEFINE_DBG(wcr, 15)} 714 // clang-format on 715}; 716 717#endif // DECLARE_REGISTER_INFOS_ARM64_STRUCT 718