RegisterInfos_arm64.h revision 275072
1185222Ssam//===-- RegisterInfos_arm64.h ----------------------------------*- C++ -*-===// 2185222Ssam// 3185222Ssam// The LLVM Compiler Infrastructure 4185222Ssam// 5185222Ssam// This file is distributed under the University of Illinois Open Source 6185222Ssam// License. See LICENSE.TXT for details. 7185222Ssam// 8185222Ssam//===---------------------------------------------------------------------===// 9185222Ssam 10185222Ssam#ifdef DECLARE_REGISTER_INFOS_ARM64_STRUCT 11185222Ssam 12185222Ssam#include <stddef.h> 13185222Ssam 14185222Ssam#include "lldb/lldb-private.h" 15185222Ssam#include "lldb/lldb-defines.h" 16185222Ssam#include "lldb/lldb-enumerations.h" 17185222Ssam 18185222Ssam#include "ARM64_GCC_Registers.h" 19185222Ssam#include "ARM64_DWARF_Registers.h" 20185222Ssam 21185222Ssam#ifndef GPR_OFFSET 22185222Ssam#error GPR_OFFSET must be defined before including this header file 23185222Ssam#endif 24185222Ssam 25185222Ssam#ifndef GPR_OFFSET_NAME 26185222Ssam#error GPR_OFFSET_NAME must be defined before including this header file 27185222Ssam#endif 28185222Ssam 29185222Ssam#ifndef FPU_OFFSET 30185222Ssam#error FPU_OFFSET must be defined before including this header file 31185222Ssam#endif 32185222Ssam 33185222Ssam#ifndef FPU_OFFSET_NAME 34185222Ssam#error FPU_OFFSET_NAME must be defined before including this header file 35185222Ssam#endif 36186334Ssam 37186334Ssam#ifndef EXC_OFFSET_NAME 38185222Ssam#error EXC_OFFSET_NAME must be defined before including this header file 39185222Ssam#endif 40185222Ssam 41185222Ssam#ifndef DBG_OFFSET_NAME 42185222Ssam#error DBG_OFFSET_NAME must be defined before including this header file 43185222Ssam#endif 44185222Ssam 45185222Ssam#ifndef DEFINE_DBG 46185222Ssam#error DEFINE_DBG must be defined before including this header file 47185222Ssam#endif 48185222Ssam 49185222Ssamenum 50185222Ssam{ 51185222Ssam gpr_x0 = 0, 52185222Ssam gpr_x1, 53185222Ssam gpr_x2, 54185222Ssam gpr_x3, 55185222Ssam gpr_x4, 56185222Ssam gpr_x5, 57185222Ssam gpr_x6, 58185222Ssam gpr_x7, 59185222Ssam gpr_x8, 60185222Ssam gpr_x9, 61185222Ssam gpr_x10, 62185222Ssam gpr_x11, 63185222Ssam gpr_x12, 64185222Ssam gpr_x13, 65185222Ssam gpr_x14, 66185222Ssam gpr_x15, 67185222Ssam gpr_x16, 68 gpr_x17, 69 gpr_x18, 70 gpr_x19, 71 gpr_x20, 72 gpr_x21, 73 gpr_x22, 74 gpr_x23, 75 gpr_x24, 76 gpr_x25, 77 gpr_x26, 78 gpr_x27, 79 gpr_x28, 80 gpr_x29 = 29, gpr_fp = gpr_x29, 81 gpr_x30 = 30, gpr_lr = gpr_x30, gpr_ra = gpr_x30, 82 gpr_x31 = 31, gpr_sp = gpr_x31, 83 gpr_pc = 32, 84 gpr_cpsr, 85 86 fpu_v0, 87 fpu_v1, 88 fpu_v2, 89 fpu_v3, 90 fpu_v4, 91 fpu_v5, 92 fpu_v6, 93 fpu_v7, 94 fpu_v8, 95 fpu_v9, 96 fpu_v10, 97 fpu_v11, 98 fpu_v12, 99 fpu_v13, 100 fpu_v14, 101 fpu_v15, 102 fpu_v16, 103 fpu_v17, 104 fpu_v18, 105 fpu_v19, 106 fpu_v20, 107 fpu_v21, 108 fpu_v22, 109 fpu_v23, 110 fpu_v24, 111 fpu_v25, 112 fpu_v26, 113 fpu_v27, 114 fpu_v28, 115 fpu_v29, 116 fpu_v30, 117 fpu_v31, 118 119 fpu_fpsr, 120 fpu_fpcr, 121 122 exc_far, 123 exc_esr, 124 exc_exception, 125 126 dbg_bvr0, 127 dbg_bvr1, 128 dbg_bvr2, 129 dbg_bvr3, 130 dbg_bvr4, 131 dbg_bvr5, 132 dbg_bvr6, 133 dbg_bvr7, 134 dbg_bvr8, 135 dbg_bvr9, 136 dbg_bvr10, 137 dbg_bvr11, 138 dbg_bvr12, 139 dbg_bvr13, 140 dbg_bvr14, 141 dbg_bvr15, 142 143 dbg_bcr0, 144 dbg_bcr1, 145 dbg_bcr2, 146 dbg_bcr3, 147 dbg_bcr4, 148 dbg_bcr5, 149 dbg_bcr6, 150 dbg_bcr7, 151 dbg_bcr8, 152 dbg_bcr9, 153 dbg_bcr10, 154 dbg_bcr11, 155 dbg_bcr12, 156 dbg_bcr13, 157 dbg_bcr14, 158 dbg_bcr15, 159 160 dbg_wvr0, 161 dbg_wvr1, 162 dbg_wvr2, 163 dbg_wvr3, 164 dbg_wvr4, 165 dbg_wvr5, 166 dbg_wvr6, 167 dbg_wvr7, 168 dbg_wvr8, 169 dbg_wvr9, 170 dbg_wvr10, 171 dbg_wvr11, 172 dbg_wvr12, 173 dbg_wvr13, 174 dbg_wvr14, 175 dbg_wvr15, 176 177 dbg_wcr0, 178 dbg_wcr1, 179 dbg_wcr2, 180 dbg_wcr3, 181 dbg_wcr4, 182 dbg_wcr5, 183 dbg_wcr6, 184 dbg_wcr7, 185 dbg_wcr8, 186 dbg_wcr9, 187 dbg_wcr10, 188 dbg_wcr11, 189 dbg_wcr12, 190 dbg_wcr13, 191 dbg_wcr14, 192 dbg_wcr15, 193 194 k_num_registers 195}; 196 197static lldb_private::RegisterInfo g_register_infos_arm64[] = { 198// General purpose registers 199// NAME ALT SZ OFFSET ENCODING FORMAT COMPILER DWARF GENERIC GDB LLDB NATIVE VALUE REGS INVALIDATE REGS 200// ====== ======= == ============= ============= ============ =============== =============== ========================= ===================== ============= ========== =============== 201{ "x0", NULL, 8, GPR_OFFSET(0), lldb::eEncodingUint, lldb::eFormatHex, { arm64_gcc::x0, arm64_dwarf::x0, LLDB_INVALID_REGNUM, arm64_gcc::x0, gpr_x0 }, NULL, NULL}, 202{ "x1", NULL, 8, GPR_OFFSET(1), lldb::eEncodingUint, lldb::eFormatHex, { arm64_gcc::x1, arm64_dwarf::x1, LLDB_INVALID_REGNUM, arm64_gcc::x1, gpr_x1 }, NULL, NULL}, 203{ "x2", NULL, 8, GPR_OFFSET(2), lldb::eEncodingUint, lldb::eFormatHex, { arm64_gcc::x2, arm64_dwarf::x2, LLDB_INVALID_REGNUM, arm64_gcc::x2, gpr_x2 }, NULL, NULL}, 204{ "x3", NULL, 8, GPR_OFFSET(3), lldb::eEncodingUint, lldb::eFormatHex, { arm64_gcc::x3, arm64_dwarf::x3, LLDB_INVALID_REGNUM, arm64_gcc::x3, gpr_x3 }, NULL, NULL}, 205{ "x4", NULL, 8, GPR_OFFSET(4), lldb::eEncodingUint, lldb::eFormatHex, { arm64_gcc::x4, arm64_dwarf::x4, LLDB_INVALID_REGNUM, arm64_gcc::x4, gpr_x4 }, NULL, NULL}, 206{ "x5", NULL, 8, GPR_OFFSET(5), lldb::eEncodingUint, lldb::eFormatHex, { arm64_gcc::x5, arm64_dwarf::x5, LLDB_INVALID_REGNUM, arm64_gcc::x5, gpr_x5 }, NULL, NULL}, 207{ "x6", NULL, 8, GPR_OFFSET(6), lldb::eEncodingUint, lldb::eFormatHex, { arm64_gcc::x6, arm64_dwarf::x6, LLDB_INVALID_REGNUM, arm64_gcc::x6, gpr_x6 }, NULL, NULL}, 208{ "x7", NULL, 8, GPR_OFFSET(7), lldb::eEncodingUint, lldb::eFormatHex, { arm64_gcc::x7, arm64_dwarf::x7, LLDB_INVALID_REGNUM, arm64_gcc::x7, gpr_x7 }, NULL, NULL}, 209{ "x8", NULL, 8, GPR_OFFSET(8), lldb::eEncodingUint, lldb::eFormatHex, { arm64_gcc::x8, arm64_dwarf::x8, LLDB_INVALID_REGNUM, arm64_gcc::x8, gpr_x8 }, NULL, NULL}, 210{ "x9", NULL, 8, GPR_OFFSET(9), lldb::eEncodingUint, lldb::eFormatHex, { arm64_gcc::x9, arm64_dwarf::x9, LLDB_INVALID_REGNUM, arm64_gcc::x9, gpr_x9 }, NULL, NULL}, 211{ "x10", NULL, 8, GPR_OFFSET(10), lldb::eEncodingUint, lldb::eFormatHex, { arm64_gcc::x10, arm64_dwarf::x10, LLDB_INVALID_REGNUM, arm64_gcc::x10, gpr_x10 }, NULL, NULL}, 212{ "x11", NULL, 8, GPR_OFFSET(11), lldb::eEncodingUint, lldb::eFormatHex, { arm64_gcc::x11, arm64_dwarf::x11, LLDB_INVALID_REGNUM, arm64_gcc::x11, gpr_x11 }, NULL, NULL}, 213{ "x12", NULL, 8, GPR_OFFSET(12), lldb::eEncodingUint, lldb::eFormatHex, { arm64_gcc::x12, arm64_dwarf::x12, LLDB_INVALID_REGNUM, arm64_gcc::x12, gpr_x12 }, NULL, NULL}, 214{ "x13", NULL, 8, GPR_OFFSET(13), lldb::eEncodingUint, lldb::eFormatHex, { arm64_gcc::x13, arm64_dwarf::x13, LLDB_INVALID_REGNUM, arm64_gcc::x13, gpr_x13 }, NULL, NULL}, 215{ "x14", NULL, 8, GPR_OFFSET(14), lldb::eEncodingUint, lldb::eFormatHex, { arm64_gcc::x14, arm64_dwarf::x14, LLDB_INVALID_REGNUM, arm64_gcc::x14, gpr_x14 }, NULL, NULL}, 216{ "x15", NULL, 8, GPR_OFFSET(15), lldb::eEncodingUint, lldb::eFormatHex, { arm64_gcc::x15, arm64_dwarf::x15, LLDB_INVALID_REGNUM, arm64_gcc::x15, gpr_x15 }, NULL, NULL}, 217{ "x16", NULL, 8, GPR_OFFSET(16), lldb::eEncodingUint, lldb::eFormatHex, { arm64_gcc::x16, arm64_dwarf::x16, LLDB_INVALID_REGNUM, arm64_gcc::x16, gpr_x16 }, NULL, NULL}, 218{ "x17", NULL, 8, GPR_OFFSET(17), lldb::eEncodingUint, lldb::eFormatHex, { arm64_gcc::x17, arm64_dwarf::x17, LLDB_INVALID_REGNUM, arm64_gcc::x17, gpr_x17 }, NULL, NULL}, 219{ "x18", NULL, 8, GPR_OFFSET(18), lldb::eEncodingUint, lldb::eFormatHex, { arm64_gcc::x18, arm64_dwarf::x18, LLDB_INVALID_REGNUM, arm64_gcc::x18, gpr_x18 }, NULL, NULL}, 220{ "x19", NULL, 8, GPR_OFFSET(19), lldb::eEncodingUint, lldb::eFormatHex, { arm64_gcc::x19, arm64_dwarf::x19, LLDB_INVALID_REGNUM, arm64_gcc::x19, gpr_x19 }, NULL, NULL}, 221{ "x20", NULL, 8, GPR_OFFSET(20), lldb::eEncodingUint, lldb::eFormatHex, { arm64_gcc::x20, arm64_dwarf::x20, LLDB_INVALID_REGNUM, arm64_gcc::x20, gpr_x20 }, NULL, NULL}, 222{ "x21", NULL, 8, GPR_OFFSET(21), lldb::eEncodingUint, lldb::eFormatHex, { arm64_gcc::x21, arm64_dwarf::x21, LLDB_INVALID_REGNUM, arm64_gcc::x21, gpr_x21 }, NULL, NULL}, 223{ "x22", NULL, 8, GPR_OFFSET(22), lldb::eEncodingUint, lldb::eFormatHex, { arm64_gcc::x22, arm64_dwarf::x22, LLDB_INVALID_REGNUM, arm64_gcc::x22, gpr_x22 }, NULL, NULL}, 224{ "x23", NULL, 8, GPR_OFFSET(23), lldb::eEncodingUint, lldb::eFormatHex, { arm64_gcc::x23, arm64_dwarf::x23, LLDB_INVALID_REGNUM, arm64_gcc::x23, gpr_x23 }, NULL, NULL}, 225{ "x24", NULL, 8, GPR_OFFSET(24), lldb::eEncodingUint, lldb::eFormatHex, { arm64_gcc::x24, arm64_dwarf::x24, LLDB_INVALID_REGNUM, arm64_gcc::x24, gpr_x24 }, NULL, NULL}, 226{ "x25", NULL, 8, GPR_OFFSET(25), lldb::eEncodingUint, lldb::eFormatHex, { arm64_gcc::x25, arm64_dwarf::x25, LLDB_INVALID_REGNUM, arm64_gcc::x25, gpr_x25 }, NULL, NULL}, 227{ "x26", NULL, 8, GPR_OFFSET(26), lldb::eEncodingUint, lldb::eFormatHex, { arm64_gcc::x26, arm64_dwarf::x26, LLDB_INVALID_REGNUM, arm64_gcc::x26, gpr_x26 }, NULL, NULL}, 228{ "x27", NULL, 8, GPR_OFFSET(27), lldb::eEncodingUint, lldb::eFormatHex, { arm64_gcc::x27, arm64_dwarf::x27, LLDB_INVALID_REGNUM, arm64_gcc::x27, gpr_x27 }, NULL, NULL}, 229{ "x28", NULL, 8, GPR_OFFSET(28), lldb::eEncodingUint, lldb::eFormatHex, { arm64_gcc::x28, arm64_dwarf::x28, LLDB_INVALID_REGNUM, arm64_gcc::x28, gpr_x28 }, NULL, NULL}, 230 231{ "fp", "x29", 8, GPR_OFFSET(29), lldb::eEncodingUint, lldb::eFormatHex, { arm64_gcc::fp, arm64_dwarf::fp, LLDB_REGNUM_GENERIC_FP, arm64_gcc::fp, gpr_fp }, NULL, NULL}, 232{ "lr", "x30", 8, GPR_OFFSET(30), lldb::eEncodingUint, lldb::eFormatHex, { arm64_gcc::lr, arm64_dwarf::lr, LLDB_REGNUM_GENERIC_RA, arm64_gcc::lr, gpr_lr }, NULL, NULL}, 233{ "sp", "x31", 8, GPR_OFFSET(31), lldb::eEncodingUint, lldb::eFormatHex, { arm64_gcc::sp, arm64_dwarf::sp, LLDB_REGNUM_GENERIC_SP, arm64_gcc::sp, gpr_sp }, NULL, NULL}, 234{ "pc", NULL, 8, GPR_OFFSET(32), lldb::eEncodingUint, lldb::eFormatHex, { arm64_gcc::pc, arm64_dwarf::pc, LLDB_REGNUM_GENERIC_PC, arm64_gcc::pc, gpr_pc }, NULL, NULL}, 235 236{ "cpsr", NULL, 4, GPR_OFFSET_NAME(cpsr), lldb::eEncodingUint, lldb::eFormatHex, { arm64_gcc::cpsr, arm64_dwarf::cpsr, LLDB_REGNUM_GENERIC_FLAGS, arm64_gcc::cpsr, gpr_cpsr }, NULL, NULL}, 237 238{ "v0", NULL, 16, FPU_OFFSET(0), lldb::eEncodingVector, lldb::eFormatVectorOfUInt8, { LLDB_INVALID_REGNUM, arm64_dwarf::v0, LLDB_INVALID_REGNUM, arm64_gcc::v0, fpu_v0 }, NULL, NULL}, 239{ "v1", NULL, 16, FPU_OFFSET(1), lldb::eEncodingVector, lldb::eFormatVectorOfUInt8, { LLDB_INVALID_REGNUM, arm64_dwarf::v1, LLDB_INVALID_REGNUM, arm64_gcc::v1, fpu_v1 }, NULL, NULL}, 240{ "v2", NULL, 16, FPU_OFFSET(2), lldb::eEncodingVector, lldb::eFormatVectorOfUInt8, { LLDB_INVALID_REGNUM, arm64_dwarf::v2, LLDB_INVALID_REGNUM, arm64_gcc::v2, fpu_v2 }, NULL, NULL}, 241{ "v3", NULL, 16, FPU_OFFSET(3), lldb::eEncodingVector, lldb::eFormatVectorOfUInt8, { LLDB_INVALID_REGNUM, arm64_dwarf::v3, LLDB_INVALID_REGNUM, arm64_gcc::v3, fpu_v3 }, NULL, NULL}, 242{ "v4", NULL, 16, FPU_OFFSET(4), lldb::eEncodingVector, lldb::eFormatVectorOfUInt8, { LLDB_INVALID_REGNUM, arm64_dwarf::v4, LLDB_INVALID_REGNUM, arm64_gcc::v4, fpu_v4 }, NULL, NULL}, 243{ "v5", NULL, 16, FPU_OFFSET(5), lldb::eEncodingVector, lldb::eFormatVectorOfUInt8, { LLDB_INVALID_REGNUM, arm64_dwarf::v5, LLDB_INVALID_REGNUM, arm64_gcc::v5, fpu_v5 }, NULL, NULL}, 244{ "v6", NULL, 16, FPU_OFFSET(6), lldb::eEncodingVector, lldb::eFormatVectorOfUInt8, { LLDB_INVALID_REGNUM, arm64_dwarf::v6, LLDB_INVALID_REGNUM, arm64_gcc::v6, fpu_v6 }, NULL, NULL}, 245{ "v7", NULL, 16, FPU_OFFSET(7), lldb::eEncodingVector, lldb::eFormatVectorOfUInt8, { LLDB_INVALID_REGNUM, arm64_dwarf::v7, LLDB_INVALID_REGNUM, arm64_gcc::v7, fpu_v7 }, NULL, NULL}, 246{ "v8", NULL, 16, FPU_OFFSET(8), lldb::eEncodingVector, lldb::eFormatVectorOfUInt8, { LLDB_INVALID_REGNUM, arm64_dwarf::v8, LLDB_INVALID_REGNUM, arm64_gcc::v8, fpu_v8 }, NULL, NULL}, 247{ "v9", NULL, 16, FPU_OFFSET(9), lldb::eEncodingVector, lldb::eFormatVectorOfUInt8, { LLDB_INVALID_REGNUM, arm64_dwarf::v9, LLDB_INVALID_REGNUM, arm64_gcc::v9, fpu_v9 }, NULL, NULL}, 248{ "v10", NULL, 16, FPU_OFFSET(10), lldb::eEncodingVector, lldb::eFormatVectorOfUInt8, { LLDB_INVALID_REGNUM, arm64_dwarf::v10, LLDB_INVALID_REGNUM, arm64_gcc::v10, fpu_v10 }, NULL, NULL}, 249{ "v11", NULL, 16, FPU_OFFSET(11), lldb::eEncodingVector, lldb::eFormatVectorOfUInt8, { LLDB_INVALID_REGNUM, arm64_dwarf::v11, LLDB_INVALID_REGNUM, arm64_gcc::v11, fpu_v11 }, NULL, NULL}, 250{ "v12", NULL, 16, FPU_OFFSET(12), lldb::eEncodingVector, lldb::eFormatVectorOfUInt8, { LLDB_INVALID_REGNUM, arm64_dwarf::v12, LLDB_INVALID_REGNUM, arm64_gcc::v12, fpu_v12 }, NULL, NULL}, 251{ "v13", NULL, 16, FPU_OFFSET(13), lldb::eEncodingVector, lldb::eFormatVectorOfUInt8, { LLDB_INVALID_REGNUM, arm64_dwarf::v13, LLDB_INVALID_REGNUM, arm64_gcc::v13, fpu_v13 }, NULL, NULL}, 252{ "v14", NULL, 16, FPU_OFFSET(14), lldb::eEncodingVector, lldb::eFormatVectorOfUInt8, { LLDB_INVALID_REGNUM, arm64_dwarf::v14, LLDB_INVALID_REGNUM, arm64_gcc::v14, fpu_v14 }, NULL, NULL}, 253{ "v15", NULL, 16, FPU_OFFSET(15), lldb::eEncodingVector, lldb::eFormatVectorOfUInt8, { LLDB_INVALID_REGNUM, arm64_dwarf::v15, LLDB_INVALID_REGNUM, arm64_gcc::v15, fpu_v15 }, NULL, NULL}, 254{ "v16", NULL, 16, FPU_OFFSET(16), lldb::eEncodingVector, lldb::eFormatVectorOfUInt8, { LLDB_INVALID_REGNUM, arm64_dwarf::v16, LLDB_INVALID_REGNUM, arm64_gcc::v16, fpu_v16 }, NULL, NULL}, 255{ "v17", NULL, 16, FPU_OFFSET(17), lldb::eEncodingVector, lldb::eFormatVectorOfUInt8, { LLDB_INVALID_REGNUM, arm64_dwarf::v17, LLDB_INVALID_REGNUM, arm64_gcc::v17, fpu_v17 }, NULL, NULL}, 256{ "v18", NULL, 16, FPU_OFFSET(18), lldb::eEncodingVector, lldb::eFormatVectorOfUInt8, { LLDB_INVALID_REGNUM, arm64_dwarf::v18, LLDB_INVALID_REGNUM, arm64_gcc::v18, fpu_v18 }, NULL, NULL}, 257{ "v19", NULL, 16, FPU_OFFSET(19), lldb::eEncodingVector, lldb::eFormatVectorOfUInt8, { LLDB_INVALID_REGNUM, arm64_dwarf::v19, LLDB_INVALID_REGNUM, arm64_gcc::v19, fpu_v19 }, NULL, NULL}, 258{ "v20", NULL, 16, FPU_OFFSET(20), lldb::eEncodingVector, lldb::eFormatVectorOfUInt8, { LLDB_INVALID_REGNUM, arm64_dwarf::v20, LLDB_INVALID_REGNUM, arm64_gcc::v20, fpu_v20 }, NULL, NULL}, 259{ "v21", NULL, 16, FPU_OFFSET(21), lldb::eEncodingVector, lldb::eFormatVectorOfUInt8, { LLDB_INVALID_REGNUM, arm64_dwarf::v21, LLDB_INVALID_REGNUM, arm64_gcc::v21, fpu_v21 }, NULL, NULL}, 260{ "v22", NULL, 16, FPU_OFFSET(22), lldb::eEncodingVector, lldb::eFormatVectorOfUInt8, { LLDB_INVALID_REGNUM, arm64_dwarf::v22, LLDB_INVALID_REGNUM, arm64_gcc::v22, fpu_v22 }, NULL, NULL}, 261{ "v23", NULL, 16, FPU_OFFSET(23), lldb::eEncodingVector, lldb::eFormatVectorOfUInt8, { LLDB_INVALID_REGNUM, arm64_dwarf::v23, LLDB_INVALID_REGNUM, arm64_gcc::v23, fpu_v23 }, NULL, NULL}, 262{ "v24", NULL, 16, FPU_OFFSET(24), lldb::eEncodingVector, lldb::eFormatVectorOfUInt8, { LLDB_INVALID_REGNUM, arm64_dwarf::v24, LLDB_INVALID_REGNUM, arm64_gcc::v24, fpu_v24 }, NULL, NULL}, 263{ "v25", NULL, 16, FPU_OFFSET(25), lldb::eEncodingVector, lldb::eFormatVectorOfUInt8, { LLDB_INVALID_REGNUM, arm64_dwarf::v25, LLDB_INVALID_REGNUM, arm64_gcc::v25, fpu_v25 }, NULL, NULL}, 264{ "v26", NULL, 16, FPU_OFFSET(26), lldb::eEncodingVector, lldb::eFormatVectorOfUInt8, { LLDB_INVALID_REGNUM, arm64_dwarf::v26, LLDB_INVALID_REGNUM, arm64_gcc::v26, fpu_v26 }, NULL, NULL}, 265{ "v27", NULL, 16, FPU_OFFSET(27), lldb::eEncodingVector, lldb::eFormatVectorOfUInt8, { LLDB_INVALID_REGNUM, arm64_dwarf::v27, LLDB_INVALID_REGNUM, arm64_gcc::v27, fpu_v27 }, NULL, NULL}, 266{ "v28", NULL, 16, FPU_OFFSET(28), lldb::eEncodingVector, lldb::eFormatVectorOfUInt8, { LLDB_INVALID_REGNUM, arm64_dwarf::v28, LLDB_INVALID_REGNUM, arm64_gcc::v28, fpu_v28 }, NULL, NULL}, 267{ "v29", NULL, 16, FPU_OFFSET(29), lldb::eEncodingVector, lldb::eFormatVectorOfUInt8, { LLDB_INVALID_REGNUM, arm64_dwarf::v29, LLDB_INVALID_REGNUM, arm64_gcc::v29, fpu_v29 }, NULL, NULL}, 268{ "v30", NULL, 16, FPU_OFFSET(30), lldb::eEncodingVector, lldb::eFormatVectorOfUInt8, { LLDB_INVALID_REGNUM, arm64_dwarf::v30, LLDB_INVALID_REGNUM, arm64_gcc::v30, fpu_v30 }, NULL, NULL}, 269{ "v31", NULL, 16, FPU_OFFSET(31), lldb::eEncodingVector, lldb::eFormatVectorOfUInt8, { LLDB_INVALID_REGNUM, arm64_dwarf::v31, LLDB_INVALID_REGNUM, arm64_gcc::v31, fpu_v31 }, NULL, NULL}, 270 271{ "fpsr", NULL, 4, FPU_OFFSET_NAME(fpsr), lldb::eEncodingUint, lldb::eFormatHex, { LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, fpu_fpsr }, NULL, NULL}, 272{ "fpcr", NULL, 4, FPU_OFFSET_NAME(fpcr), lldb::eEncodingUint, lldb::eFormatHex, { LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, fpu_fpcr }, NULL, NULL}, 273 274{ "far", NULL, 8, EXC_OFFSET_NAME(far), lldb::eEncodingUint, lldb::eFormatHex, { LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, exc_far }, NULL, NULL}, 275{ "esr", NULL, 4, EXC_OFFSET_NAME(esr), lldb::eEncodingUint, lldb::eFormatHex, { LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, exc_esr }, NULL, NULL}, 276{ "exception",NULL, 4, EXC_OFFSET_NAME(exception), lldb::eEncodingUint, lldb::eFormatHex, { LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, exc_exception }, NULL, NULL}, 277 278{ DEFINE_DBG (bvr, 0) }, 279{ DEFINE_DBG (bvr, 1) }, 280{ DEFINE_DBG (bvr, 2) }, 281{ DEFINE_DBG (bvr, 3) }, 282{ DEFINE_DBG (bvr, 4) }, 283{ DEFINE_DBG (bvr, 5) }, 284{ DEFINE_DBG (bvr, 6) }, 285{ DEFINE_DBG (bvr, 7) }, 286{ DEFINE_DBG (bvr, 8) }, 287{ DEFINE_DBG (bvr, 9) }, 288{ DEFINE_DBG (bvr, 10) }, 289{ DEFINE_DBG (bvr, 11) }, 290{ DEFINE_DBG (bvr, 12) }, 291{ DEFINE_DBG (bvr, 13) }, 292{ DEFINE_DBG (bvr, 14) }, 293{ DEFINE_DBG (bvr, 15) }, 294 295{ DEFINE_DBG (bcr, 0) }, 296{ DEFINE_DBG (bcr, 1) }, 297{ DEFINE_DBG (bcr, 2) }, 298{ DEFINE_DBG (bcr, 3) }, 299{ DEFINE_DBG (bcr, 4) }, 300{ DEFINE_DBG (bcr, 5) }, 301{ DEFINE_DBG (bcr, 6) }, 302{ DEFINE_DBG (bcr, 7) }, 303{ DEFINE_DBG (bcr, 8) }, 304{ DEFINE_DBG (bcr, 9) }, 305{ DEFINE_DBG (bcr, 10) }, 306{ DEFINE_DBG (bcr, 11) }, 307{ DEFINE_DBG (bcr, 12) }, 308{ DEFINE_DBG (bcr, 13) }, 309{ DEFINE_DBG (bcr, 14) }, 310{ DEFINE_DBG (bcr, 15) }, 311 312{ DEFINE_DBG (wvr, 0) }, 313{ DEFINE_DBG (wvr, 1) }, 314{ DEFINE_DBG (wvr, 2) }, 315{ DEFINE_DBG (wvr, 3) }, 316{ DEFINE_DBG (wvr, 4) }, 317{ DEFINE_DBG (wvr, 5) }, 318{ DEFINE_DBG (wvr, 6) }, 319{ DEFINE_DBG (wvr, 7) }, 320{ DEFINE_DBG (wvr, 8) }, 321{ DEFINE_DBG (wvr, 9) }, 322{ DEFINE_DBG (wvr, 10) }, 323{ DEFINE_DBG (wvr, 11) }, 324{ DEFINE_DBG (wvr, 12) }, 325{ DEFINE_DBG (wvr, 13) }, 326{ DEFINE_DBG (wvr, 14) }, 327{ DEFINE_DBG (wvr, 15) }, 328 329{ DEFINE_DBG (wcr, 0) }, 330{ DEFINE_DBG (wcr, 1) }, 331{ DEFINE_DBG (wcr, 2) }, 332{ DEFINE_DBG (wcr, 3) }, 333{ DEFINE_DBG (wcr, 4) }, 334{ DEFINE_DBG (wcr, 5) }, 335{ DEFINE_DBG (wcr, 6) }, 336{ DEFINE_DBG (wcr, 7) }, 337{ DEFINE_DBG (wcr, 8) }, 338{ DEFINE_DBG (wcr, 9) }, 339{ DEFINE_DBG (wcr, 10) }, 340{ DEFINE_DBG (wcr, 11) }, 341{ DEFINE_DBG (wcr, 12) }, 342{ DEFINE_DBG (wcr, 13) }, 343{ DEFINE_DBG (wcr, 14) }, 344{ DEFINE_DBG (wcr, 15) } 345}; 346 347#endif // DECLARE_REGISTER_INFOS_ARM64_STRUCT 348