RegisterContext_mips.h revision 288943
1//===-- RegisterContext_mips.h --------------------------------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9 10#ifndef liblldb_RegisterContext_mips64_H_ 11#define liblldb_RegisterContext_mips64_H_ 12 13// eh_frame and DWARF Register numbers (eRegisterKindEHFrame & eRegisterKindDWARF) 14 15enum 16{ 17 // GP Registers 18 gcc_dwarf_zero_mips = 0, 19 gcc_dwarf_r1_mips, 20 gcc_dwarf_r2_mips, 21 gcc_dwarf_r3_mips, 22 gcc_dwarf_r4_mips, 23 gcc_dwarf_r5_mips, 24 gcc_dwarf_r6_mips, 25 gcc_dwarf_r7_mips, 26 gcc_dwarf_r8_mips, 27 gcc_dwarf_r9_mips, 28 gcc_dwarf_r10_mips, 29 gcc_dwarf_r11_mips, 30 gcc_dwarf_r12_mips, 31 gcc_dwarf_r13_mips, 32 gcc_dwarf_r14_mips, 33 gcc_dwarf_r15_mips, 34 gcc_dwarf_r16_mips, 35 gcc_dwarf_r17_mips, 36 gcc_dwarf_r18_mips, 37 gcc_dwarf_r19_mips, 38 gcc_dwarf_r20_mips, 39 gcc_dwarf_r21_mips, 40 gcc_dwarf_r22_mips, 41 gcc_dwarf_r23_mips, 42 gcc_dwarf_r24_mips, 43 gcc_dwarf_r25_mips, 44 gcc_dwarf_r26_mips, 45 gcc_dwarf_r27_mips, 46 gcc_dwarf_gp_mips, 47 gcc_dwarf_sp_mips, 48 gcc_dwarf_r30_mips, 49 gcc_dwarf_ra_mips, 50 gcc_dwarf_sr_mips, 51 gcc_dwarf_lo_mips, 52 gcc_dwarf_hi_mips, 53 gcc_dwarf_bad_mips, 54 gcc_dwarf_cause_mips, 55 gcc_dwarf_pc_mips, 56 gcc_dwarf_f0_mips, 57 gcc_dwarf_f1_mips, 58 gcc_dwarf_f2_mips, 59 gcc_dwarf_f3_mips, 60 gcc_dwarf_f4_mips, 61 gcc_dwarf_f5_mips, 62 gcc_dwarf_f6_mips, 63 gcc_dwarf_f7_mips, 64 gcc_dwarf_f8_mips, 65 gcc_dwarf_f9_mips, 66 gcc_dwarf_f10_mips, 67 gcc_dwarf_f11_mips, 68 gcc_dwarf_f12_mips, 69 gcc_dwarf_f13_mips, 70 gcc_dwarf_f14_mips, 71 gcc_dwarf_f15_mips, 72 gcc_dwarf_f16_mips, 73 gcc_dwarf_f17_mips, 74 gcc_dwarf_f18_mips, 75 gcc_dwarf_f19_mips, 76 gcc_dwarf_f20_mips, 77 gcc_dwarf_f21_mips, 78 gcc_dwarf_f22_mips, 79 gcc_dwarf_f23_mips, 80 gcc_dwarf_f24_mips, 81 gcc_dwarf_f25_mips, 82 gcc_dwarf_f26_mips, 83 gcc_dwarf_f27_mips, 84 gcc_dwarf_f28_mips, 85 gcc_dwarf_f29_mips, 86 gcc_dwarf_f30_mips, 87 gcc_dwarf_f31_mips, 88 gcc_dwarf_fcsr_mips, 89 gcc_dwarf_fir_mips, 90 gcc_dwarf_w0_mips, 91 gcc_dwarf_w1_mips, 92 gcc_dwarf_w2_mips, 93 gcc_dwarf_w3_mips, 94 gcc_dwarf_w4_mips, 95 gcc_dwarf_w5_mips, 96 gcc_dwarf_w6_mips, 97 gcc_dwarf_w7_mips, 98 gcc_dwarf_w8_mips, 99 gcc_dwarf_w9_mips, 100 gcc_dwarf_w10_mips, 101 gcc_dwarf_w11_mips, 102 gcc_dwarf_w12_mips, 103 gcc_dwarf_w13_mips, 104 gcc_dwarf_w14_mips, 105 gcc_dwarf_w15_mips, 106 gcc_dwarf_w16_mips, 107 gcc_dwarf_w17_mips, 108 gcc_dwarf_w18_mips, 109 gcc_dwarf_w19_mips, 110 gcc_dwarf_w20_mips, 111 gcc_dwarf_w21_mips, 112 gcc_dwarf_w22_mips, 113 gcc_dwarf_w23_mips, 114 gcc_dwarf_w24_mips, 115 gcc_dwarf_w25_mips, 116 gcc_dwarf_w26_mips, 117 gcc_dwarf_w27_mips, 118 gcc_dwarf_w28_mips, 119 gcc_dwarf_w29_mips, 120 gcc_dwarf_w30_mips, 121 gcc_dwarf_w31_mips, 122 gcc_dwarf_mcsr_mips, 123 gcc_dwarf_mir_mips, 124 gcc_dwarf_config5_mips, 125 gcc_dwarf_ic_mips, 126 gcc_dwarf_dummy_mips 127}; 128 129enum 130{ 131 gcc_dwarf_zero_mips64 = 0, 132 gcc_dwarf_r1_mips64, 133 gcc_dwarf_r2_mips64, 134 gcc_dwarf_r3_mips64, 135 gcc_dwarf_r4_mips64, 136 gcc_dwarf_r5_mips64, 137 gcc_dwarf_r6_mips64, 138 gcc_dwarf_r7_mips64, 139 gcc_dwarf_r8_mips64, 140 gcc_dwarf_r9_mips64, 141 gcc_dwarf_r10_mips64, 142 gcc_dwarf_r11_mips64, 143 gcc_dwarf_r12_mips64, 144 gcc_dwarf_r13_mips64, 145 gcc_dwarf_r14_mips64, 146 gcc_dwarf_r15_mips64, 147 gcc_dwarf_r16_mips64, 148 gcc_dwarf_r17_mips64, 149 gcc_dwarf_r18_mips64, 150 gcc_dwarf_r19_mips64, 151 gcc_dwarf_r20_mips64, 152 gcc_dwarf_r21_mips64, 153 gcc_dwarf_r22_mips64, 154 gcc_dwarf_r23_mips64, 155 gcc_dwarf_r24_mips64, 156 gcc_dwarf_r25_mips64, 157 gcc_dwarf_r26_mips64, 158 gcc_dwarf_r27_mips64, 159 gcc_dwarf_gp_mips64, 160 gcc_dwarf_sp_mips64, 161 gcc_dwarf_r30_mips64, 162 gcc_dwarf_ra_mips64, 163 gcc_dwarf_sr_mips64, 164 gcc_dwarf_lo_mips64, 165 gcc_dwarf_hi_mips64, 166 gcc_dwarf_bad_mips64, 167 gcc_dwarf_cause_mips64, 168 gcc_dwarf_pc_mips64, 169 gcc_dwarf_f0_mips64, 170 gcc_dwarf_f1_mips64, 171 gcc_dwarf_f2_mips64, 172 gcc_dwarf_f3_mips64, 173 gcc_dwarf_f4_mips64, 174 gcc_dwarf_f5_mips64, 175 gcc_dwarf_f6_mips64, 176 gcc_dwarf_f7_mips64, 177 gcc_dwarf_f8_mips64, 178 gcc_dwarf_f9_mips64, 179 gcc_dwarf_f10_mips64, 180 gcc_dwarf_f11_mips64, 181 gcc_dwarf_f12_mips64, 182 gcc_dwarf_f13_mips64, 183 gcc_dwarf_f14_mips64, 184 gcc_dwarf_f15_mips64, 185 gcc_dwarf_f16_mips64, 186 gcc_dwarf_f17_mips64, 187 gcc_dwarf_f18_mips64, 188 gcc_dwarf_f19_mips64, 189 gcc_dwarf_f20_mips64, 190 gcc_dwarf_f21_mips64, 191 gcc_dwarf_f22_mips64, 192 gcc_dwarf_f23_mips64, 193 gcc_dwarf_f24_mips64, 194 gcc_dwarf_f25_mips64, 195 gcc_dwarf_f26_mips64, 196 gcc_dwarf_f27_mips64, 197 gcc_dwarf_f28_mips64, 198 gcc_dwarf_f29_mips64, 199 gcc_dwarf_f30_mips64, 200 gcc_dwarf_f31_mips64, 201 gcc_dwarf_fcsr_mips64, 202 gcc_dwarf_fir_mips64, 203 gcc_dwarf_ic_mips64, 204 gcc_dwarf_dummy_mips64, 205 gcc_dwarf_w0_mips64, 206 gcc_dwarf_w1_mips64, 207 gcc_dwarf_w2_mips64, 208 gcc_dwarf_w3_mips64, 209 gcc_dwarf_w4_mips64, 210 gcc_dwarf_w5_mips64, 211 gcc_dwarf_w6_mips64, 212 gcc_dwarf_w7_mips64, 213 gcc_dwarf_w8_mips64, 214 gcc_dwarf_w9_mips64, 215 gcc_dwarf_w10_mips64, 216 gcc_dwarf_w11_mips64, 217 gcc_dwarf_w12_mips64, 218 gcc_dwarf_w13_mips64, 219 gcc_dwarf_w14_mips64, 220 gcc_dwarf_w15_mips64, 221 gcc_dwarf_w16_mips64, 222 gcc_dwarf_w17_mips64, 223 gcc_dwarf_w18_mips64, 224 gcc_dwarf_w19_mips64, 225 gcc_dwarf_w20_mips64, 226 gcc_dwarf_w21_mips64, 227 gcc_dwarf_w22_mips64, 228 gcc_dwarf_w23_mips64, 229 gcc_dwarf_w24_mips64, 230 gcc_dwarf_w25_mips64, 231 gcc_dwarf_w26_mips64, 232 gcc_dwarf_w27_mips64, 233 gcc_dwarf_w28_mips64, 234 gcc_dwarf_w29_mips64, 235 gcc_dwarf_w30_mips64, 236 gcc_dwarf_w31_mips64, 237 gcc_dwarf_mcsr_mips64, 238 gcc_dwarf_mir_mips64, 239 gcc_dwarf_config5_mips64, 240}; 241 242// GDB Register numbers (eRegisterKindGDB) 243enum 244{ 245 gdb_zero_mips = 0, 246 gdb_r1_mips, 247 gdb_r2_mips, 248 gdb_r3_mips, 249 gdb_r4_mips, 250 gdb_r5_mips, 251 gdb_r6_mips, 252 gdb_r7_mips, 253 gdb_r8_mips, 254 gdb_r9_mips, 255 gdb_r10_mips, 256 gdb_r11_mips, 257 gdb_r12_mips, 258 gdb_r13_mips, 259 gdb_r14_mips, 260 gdb_r15_mips, 261 gdb_r16_mips, 262 gdb_r17_mips, 263 gdb_r18_mips, 264 gdb_r19_mips, 265 gdb_r20_mips, 266 gdb_r21_mips, 267 gdb_r22_mips, 268 gdb_r23_mips, 269 gdb_r24_mips, 270 gdb_r25_mips, 271 gdb_r26_mips, 272 gdb_r27_mips, 273 gdb_gp_mips, 274 gdb_sp_mips, 275 gdb_r30_mips, 276 gdb_ra_mips, 277 gdb_sr_mips, 278 gdb_lo_mips, 279 gdb_hi_mips, 280 gdb_bad_mips, 281 gdb_cause_mips, 282 gdb_pc_mips, 283 gdb_f0_mips, 284 gdb_f1_mips, 285 gdb_f2_mips, 286 gdb_f3_mips, 287 gdb_f4_mips, 288 gdb_f5_mips, 289 gdb_f6_mips, 290 gdb_f7_mips, 291 gdb_f8_mips, 292 gdb_f9_mips, 293 gdb_f10_mips, 294 gdb_f11_mips, 295 gdb_f12_mips, 296 gdb_f13_mips, 297 gdb_f14_mips, 298 gdb_f15_mips, 299 gdb_f16_mips, 300 gdb_f17_mips, 301 gdb_f18_mips, 302 gdb_f19_mips, 303 gdb_f20_mips, 304 gdb_f21_mips, 305 gdb_f22_mips, 306 gdb_f23_mips, 307 gdb_f24_mips, 308 gdb_f25_mips, 309 gdb_f26_mips, 310 gdb_f27_mips, 311 gdb_f28_mips, 312 gdb_f29_mips, 313 gdb_f30_mips, 314 gdb_f31_mips, 315 gdb_fcsr_mips, 316 gdb_fir_mips, 317 gdb_w0_mips, 318 gdb_w1_mips, 319 gdb_w2_mips, 320 gdb_w3_mips, 321 gdb_w4_mips, 322 gdb_w5_mips, 323 gdb_w6_mips, 324 gdb_w7_mips, 325 gdb_w8_mips, 326 gdb_w9_mips, 327 gdb_w10_mips, 328 gdb_w11_mips, 329 gdb_w12_mips, 330 gdb_w13_mips, 331 gdb_w14_mips, 332 gdb_w15_mips, 333 gdb_w16_mips, 334 gdb_w17_mips, 335 gdb_w18_mips, 336 gdb_w19_mips, 337 gdb_w20_mips, 338 gdb_w21_mips, 339 gdb_w22_mips, 340 gdb_w23_mips, 341 gdb_w24_mips, 342 gdb_w25_mips, 343 gdb_w26_mips, 344 gdb_w27_mips, 345 gdb_w28_mips, 346 gdb_w29_mips, 347 gdb_w30_mips, 348 gdb_w31_mips, 349 gdb_mcsr_mips, 350 gdb_mir_mips, 351 gdb_config5_mips, 352 gdb_ic_mips, 353 gdb_dummy_mips 354}; 355 356enum 357{ 358 gdb_zero_mips64 = 0, 359 gdb_r1_mips64, 360 gdb_r2_mips64, 361 gdb_r3_mips64, 362 gdb_r4_mips64, 363 gdb_r5_mips64, 364 gdb_r6_mips64, 365 gdb_r7_mips64, 366 gdb_r8_mips64, 367 gdb_r9_mips64, 368 gdb_r10_mips64, 369 gdb_r11_mips64, 370 gdb_r12_mips64, 371 gdb_r13_mips64, 372 gdb_r14_mips64, 373 gdb_r15_mips64, 374 gdb_r16_mips64, 375 gdb_r17_mips64, 376 gdb_r18_mips64, 377 gdb_r19_mips64, 378 gdb_r20_mips64, 379 gdb_r21_mips64, 380 gdb_r22_mips64, 381 gdb_r23_mips64, 382 gdb_r24_mips64, 383 gdb_r25_mips64, 384 gdb_r26_mips64, 385 gdb_r27_mips64, 386 gdb_gp_mips64, 387 gdb_sp_mips64, 388 gdb_r30_mips64, 389 gdb_ra_mips64, 390 gdb_sr_mips64, 391 gdb_lo_mips64, 392 gdb_hi_mips64, 393 gdb_bad_mips64, 394 gdb_cause_mips64, 395 gdb_pc_mips64, 396 gdb_f0_mips64, 397 gdb_f1_mips64, 398 gdb_f2_mips64, 399 gdb_f3_mips64, 400 gdb_f4_mips64, 401 gdb_f5_mips64, 402 gdb_f6_mips64, 403 gdb_f7_mips64, 404 gdb_f8_mips64, 405 gdb_f9_mips64, 406 gdb_f10_mips64, 407 gdb_f11_mips64, 408 gdb_f12_mips64, 409 gdb_f13_mips64, 410 gdb_f14_mips64, 411 gdb_f15_mips64, 412 gdb_f16_mips64, 413 gdb_f17_mips64, 414 gdb_f18_mips64, 415 gdb_f19_mips64, 416 gdb_f20_mips64, 417 gdb_f21_mips64, 418 gdb_f22_mips64, 419 gdb_f23_mips64, 420 gdb_f24_mips64, 421 gdb_f25_mips64, 422 gdb_f26_mips64, 423 gdb_f27_mips64, 424 gdb_f28_mips64, 425 gdb_f29_mips64, 426 gdb_f30_mips64, 427 gdb_f31_mips64, 428 gdb_fcsr_mips64, 429 gdb_fir_mips64, 430 gdb_ic_mips64, 431 gdb_dummy_mips64, 432 gdb_w0_mips64, 433 gdb_w1_mips64, 434 gdb_w2_mips64, 435 gdb_w3_mips64, 436 gdb_w4_mips64, 437 gdb_w5_mips64, 438 gdb_w6_mips64, 439 gdb_w7_mips64, 440 gdb_w8_mips64, 441 gdb_w9_mips64, 442 gdb_w10_mips64, 443 gdb_w11_mips64, 444 gdb_w12_mips64, 445 gdb_w13_mips64, 446 gdb_w14_mips64, 447 gdb_w15_mips64, 448 gdb_w16_mips64, 449 gdb_w17_mips64, 450 gdb_w18_mips64, 451 gdb_w19_mips64, 452 gdb_w20_mips64, 453 gdb_w21_mips64, 454 gdb_w22_mips64, 455 gdb_w23_mips64, 456 gdb_w24_mips64, 457 gdb_w25_mips64, 458 gdb_w26_mips64, 459 gdb_w27_mips64, 460 gdb_w28_mips64, 461 gdb_w29_mips64, 462 gdb_w30_mips64, 463 gdb_w31_mips64, 464 gdb_mcsr_mips64, 465 gdb_mir_mips64, 466 gdb_config5_mips64, 467}; 468 469struct IOVEC_mips 470{ 471 void *iov_base; 472 size_t iov_len; 473}; 474 475// GP registers 476struct GPR_linux_mips 477{ 478 uint64_t zero; 479 uint64_t r1; 480 uint64_t r2; 481 uint64_t r3; 482 uint64_t r4; 483 uint64_t r5; 484 uint64_t r6; 485 uint64_t r7; 486 uint64_t r8; 487 uint64_t r9; 488 uint64_t r10; 489 uint64_t r11; 490 uint64_t r12; 491 uint64_t r13; 492 uint64_t r14; 493 uint64_t r15; 494 uint64_t r16; 495 uint64_t r17; 496 uint64_t r18; 497 uint64_t r19; 498 uint64_t r20; 499 uint64_t r21; 500 uint64_t r22; 501 uint64_t r23; 502 uint64_t r24; 503 uint64_t r25; 504 uint64_t r26; 505 uint64_t r27; 506 uint64_t gp; 507 uint64_t sp; 508 uint64_t r30; 509 uint64_t ra; 510 uint64_t mullo; 511 uint64_t mulhi; 512 uint64_t pc; 513 uint64_t badvaddr; 514 uint64_t sr; 515 uint64_t cause; 516 uint64_t config5; 517}; 518 519struct FPR_linux_mips 520{ 521 uint64_t f0; 522 uint64_t f1; 523 uint64_t f2; 524 uint64_t f3; 525 uint64_t f4; 526 uint64_t f5; 527 uint64_t f6; 528 uint64_t f7; 529 uint64_t f8; 530 uint64_t f9; 531 uint64_t f10; 532 uint64_t f11; 533 uint64_t f12; 534 uint64_t f13; 535 uint64_t f14; 536 uint64_t f15; 537 uint64_t f16; 538 uint64_t f17; 539 uint64_t f18; 540 uint64_t f19; 541 uint64_t f20; 542 uint64_t f21; 543 uint64_t f22; 544 uint64_t f23; 545 uint64_t f24; 546 uint64_t f25; 547 uint64_t f26; 548 uint64_t f27; 549 uint64_t f28; 550 uint64_t f29; 551 uint64_t f30; 552 uint64_t f31; 553 uint32_t fcsr; 554 uint32_t fir; 555 uint32_t config5; 556}; 557 558struct MSAReg 559{ 560 uint8_t byte[16]; 561}; 562 563struct MSA_linux_mips 564{ 565 MSAReg w0; 566 MSAReg w1; 567 MSAReg w2; 568 MSAReg w3; 569 MSAReg w4; 570 MSAReg w5; 571 MSAReg w6; 572 MSAReg w7; 573 MSAReg w8; 574 MSAReg w9; 575 MSAReg w10; 576 MSAReg w11; 577 MSAReg w12; 578 MSAReg w13; 579 MSAReg w14; 580 MSAReg w15; 581 MSAReg w16; 582 MSAReg w17; 583 MSAReg w18; 584 MSAReg w19; 585 MSAReg w20; 586 MSAReg w21; 587 MSAReg w22; 588 MSAReg w23; 589 MSAReg w24; 590 MSAReg w25; 591 MSAReg w26; 592 MSAReg w27; 593 MSAReg w28; 594 MSAReg w29; 595 MSAReg w30; 596 MSAReg w31; 597 uint32_t fcsr; /* FPU control status register */ 598 uint32_t fir; /* FPU implementaion revision */ 599 uint32_t mcsr; /* MSA control status register */ 600 uint32_t mir; /* MSA implementation revision */ 601 uint32_t config5; /* Config5 register */ 602}; 603 604struct UserArea 605{ 606 GPR_linux_mips gpr; // General purpose registers. 607 FPR_linux_mips fpr; // Floating point registers. 608 MSA_linux_mips msa; // MSA registers. 609}; 610 611#endif // liblldb_RegisterContext_mips64_H_ 612