1326949Sdim//===-- ArchitectureArm.cpp -------------------------------------*- C++ -*-===// 2326949Sdim// 3353358Sdim// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4353358Sdim// See https://llvm.org/LICENSE.txt for license information. 5353358Sdim// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6326949Sdim// 7326949Sdim//===----------------------------------------------------------------------===// 8326949Sdim 9326949Sdim#include "Plugins/Architecture/Arm/ArchitectureArm.h" 10326949Sdim#include "Plugins/Process/Utility/ARMDefines.h" 11326949Sdim#include "Plugins/Process/Utility/InstructionUtils.h" 12326949Sdim#include "lldb/Core/PluginManager.h" 13326949Sdim#include "lldb/Target/RegisterContext.h" 14326949Sdim#include "lldb/Target/Thread.h" 15326949Sdim#include "lldb/Utility/ArchSpec.h" 16326949Sdim 17326949Sdimusing namespace lldb_private; 18326949Sdimusing namespace lldb; 19326949Sdim 20326949SdimConstString ArchitectureArm::GetPluginNameStatic() { 21326949Sdim return ConstString("arm"); 22326949Sdim} 23326949Sdim 24326949Sdimvoid ArchitectureArm::Initialize() { 25326949Sdim PluginManager::RegisterPlugin(GetPluginNameStatic(), 26326949Sdim "Arm-specific algorithms", 27326949Sdim &ArchitectureArm::Create); 28326949Sdim} 29326949Sdim 30326949Sdimvoid ArchitectureArm::Terminate() { 31326949Sdim PluginManager::UnregisterPlugin(&ArchitectureArm::Create); 32326949Sdim} 33326949Sdim 34326949Sdimstd::unique_ptr<Architecture> ArchitectureArm::Create(const ArchSpec &arch) { 35326949Sdim if (arch.GetMachine() != llvm::Triple::arm) 36326949Sdim return nullptr; 37326949Sdim return std::unique_ptr<Architecture>(new ArchitectureArm()); 38326949Sdim} 39326949Sdim 40326949SdimConstString ArchitectureArm::GetPluginName() { return GetPluginNameStatic(); } 41326949Sdimuint32_t ArchitectureArm::GetPluginVersion() { return 1; } 42326949Sdim 43341825Sdimvoid ArchitectureArm::OverrideStopInfo(Thread &thread) const { 44341825Sdim // We need to check if we are stopped in Thumb mode in a IT instruction and 45341825Sdim // detect if the condition doesn't pass. If this is the case it means we 46341825Sdim // won't actually execute this instruction. If this happens we need to clear 47341825Sdim // the stop reason to no thread plans think we are stopped for a reason and 48341825Sdim // the plans should keep going. 49326949Sdim // 50326949Sdim // We do this because when single stepping many ARM processes, debuggers 51341825Sdim // often use the BVR/BCR registers that says "stop when the PC is not equal 52341825Sdim // to its current value". This method of stepping means we can end up 53341825Sdim // stopping on instructions inside an if/then block that wouldn't get 54341825Sdim // executed. By fixing this we can stop the debugger from seeming like you 55341825Sdim // stepped through both the "if" _and_ the "else" clause when source level 56341825Sdim // stepping because the debugger stops regardless due to the BVR/BCR 57326949Sdim // triggering a stop. 58326949Sdim // 59341825Sdim // It also means we can set breakpoints on instructions inside an an if/then 60341825Sdim // block and correctly skip them if we use the BKPT instruction. The ARM and 61341825Sdim // Thumb BKPT instructions are unconditional even when executed in a Thumb IT 62341825Sdim // block. 63326949Sdim // 64341825Sdim // If your debugger inserts software traps in ARM/Thumb code, it will need to 65341825Sdim // use 16 and 32 bit instruction for 16 and 32 bit thumb instructions 66341825Sdim // respectively. If your debugger inserts a 16 bit thumb trap on top of a 32 67341825Sdim // bit thumb instruction for an opcode that is inside an if/then, it will 68341825Sdim // change the it/then to conditionally execute your 69326949Sdim // 16 bit trap and then cause your program to crash if it executes the 70326949Sdim // trailing 16 bits (the second half of the 32 bit thumb instruction you 71326949Sdim // partially overwrote). 72326949Sdim 73326949Sdim RegisterContextSP reg_ctx_sp(thread.GetRegisterContext()); 74326949Sdim if (!reg_ctx_sp) 75326949Sdim return; 76326949Sdim 77326949Sdim const uint32_t cpsr = reg_ctx_sp->GetFlags(0); 78326949Sdim if (cpsr == 0) 79326949Sdim return; 80326949Sdim 81326949Sdim // Read the J and T bits to get the ISETSTATE 82326949Sdim const uint32_t J = Bit32(cpsr, 24); 83326949Sdim const uint32_t T = Bit32(cpsr, 5); 84326949Sdim const uint32_t ISETSTATE = J << 1 | T; 85326949Sdim if (ISETSTATE == 0) { 86326949Sdim// NOTE: I am pretty sure we want to enable the code below 87341825Sdim// that detects when we stop on an instruction in ARM mode that is conditional 88341825Sdim// and the condition doesn't pass. This can happen if you set a breakpoint on 89341825Sdim// an instruction that is conditional. We currently will _always_ stop on the 90341825Sdim// instruction which is bad. You can also run into this while single stepping 91341825Sdim// and you could appear to run code in the "if" and in the "else" clause 92341825Sdim// because it would stop at all of the conditional instructions in both. In 93341825Sdim// such cases, we really don't want to stop at this location. 94326949Sdim// I will check with the lldb-dev list first before I enable this. 95326949Sdim#if 0 96341825Sdim // ARM mode: check for condition on instruction 97326949Sdim const addr_t pc = reg_ctx_sp->GetPC(); 98326949Sdim Status error; 99341825Sdim // If we fail to read the opcode we will get UINT64_MAX as the result in 100341825Sdim // "opcode" which we can use to detect if we read a valid opcode. 101326949Sdim const uint64_t opcode = thread.GetProcess()->ReadUnsignedIntegerFromMemory(pc, 4, UINT64_MAX, error); 102326949Sdim if (opcode <= UINT32_MAX) 103326949Sdim { 104326949Sdim const uint32_t condition = Bits32((uint32_t)opcode, 31, 28); 105326949Sdim if (!ARMConditionPassed(condition, cpsr)) 106326949Sdim { 107326949Sdim // We ARE stopped on an ARM instruction whose condition doesn't 108341825Sdim // pass so this instruction won't get executed. Regardless of why 109341825Sdim // it stopped, we need to clear the stop info 110326949Sdim thread.SetStopInfo (StopInfoSP()); 111326949Sdim } 112326949Sdim } 113326949Sdim#endif 114326949Sdim } else if (ISETSTATE == 1) { 115326949Sdim // Thumb mode 116326949Sdim const uint32_t ITSTATE = Bits32(cpsr, 15, 10) << 2 | Bits32(cpsr, 26, 25); 117326949Sdim if (ITSTATE != 0) { 118326949Sdim const uint32_t condition = Bits32(ITSTATE, 7, 4); 119326949Sdim if (!ARMConditionPassed(condition, cpsr)) { 120326949Sdim // We ARE stopped in a Thumb IT instruction on an instruction whose 121326949Sdim // condition doesn't pass so this instruction won't get executed. 122326949Sdim // Regardless of why it stopped, we need to clear the stop info 123326949Sdim thread.SetStopInfo(StopInfoSP()); 124326949Sdim } 125326949Sdim } 126326949Sdim } 127326949Sdim} 128344779Sdim 129344779Sdimaddr_t ArchitectureArm::GetCallableLoadAddress(addr_t code_addr, 130344779Sdim AddressClass addr_class) const { 131344779Sdim bool is_alternate_isa = false; 132344779Sdim 133344779Sdim switch (addr_class) { 134344779Sdim case AddressClass::eData: 135344779Sdim case AddressClass::eDebug: 136344779Sdim return LLDB_INVALID_ADDRESS; 137344779Sdim case AddressClass::eCodeAlternateISA: 138344779Sdim is_alternate_isa = true; 139344779Sdim break; 140344779Sdim default: break; 141344779Sdim } 142344779Sdim 143344779Sdim if ((code_addr & 2u) || is_alternate_isa) 144344779Sdim return code_addr | 1u; 145344779Sdim return code_addr; 146344779Sdim} 147344779Sdim 148344779Sdimaddr_t ArchitectureArm::GetOpcodeLoadAddress(addr_t opcode_addr, 149344779Sdim AddressClass addr_class) const { 150344779Sdim switch (addr_class) { 151344779Sdim case AddressClass::eData: 152344779Sdim case AddressClass::eDebug: 153344779Sdim return LLDB_INVALID_ADDRESS; 154344779Sdim default: break; 155344779Sdim } 156344779Sdim return opcode_addr & ~(1ull); 157344779Sdim} 158