1288149Semaste//===---------------------------- libunwind.h -----------------------------===// 2288149Semaste// 3353358Sdim// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4353358Sdim// See https://llvm.org/LICENSE.txt for license information. 5353358Sdim// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6288149Semaste// 7288149Semaste// 8308006Semaste// Compatible with libunwind API documented at: 9288149Semaste// http://www.nongnu.org/libunwind/man/libunwind(3).html 10288149Semaste// 11288149Semaste//===----------------------------------------------------------------------===// 12288149Semaste 13288149Semaste#ifndef __LIBUNWIND__ 14288149Semaste#define __LIBUNWIND__ 15288149Semaste 16288149Semaste#include <__libunwind_config.h> 17288149Semaste 18288149Semaste#include <stdint.h> 19288149Semaste#include <stddef.h> 20288149Semaste 21288149Semaste#ifdef __APPLE__ 22345018Sdim #if __clang__ 23345018Sdim #if __has_include(<Availability.h>) 24345018Sdim #include <Availability.h> 25345018Sdim #endif 26345018Sdim #elif __ENVIRONMENT_MAC_OS_X_VERSION_MIN_REQUIRED__ >= 1050 27345018Sdim #include <Availability.h> 28345018Sdim #endif 29345018Sdim 30345018Sdim #ifdef __arm__ 31345018Sdim #define LIBUNWIND_AVAIL __attribute__((unavailable)) 32345018Sdim #elif defined(__OSX_AVAILABLE_STARTING) 33345018Sdim #define LIBUNWIND_AVAIL __OSX_AVAILABLE_STARTING(__MAC_10_6, __IPHONE_5_0) 34345018Sdim #else 35345018Sdim #include <AvailabilityMacros.h> 36345018Sdim #ifdef AVAILABLE_MAC_OS_X_VERSION_10_6_AND_LATER 37345018Sdim #define LIBUNWIND_AVAIL AVAILABLE_MAC_OS_X_VERSION_10_6_AND_LATER 38288149Semaste #else 39345018Sdim #define LIBUNWIND_AVAIL __attribute__((unavailable)) 40288149Semaste #endif 41345018Sdim #endif 42288149Semaste#else 43288149Semaste #define LIBUNWIND_AVAIL 44288149Semaste#endif 45288149Semaste 46288149Semaste/* error codes */ 47288149Semasteenum { 48288149Semaste UNW_ESUCCESS = 0, /* no error */ 49288149Semaste UNW_EUNSPEC = -6540, /* unspecified (general) error */ 50288149Semaste UNW_ENOMEM = -6541, /* out of memory */ 51288149Semaste UNW_EBADREG = -6542, /* bad register number */ 52288149Semaste UNW_EREADONLYREG = -6543, /* attempt to write read-only register */ 53288149Semaste UNW_ESTOPUNWIND = -6544, /* stop unwinding */ 54288149Semaste UNW_EINVALIDIP = -6545, /* invalid IP */ 55288149Semaste UNW_EBADFRAME = -6546, /* bad frame */ 56288149Semaste UNW_EINVAL = -6547, /* unsupported operation or bad value */ 57288149Semaste UNW_EBADVERSION = -6548, /* unwind info has unsupported version */ 58288149Semaste UNW_ENOINFO = -6549 /* no unwind info found */ 59345018Sdim#if defined(_LIBUNWIND_TARGET_AARCH64) && !defined(_LIBUNWIND_IS_NATIVE_ONLY) 60345018Sdim , UNW_ECROSSRASIGNING = -6550 /* cross unwind with return address signing */ 61345018Sdim#endif 62288149Semaste}; 63288149Semaste 64288149Semastestruct unw_context_t { 65302450Semaste uint64_t data[_LIBUNWIND_CONTEXT_SIZE]; 66288149Semaste}; 67288149Semastetypedef struct unw_context_t unw_context_t; 68288149Semaste 69288149Semastestruct unw_cursor_t { 70302450Semaste uint64_t data[_LIBUNWIND_CURSOR_SIZE]; 71288149Semaste}; 72288149Semastetypedef struct unw_cursor_t unw_cursor_t; 73288149Semaste 74288149Semastetypedef struct unw_addr_space *unw_addr_space_t; 75288149Semaste 76288149Semastetypedef int unw_regnum_t; 77345018Sdimtypedef uintptr_t unw_word_t; 78353358Sdim#if defined(__arm__) && !defined(__ARM_DWARF_EH__) 79288149Semastetypedef uint64_t unw_fpreg_t; 80288149Semaste#else 81288149Semastetypedef double unw_fpreg_t; 82288149Semaste#endif 83288149Semaste 84288149Semastestruct unw_proc_info_t { 85288149Semaste unw_word_t start_ip; /* start address of function */ 86288149Semaste unw_word_t end_ip; /* address after end of function */ 87288149Semaste unw_word_t lsda; /* address of language specific data area, */ 88288149Semaste /* or zero if not used */ 89288149Semaste unw_word_t handler; /* personality routine, or zero if not used */ 90288149Semaste unw_word_t gp; /* not used */ 91288149Semaste unw_word_t flags; /* not used */ 92288149Semaste uint32_t format; /* compact unwind encoding, or zero if none */ 93345018Sdim uint32_t unwind_info_size; /* size of DWARF unwind info, or zero if none */ 94345018Sdim unw_word_t unwind_info; /* address of DWARF unwind info, or zero */ 95288149Semaste unw_word_t extra; /* mach_header of mach-o image containing func */ 96288149Semaste}; 97288149Semastetypedef struct unw_proc_info_t unw_proc_info_t; 98288149Semaste 99288149Semaste#ifdef __cplusplus 100288149Semasteextern "C" { 101288149Semaste#endif 102288149Semaste 103288149Semasteextern int unw_getcontext(unw_context_t *) LIBUNWIND_AVAIL; 104288149Semasteextern int unw_init_local(unw_cursor_t *, unw_context_t *) LIBUNWIND_AVAIL; 105288149Semasteextern int unw_step(unw_cursor_t *) LIBUNWIND_AVAIL; 106288149Semasteextern int unw_get_reg(unw_cursor_t *, unw_regnum_t, unw_word_t *) LIBUNWIND_AVAIL; 107288149Semasteextern int unw_get_fpreg(unw_cursor_t *, unw_regnum_t, unw_fpreg_t *) LIBUNWIND_AVAIL; 108288149Semasteextern int unw_set_reg(unw_cursor_t *, unw_regnum_t, unw_word_t) LIBUNWIND_AVAIL; 109288149Semasteextern int unw_set_fpreg(unw_cursor_t *, unw_regnum_t, unw_fpreg_t) LIBUNWIND_AVAIL; 110288149Semasteextern int unw_resume(unw_cursor_t *) LIBUNWIND_AVAIL; 111288149Semaste 112288149Semaste#ifdef __arm__ 113288149Semaste/* Save VFP registers in FSTMX format (instead of FSTMD). */ 114288149Semasteextern void unw_save_vfp_as_X(unw_cursor_t *) LIBUNWIND_AVAIL; 115288149Semaste#endif 116288149Semaste 117288149Semaste 118288149Semasteextern const char *unw_regname(unw_cursor_t *, unw_regnum_t) LIBUNWIND_AVAIL; 119288149Semasteextern int unw_get_proc_info(unw_cursor_t *, unw_proc_info_t *) LIBUNWIND_AVAIL; 120288149Semasteextern int unw_is_fpreg(unw_cursor_t *, unw_regnum_t) LIBUNWIND_AVAIL; 121288149Semasteextern int unw_is_signal_frame(unw_cursor_t *) LIBUNWIND_AVAIL; 122288149Semasteextern int unw_get_proc_name(unw_cursor_t *, char *, size_t, unw_word_t *) LIBUNWIND_AVAIL; 123288149Semaste//extern int unw_get_save_loc(unw_cursor_t*, int, unw_save_loc_t*); 124288149Semaste 125288149Semasteextern unw_addr_space_t unw_local_addr_space; 126288149Semaste 127288149Semaste#ifdef __cplusplus 128288149Semaste} 129288149Semaste#endif 130288149Semaste 131288149Semaste// architecture independent register numbers 132288149Semasteenum { 133288149Semaste UNW_REG_IP = -1, // instruction pointer 134288149Semaste UNW_REG_SP = -2, // stack pointer 135288149Semaste}; 136288149Semaste 137288149Semaste// 32-bit x86 registers 138288149Semasteenum { 139288149Semaste UNW_X86_EAX = 0, 140288149Semaste UNW_X86_ECX = 1, 141288149Semaste UNW_X86_EDX = 2, 142288149Semaste UNW_X86_EBX = 3, 143345018Sdim UNW_X86_EBP = 4, 144345018Sdim UNW_X86_ESP = 5, 145288149Semaste UNW_X86_ESI = 6, 146288149Semaste UNW_X86_EDI = 7 147288149Semaste}; 148288149Semaste 149288149Semaste// 64-bit x86_64 registers 150288149Semasteenum { 151288149Semaste UNW_X86_64_RAX = 0, 152288149Semaste UNW_X86_64_RDX = 1, 153288149Semaste UNW_X86_64_RCX = 2, 154288149Semaste UNW_X86_64_RBX = 3, 155288149Semaste UNW_X86_64_RSI = 4, 156288149Semaste UNW_X86_64_RDI = 5, 157288149Semaste UNW_X86_64_RBP = 6, 158288149Semaste UNW_X86_64_RSP = 7, 159288149Semaste UNW_X86_64_R8 = 8, 160288149Semaste UNW_X86_64_R9 = 9, 161288149Semaste UNW_X86_64_R10 = 10, 162288149Semaste UNW_X86_64_R11 = 11, 163288149Semaste UNW_X86_64_R12 = 12, 164288149Semaste UNW_X86_64_R13 = 13, 165288149Semaste UNW_X86_64_R14 = 14, 166345018Sdim UNW_X86_64_R15 = 15, 167345018Sdim UNW_X86_64_RIP = 16, 168345018Sdim UNW_X86_64_XMM0 = 17, 169345018Sdim UNW_X86_64_XMM1 = 18, 170345018Sdim UNW_X86_64_XMM2 = 19, 171345018Sdim UNW_X86_64_XMM3 = 20, 172345018Sdim UNW_X86_64_XMM4 = 21, 173345018Sdim UNW_X86_64_XMM5 = 22, 174345018Sdim UNW_X86_64_XMM6 = 23, 175345018Sdim UNW_X86_64_XMM7 = 24, 176345018Sdim UNW_X86_64_XMM8 = 25, 177345018Sdim UNW_X86_64_XMM9 = 26, 178345018Sdim UNW_X86_64_XMM10 = 27, 179345018Sdim UNW_X86_64_XMM11 = 28, 180345018Sdim UNW_X86_64_XMM12 = 29, 181345018Sdim UNW_X86_64_XMM13 = 30, 182345018Sdim UNW_X86_64_XMM14 = 31, 183345018Sdim UNW_X86_64_XMM15 = 32, 184288149Semaste}; 185288149Semaste 186288149Semaste 187288149Semaste// 32-bit ppc register numbers 188288149Semasteenum { 189288149Semaste UNW_PPC_R0 = 0, 190288149Semaste UNW_PPC_R1 = 1, 191288149Semaste UNW_PPC_R2 = 2, 192288149Semaste UNW_PPC_R3 = 3, 193288149Semaste UNW_PPC_R4 = 4, 194288149Semaste UNW_PPC_R5 = 5, 195288149Semaste UNW_PPC_R6 = 6, 196288149Semaste UNW_PPC_R7 = 7, 197288149Semaste UNW_PPC_R8 = 8, 198288149Semaste UNW_PPC_R9 = 9, 199288149Semaste UNW_PPC_R10 = 10, 200288149Semaste UNW_PPC_R11 = 11, 201288149Semaste UNW_PPC_R12 = 12, 202288149Semaste UNW_PPC_R13 = 13, 203288149Semaste UNW_PPC_R14 = 14, 204288149Semaste UNW_PPC_R15 = 15, 205288149Semaste UNW_PPC_R16 = 16, 206288149Semaste UNW_PPC_R17 = 17, 207288149Semaste UNW_PPC_R18 = 18, 208288149Semaste UNW_PPC_R19 = 19, 209288149Semaste UNW_PPC_R20 = 20, 210288149Semaste UNW_PPC_R21 = 21, 211288149Semaste UNW_PPC_R22 = 22, 212288149Semaste UNW_PPC_R23 = 23, 213288149Semaste UNW_PPC_R24 = 24, 214288149Semaste UNW_PPC_R25 = 25, 215288149Semaste UNW_PPC_R26 = 26, 216288149Semaste UNW_PPC_R27 = 27, 217288149Semaste UNW_PPC_R28 = 28, 218288149Semaste UNW_PPC_R29 = 29, 219288149Semaste UNW_PPC_R30 = 30, 220288149Semaste UNW_PPC_R31 = 31, 221288149Semaste UNW_PPC_F0 = 32, 222288149Semaste UNW_PPC_F1 = 33, 223288149Semaste UNW_PPC_F2 = 34, 224288149Semaste UNW_PPC_F3 = 35, 225288149Semaste UNW_PPC_F4 = 36, 226288149Semaste UNW_PPC_F5 = 37, 227288149Semaste UNW_PPC_F6 = 38, 228288149Semaste UNW_PPC_F7 = 39, 229288149Semaste UNW_PPC_F8 = 40, 230288149Semaste UNW_PPC_F9 = 41, 231288149Semaste UNW_PPC_F10 = 42, 232288149Semaste UNW_PPC_F11 = 43, 233288149Semaste UNW_PPC_F12 = 44, 234288149Semaste UNW_PPC_F13 = 45, 235288149Semaste UNW_PPC_F14 = 46, 236288149Semaste UNW_PPC_F15 = 47, 237288149Semaste UNW_PPC_F16 = 48, 238288149Semaste UNW_PPC_F17 = 49, 239288149Semaste UNW_PPC_F18 = 50, 240288149Semaste UNW_PPC_F19 = 51, 241288149Semaste UNW_PPC_F20 = 52, 242288149Semaste UNW_PPC_F21 = 53, 243288149Semaste UNW_PPC_F22 = 54, 244288149Semaste UNW_PPC_F23 = 55, 245288149Semaste UNW_PPC_F24 = 56, 246288149Semaste UNW_PPC_F25 = 57, 247288149Semaste UNW_PPC_F26 = 58, 248288149Semaste UNW_PPC_F27 = 59, 249288149Semaste UNW_PPC_F28 = 60, 250288149Semaste UNW_PPC_F29 = 61, 251288149Semaste UNW_PPC_F30 = 62, 252288149Semaste UNW_PPC_F31 = 63, 253288149Semaste UNW_PPC_MQ = 64, 254288149Semaste UNW_PPC_LR = 65, 255288149Semaste UNW_PPC_CTR = 66, 256288149Semaste UNW_PPC_AP = 67, 257288149Semaste UNW_PPC_CR0 = 68, 258288149Semaste UNW_PPC_CR1 = 69, 259288149Semaste UNW_PPC_CR2 = 70, 260288149Semaste UNW_PPC_CR3 = 71, 261288149Semaste UNW_PPC_CR4 = 72, 262288149Semaste UNW_PPC_CR5 = 73, 263288149Semaste UNW_PPC_CR6 = 74, 264288149Semaste UNW_PPC_CR7 = 75, 265288149Semaste UNW_PPC_XER = 76, 266288149Semaste UNW_PPC_V0 = 77, 267288149Semaste UNW_PPC_V1 = 78, 268288149Semaste UNW_PPC_V2 = 79, 269288149Semaste UNW_PPC_V3 = 80, 270288149Semaste UNW_PPC_V4 = 81, 271288149Semaste UNW_PPC_V5 = 82, 272288149Semaste UNW_PPC_V6 = 83, 273288149Semaste UNW_PPC_V7 = 84, 274288149Semaste UNW_PPC_V8 = 85, 275288149Semaste UNW_PPC_V9 = 86, 276288149Semaste UNW_PPC_V10 = 87, 277288149Semaste UNW_PPC_V11 = 88, 278288149Semaste UNW_PPC_V12 = 89, 279288149Semaste UNW_PPC_V13 = 90, 280288149Semaste UNW_PPC_V14 = 91, 281288149Semaste UNW_PPC_V15 = 92, 282288149Semaste UNW_PPC_V16 = 93, 283288149Semaste UNW_PPC_V17 = 94, 284288149Semaste UNW_PPC_V18 = 95, 285288149Semaste UNW_PPC_V19 = 96, 286288149Semaste UNW_PPC_V20 = 97, 287288149Semaste UNW_PPC_V21 = 98, 288288149Semaste UNW_PPC_V22 = 99, 289288149Semaste UNW_PPC_V23 = 100, 290288149Semaste UNW_PPC_V24 = 101, 291288149Semaste UNW_PPC_V25 = 102, 292288149Semaste UNW_PPC_V26 = 103, 293288149Semaste UNW_PPC_V27 = 104, 294288149Semaste UNW_PPC_V28 = 105, 295288149Semaste UNW_PPC_V29 = 106, 296288149Semaste UNW_PPC_V30 = 107, 297288149Semaste UNW_PPC_V31 = 108, 298288149Semaste UNW_PPC_VRSAVE = 109, 299288149Semaste UNW_PPC_VSCR = 110, 300288149Semaste UNW_PPC_SPE_ACC = 111, 301288149Semaste UNW_PPC_SPEFSCR = 112 302288149Semaste}; 303288149Semaste 304345018Sdim// 64-bit ppc register numbers 305345018Sdimenum { 306345018Sdim UNW_PPC64_R0 = 0, 307345018Sdim UNW_PPC64_R1 = 1, 308345018Sdim UNW_PPC64_R2 = 2, 309345018Sdim UNW_PPC64_R3 = 3, 310345018Sdim UNW_PPC64_R4 = 4, 311345018Sdim UNW_PPC64_R5 = 5, 312345018Sdim UNW_PPC64_R6 = 6, 313345018Sdim UNW_PPC64_R7 = 7, 314345018Sdim UNW_PPC64_R8 = 8, 315345018Sdim UNW_PPC64_R9 = 9, 316345018Sdim UNW_PPC64_R10 = 10, 317345018Sdim UNW_PPC64_R11 = 11, 318345018Sdim UNW_PPC64_R12 = 12, 319345018Sdim UNW_PPC64_R13 = 13, 320345018Sdim UNW_PPC64_R14 = 14, 321345018Sdim UNW_PPC64_R15 = 15, 322345018Sdim UNW_PPC64_R16 = 16, 323345018Sdim UNW_PPC64_R17 = 17, 324345018Sdim UNW_PPC64_R18 = 18, 325345018Sdim UNW_PPC64_R19 = 19, 326345018Sdim UNW_PPC64_R20 = 20, 327345018Sdim UNW_PPC64_R21 = 21, 328345018Sdim UNW_PPC64_R22 = 22, 329345018Sdim UNW_PPC64_R23 = 23, 330345018Sdim UNW_PPC64_R24 = 24, 331345018Sdim UNW_PPC64_R25 = 25, 332345018Sdim UNW_PPC64_R26 = 26, 333345018Sdim UNW_PPC64_R27 = 27, 334345018Sdim UNW_PPC64_R28 = 28, 335345018Sdim UNW_PPC64_R29 = 29, 336345018Sdim UNW_PPC64_R30 = 30, 337345018Sdim UNW_PPC64_R31 = 31, 338345018Sdim UNW_PPC64_F0 = 32, 339345018Sdim UNW_PPC64_F1 = 33, 340345018Sdim UNW_PPC64_F2 = 34, 341345018Sdim UNW_PPC64_F3 = 35, 342345018Sdim UNW_PPC64_F4 = 36, 343345018Sdim UNW_PPC64_F5 = 37, 344345018Sdim UNW_PPC64_F6 = 38, 345345018Sdim UNW_PPC64_F7 = 39, 346345018Sdim UNW_PPC64_F8 = 40, 347345018Sdim UNW_PPC64_F9 = 41, 348345018Sdim UNW_PPC64_F10 = 42, 349345018Sdim UNW_PPC64_F11 = 43, 350345018Sdim UNW_PPC64_F12 = 44, 351345018Sdim UNW_PPC64_F13 = 45, 352345018Sdim UNW_PPC64_F14 = 46, 353345018Sdim UNW_PPC64_F15 = 47, 354345018Sdim UNW_PPC64_F16 = 48, 355345018Sdim UNW_PPC64_F17 = 49, 356345018Sdim UNW_PPC64_F18 = 50, 357345018Sdim UNW_PPC64_F19 = 51, 358345018Sdim UNW_PPC64_F20 = 52, 359345018Sdim UNW_PPC64_F21 = 53, 360345018Sdim UNW_PPC64_F22 = 54, 361345018Sdim UNW_PPC64_F23 = 55, 362345018Sdim UNW_PPC64_F24 = 56, 363345018Sdim UNW_PPC64_F25 = 57, 364345018Sdim UNW_PPC64_F26 = 58, 365345018Sdim UNW_PPC64_F27 = 59, 366345018Sdim UNW_PPC64_F28 = 60, 367345018Sdim UNW_PPC64_F29 = 61, 368345018Sdim UNW_PPC64_F30 = 62, 369345018Sdim UNW_PPC64_F31 = 63, 370345018Sdim // 64: reserved 371345018Sdim UNW_PPC64_LR = 65, 372345018Sdim UNW_PPC64_CTR = 66, 373345018Sdim // 67: reserved 374345018Sdim UNW_PPC64_CR0 = 68, 375345018Sdim UNW_PPC64_CR1 = 69, 376345018Sdim UNW_PPC64_CR2 = 70, 377345018Sdim UNW_PPC64_CR3 = 71, 378345018Sdim UNW_PPC64_CR4 = 72, 379345018Sdim UNW_PPC64_CR5 = 73, 380345018Sdim UNW_PPC64_CR6 = 74, 381345018Sdim UNW_PPC64_CR7 = 75, 382345018Sdim UNW_PPC64_XER = 76, 383345018Sdim UNW_PPC64_V0 = 77, 384345018Sdim UNW_PPC64_V1 = 78, 385345018Sdim UNW_PPC64_V2 = 79, 386345018Sdim UNW_PPC64_V3 = 80, 387345018Sdim UNW_PPC64_V4 = 81, 388345018Sdim UNW_PPC64_V5 = 82, 389345018Sdim UNW_PPC64_V6 = 83, 390345018Sdim UNW_PPC64_V7 = 84, 391345018Sdim UNW_PPC64_V8 = 85, 392345018Sdim UNW_PPC64_V9 = 86, 393345018Sdim UNW_PPC64_V10 = 87, 394345018Sdim UNW_PPC64_V11 = 88, 395345018Sdim UNW_PPC64_V12 = 89, 396345018Sdim UNW_PPC64_V13 = 90, 397345018Sdim UNW_PPC64_V14 = 91, 398345018Sdim UNW_PPC64_V15 = 92, 399345018Sdim UNW_PPC64_V16 = 93, 400345018Sdim UNW_PPC64_V17 = 94, 401345018Sdim UNW_PPC64_V18 = 95, 402345018Sdim UNW_PPC64_V19 = 96, 403345018Sdim UNW_PPC64_V20 = 97, 404345018Sdim UNW_PPC64_V21 = 98, 405345018Sdim UNW_PPC64_V22 = 99, 406345018Sdim UNW_PPC64_V23 = 100, 407345018Sdim UNW_PPC64_V24 = 101, 408345018Sdim UNW_PPC64_V25 = 102, 409345018Sdim UNW_PPC64_V26 = 103, 410345018Sdim UNW_PPC64_V27 = 104, 411345018Sdim UNW_PPC64_V28 = 105, 412345018Sdim UNW_PPC64_V29 = 106, 413345018Sdim UNW_PPC64_V30 = 107, 414345018Sdim UNW_PPC64_V31 = 108, 415345018Sdim // 109, 111-113: OpenPOWER ELF V2 ABI: reserved 416345018Sdim // Borrowing VRSAVE number from PPC32. 417345018Sdim UNW_PPC64_VRSAVE = 109, 418345018Sdim UNW_PPC64_VSCR = 110, 419345018Sdim UNW_PPC64_TFHAR = 114, 420345018Sdim UNW_PPC64_TFIAR = 115, 421345018Sdim UNW_PPC64_TEXASR = 116, 422345018Sdim UNW_PPC64_VS0 = UNW_PPC64_F0, 423345018Sdim UNW_PPC64_VS1 = UNW_PPC64_F1, 424345018Sdim UNW_PPC64_VS2 = UNW_PPC64_F2, 425345018Sdim UNW_PPC64_VS3 = UNW_PPC64_F3, 426345018Sdim UNW_PPC64_VS4 = UNW_PPC64_F4, 427345018Sdim UNW_PPC64_VS5 = UNW_PPC64_F5, 428345018Sdim UNW_PPC64_VS6 = UNW_PPC64_F6, 429345018Sdim UNW_PPC64_VS7 = UNW_PPC64_F7, 430345018Sdim UNW_PPC64_VS8 = UNW_PPC64_F8, 431345018Sdim UNW_PPC64_VS9 = UNW_PPC64_F9, 432345018Sdim UNW_PPC64_VS10 = UNW_PPC64_F10, 433345018Sdim UNW_PPC64_VS11 = UNW_PPC64_F11, 434345018Sdim UNW_PPC64_VS12 = UNW_PPC64_F12, 435345018Sdim UNW_PPC64_VS13 = UNW_PPC64_F13, 436345018Sdim UNW_PPC64_VS14 = UNW_PPC64_F14, 437345018Sdim UNW_PPC64_VS15 = UNW_PPC64_F15, 438345018Sdim UNW_PPC64_VS16 = UNW_PPC64_F16, 439345018Sdim UNW_PPC64_VS17 = UNW_PPC64_F17, 440345018Sdim UNW_PPC64_VS18 = UNW_PPC64_F18, 441345018Sdim UNW_PPC64_VS19 = UNW_PPC64_F19, 442345018Sdim UNW_PPC64_VS20 = UNW_PPC64_F20, 443345018Sdim UNW_PPC64_VS21 = UNW_PPC64_F21, 444345018Sdim UNW_PPC64_VS22 = UNW_PPC64_F22, 445345018Sdim UNW_PPC64_VS23 = UNW_PPC64_F23, 446345018Sdim UNW_PPC64_VS24 = UNW_PPC64_F24, 447345018Sdim UNW_PPC64_VS25 = UNW_PPC64_F25, 448345018Sdim UNW_PPC64_VS26 = UNW_PPC64_F26, 449345018Sdim UNW_PPC64_VS27 = UNW_PPC64_F27, 450345018Sdim UNW_PPC64_VS28 = UNW_PPC64_F28, 451345018Sdim UNW_PPC64_VS29 = UNW_PPC64_F29, 452345018Sdim UNW_PPC64_VS30 = UNW_PPC64_F30, 453345018Sdim UNW_PPC64_VS31 = UNW_PPC64_F31, 454345018Sdim UNW_PPC64_VS32 = UNW_PPC64_V0, 455345018Sdim UNW_PPC64_VS33 = UNW_PPC64_V1, 456345018Sdim UNW_PPC64_VS34 = UNW_PPC64_V2, 457345018Sdim UNW_PPC64_VS35 = UNW_PPC64_V3, 458345018Sdim UNW_PPC64_VS36 = UNW_PPC64_V4, 459345018Sdim UNW_PPC64_VS37 = UNW_PPC64_V5, 460345018Sdim UNW_PPC64_VS38 = UNW_PPC64_V6, 461345018Sdim UNW_PPC64_VS39 = UNW_PPC64_V7, 462345018Sdim UNW_PPC64_VS40 = UNW_PPC64_V8, 463345018Sdim UNW_PPC64_VS41 = UNW_PPC64_V9, 464345018Sdim UNW_PPC64_VS42 = UNW_PPC64_V10, 465345018Sdim UNW_PPC64_VS43 = UNW_PPC64_V11, 466345018Sdim UNW_PPC64_VS44 = UNW_PPC64_V12, 467345018Sdim UNW_PPC64_VS45 = UNW_PPC64_V13, 468345018Sdim UNW_PPC64_VS46 = UNW_PPC64_V14, 469345018Sdim UNW_PPC64_VS47 = UNW_PPC64_V15, 470345018Sdim UNW_PPC64_VS48 = UNW_PPC64_V16, 471345018Sdim UNW_PPC64_VS49 = UNW_PPC64_V17, 472345018Sdim UNW_PPC64_VS50 = UNW_PPC64_V18, 473345018Sdim UNW_PPC64_VS51 = UNW_PPC64_V19, 474345018Sdim UNW_PPC64_VS52 = UNW_PPC64_V20, 475345018Sdim UNW_PPC64_VS53 = UNW_PPC64_V21, 476345018Sdim UNW_PPC64_VS54 = UNW_PPC64_V22, 477345018Sdim UNW_PPC64_VS55 = UNW_PPC64_V23, 478345018Sdim UNW_PPC64_VS56 = UNW_PPC64_V24, 479345018Sdim UNW_PPC64_VS57 = UNW_PPC64_V25, 480345018Sdim UNW_PPC64_VS58 = UNW_PPC64_V26, 481345018Sdim UNW_PPC64_VS59 = UNW_PPC64_V27, 482345018Sdim UNW_PPC64_VS60 = UNW_PPC64_V28, 483345018Sdim UNW_PPC64_VS61 = UNW_PPC64_V29, 484345018Sdim UNW_PPC64_VS62 = UNW_PPC64_V30, 485345018Sdim UNW_PPC64_VS63 = UNW_PPC64_V31 486345018Sdim}; 487345018Sdim 488288149Semaste// 64-bit ARM64 registers 489288149Semasteenum { 490288149Semaste UNW_ARM64_X0 = 0, 491288149Semaste UNW_ARM64_X1 = 1, 492288149Semaste UNW_ARM64_X2 = 2, 493288149Semaste UNW_ARM64_X3 = 3, 494288149Semaste UNW_ARM64_X4 = 4, 495288149Semaste UNW_ARM64_X5 = 5, 496288149Semaste UNW_ARM64_X6 = 6, 497288149Semaste UNW_ARM64_X7 = 7, 498288149Semaste UNW_ARM64_X8 = 8, 499288149Semaste UNW_ARM64_X9 = 9, 500288149Semaste UNW_ARM64_X10 = 10, 501288149Semaste UNW_ARM64_X11 = 11, 502288149Semaste UNW_ARM64_X12 = 12, 503288149Semaste UNW_ARM64_X13 = 13, 504288149Semaste UNW_ARM64_X14 = 14, 505288149Semaste UNW_ARM64_X15 = 15, 506288149Semaste UNW_ARM64_X16 = 16, 507288149Semaste UNW_ARM64_X17 = 17, 508288149Semaste UNW_ARM64_X18 = 18, 509288149Semaste UNW_ARM64_X19 = 19, 510288149Semaste UNW_ARM64_X20 = 20, 511288149Semaste UNW_ARM64_X21 = 21, 512288149Semaste UNW_ARM64_X22 = 22, 513288149Semaste UNW_ARM64_X23 = 23, 514288149Semaste UNW_ARM64_X24 = 24, 515288149Semaste UNW_ARM64_X25 = 25, 516288149Semaste UNW_ARM64_X26 = 26, 517288149Semaste UNW_ARM64_X27 = 27, 518288149Semaste UNW_ARM64_X28 = 28, 519288149Semaste UNW_ARM64_X29 = 29, 520288149Semaste UNW_ARM64_FP = 29, 521288149Semaste UNW_ARM64_X30 = 30, 522288149Semaste UNW_ARM64_LR = 30, 523288149Semaste UNW_ARM64_X31 = 31, 524288149Semaste UNW_ARM64_SP = 31, 525288149Semaste // reserved block 526345018Sdim UNW_ARM64_RA_SIGN_STATE = 34, 527345018Sdim // reserved block 528288149Semaste UNW_ARM64_D0 = 64, 529288149Semaste UNW_ARM64_D1 = 65, 530288149Semaste UNW_ARM64_D2 = 66, 531288149Semaste UNW_ARM64_D3 = 67, 532288149Semaste UNW_ARM64_D4 = 68, 533288149Semaste UNW_ARM64_D5 = 69, 534288149Semaste UNW_ARM64_D6 = 70, 535288149Semaste UNW_ARM64_D7 = 71, 536288149Semaste UNW_ARM64_D8 = 72, 537288149Semaste UNW_ARM64_D9 = 73, 538288149Semaste UNW_ARM64_D10 = 74, 539288149Semaste UNW_ARM64_D11 = 75, 540288149Semaste UNW_ARM64_D12 = 76, 541288149Semaste UNW_ARM64_D13 = 77, 542288149Semaste UNW_ARM64_D14 = 78, 543288149Semaste UNW_ARM64_D15 = 79, 544288149Semaste UNW_ARM64_D16 = 80, 545288149Semaste UNW_ARM64_D17 = 81, 546288149Semaste UNW_ARM64_D18 = 82, 547288149Semaste UNW_ARM64_D19 = 83, 548288149Semaste UNW_ARM64_D20 = 84, 549288149Semaste UNW_ARM64_D21 = 85, 550288149Semaste UNW_ARM64_D22 = 86, 551288149Semaste UNW_ARM64_D23 = 87, 552288149Semaste UNW_ARM64_D24 = 88, 553288149Semaste UNW_ARM64_D25 = 89, 554288149Semaste UNW_ARM64_D26 = 90, 555288149Semaste UNW_ARM64_D27 = 91, 556288149Semaste UNW_ARM64_D28 = 92, 557288149Semaste UNW_ARM64_D29 = 93, 558288149Semaste UNW_ARM64_D30 = 94, 559288149Semaste UNW_ARM64_D31 = 95, 560288149Semaste}; 561288149Semaste 562288149Semaste// 32-bit ARM registers. Numbers match DWARF for ARM spec #3.1 Table 1. 563288149Semaste// Naming scheme uses recommendations given in Note 4 for VFP-v2 and VFP-v3. 564288149Semaste// In this scheme, even though the 64-bit floating point registers D0-D31 565288149Semaste// overlap physically with the 32-bit floating pointer registers S0-S31, 566288149Semaste// they are given a non-overlapping range of register numbers. 567288149Semaste// 568288149Semaste// Commented out ranges are not preserved during unwinding. 569288149Semasteenum { 570288149Semaste UNW_ARM_R0 = 0, 571288149Semaste UNW_ARM_R1 = 1, 572288149Semaste UNW_ARM_R2 = 2, 573288149Semaste UNW_ARM_R3 = 3, 574288149Semaste UNW_ARM_R4 = 4, 575288149Semaste UNW_ARM_R5 = 5, 576288149Semaste UNW_ARM_R6 = 6, 577288149Semaste UNW_ARM_R7 = 7, 578288149Semaste UNW_ARM_R8 = 8, 579288149Semaste UNW_ARM_R9 = 9, 580288149Semaste UNW_ARM_R10 = 10, 581288149Semaste UNW_ARM_R11 = 11, 582288149Semaste UNW_ARM_R12 = 12, 583288149Semaste UNW_ARM_SP = 13, // Logical alias for UNW_REG_SP 584288149Semaste UNW_ARM_R13 = 13, 585288149Semaste UNW_ARM_LR = 14, 586288149Semaste UNW_ARM_R14 = 14, 587288149Semaste UNW_ARM_IP = 15, // Logical alias for UNW_REG_IP 588288149Semaste UNW_ARM_R15 = 15, 589288149Semaste // 16-63 -- OBSOLETE. Used in VFP1 to represent both S0-S31 and D0-D31. 590288149Semaste UNW_ARM_S0 = 64, 591288149Semaste UNW_ARM_S1 = 65, 592288149Semaste UNW_ARM_S2 = 66, 593288149Semaste UNW_ARM_S3 = 67, 594288149Semaste UNW_ARM_S4 = 68, 595288149Semaste UNW_ARM_S5 = 69, 596288149Semaste UNW_ARM_S6 = 70, 597288149Semaste UNW_ARM_S7 = 71, 598288149Semaste UNW_ARM_S8 = 72, 599288149Semaste UNW_ARM_S9 = 73, 600288149Semaste UNW_ARM_S10 = 74, 601288149Semaste UNW_ARM_S11 = 75, 602288149Semaste UNW_ARM_S12 = 76, 603288149Semaste UNW_ARM_S13 = 77, 604288149Semaste UNW_ARM_S14 = 78, 605288149Semaste UNW_ARM_S15 = 79, 606288149Semaste UNW_ARM_S16 = 80, 607288149Semaste UNW_ARM_S17 = 81, 608288149Semaste UNW_ARM_S18 = 82, 609288149Semaste UNW_ARM_S19 = 83, 610288149Semaste UNW_ARM_S20 = 84, 611288149Semaste UNW_ARM_S21 = 85, 612288149Semaste UNW_ARM_S22 = 86, 613288149Semaste UNW_ARM_S23 = 87, 614288149Semaste UNW_ARM_S24 = 88, 615288149Semaste UNW_ARM_S25 = 89, 616288149Semaste UNW_ARM_S26 = 90, 617288149Semaste UNW_ARM_S27 = 91, 618288149Semaste UNW_ARM_S28 = 92, 619288149Semaste UNW_ARM_S29 = 93, 620288149Semaste UNW_ARM_S30 = 94, 621288149Semaste UNW_ARM_S31 = 95, 622288149Semaste // 96-103 -- OBSOLETE. F0-F7. Used by the FPA system. Superseded by VFP. 623288149Semaste // 104-111 -- wCGR0-wCGR7, ACC0-ACC7 (Intel wireless MMX) 624288149Semaste UNW_ARM_WR0 = 112, 625288149Semaste UNW_ARM_WR1 = 113, 626288149Semaste UNW_ARM_WR2 = 114, 627288149Semaste UNW_ARM_WR3 = 115, 628288149Semaste UNW_ARM_WR4 = 116, 629288149Semaste UNW_ARM_WR5 = 117, 630288149Semaste UNW_ARM_WR6 = 118, 631288149Semaste UNW_ARM_WR7 = 119, 632288149Semaste UNW_ARM_WR8 = 120, 633288149Semaste UNW_ARM_WR9 = 121, 634288149Semaste UNW_ARM_WR10 = 122, 635288149Semaste UNW_ARM_WR11 = 123, 636288149Semaste UNW_ARM_WR12 = 124, 637288149Semaste UNW_ARM_WR13 = 125, 638288149Semaste UNW_ARM_WR14 = 126, 639288149Semaste UNW_ARM_WR15 = 127, 640288149Semaste // 128-133 -- SPSR, SPSR_{FIQ|IRQ|ABT|UND|SVC} 641288149Semaste // 134-143 -- Reserved 642288149Semaste // 144-150 -- R8_USR-R14_USR 643288149Semaste // 151-157 -- R8_FIQ-R14_FIQ 644288149Semaste // 158-159 -- R13_IRQ-R14_IRQ 645288149Semaste // 160-161 -- R13_ABT-R14_ABT 646288149Semaste // 162-163 -- R13_UND-R14_UND 647288149Semaste // 164-165 -- R13_SVC-R14_SVC 648288149Semaste // 166-191 -- Reserved 649288149Semaste UNW_ARM_WC0 = 192, 650288149Semaste UNW_ARM_WC1 = 193, 651288149Semaste UNW_ARM_WC2 = 194, 652288149Semaste UNW_ARM_WC3 = 195, 653288149Semaste // 196-199 -- wC4-wC7 (Intel wireless MMX control) 654288149Semaste // 200-255 -- Reserved 655288149Semaste UNW_ARM_D0 = 256, 656288149Semaste UNW_ARM_D1 = 257, 657288149Semaste UNW_ARM_D2 = 258, 658288149Semaste UNW_ARM_D3 = 259, 659288149Semaste UNW_ARM_D4 = 260, 660288149Semaste UNW_ARM_D5 = 261, 661288149Semaste UNW_ARM_D6 = 262, 662288149Semaste UNW_ARM_D7 = 263, 663288149Semaste UNW_ARM_D8 = 264, 664288149Semaste UNW_ARM_D9 = 265, 665288149Semaste UNW_ARM_D10 = 266, 666288149Semaste UNW_ARM_D11 = 267, 667288149Semaste UNW_ARM_D12 = 268, 668288149Semaste UNW_ARM_D13 = 269, 669288149Semaste UNW_ARM_D14 = 270, 670288149Semaste UNW_ARM_D15 = 271, 671288149Semaste UNW_ARM_D16 = 272, 672288149Semaste UNW_ARM_D17 = 273, 673288149Semaste UNW_ARM_D18 = 274, 674288149Semaste UNW_ARM_D19 = 275, 675288149Semaste UNW_ARM_D20 = 276, 676288149Semaste UNW_ARM_D21 = 277, 677288149Semaste UNW_ARM_D22 = 278, 678288149Semaste UNW_ARM_D23 = 279, 679288149Semaste UNW_ARM_D24 = 280, 680288149Semaste UNW_ARM_D25 = 281, 681288149Semaste UNW_ARM_D26 = 282, 682288149Semaste UNW_ARM_D27 = 283, 683288149Semaste UNW_ARM_D28 = 284, 684288149Semaste UNW_ARM_D29 = 285, 685288149Semaste UNW_ARM_D30 = 286, 686288149Semaste UNW_ARM_D31 = 287, 687288149Semaste // 288-319 -- Reserved for VFP/Neon 688288149Semaste // 320-8191 -- Reserved 689288149Semaste // 8192-16383 -- Unspecified vendor co-processor register. 690288149Semaste}; 691288149Semaste 692288149Semaste// OpenRISC1000 register numbers 693288149Semasteenum { 694288149Semaste UNW_OR1K_R0 = 0, 695288149Semaste UNW_OR1K_R1 = 1, 696288149Semaste UNW_OR1K_R2 = 2, 697288149Semaste UNW_OR1K_R3 = 3, 698288149Semaste UNW_OR1K_R4 = 4, 699288149Semaste UNW_OR1K_R5 = 5, 700288149Semaste UNW_OR1K_R6 = 6, 701288149Semaste UNW_OR1K_R7 = 7, 702288149Semaste UNW_OR1K_R8 = 8, 703288149Semaste UNW_OR1K_R9 = 9, 704288149Semaste UNW_OR1K_R10 = 10, 705288149Semaste UNW_OR1K_R11 = 11, 706288149Semaste UNW_OR1K_R12 = 12, 707288149Semaste UNW_OR1K_R13 = 13, 708288149Semaste UNW_OR1K_R14 = 14, 709288149Semaste UNW_OR1K_R15 = 15, 710288149Semaste UNW_OR1K_R16 = 16, 711288149Semaste UNW_OR1K_R17 = 17, 712288149Semaste UNW_OR1K_R18 = 18, 713288149Semaste UNW_OR1K_R19 = 19, 714288149Semaste UNW_OR1K_R20 = 20, 715288149Semaste UNW_OR1K_R21 = 21, 716288149Semaste UNW_OR1K_R22 = 22, 717288149Semaste UNW_OR1K_R23 = 23, 718288149Semaste UNW_OR1K_R24 = 24, 719288149Semaste UNW_OR1K_R25 = 25, 720288149Semaste UNW_OR1K_R26 = 26, 721288149Semaste UNW_OR1K_R27 = 27, 722288149Semaste UNW_OR1K_R28 = 28, 723288149Semaste UNW_OR1K_R29 = 29, 724288149Semaste UNW_OR1K_R30 = 30, 725288149Semaste UNW_OR1K_R31 = 31, 726345018Sdim UNW_OR1K_EPCR = 32, 727288149Semaste}; 728288149Semaste 729331244Sjhb// MIPS registers 730331244Sjhbenum { 731331244Sjhb UNW_MIPS_R0 = 0, 732331244Sjhb UNW_MIPS_R1 = 1, 733331244Sjhb UNW_MIPS_R2 = 2, 734331244Sjhb UNW_MIPS_R3 = 3, 735331244Sjhb UNW_MIPS_R4 = 4, 736331244Sjhb UNW_MIPS_R5 = 5, 737331244Sjhb UNW_MIPS_R6 = 6, 738331244Sjhb UNW_MIPS_R7 = 7, 739331244Sjhb UNW_MIPS_R8 = 8, 740331244Sjhb UNW_MIPS_R9 = 9, 741331244Sjhb UNW_MIPS_R10 = 10, 742331244Sjhb UNW_MIPS_R11 = 11, 743331244Sjhb UNW_MIPS_R12 = 12, 744331244Sjhb UNW_MIPS_R13 = 13, 745331244Sjhb UNW_MIPS_R14 = 14, 746331244Sjhb UNW_MIPS_R15 = 15, 747331244Sjhb UNW_MIPS_R16 = 16, 748331244Sjhb UNW_MIPS_R17 = 17, 749331244Sjhb UNW_MIPS_R18 = 18, 750331244Sjhb UNW_MIPS_R19 = 19, 751331244Sjhb UNW_MIPS_R20 = 20, 752331244Sjhb UNW_MIPS_R21 = 21, 753331244Sjhb UNW_MIPS_R22 = 22, 754331244Sjhb UNW_MIPS_R23 = 23, 755331244Sjhb UNW_MIPS_R24 = 24, 756331244Sjhb UNW_MIPS_R25 = 25, 757331244Sjhb UNW_MIPS_R26 = 26, 758331244Sjhb UNW_MIPS_R27 = 27, 759331244Sjhb UNW_MIPS_R28 = 28, 760331244Sjhb UNW_MIPS_R29 = 29, 761331244Sjhb UNW_MIPS_R30 = 30, 762331244Sjhb UNW_MIPS_R31 = 31, 763331244Sjhb UNW_MIPS_F0 = 32, 764331244Sjhb UNW_MIPS_F1 = 33, 765331244Sjhb UNW_MIPS_F2 = 34, 766331244Sjhb UNW_MIPS_F3 = 35, 767331244Sjhb UNW_MIPS_F4 = 36, 768331244Sjhb UNW_MIPS_F5 = 37, 769331244Sjhb UNW_MIPS_F6 = 38, 770331244Sjhb UNW_MIPS_F7 = 39, 771331244Sjhb UNW_MIPS_F8 = 40, 772331244Sjhb UNW_MIPS_F9 = 41, 773331244Sjhb UNW_MIPS_F10 = 42, 774331244Sjhb UNW_MIPS_F11 = 43, 775331244Sjhb UNW_MIPS_F12 = 44, 776331244Sjhb UNW_MIPS_F13 = 45, 777331244Sjhb UNW_MIPS_F14 = 46, 778331244Sjhb UNW_MIPS_F15 = 47, 779331244Sjhb UNW_MIPS_F16 = 48, 780331244Sjhb UNW_MIPS_F17 = 49, 781331244Sjhb UNW_MIPS_F18 = 50, 782331244Sjhb UNW_MIPS_F19 = 51, 783331244Sjhb UNW_MIPS_F20 = 52, 784331244Sjhb UNW_MIPS_F21 = 53, 785331244Sjhb UNW_MIPS_F22 = 54, 786331244Sjhb UNW_MIPS_F23 = 55, 787331244Sjhb UNW_MIPS_F24 = 56, 788331244Sjhb UNW_MIPS_F25 = 57, 789331244Sjhb UNW_MIPS_F26 = 58, 790331244Sjhb UNW_MIPS_F27 = 59, 791331244Sjhb UNW_MIPS_F28 = 60, 792331244Sjhb UNW_MIPS_F29 = 61, 793331244Sjhb UNW_MIPS_F30 = 62, 794331244Sjhb UNW_MIPS_F31 = 63, 795331244Sjhb UNW_MIPS_HI = 64, 796331244Sjhb UNW_MIPS_LO = 65, 797331244Sjhb}; 798331244Sjhb 799345018Sdim// SPARC registers 800345018Sdimenum { 801345018Sdim UNW_SPARC_G0 = 0, 802345018Sdim UNW_SPARC_G1 = 1, 803345018Sdim UNW_SPARC_G2 = 2, 804345018Sdim UNW_SPARC_G3 = 3, 805345018Sdim UNW_SPARC_G4 = 4, 806345018Sdim UNW_SPARC_G5 = 5, 807345018Sdim UNW_SPARC_G6 = 6, 808345018Sdim UNW_SPARC_G7 = 7, 809345018Sdim UNW_SPARC_O0 = 8, 810345018Sdim UNW_SPARC_O1 = 9, 811345018Sdim UNW_SPARC_O2 = 10, 812345018Sdim UNW_SPARC_O3 = 11, 813345018Sdim UNW_SPARC_O4 = 12, 814345018Sdim UNW_SPARC_O5 = 13, 815345018Sdim UNW_SPARC_O6 = 14, 816345018Sdim UNW_SPARC_O7 = 15, 817345018Sdim UNW_SPARC_L0 = 16, 818345018Sdim UNW_SPARC_L1 = 17, 819345018Sdim UNW_SPARC_L2 = 18, 820345018Sdim UNW_SPARC_L3 = 19, 821345018Sdim UNW_SPARC_L4 = 20, 822345018Sdim UNW_SPARC_L5 = 21, 823345018Sdim UNW_SPARC_L6 = 22, 824345018Sdim UNW_SPARC_L7 = 23, 825345018Sdim UNW_SPARC_I0 = 24, 826345018Sdim UNW_SPARC_I1 = 25, 827345018Sdim UNW_SPARC_I2 = 26, 828345018Sdim UNW_SPARC_I3 = 27, 829345018Sdim UNW_SPARC_I4 = 28, 830345018Sdim UNW_SPARC_I5 = 29, 831345018Sdim UNW_SPARC_I6 = 30, 832345018Sdim UNW_SPARC_I7 = 31, 833345018Sdim}; 834345018Sdim 835360784Sdim// RISC-V registers. These match the DWARF register numbers defined by section 836360784Sdim// 4 of the RISC-V ELF psABI specification, which can be found at: 837360784Sdim// 838360784Sdim// https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md 839360784Sdimenum { 840360784Sdim UNW_RISCV_X0 = 0, 841360784Sdim UNW_RISCV_X1 = 1, 842360784Sdim UNW_RISCV_X2 = 2, 843360784Sdim UNW_RISCV_X3 = 3, 844360784Sdim UNW_RISCV_X4 = 4, 845360784Sdim UNW_RISCV_X5 = 5, 846360784Sdim UNW_RISCV_X6 = 6, 847360784Sdim UNW_RISCV_X7 = 7, 848360784Sdim UNW_RISCV_X8 = 8, 849360784Sdim UNW_RISCV_X9 = 9, 850360784Sdim UNW_RISCV_X10 = 10, 851360784Sdim UNW_RISCV_X11 = 11, 852360784Sdim UNW_RISCV_X12 = 12, 853360784Sdim UNW_RISCV_X13 = 13, 854360784Sdim UNW_RISCV_X14 = 14, 855360784Sdim UNW_RISCV_X15 = 15, 856360784Sdim UNW_RISCV_X16 = 16, 857360784Sdim UNW_RISCV_X17 = 17, 858360784Sdim UNW_RISCV_X18 = 18, 859360784Sdim UNW_RISCV_X19 = 19, 860360784Sdim UNW_RISCV_X20 = 20, 861360784Sdim UNW_RISCV_X21 = 21, 862360784Sdim UNW_RISCV_X22 = 22, 863360784Sdim UNW_RISCV_X23 = 23, 864360784Sdim UNW_RISCV_X24 = 24, 865360784Sdim UNW_RISCV_X25 = 25, 866360784Sdim UNW_RISCV_X26 = 26, 867360784Sdim UNW_RISCV_X27 = 27, 868360784Sdim UNW_RISCV_X28 = 28, 869360784Sdim UNW_RISCV_X29 = 29, 870360784Sdim UNW_RISCV_X30 = 30, 871360784Sdim UNW_RISCV_X31 = 31, 872360784Sdim UNW_RISCV_F0 = 32, 873360784Sdim UNW_RISCV_F1 = 33, 874360784Sdim UNW_RISCV_F2 = 34, 875360784Sdim UNW_RISCV_F3 = 35, 876360784Sdim UNW_RISCV_F4 = 36, 877360784Sdim UNW_RISCV_F5 = 37, 878360784Sdim UNW_RISCV_F6 = 38, 879360784Sdim UNW_RISCV_F7 = 39, 880360784Sdim UNW_RISCV_F8 = 40, 881360784Sdim UNW_RISCV_F9 = 41, 882360784Sdim UNW_RISCV_F10 = 42, 883360784Sdim UNW_RISCV_F11 = 43, 884360784Sdim UNW_RISCV_F12 = 44, 885360784Sdim UNW_RISCV_F13 = 45, 886360784Sdim UNW_RISCV_F14 = 46, 887360784Sdim UNW_RISCV_F15 = 47, 888360784Sdim UNW_RISCV_F16 = 48, 889360784Sdim UNW_RISCV_F17 = 49, 890360784Sdim UNW_RISCV_F18 = 50, 891360784Sdim UNW_RISCV_F19 = 51, 892360784Sdim UNW_RISCV_F20 = 52, 893360784Sdim UNW_RISCV_F21 = 53, 894360784Sdim UNW_RISCV_F22 = 54, 895360784Sdim UNW_RISCV_F23 = 55, 896360784Sdim UNW_RISCV_F24 = 56, 897360784Sdim UNW_RISCV_F25 = 57, 898360784Sdim UNW_RISCV_F26 = 58, 899360784Sdim UNW_RISCV_F27 = 59, 900360784Sdim UNW_RISCV_F28 = 60, 901360784Sdim UNW_RISCV_F29 = 61, 902360784Sdim UNW_RISCV_F30 = 62, 903360784Sdim UNW_RISCV_F31 = 63, 904360784Sdim}; 905360784Sdim 906288149Semaste#endif 907