1353358Sdim//===-- clear_cache.c - Implement __clear_cache ---------------------------===// 2353358Sdim// 3353358Sdim// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4353358Sdim// See https://llvm.org/LICENSE.txt for license information. 5353358Sdim// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6353358Sdim// 7353358Sdim//===----------------------------------------------------------------------===// 8276789Sdim 9276789Sdim#include "int_lib.h" 10327952Sdim#include <assert.h> 11280333Sdim#include <stddef.h> 12276789Sdim 13276789Sdim#if __APPLE__ 14353358Sdim#include <libkern/OSCacheControl.h> 15276789Sdim#endif 16309124Sdim 17309124Sdim#if defined(_WIN32) 18353358Sdim// Forward declare Win32 APIs since the GCC mode driver does not handle the 19353358Sdim// newer SDKs as well as needed. 20309124Sdimuint32_t FlushInstructionCache(uintptr_t hProcess, void *lpBaseAddress, 21309124Sdim uintptr_t dwSize); 22309124Sdimuintptr_t GetCurrentProcess(void); 23309124Sdim#endif 24309124Sdim 25327952Sdim#if defined(__FreeBSD__) && defined(__arm__) 26360784Sdim// clang-format off 27360784Sdim#include <sys/types.h> 28353358Sdim#include <machine/sysarch.h> 29360784Sdim// clang-format on 30277089Sdim#endif 31277089Sdim 32276789Sdim#if defined(__NetBSD__) && defined(__arm__) 33353358Sdim#include <machine/sysarch.h> 34276789Sdim#endif 35276789Sdim 36328381Sdim#if defined(__OpenBSD__) && defined(__mips__) 37360784Sdim// clang-format off 38360784Sdim#include <sys/types.h> 39353358Sdim#include <machine/sysarch.h> 40360784Sdim// clang-format on 41328381Sdim#endif 42328381Sdim 43327952Sdim#if defined(__linux__) && defined(__mips__) 44353358Sdim#include <sys/cachectl.h> 45353358Sdim#include <sys/syscall.h> 46353358Sdim#include <unistd.h> 47276789Sdim#endif 48276789Sdim 49353358Sdim// The compiler generates calls to __clear_cache() when creating 50353358Sdim// trampoline functions on the stack for use with nested functions. 51353358Sdim// It is expected to invalidate the instruction cache for the 52353358Sdim// specified range. 53276789Sdim 54276789Sdimvoid __clear_cache(void *start, void *end) { 55321369Sdim#if __i386__ || __x86_64__ || defined(_M_IX86) || defined(_M_X64) 56353358Sdim// Intel processors have a unified instruction and data cache 57353358Sdim// so there is nothing to do 58341825Sdim#elif defined(_WIN32) && (defined(__arm__) || defined(__aarch64__)) 59353358Sdim FlushInstructionCache(GetCurrentProcess(), start, end - start); 60276789Sdim#elif defined(__arm__) && !defined(__APPLE__) 61353358Sdim#if defined(__FreeBSD__) || defined(__NetBSD__) 62353358Sdim struct arm_sync_icache_args arg; 63276789Sdim 64353358Sdim arg.addr = (uintptr_t)start; 65353358Sdim arg.len = (uintptr_t)end - (uintptr_t)start; 66276789Sdim 67353358Sdim sysarch(ARM_SYNC_ICACHE, &arg); 68353358Sdim#elif defined(__linux__) 69353358Sdim// We used to include asm/unistd.h for the __ARM_NR_cacheflush define, but 70353358Sdim// it also brought many other unused defines, as well as a dependency on 71353358Sdim// kernel headers to be installed. 72353358Sdim// 73353358Sdim// This value is stable at least since Linux 3.13 and should remain so for 74353358Sdim// compatibility reasons, warranting it's re-definition here. 75353358Sdim#define __ARM_NR_cacheflush 0x0f0002 76353358Sdim register int start_reg __asm("r0") = (int)(intptr_t)start; 77353358Sdim const register int end_reg __asm("r1") = (int)(intptr_t)end; 78353358Sdim const register int flags __asm("r2") = 0; 79353358Sdim const register int syscall_nr __asm("r7") = __ARM_NR_cacheflush; 80353358Sdim __asm __volatile("svc 0x0" 81353358Sdim : "=r"(start_reg) 82353358Sdim : "r"(syscall_nr), "r"(start_reg), "r"(end_reg), "r"(flags)); 83353358Sdim assert(start_reg == 0 && "Cache flush syscall failed."); 84353358Sdim#else 85353358Sdim compilerrt_abort(); 86353358Sdim#endif 87327952Sdim#elif defined(__linux__) && defined(__mips__) 88353358Sdim const uintptr_t start_int = (uintptr_t)start; 89353358Sdim const uintptr_t end_int = (uintptr_t)end; 90353358Sdim syscall(__NR_cacheflush, start, (end_int - start_int), BCACHE); 91328381Sdim#elif defined(__mips__) && defined(__OpenBSD__) 92328381Sdim cacheflush(start, (uintptr_t)end - (uintptr_t)start, BCACHE); 93276789Sdim#elif defined(__aarch64__) && !defined(__APPLE__) 94353358Sdim uint64_t xstart = (uint64_t)(uintptr_t)start; 95353358Sdim uint64_t xend = (uint64_t)(uintptr_t)end; 96276789Sdim 97360784Sdim // Get Cache Type Info. 98360784Sdim static uint64_t ctr_el0 = 0; 99360784Sdim if (ctr_el0 == 0) 100360784Sdim __asm __volatile("mrs %0, ctr_el0" : "=r"(ctr_el0)); 101276789Sdim 102360784Sdim // The DC and IC instructions must use 64-bit registers so we don't use 103353358Sdim // uintptr_t in case this runs in an IPL32 environment. 104360784Sdim uint64_t addr; 105360784Sdim 106360784Sdim // If CTR_EL0.IDC is set, data cache cleaning to the point of unification 107360784Sdim // is not required for instruction to data coherence. 108360784Sdim if (((ctr_el0 >> 28) & 0x1) == 0x0) { 109360784Sdim const size_t dcache_line_size = 4 << ((ctr_el0 >> 16) & 15); 110360784Sdim for (addr = xstart & ~(dcache_line_size - 1); addr < xend; 111360784Sdim addr += dcache_line_size) 112360784Sdim __asm __volatile("dc cvau, %0" ::"r"(addr)); 113360784Sdim } 114276789Sdim __asm __volatile("dsb ish"); 115276789Sdim 116360784Sdim // If CTR_EL0.DIC is set, instruction cache invalidation to the point of 117360784Sdim // unification is not required for instruction to data coherence. 118360784Sdim if (((ctr_el0 >> 29) & 0x1) == 0x0) { 119360784Sdim const size_t icache_line_size = 4 << ((ctr_el0 >> 0) & 15); 120360784Sdim for (addr = xstart & ~(icache_line_size - 1); addr < xend; 121360784Sdim addr += icache_line_size) 122360784Sdim __asm __volatile("ic ivau, %0" ::"r"(addr)); 123360784Sdim } 124276789Sdim __asm __volatile("isb sy"); 125353358Sdim#elif defined(__powerpc64__) 126327952Sdim const size_t line_size = 32; 127327952Sdim const size_t len = (uintptr_t)end - (uintptr_t)start; 128327952Sdim 129327952Sdim const uintptr_t mask = ~(line_size - 1); 130327952Sdim const uintptr_t start_line = ((uintptr_t)start) & mask; 131327952Sdim const uintptr_t end_line = ((uintptr_t)start + len + line_size - 1) & mask; 132327952Sdim 133327952Sdim for (uintptr_t line = start_line; line < end_line; line += line_size) 134327952Sdim __asm__ volatile("dcbf 0, %0" : : "r"(line)); 135327952Sdim __asm__ volatile("sync"); 136327952Sdim 137327952Sdim for (uintptr_t line = start_line; line < end_line; line += line_size) 138327952Sdim __asm__ volatile("icbi 0, %0" : : "r"(line)); 139327952Sdim __asm__ volatile("isync"); 140360784Sdim#elif defined(__sparc__) 141360784Sdim const size_t dword_size = 8; 142360784Sdim const size_t len = (uintptr_t)end - (uintptr_t)start; 143360784Sdim 144360784Sdim const uintptr_t mask = ~(dword_size - 1); 145360784Sdim const uintptr_t start_dword = ((uintptr_t)start) & mask; 146360784Sdim const uintptr_t end_dword = ((uintptr_t)start + len + dword_size - 1) & mask; 147360784Sdim 148360784Sdim for (uintptr_t dword = start_dword; dword < end_dword; dword += dword_size) 149360784Sdim __asm__ volatile("flush %0" : : "r"(dword)); 150276789Sdim#else 151353358Sdim#if __APPLE__ 152353358Sdim // On Darwin, sys_icache_invalidate() provides this functionality 153353358Sdim sys_icache_invalidate(start, end - start); 154353358Sdim#else 155353358Sdim compilerrt_abort(); 156276789Sdim#endif 157353358Sdim#endif 158276789Sdim} 159