cpuid.h revision 321369
1238423Sjhb/*===---- cpuid.h - X86 cpu model detection --------------------------------=== 2238423Sjhb * 3264996Sjmmv * Permission is hereby granted, free of charge, to any person obtaining a copy 4264996Sjmmv * of this software and associated documentation files (the "Software"), to deal 5238423Sjhb * in the Software without restriction, including without limitation the rights 6238423Sjhb * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 7238423Sjhb * copies of the Software, and to permit persons to whom the Software is 8264996Sjmmv * furnished to do so, subject to the following conditions: 9264996Sjmmv * 10264996Sjmmv * The above copyright notice and this permission notice shall be included in 11264996Sjmmv * all copies or substantial portions of the Software. 12238423Sjhb * 13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 15 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 16 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 17 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 18 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 19 * THE SOFTWARE. 20 * 21 *===-----------------------------------------------------------------------=== 22 */ 23 24#if !(__x86_64__ || __i386__) 25#error this header is for x86 only 26#endif 27 28/* Responses identification request with %eax 0 */ 29/* AMD: "AuthenticAMD" */ 30#define signature_AMD_ebx 0x68747541 31#define signature_AMD_edx 0x69746e65 32#define signature_AMD_ecx 0x444d4163 33/* CENTAUR: "CentaurHauls" */ 34#define signature_CENTAUR_ebx 0x746e6543 35#define signature_CENTAUR_edx 0x48727561 36#define signature_CENTAUR_ecx 0x736c7561 37/* CYRIX: "CyrixInstead" */ 38#define signature_CYRIX_ebx 0x69727943 39#define signature_CYRIX_edx 0x736e4978 40#define signature_CYRIX_ecx 0x64616574 41/* INTEL: "GenuineIntel" */ 42#define signature_INTEL_ebx 0x756e6547 43#define signature_INTEL_edx 0x49656e69 44#define signature_INTEL_ecx 0x6c65746e 45/* TM1: "TransmetaCPU" */ 46#define signature_TM1_ebx 0x6e617254 47#define signature_TM1_edx 0x74656d73 48#define signature_TM1_ecx 0x55504361 49/* TM2: "GenuineTMx86" */ 50#define signature_TM2_ebx 0x756e6547 51#define signature_TM2_edx 0x54656e69 52#define signature_TM2_ecx 0x3638784d 53/* NSC: "Geode by NSC" */ 54#define signature_NSC_ebx 0x646f6547 55#define signature_NSC_edx 0x43534e20 56#define signature_NSC_ecx 0x79622065 57/* NEXGEN: "NexGenDriven" */ 58#define signature_NEXGEN_ebx 0x4778654e 59#define signature_NEXGEN_edx 0x72446e65 60#define signature_NEXGEN_ecx 0x6e657669 61/* RISE: "RiseRiseRise" */ 62#define signature_RISE_ebx 0x65736952 63#define signature_RISE_edx 0x65736952 64#define signature_RISE_ecx 0x65736952 65/* SIS: "SiS SiS SiS " */ 66#define signature_SIS_ebx 0x20536953 67#define signature_SIS_edx 0x20536953 68#define signature_SIS_ecx 0x20536953 69/* UMC: "UMC UMC UMC " */ 70#define signature_UMC_ebx 0x20434d55 71#define signature_UMC_edx 0x20434d55 72#define signature_UMC_ecx 0x20434d55 73/* VIA: "VIA VIA VIA " */ 74#define signature_VIA_ebx 0x20414956 75#define signature_VIA_edx 0x20414956 76#define signature_VIA_ecx 0x20414956 77/* VORTEX: "Vortex86 SoC" */ 78#define signature_VORTEX_ebx 0x74726f56 79#define signature_VORTEX_edx 0x36387865 80#define signature_VORTEX_ecx 0x436f5320 81 82/* Features in %ecx for leaf 1 */ 83#define bit_SSE3 0x00000001 84#define bit_PCLMULQDQ 0x00000002 85#define bit_PCLMUL bit_PCLMULQDQ /* for gcc compat */ 86#define bit_DTES64 0x00000004 87#define bit_MONITOR 0x00000008 88#define bit_DSCPL 0x00000010 89#define bit_VMX 0x00000020 90#define bit_SMX 0x00000040 91#define bit_EIST 0x00000080 92#define bit_TM2 0x00000100 93#define bit_SSSE3 0x00000200 94#define bit_CNXTID 0x00000400 95#define bit_FMA 0x00001000 96#define bit_CMPXCHG16B 0x00002000 97#define bit_xTPR 0x00004000 98#define bit_PDCM 0x00008000 99#define bit_PCID 0x00020000 100#define bit_DCA 0x00040000 101#define bit_SSE41 0x00080000 102#define bit_SSE4_1 bit_SSE41 /* for gcc compat */ 103#define bit_SSE42 0x00100000 104#define bit_SSE4_2 bit_SSE42 /* for gcc compat */ 105#define bit_x2APIC 0x00200000 106#define bit_MOVBE 0x00400000 107#define bit_POPCNT 0x00800000 108#define bit_TSCDeadline 0x01000000 109#define bit_AESNI 0x02000000 110#define bit_AES bit_AESNI /* for gcc compat */ 111#define bit_XSAVE 0x04000000 112#define bit_OSXSAVE 0x08000000 113#define bit_AVX 0x10000000 114#define bit_F16C 0x20000000 115#define bit_RDRND 0x40000000 116 117/* Features in %edx for leaf 1 */ 118#define bit_FPU 0x00000001 119#define bit_VME 0x00000002 120#define bit_DE 0x00000004 121#define bit_PSE 0x00000008 122#define bit_TSC 0x00000010 123#define bit_MSR 0x00000020 124#define bit_PAE 0x00000040 125#define bit_MCE 0x00000080 126#define bit_CX8 0x00000100 127#define bit_CMPXCHG8B bit_CX8 /* for gcc compat */ 128#define bit_APIC 0x00000200 129#define bit_SEP 0x00000800 130#define bit_MTRR 0x00001000 131#define bit_PGE 0x00002000 132#define bit_MCA 0x00004000 133#define bit_CMOV 0x00008000 134#define bit_PAT 0x00010000 135#define bit_PSE36 0x00020000 136#define bit_PSN 0x00040000 137#define bit_CLFSH 0x00080000 138#define bit_DS 0x00200000 139#define bit_ACPI 0x00400000 140#define bit_MMX 0x00800000 141#define bit_FXSR 0x01000000 142#define bit_FXSAVE bit_FXSR /* for gcc compat */ 143#define bit_SSE 0x02000000 144#define bit_SSE2 0x04000000 145#define bit_SS 0x08000000 146#define bit_HTT 0x10000000 147#define bit_TM 0x20000000 148#define bit_PBE 0x80000000 149 150/* Features in %ebx for leaf 7 sub-leaf 0 */ 151#define bit_FSGSBASE 0x00000001 152#define bit_SGX 0x00000004 153#define bit_BMI 0x00000008 154#define bit_HLE 0x00000010 155#define bit_AVX2 0x00000020 156#define bit_SMEP 0x00000080 157#define bit_BMI2 0x00000100 158#define bit_ENH_MOVSB 0x00000200 159#define bit_RTM 0x00000800 160#define bit_MPX 0x00004000 161#define bit_AVX512F 0x00010000 162#define bit_AVX512DQ 0x00020000 163#define bit_RDSEED 0x00040000 164#define bit_ADX 0x00080000 165#define bit_AVX512IFMA 0x00200000 166#define bit_CLFLUSHOPT 0x00800000 167#define bit_CLWB 0x01000000 168#define bit_AVX512PF 0x04000000 169#define bit_AVX51SER 0x08000000 170#define bit_AVX512CD 0x10000000 171#define bit_SHA 0x20000000 172#define bit_AVX512BW 0x40000000 173#define bit_AVX512VL 0x80000000 174 175/* Features in %ecx for leaf 7 sub-leaf 0 */ 176#define bit_PREFTCHWT1 0x00000001 177#define bit_AVX512VBMI 0x00000002 178#define bit_PKU 0x00000004 179#define bit_OSPKE 0x00000010 180#define bit_AVX512VPOPCNTDQ 0x00004000 181#define bit_RDPID 0x00400000 182 183/* Features in %edx for leaf 7 sub-leaf 0 */ 184#define bit_AVX5124VNNIW 0x00000004 185#define bit_AVX5124FMAPS 0x00000008 186 187/* Features in %eax for leaf 13 sub-leaf 1 */ 188#define bit_XSAVEOPT 0x00000001 189#define bit_XSAVEC 0x00000002 190#define bit_XSAVES 0x00000008 191 192/* Features in %ecx for leaf 0x80000001 */ 193#define bit_LAHF_LM 0x00000001 194#define bit_ABM 0x00000020 195#define bit_SSE4a 0x00000040 196#define bit_PRFCHW 0x00000100 197#define bit_XOP 0x00000800 198#define bit_LWP 0x00008000 199#define bit_FMA4 0x00010000 200#define bit_TBM 0x00200000 201#define bit_MWAITX 0x20000000 202 203/* Features in %edx for leaf 0x80000001 */ 204#define bit_MMXEXT 0x00400000 205#define bit_LM 0x20000000 206#define bit_3DNOWP 0x40000000 207#define bit_3DNOW 0x80000000 208 209/* Features in %ebx for leaf 0x80000001 */ 210#define bit_CLZERO 0x00000001 211 212 213#if __i386__ 214#define __cpuid(__leaf, __eax, __ebx, __ecx, __edx) \ 215 __asm("cpuid" : "=a"(__eax), "=b" (__ebx), "=c"(__ecx), "=d"(__edx) \ 216 : "0"(__leaf)) 217 218#define __cpuid_count(__leaf, __count, __eax, __ebx, __ecx, __edx) \ 219 __asm("cpuid" : "=a"(__eax), "=b" (__ebx), "=c"(__ecx), "=d"(__edx) \ 220 : "0"(__leaf), "2"(__count)) 221#else 222/* x86-64 uses %rbx as the base register, so preserve it. */ 223#define __cpuid(__leaf, __eax, __ebx, __ecx, __edx) \ 224 __asm(" xchgq %%rbx,%q1\n" \ 225 " cpuid\n" \ 226 " xchgq %%rbx,%q1" \ 227 : "=a"(__eax), "=r" (__ebx), "=c"(__ecx), "=d"(__edx) \ 228 : "0"(__leaf)) 229 230#define __cpuid_count(__leaf, __count, __eax, __ebx, __ecx, __edx) \ 231 __asm(" xchgq %%rbx,%q1\n" \ 232 " cpuid\n" \ 233 " xchgq %%rbx,%q1" \ 234 : "=a"(__eax), "=r" (__ebx), "=c"(__ecx), "=d"(__edx) \ 235 : "0"(__leaf), "2"(__count)) 236#endif 237 238static __inline int __get_cpuid_max (unsigned int __leaf, unsigned int *__sig) 239{ 240 unsigned int __eax, __ebx, __ecx, __edx; 241#if __i386__ 242 int __cpuid_supported; 243 244 __asm(" pushfl\n" 245 " popl %%eax\n" 246 " movl %%eax,%%ecx\n" 247 " xorl $0x00200000,%%eax\n" 248 " pushl %%eax\n" 249 " popfl\n" 250 " pushfl\n" 251 " popl %%eax\n" 252 " movl $0,%0\n" 253 " cmpl %%eax,%%ecx\n" 254 " je 1f\n" 255 " movl $1,%0\n" 256 "1:" 257 : "=r" (__cpuid_supported) : : "eax", "ecx"); 258 if (!__cpuid_supported) 259 return 0; 260#endif 261 262 __cpuid(__leaf, __eax, __ebx, __ecx, __edx); 263 if (__sig) 264 *__sig = __ebx; 265 return __eax; 266} 267 268static __inline int __get_cpuid (unsigned int __leaf, unsigned int *__eax, 269 unsigned int *__ebx, unsigned int *__ecx, 270 unsigned int *__edx) 271{ 272 unsigned int __max_leaf = __get_cpuid_max(__leaf & 0x80000000, 0); 273 274 if (__max_leaf == 0 || __max_leaf < __leaf) 275 return 0; 276 277 __cpuid(__leaf, *__eax, *__ebx, *__ecx, *__edx); 278 return 1; 279} 280 281static __inline int __get_cpuid_count (unsigned int __leaf, 282 unsigned int __subleaf, 283 unsigned int *__eax, unsigned int *__ebx, 284 unsigned int *__ecx, unsigned int *__edx) 285{ 286 unsigned int __max_leaf = __get_cpuid_max(__leaf & 0x80000000, 0); 287 288 if (__max_leaf == 0 || __max_leaf < __leaf) 289 return 0; 290 291 __cpuid_count(__leaf, __subleaf, *__eax, *__ebx, *__ecx, *__edx); 292 return 1; 293} 294