sparc.c revision 161651
1/* Subroutines for insn-output.c for SPARC. 2 Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 3 1999, 2000, 2001, 2002, 2003, 2004 Free Software Foundation, Inc. 4 Contributed by Michael Tiemann (tiemann@cygnus.com) 5 64-bit SPARC-V9 support by Michael Tiemann, Jim Wilson, and Doug Evans, 6 at Cygnus Support. 7 8This file is part of GCC. 9 10GCC is free software; you can redistribute it and/or modify 11it under the terms of the GNU General Public License as published by 12the Free Software Foundation; either version 2, or (at your option) 13any later version. 14 15GCC is distributed in the hope that it will be useful, 16but WITHOUT ANY WARRANTY; without even the implied warranty of 17MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18GNU General Public License for more details. 19 20You should have received a copy of the GNU General Public License 21along with GCC; see the file COPYING. If not, write to 22the Free Software Foundation, 59 Temple Place - Suite 330, 23Boston, MA 02111-1307, USA. */ 24 25#include "config.h" 26#include "system.h" 27#include "coretypes.h" 28#include "tm.h" 29#include "tree.h" 30#include "rtl.h" 31#include "regs.h" 32#include "hard-reg-set.h" 33#include "real.h" 34#include "insn-config.h" 35#include "conditions.h" 36#include "output.h" 37#include "insn-attr.h" 38#include "flags.h" 39#include "function.h" 40#include "expr.h" 41#include "optabs.h" 42#include "recog.h" 43#include "toplev.h" 44#include "ggc.h" 45#include "tm_p.h" 46#include "debug.h" 47#include "target.h" 48#include "target-def.h" 49#include "cfglayout.h" 50 51/* 1 if the caller has placed an "unimp" insn immediately after the call. 52 This is used in v8 code when calling a function that returns a structure. 53 v9 doesn't have this. Be careful to have this test be the same as that 54 used on the call. */ 55 56#define SKIP_CALLERS_UNIMP_P \ 57(!TARGET_ARCH64 && current_function_returns_struct \ 58 && ! integer_zerop (DECL_SIZE (DECL_RESULT (current_function_decl))) \ 59 && (TREE_CODE (DECL_SIZE (DECL_RESULT (current_function_decl))) \ 60 == INTEGER_CST)) 61 62/* Global variables for machine-dependent things. */ 63 64/* Size of frame. Need to know this to emit return insns from leaf procedures. 65 ACTUAL_FSIZE is set by compute_frame_size() which is called during the 66 reload pass. This is important as the value is later used in insn 67 scheduling (to see what can go in a delay slot). 68 APPARENT_FSIZE is the size of the stack less the register save area and less 69 the outgoing argument area. It is used when saving call preserved regs. */ 70static HOST_WIDE_INT apparent_fsize; 71static HOST_WIDE_INT actual_fsize; 72 73/* Number of live general or floating point registers needed to be 74 saved (as 4-byte quantities). */ 75static int num_gfregs; 76 77/* Save the operands last given to a compare for use when we 78 generate a scc or bcc insn. */ 79rtx sparc_compare_op0, sparc_compare_op1; 80 81/* Coordinate with the md file wrt special insns created by 82 sparc_nonflat_function_epilogue. */ 83bool sparc_emitting_epilogue; 84 85/* Vector to say how input registers are mapped to output registers. 86 HARD_FRAME_POINTER_REGNUM cannot be remapped by this function to 87 eliminate it. You must use -fomit-frame-pointer to get that. */ 88char leaf_reg_remap[] = 89{ 0, 1, 2, 3, 4, 5, 6, 7, 90 -1, -1, -1, -1, -1, -1, 14, -1, 91 -1, -1, -1, -1, -1, -1, -1, -1, 92 8, 9, 10, 11, 12, 13, -1, 15, 93 94 32, 33, 34, 35, 36, 37, 38, 39, 95 40, 41, 42, 43, 44, 45, 46, 47, 96 48, 49, 50, 51, 52, 53, 54, 55, 97 56, 57, 58, 59, 60, 61, 62, 63, 98 64, 65, 66, 67, 68, 69, 70, 71, 99 72, 73, 74, 75, 76, 77, 78, 79, 100 80, 81, 82, 83, 84, 85, 86, 87, 101 88, 89, 90, 91, 92, 93, 94, 95, 102 96, 97, 98, 99, 100}; 103 104/* Vector, indexed by hard register number, which contains 1 105 for a register that is allowable in a candidate for leaf 106 function treatment. */ 107char sparc_leaf_regs[] = 108{ 1, 1, 1, 1, 1, 1, 1, 1, 109 0, 0, 0, 0, 0, 0, 1, 0, 110 0, 0, 0, 0, 0, 0, 0, 0, 111 1, 1, 1, 1, 1, 1, 0, 1, 112 1, 1, 1, 1, 1, 1, 1, 1, 113 1, 1, 1, 1, 1, 1, 1, 1, 114 1, 1, 1, 1, 1, 1, 1, 1, 115 1, 1, 1, 1, 1, 1, 1, 1, 116 1, 1, 1, 1, 1, 1, 1, 1, 117 1, 1, 1, 1, 1, 1, 1, 1, 118 1, 1, 1, 1, 1, 1, 1, 1, 119 1, 1, 1, 1, 1, 1, 1, 1, 120 1, 1, 1, 1, 1}; 121 122struct machine_function GTY(()) 123{ 124 /* Some local-dynamic TLS symbol name. */ 125 const char *some_ld_name; 126}; 127 128/* Name of where we pretend to think the frame pointer points. 129 Normally, this is "%fp", but if we are in a leaf procedure, 130 this is "%sp+something". We record "something" separately as it may be 131 too big for reg+constant addressing. */ 132 133static const char *frame_base_name; 134static HOST_WIDE_INT frame_base_offset; 135 136static void sparc_init_modes (void); 137static int save_regs (FILE *, int, int, const char *, int, int, HOST_WIDE_INT); 138static int restore_regs (FILE *, int, int, const char *, int, int); 139static void build_big_number (FILE *, HOST_WIDE_INT, const char *); 140static void scan_record_type (tree, int *, int *, int *); 141static int function_arg_slotno (const CUMULATIVE_ARGS *, enum machine_mode, 142 tree, int, int, int *, int *); 143 144static int supersparc_adjust_cost (rtx, rtx, rtx, int); 145static int hypersparc_adjust_cost (rtx, rtx, rtx, int); 146 147static void sparc_output_addr_vec (rtx); 148static void sparc_output_addr_diff_vec (rtx); 149static void sparc_output_deferred_case_vectors (void); 150static int check_return_regs (rtx); 151static int epilogue_renumber (rtx *, int); 152static bool sparc_assemble_integer (rtx, unsigned int, int); 153static int set_extends (rtx); 154static void output_restore_regs (FILE *, int); 155static void sparc_output_function_prologue (FILE *, HOST_WIDE_INT); 156static void sparc_output_function_epilogue (FILE *, HOST_WIDE_INT); 157static void sparc_flat_function_epilogue (FILE *, HOST_WIDE_INT); 158static void sparc_flat_function_prologue (FILE *, HOST_WIDE_INT); 159static void sparc_flat_save_restore (FILE *, const char *, int, 160 unsigned long, unsigned long, 161 const char *, const char *, 162 HOST_WIDE_INT); 163static void sparc_nonflat_function_epilogue (FILE *, HOST_WIDE_INT, int); 164static void sparc_nonflat_function_prologue (FILE *, HOST_WIDE_INT, int); 165#ifdef OBJECT_FORMAT_ELF 166static void sparc_elf_asm_named_section (const char *, unsigned int); 167#endif 168static void sparc_aout_select_section (tree, int, unsigned HOST_WIDE_INT) 169 ATTRIBUTE_UNUSED; 170static void sparc_aout_select_rtx_section (enum machine_mode, rtx, 171 unsigned HOST_WIDE_INT) 172 ATTRIBUTE_UNUSED; 173 174static int sparc_adjust_cost (rtx, rtx, rtx, int); 175static int sparc_issue_rate (void); 176static void sparc_sched_init (FILE *, int, int); 177static int sparc_use_dfa_pipeline_interface (void); 178static int sparc_use_sched_lookahead (void); 179 180static void emit_soft_tfmode_libcall (const char *, int, rtx *); 181static void emit_soft_tfmode_binop (enum rtx_code, rtx *); 182static void emit_soft_tfmode_unop (enum rtx_code, rtx *); 183static void emit_soft_tfmode_cvt (enum rtx_code, rtx *); 184static void emit_hard_tfmode_operation (enum rtx_code, rtx *); 185 186static bool sparc_function_ok_for_sibcall (tree, tree); 187static void sparc_init_libfuncs (void); 188static void sparc_output_mi_thunk (FILE *, tree, HOST_WIDE_INT, 189 HOST_WIDE_INT, tree); 190static bool sparc_can_output_mi_thunk (tree, HOST_WIDE_INT, 191 HOST_WIDE_INT, tree); 192static struct machine_function * sparc_init_machine_status (void); 193static bool sparc_cannot_force_const_mem (rtx); 194static rtx sparc_tls_get_addr (void); 195static rtx sparc_tls_got (void); 196static const char *get_some_local_dynamic_name (void); 197static int get_some_local_dynamic_name_1 (rtx *, void *); 198static bool sparc_rtx_costs (rtx, int, int, int *); 199 200/* Option handling. */ 201 202/* Code model option as passed by user. */ 203const char *sparc_cmodel_string; 204/* Parsed value. */ 205enum cmodel sparc_cmodel; 206 207char sparc_hard_reg_printed[8]; 208 209struct sparc_cpu_select sparc_select[] = 210{ 211 /* switch name, tune arch */ 212 { (char *)0, "default", 1, 1 }, 213 { (char *)0, "-mcpu=", 1, 1 }, 214 { (char *)0, "-mtune=", 1, 0 }, 215 { 0, 0, 0, 0 } 216}; 217 218/* CPU type. This is set from TARGET_CPU_DEFAULT and -m{cpu,tune}=xxx. */ 219enum processor_type sparc_cpu; 220 221/* Initialize the GCC target structure. */ 222 223/* The sparc default is to use .half rather than .short for aligned 224 HI objects. Use .word instead of .long on non-ELF systems. */ 225#undef TARGET_ASM_ALIGNED_HI_OP 226#define TARGET_ASM_ALIGNED_HI_OP "\t.half\t" 227#ifndef OBJECT_FORMAT_ELF 228#undef TARGET_ASM_ALIGNED_SI_OP 229#define TARGET_ASM_ALIGNED_SI_OP "\t.word\t" 230#endif 231 232#undef TARGET_ASM_UNALIGNED_HI_OP 233#define TARGET_ASM_UNALIGNED_HI_OP "\t.uahalf\t" 234#undef TARGET_ASM_UNALIGNED_SI_OP 235#define TARGET_ASM_UNALIGNED_SI_OP "\t.uaword\t" 236#undef TARGET_ASM_UNALIGNED_DI_OP 237#define TARGET_ASM_UNALIGNED_DI_OP "\t.uaxword\t" 238 239/* The target hook has to handle DI-mode values. */ 240#undef TARGET_ASM_INTEGER 241#define TARGET_ASM_INTEGER sparc_assemble_integer 242 243#undef TARGET_ASM_FUNCTION_PROLOGUE 244#define TARGET_ASM_FUNCTION_PROLOGUE sparc_output_function_prologue 245#undef TARGET_ASM_FUNCTION_EPILOGUE 246#define TARGET_ASM_FUNCTION_EPILOGUE sparc_output_function_epilogue 247 248#undef TARGET_SCHED_ADJUST_COST 249#define TARGET_SCHED_ADJUST_COST sparc_adjust_cost 250#undef TARGET_SCHED_ISSUE_RATE 251#define TARGET_SCHED_ISSUE_RATE sparc_issue_rate 252#undef TARGET_SCHED_INIT 253#define TARGET_SCHED_INIT sparc_sched_init 254#undef TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE 255#define TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE sparc_use_dfa_pipeline_interface 256#undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD 257#define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD sparc_use_sched_lookahead 258 259#undef TARGET_FUNCTION_OK_FOR_SIBCALL 260#define TARGET_FUNCTION_OK_FOR_SIBCALL sparc_function_ok_for_sibcall 261 262#undef TARGET_INIT_LIBFUNCS 263#define TARGET_INIT_LIBFUNCS sparc_init_libfuncs 264 265#ifdef HAVE_AS_TLS 266#undef TARGET_HAVE_TLS 267#define TARGET_HAVE_TLS true 268#endif 269#undef TARGET_CANNOT_FORCE_CONST_MEM 270#define TARGET_CANNOT_FORCE_CONST_MEM sparc_cannot_force_const_mem 271 272#undef TARGET_ASM_OUTPUT_MI_THUNK 273#define TARGET_ASM_OUTPUT_MI_THUNK sparc_output_mi_thunk 274#undef TARGET_ASM_CAN_OUTPUT_MI_THUNK 275#define TARGET_ASM_CAN_OUTPUT_MI_THUNK sparc_can_output_mi_thunk 276 277#undef TARGET_RTX_COSTS 278#define TARGET_RTX_COSTS sparc_rtx_costs 279#undef TARGET_ADDRESS_COST 280#define TARGET_ADDRESS_COST hook_int_rtx_0 281 282struct gcc_target targetm = TARGET_INITIALIZER; 283 284/* Validate and override various options, and do some machine dependent 285 initialization. */ 286 287void 288sparc_override_options (void) 289{ 290 static struct code_model { 291 const char *const name; 292 const int value; 293 } const cmodels[] = { 294 { "32", CM_32 }, 295 { "medlow", CM_MEDLOW }, 296 { "medmid", CM_MEDMID }, 297 { "medany", CM_MEDANY }, 298 { "embmedany", CM_EMBMEDANY }, 299 { 0, 0 } 300 }; 301 const struct code_model *cmodel; 302 /* Map TARGET_CPU_DEFAULT to value for -m{arch,tune}=. */ 303 static struct cpu_default { 304 const int cpu; 305 const char *const name; 306 } const cpu_default[] = { 307 /* There must be one entry here for each TARGET_CPU value. */ 308 { TARGET_CPU_sparc, "cypress" }, 309 { TARGET_CPU_sparclet, "tsc701" }, 310 { TARGET_CPU_sparclite, "f930" }, 311 { TARGET_CPU_v8, "v8" }, 312 { TARGET_CPU_hypersparc, "hypersparc" }, 313 { TARGET_CPU_sparclite86x, "sparclite86x" }, 314 { TARGET_CPU_supersparc, "supersparc" }, 315 { TARGET_CPU_v9, "v9" }, 316 { TARGET_CPU_ultrasparc, "ultrasparc" }, 317 { TARGET_CPU_ultrasparc3, "ultrasparc3" }, 318 { 0, 0 } 319 }; 320 const struct cpu_default *def; 321 /* Table of values for -m{cpu,tune}=. */ 322 static struct cpu_table { 323 const char *const name; 324 const enum processor_type processor; 325 const int disable; 326 const int enable; 327 } const cpu_table[] = { 328 { "v7", PROCESSOR_V7, MASK_ISA, 0 }, 329 { "cypress", PROCESSOR_CYPRESS, MASK_ISA, 0 }, 330 { "v8", PROCESSOR_V8, MASK_ISA, MASK_V8 }, 331 /* TI TMS390Z55 supersparc */ 332 { "supersparc", PROCESSOR_SUPERSPARC, MASK_ISA, MASK_V8 }, 333 { "sparclite", PROCESSOR_SPARCLITE, MASK_ISA, MASK_SPARCLITE }, 334 /* The Fujitsu MB86930 is the original sparclite chip, with no fpu. 335 The Fujitsu MB86934 is the recent sparclite chip, with an fpu. */ 336 { "f930", PROCESSOR_F930, MASK_ISA|MASK_FPU, MASK_SPARCLITE }, 337 { "f934", PROCESSOR_F934, MASK_ISA, MASK_SPARCLITE|MASK_FPU }, 338 { "hypersparc", PROCESSOR_HYPERSPARC, MASK_ISA, MASK_V8|MASK_FPU }, 339 { "sparclite86x", PROCESSOR_SPARCLITE86X, MASK_ISA|MASK_FPU, 340 MASK_SPARCLITE }, 341 { "sparclet", PROCESSOR_SPARCLET, MASK_ISA, MASK_SPARCLET }, 342 /* TEMIC sparclet */ 343 { "tsc701", PROCESSOR_TSC701, MASK_ISA, MASK_SPARCLET }, 344 { "v9", PROCESSOR_V9, MASK_ISA, MASK_V9 }, 345 /* TI ultrasparc I, II, IIi */ 346 { "ultrasparc", PROCESSOR_ULTRASPARC, MASK_ISA, MASK_V9 347 /* Although insns using %y are deprecated, it is a clear win on current 348 ultrasparcs. */ 349 |MASK_DEPRECATED_V8_INSNS}, 350 /* TI ultrasparc III */ 351 /* ??? Check if %y issue still holds true in ultra3. */ 352 { "ultrasparc3", PROCESSOR_ULTRASPARC3, MASK_ISA, MASK_V9|MASK_DEPRECATED_V8_INSNS}, 353 { 0, 0, 0, 0 } 354 }; 355 const struct cpu_table *cpu; 356 const struct sparc_cpu_select *sel; 357 int fpu; 358 359#ifndef SPARC_BI_ARCH 360 /* Check for unsupported architecture size. */ 361 if (! TARGET_64BIT != DEFAULT_ARCH32_P) 362 error ("%s is not supported by this configuration", 363 DEFAULT_ARCH32_P ? "-m64" : "-m32"); 364#endif 365 366 /* We force all 64bit archs to use 128 bit long double */ 367 if (TARGET_64BIT && ! TARGET_LONG_DOUBLE_128) 368 { 369 error ("-mlong-double-64 not allowed with -m64"); 370 target_flags |= MASK_LONG_DOUBLE_128; 371 } 372 373 /* Code model selection. */ 374 sparc_cmodel = SPARC_DEFAULT_CMODEL; 375 376#ifdef SPARC_BI_ARCH 377 if (TARGET_ARCH32) 378 sparc_cmodel = CM_32; 379#endif 380 381 if (sparc_cmodel_string != NULL) 382 { 383 if (TARGET_ARCH64) 384 { 385 for (cmodel = &cmodels[0]; cmodel->name; cmodel++) 386 if (strcmp (sparc_cmodel_string, cmodel->name) == 0) 387 break; 388 if (cmodel->name == NULL) 389 error ("bad value (%s) for -mcmodel= switch", sparc_cmodel_string); 390 else 391 sparc_cmodel = cmodel->value; 392 } 393 else 394 error ("-mcmodel= is not supported on 32 bit systems"); 395 } 396 397 fpu = TARGET_FPU; /* save current -mfpu status */ 398 399 /* Set the default CPU. */ 400 for (def = &cpu_default[0]; def->name; ++def) 401 if (def->cpu == TARGET_CPU_DEFAULT) 402 break; 403 if (! def->name) 404 abort (); 405 sparc_select[0].string = def->name; 406 407 for (sel = &sparc_select[0]; sel->name; ++sel) 408 { 409 if (sel->string) 410 { 411 for (cpu = &cpu_table[0]; cpu->name; ++cpu) 412 if (! strcmp (sel->string, cpu->name)) 413 { 414 if (sel->set_tune_p) 415 sparc_cpu = cpu->processor; 416 417 if (sel->set_arch_p) 418 { 419 target_flags &= ~cpu->disable; 420 target_flags |= cpu->enable; 421 } 422 break; 423 } 424 425 if (! cpu->name) 426 error ("bad value (%s) for %s switch", sel->string, sel->name); 427 } 428 } 429 430 /* If -mfpu or -mno-fpu was explicitly used, don't override with 431 the processor default. Clear MASK_FPU_SET to avoid confusing 432 the reverse mapping from switch values to names. */ 433 if (TARGET_FPU_SET) 434 { 435 target_flags = (target_flags & ~MASK_FPU) | fpu; 436 target_flags &= ~MASK_FPU_SET; 437 } 438 439 /* Don't allow -mvis if FPU is disabled. */ 440 if (! TARGET_FPU) 441 target_flags &= ~MASK_VIS; 442 443 /* -mvis assumes UltraSPARC+, so we are sure v9 instructions 444 are available. 445 -m64 also implies v9. */ 446 if (TARGET_VIS || TARGET_ARCH64) 447 { 448 target_flags |= MASK_V9; 449 target_flags &= ~(MASK_V8 | MASK_SPARCLET | MASK_SPARCLITE); 450 } 451 452 /* Use the deprecated v8 insns for sparc64 in 32 bit mode. */ 453 if (TARGET_V9 && TARGET_ARCH32) 454 target_flags |= MASK_DEPRECATED_V8_INSNS; 455 456 /* V8PLUS requires V9, makes no sense in 64 bit mode. */ 457 if (! TARGET_V9 || TARGET_ARCH64) 458 target_flags &= ~MASK_V8PLUS; 459 460 /* Don't use stack biasing in 32 bit mode. */ 461 if (TARGET_ARCH32) 462 target_flags &= ~MASK_STACK_BIAS; 463 464 /* Supply a default value for align_functions. */ 465 if (align_functions == 0 466 && (sparc_cpu == PROCESSOR_ULTRASPARC 467 || sparc_cpu == PROCESSOR_ULTRASPARC3)) 468 align_functions = 32; 469 470 /* Validate PCC_STRUCT_RETURN. */ 471 if (flag_pcc_struct_return == DEFAULT_PCC_STRUCT_RETURN) 472 flag_pcc_struct_return = (TARGET_ARCH64 ? 0 : 1); 473 474 /* Only use .uaxword when compiling for a 64-bit target. */ 475 if (!TARGET_ARCH64) 476 targetm.asm_out.unaligned_op.di = NULL; 477 478 /* Do various machine dependent initializations. */ 479 sparc_init_modes (); 480 481 /* Set up function hooks. */ 482 init_machine_status = sparc_init_machine_status; 483} 484 485/* Miscellaneous utilities. */ 486 487/* Nonzero if CODE, a comparison, is suitable for use in v9 conditional move 488 or branch on register contents instructions. */ 489 490int 491v9_regcmp_p (enum rtx_code code) 492{ 493 return (code == EQ || code == NE || code == GE || code == LT 494 || code == LE || code == GT); 495} 496 497 498/* Operand constraints. */ 499 500/* Return nonzero only if OP is a register of mode MODE, 501 or const0_rtx. */ 502 503int 504reg_or_0_operand (rtx op, enum machine_mode mode) 505{ 506 if (register_operand (op, mode)) 507 return 1; 508 if (op == const0_rtx) 509 return 1; 510 if (GET_MODE (op) == VOIDmode && GET_CODE (op) == CONST_DOUBLE 511 && CONST_DOUBLE_HIGH (op) == 0 512 && CONST_DOUBLE_LOW (op) == 0) 513 return 1; 514 if (fp_zero_operand (op, mode)) 515 return 1; 516 return 0; 517} 518 519/* Return nonzero only if OP is const1_rtx. */ 520 521int 522const1_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) 523{ 524 return op == const1_rtx; 525} 526 527/* Nonzero if OP is a floating point value with value 0.0. */ 528 529int 530fp_zero_operand (rtx op, enum machine_mode mode) 531{ 532 if (GET_MODE_CLASS (GET_MODE (op)) != MODE_FLOAT) 533 return 0; 534 return op == CONST0_RTX (mode); 535} 536 537/* Nonzero if OP is a register operand in floating point register. */ 538 539int 540fp_register_operand (rtx op, enum machine_mode mode) 541{ 542 if (! register_operand (op, mode)) 543 return 0; 544 if (GET_CODE (op) == SUBREG) 545 op = SUBREG_REG (op); 546 return GET_CODE (op) == REG && SPARC_FP_REG_P (REGNO (op)); 547} 548 549/* Nonzero if OP is a floating point constant which can 550 be loaded into an integer register using a single 551 sethi instruction. */ 552 553int 554fp_sethi_p (rtx op) 555{ 556 if (GET_CODE (op) == CONST_DOUBLE) 557 { 558 REAL_VALUE_TYPE r; 559 long i; 560 561 REAL_VALUE_FROM_CONST_DOUBLE (r, op); 562 if (REAL_VALUES_EQUAL (r, dconst0) && 563 ! REAL_VALUE_MINUS_ZERO (r)) 564 return 0; 565 REAL_VALUE_TO_TARGET_SINGLE (r, i); 566 if (SPARC_SETHI_P (i)) 567 return 1; 568 } 569 570 return 0; 571} 572 573/* Nonzero if OP is a floating point constant which can 574 be loaded into an integer register using a single 575 mov instruction. */ 576 577int 578fp_mov_p (rtx op) 579{ 580 if (GET_CODE (op) == CONST_DOUBLE) 581 { 582 REAL_VALUE_TYPE r; 583 long i; 584 585 REAL_VALUE_FROM_CONST_DOUBLE (r, op); 586 if (REAL_VALUES_EQUAL (r, dconst0) && 587 ! REAL_VALUE_MINUS_ZERO (r)) 588 return 0; 589 REAL_VALUE_TO_TARGET_SINGLE (r, i); 590 if (SPARC_SIMM13_P (i)) 591 return 1; 592 } 593 594 return 0; 595} 596 597/* Nonzero if OP is a floating point constant which can 598 be loaded into an integer register using a high/losum 599 instruction sequence. */ 600 601int 602fp_high_losum_p (rtx op) 603{ 604 /* The constraints calling this should only be in 605 SFmode move insns, so any constant which cannot 606 be moved using a single insn will do. */ 607 if (GET_CODE (op) == CONST_DOUBLE) 608 { 609 REAL_VALUE_TYPE r; 610 long i; 611 612 REAL_VALUE_FROM_CONST_DOUBLE (r, op); 613 if (REAL_VALUES_EQUAL (r, dconst0) && 614 ! REAL_VALUE_MINUS_ZERO (r)) 615 return 0; 616 REAL_VALUE_TO_TARGET_SINGLE (r, i); 617 if (! SPARC_SETHI_P (i) 618 && ! SPARC_SIMM13_P (i)) 619 return 1; 620 } 621 622 return 0; 623} 624 625/* Nonzero if OP is an integer register. */ 626 627int 628intreg_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) 629{ 630 return (register_operand (op, SImode) 631 || (TARGET_ARCH64 && register_operand (op, DImode))); 632} 633 634/* Nonzero if OP is a floating point condition code register. */ 635 636int 637fcc_reg_operand (rtx op, enum machine_mode mode) 638{ 639 /* This can happen when recog is called from combine. Op may be a MEM. 640 Fail instead of calling abort in this case. */ 641 if (GET_CODE (op) != REG) 642 return 0; 643 644 if (mode != VOIDmode && mode != GET_MODE (op)) 645 return 0; 646 if (mode == VOIDmode 647 && (GET_MODE (op) != CCFPmode && GET_MODE (op) != CCFPEmode)) 648 return 0; 649 650#if 0 /* ??? ==> 1 when %fcc0-3 are pseudos first. See gen_compare_reg(). */ 651 if (reg_renumber == 0) 652 return REGNO (op) >= FIRST_PSEUDO_REGISTER; 653 return REGNO_OK_FOR_CCFP_P (REGNO (op)); 654#else 655 return (unsigned) REGNO (op) - SPARC_FIRST_V9_FCC_REG < 4; 656#endif 657} 658 659/* Nonzero if OP is a floating point condition code fcc0 register. */ 660 661int 662fcc0_reg_operand (rtx op, enum machine_mode mode) 663{ 664 /* This can happen when recog is called from combine. Op may be a MEM. 665 Fail instead of calling abort in this case. */ 666 if (GET_CODE (op) != REG) 667 return 0; 668 669 if (mode != VOIDmode && mode != GET_MODE (op)) 670 return 0; 671 if (mode == VOIDmode 672 && (GET_MODE (op) != CCFPmode && GET_MODE (op) != CCFPEmode)) 673 return 0; 674 675 return REGNO (op) == SPARC_FCC_REG; 676} 677 678/* Nonzero if OP is an integer or floating point condition code register. */ 679 680int 681icc_or_fcc_reg_operand (rtx op, enum machine_mode mode) 682{ 683 if (GET_CODE (op) == REG && REGNO (op) == SPARC_ICC_REG) 684 { 685 if (mode != VOIDmode && mode != GET_MODE (op)) 686 return 0; 687 if (mode == VOIDmode 688 && GET_MODE (op) != CCmode && GET_MODE (op) != CCXmode) 689 return 0; 690 return 1; 691 } 692 693 return fcc_reg_operand (op, mode); 694} 695 696/* Nonzero if OP can appear as the dest of a RESTORE insn. */ 697int 698restore_operand (rtx op, enum machine_mode mode) 699{ 700 return (GET_CODE (op) == REG && GET_MODE (op) == mode 701 && (REGNO (op) < 8 || (REGNO (op) >= 24 && REGNO (op) < 32))); 702} 703 704/* Call insn on SPARC can take a PC-relative constant address, or any regular 705 memory address. */ 706 707int 708call_operand (rtx op, enum machine_mode mode) 709{ 710 if (GET_CODE (op) != MEM) 711 abort (); 712 op = XEXP (op, 0); 713 return (symbolic_operand (op, mode) || memory_address_p (Pmode, op)); 714} 715 716int 717call_operand_address (rtx op, enum machine_mode mode) 718{ 719 return (symbolic_operand (op, mode) || memory_address_p (Pmode, op)); 720} 721 722/* If OP is a SYMBOL_REF of a thread-local symbol, return its TLS mode, 723 otherwise return 0. */ 724 725int 726tls_symbolic_operand (rtx op) 727{ 728 if (GET_CODE (op) != SYMBOL_REF) 729 return 0; 730 return SYMBOL_REF_TLS_MODEL (op); 731} 732 733int 734tgd_symbolic_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) 735{ 736 return tls_symbolic_operand (op) == TLS_MODEL_GLOBAL_DYNAMIC; 737} 738 739int 740tld_symbolic_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) 741{ 742 return tls_symbolic_operand (op) == TLS_MODEL_LOCAL_DYNAMIC; 743} 744 745int 746tie_symbolic_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) 747{ 748 return tls_symbolic_operand (op) == TLS_MODEL_INITIAL_EXEC; 749} 750 751int 752tle_symbolic_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) 753{ 754 return tls_symbolic_operand (op) == TLS_MODEL_LOCAL_EXEC; 755} 756 757/* Returns 1 if OP is either a symbol reference or a sum of a symbol 758 reference and a constant. */ 759 760int 761symbolic_operand (register rtx op, enum machine_mode mode) 762{ 763 enum machine_mode omode = GET_MODE (op); 764 765 if (omode != mode && omode != VOIDmode && mode != VOIDmode) 766 return 0; 767 768 switch (GET_CODE (op)) 769 { 770 case SYMBOL_REF: 771 return !SYMBOL_REF_TLS_MODEL (op); 772 773 case LABEL_REF: 774 return 1; 775 776 case CONST: 777 op = XEXP (op, 0); 778 return (((GET_CODE (XEXP (op, 0)) == SYMBOL_REF 779 && !SYMBOL_REF_TLS_MODEL (XEXP (op, 0))) 780 || GET_CODE (XEXP (op, 0)) == LABEL_REF) 781 && GET_CODE (XEXP (op, 1)) == CONST_INT); 782 783 default: 784 return 0; 785 } 786} 787 788/* Return truth value of statement that OP is a symbolic memory 789 operand of mode MODE. */ 790 791int 792symbolic_memory_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) 793{ 794 if (GET_CODE (op) == SUBREG) 795 op = SUBREG_REG (op); 796 if (GET_CODE (op) != MEM) 797 return 0; 798 op = XEXP (op, 0); 799 return ((GET_CODE (op) == SYMBOL_REF && !SYMBOL_REF_TLS_MODEL (op)) 800 || GET_CODE (op) == CONST || GET_CODE (op) == HIGH 801 || GET_CODE (op) == LABEL_REF); 802} 803 804/* Return truth value of statement that OP is a LABEL_REF of mode MODE. */ 805 806int 807label_ref_operand (rtx op, enum machine_mode mode) 808{ 809 if (GET_CODE (op) != LABEL_REF) 810 return 0; 811 if (GET_MODE (op) != mode) 812 return 0; 813 return 1; 814} 815 816/* Return 1 if the operand is an argument used in generating pic references 817 in either the medium/low or medium/anywhere code models of sparc64. */ 818 819int 820sp64_medium_pic_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) 821{ 822 /* Check for (const (minus (symbol_ref:GOT) 823 (const (minus (label) (pc))))). */ 824 if (GET_CODE (op) != CONST) 825 return 0; 826 op = XEXP (op, 0); 827 if (GET_CODE (op) != MINUS) 828 return 0; 829 if (GET_CODE (XEXP (op, 0)) != SYMBOL_REF) 830 return 0; 831 /* ??? Ensure symbol is GOT. */ 832 if (GET_CODE (XEXP (op, 1)) != CONST) 833 return 0; 834 if (GET_CODE (XEXP (XEXP (op, 1), 0)) != MINUS) 835 return 0; 836 return 1; 837} 838 839/* Return 1 if the operand is a data segment reference. This includes 840 the readonly data segment, or in other words anything but the text segment. 841 This is needed in the medium/anywhere code model on v9. These values 842 are accessed with EMBMEDANY_BASE_REG. */ 843 844int 845data_segment_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) 846{ 847 switch (GET_CODE (op)) 848 { 849 case SYMBOL_REF : 850 return ! SYMBOL_REF_FUNCTION_P (op); 851 case PLUS : 852 /* Assume canonical format of symbol + constant. 853 Fall through. */ 854 case CONST : 855 return data_segment_operand (XEXP (op, 0), VOIDmode); 856 default : 857 return 0; 858 } 859} 860 861/* Return 1 if the operand is a text segment reference. 862 This is needed in the medium/anywhere code model on v9. */ 863 864int 865text_segment_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) 866{ 867 switch (GET_CODE (op)) 868 { 869 case LABEL_REF : 870 return 1; 871 case SYMBOL_REF : 872 return SYMBOL_REF_FUNCTION_P (op); 873 case PLUS : 874 /* Assume canonical format of symbol + constant. 875 Fall through. */ 876 case CONST : 877 return text_segment_operand (XEXP (op, 0), VOIDmode); 878 default : 879 return 0; 880 } 881} 882 883/* Return 1 if the operand is either a register or a memory operand that is 884 not symbolic. */ 885 886int 887reg_or_nonsymb_mem_operand (register rtx op, enum machine_mode mode) 888{ 889 if (register_operand (op, mode)) 890 return 1; 891 892 if (memory_operand (op, mode) && ! symbolic_memory_operand (op, mode)) 893 return 1; 894 895 return 0; 896} 897 898int 899splittable_symbolic_memory_operand (rtx op, 900 enum machine_mode mode ATTRIBUTE_UNUSED) 901{ 902 if (GET_CODE (op) != MEM) 903 return 0; 904 if (! symbolic_operand (XEXP (op, 0), Pmode)) 905 return 0; 906 return 1; 907} 908 909int 910splittable_immediate_memory_operand (rtx op, 911 enum machine_mode mode ATTRIBUTE_UNUSED) 912{ 913 if (GET_CODE (op) != MEM) 914 return 0; 915 if (! immediate_operand (XEXP (op, 0), Pmode)) 916 return 0; 917 return 1; 918} 919 920/* Return truth value of whether OP is EQ or NE. */ 921 922int 923eq_or_neq (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) 924{ 925 return (GET_CODE (op) == EQ || GET_CODE (op) == NE); 926} 927 928/* Return 1 if this is a comparison operator, but not an EQ, NE, GEU, 929 or LTU for non-floating-point. We handle those specially. */ 930 931int 932normal_comp_operator (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) 933{ 934 enum rtx_code code = GET_CODE (op); 935 936 if (GET_RTX_CLASS (code) != '<') 937 return 0; 938 939 if (GET_MODE (XEXP (op, 0)) == CCFPmode 940 || GET_MODE (XEXP (op, 0)) == CCFPEmode) 941 return 1; 942 943 return (code != NE && code != EQ && code != GEU && code != LTU); 944} 945 946/* Return 1 if this is a comparison operator. This allows the use of 947 MATCH_OPERATOR to recognize all the branch insns. */ 948 949int 950noov_compare_op (register rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) 951{ 952 enum rtx_code code = GET_CODE (op); 953 954 if (GET_RTX_CLASS (code) != '<') 955 return 0; 956 957 if (GET_MODE (XEXP (op, 0)) == CC_NOOVmode 958 || GET_MODE (XEXP (op, 0)) == CCX_NOOVmode) 959 /* These are the only branches which work with CC_NOOVmode. */ 960 return (code == EQ || code == NE || code == GE || code == LT); 961 return 1; 962} 963 964/* Return 1 if this is a 64-bit comparison operator. This allows the use of 965 MATCH_OPERATOR to recognize all the branch insns. */ 966 967int 968noov_compare64_op (register rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) 969{ 970 enum rtx_code code = GET_CODE (op); 971 972 if (! TARGET_V9) 973 return 0; 974 975 if (GET_RTX_CLASS (code) != '<') 976 return 0; 977 978 if (GET_MODE (XEXP (op, 0)) == CCX_NOOVmode) 979 /* These are the only branches which work with CCX_NOOVmode. */ 980 return (code == EQ || code == NE || code == GE || code == LT); 981 return (GET_MODE (XEXP (op, 0)) == CCXmode); 982} 983 984/* Nonzero if OP is a comparison operator suitable for use in v9 985 conditional move or branch on register contents instructions. */ 986 987int 988v9_regcmp_op (register rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) 989{ 990 enum rtx_code code = GET_CODE (op); 991 992 if (GET_RTX_CLASS (code) != '<') 993 return 0; 994 995 return v9_regcmp_p (code); 996} 997 998/* Return 1 if this is a SIGN_EXTEND or ZERO_EXTEND operation. */ 999 1000int 1001extend_op (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) 1002{ 1003 return GET_CODE (op) == SIGN_EXTEND || GET_CODE (op) == ZERO_EXTEND; 1004} 1005 1006/* Return nonzero if OP is an operator of mode MODE which can set 1007 the condition codes explicitly. We do not include PLUS and MINUS 1008 because these require CC_NOOVmode, which we handle explicitly. */ 1009 1010int 1011cc_arithop (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) 1012{ 1013 if (GET_CODE (op) == AND 1014 || GET_CODE (op) == IOR 1015 || GET_CODE (op) == XOR) 1016 return 1; 1017 1018 return 0; 1019} 1020 1021/* Return nonzero if OP is an operator of mode MODE which can bitwise 1022 complement its second operand and set the condition codes explicitly. */ 1023 1024int 1025cc_arithopn (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) 1026{ 1027 /* XOR is not here because combine canonicalizes (xor (not ...) ...) 1028 and (xor ... (not ...)) to (not (xor ...)). */ 1029 return (GET_CODE (op) == AND 1030 || GET_CODE (op) == IOR); 1031} 1032 1033/* Return true if OP is a register, or is a CONST_INT that can fit in a 1034 signed 13 bit immediate field. This is an acceptable SImode operand for 1035 most 3 address instructions. */ 1036 1037int 1038arith_operand (rtx op, enum machine_mode mode) 1039{ 1040 if (register_operand (op, mode)) 1041 return 1; 1042 if (GET_CODE (op) != CONST_INT) 1043 return 0; 1044 return SMALL_INT32 (op); 1045} 1046 1047/* Return true if OP is a constant 4096 */ 1048 1049int 1050arith_4096_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) 1051{ 1052 if (GET_CODE (op) != CONST_INT) 1053 return 0; 1054 else 1055 return INTVAL (op) == 4096; 1056} 1057 1058/* Return true if OP is suitable as second operand for add/sub */ 1059 1060int 1061arith_add_operand (rtx op, enum machine_mode mode) 1062{ 1063 return arith_operand (op, mode) || arith_4096_operand (op, mode); 1064} 1065 1066/* Return true if OP is a CONST_INT or a CONST_DOUBLE which can fit in the 1067 immediate field of OR and XOR instructions. Used for 64-bit 1068 constant formation patterns. */ 1069int 1070const64_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) 1071{ 1072 return ((GET_CODE (op) == CONST_INT 1073 && SPARC_SIMM13_P (INTVAL (op))) 1074#if HOST_BITS_PER_WIDE_INT != 64 1075 || (GET_CODE (op) == CONST_DOUBLE 1076 && SPARC_SIMM13_P (CONST_DOUBLE_LOW (op)) 1077 && (CONST_DOUBLE_HIGH (op) == 1078 ((CONST_DOUBLE_LOW (op) & 0x80000000) != 0 ? 1079 (HOST_WIDE_INT)-1 : 0))) 1080#endif 1081 ); 1082} 1083 1084/* The same, but only for sethi instructions. */ 1085int 1086const64_high_operand (rtx op, enum machine_mode mode) 1087{ 1088 return ((GET_CODE (op) == CONST_INT 1089 && (INTVAL (op) & ~(HOST_WIDE_INT)0x3ff) != 0 1090 && SPARC_SETHI_P (INTVAL (op) & GET_MODE_MASK (mode)) 1091 ) 1092 || (GET_CODE (op) == CONST_DOUBLE 1093 && CONST_DOUBLE_HIGH (op) == 0 1094 && (CONST_DOUBLE_LOW (op) & ~(HOST_WIDE_INT)0x3ff) != 0 1095 && SPARC_SETHI_P (CONST_DOUBLE_LOW (op)))); 1096} 1097 1098/* Return true if OP is a register, or is a CONST_INT that can fit in a 1099 signed 11 bit immediate field. This is an acceptable SImode operand for 1100 the movcc instructions. */ 1101 1102int 1103arith11_operand (rtx op, enum machine_mode mode) 1104{ 1105 return (register_operand (op, mode) 1106 || (GET_CODE (op) == CONST_INT && SPARC_SIMM11_P (INTVAL (op)))); 1107} 1108 1109/* Return true if OP is a register, or is a CONST_INT that can fit in a 1110 signed 10 bit immediate field. This is an acceptable SImode operand for 1111 the movrcc instructions. */ 1112 1113int 1114arith10_operand (rtx op, enum machine_mode mode) 1115{ 1116 return (register_operand (op, mode) 1117 || (GET_CODE (op) == CONST_INT && SPARC_SIMM10_P (INTVAL (op)))); 1118} 1119 1120/* Return true if OP is a register, is a CONST_INT that fits in a 13 bit 1121 immediate field, or is a CONST_DOUBLE whose both parts fit in a 13 bit 1122 immediate field. 1123 v9: Return true if OP is a register, or is a CONST_INT or CONST_DOUBLE that 1124 can fit in a 13 bit immediate field. This is an acceptable DImode operand 1125 for most 3 address instructions. */ 1126 1127int 1128arith_double_operand (rtx op, enum machine_mode mode) 1129{ 1130 return (register_operand (op, mode) 1131 || (GET_CODE (op) == CONST_INT && SMALL_INT (op)) 1132 || (! TARGET_ARCH64 1133 && GET_CODE (op) == CONST_DOUBLE 1134 && (unsigned HOST_WIDE_INT) (CONST_DOUBLE_LOW (op) + 0x1000) < 0x2000 1135 && (unsigned HOST_WIDE_INT) (CONST_DOUBLE_HIGH (op) + 0x1000) < 0x2000) 1136 || (TARGET_ARCH64 1137 && GET_CODE (op) == CONST_DOUBLE 1138 && (unsigned HOST_WIDE_INT) (CONST_DOUBLE_LOW (op) + 0x1000) < 0x2000 1139 && ((CONST_DOUBLE_HIGH (op) == -1 1140 && (CONST_DOUBLE_LOW (op) & 0x1000) == 0x1000) 1141 || (CONST_DOUBLE_HIGH (op) == 0 1142 && (CONST_DOUBLE_LOW (op) & 0x1000) == 0)))); 1143} 1144 1145/* Return true if OP is a constant 4096 for DImode on ARCH64 */ 1146 1147int 1148arith_double_4096_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) 1149{ 1150 return (TARGET_ARCH64 && 1151 ((GET_CODE (op) == CONST_INT && INTVAL (op) == 4096) || 1152 (GET_CODE (op) == CONST_DOUBLE && 1153 CONST_DOUBLE_LOW (op) == 4096 && 1154 CONST_DOUBLE_HIGH (op) == 0))); 1155} 1156 1157/* Return true if OP is suitable as second operand for add/sub in DImode */ 1158 1159int 1160arith_double_add_operand (rtx op, enum machine_mode mode) 1161{ 1162 return arith_double_operand (op, mode) || arith_double_4096_operand (op, mode); 1163} 1164 1165/* Return true if OP is a register, or is a CONST_INT or CONST_DOUBLE that 1166 can fit in an 11 bit immediate field. This is an acceptable DImode 1167 operand for the movcc instructions. */ 1168/* ??? Replace with arith11_operand? */ 1169 1170int 1171arith11_double_operand (rtx op, enum machine_mode mode) 1172{ 1173 return (register_operand (op, mode) 1174 || (GET_CODE (op) == CONST_DOUBLE 1175 && (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode) 1176 && (unsigned HOST_WIDE_INT) (CONST_DOUBLE_LOW (op) + 0x400) < 0x800 1177 && ((CONST_DOUBLE_HIGH (op) == -1 1178 && (CONST_DOUBLE_LOW (op) & 0x400) == 0x400) 1179 || (CONST_DOUBLE_HIGH (op) == 0 1180 && (CONST_DOUBLE_LOW (op) & 0x400) == 0))) 1181 || (GET_CODE (op) == CONST_INT 1182 && (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode) 1183 && (unsigned HOST_WIDE_INT) (INTVAL (op) + 0x400) < 0x800)); 1184} 1185 1186/* Return true if OP is a register, or is a CONST_INT or CONST_DOUBLE that 1187 can fit in an 10 bit immediate field. This is an acceptable DImode 1188 operand for the movrcc instructions. */ 1189/* ??? Replace with arith10_operand? */ 1190 1191int 1192arith10_double_operand (rtx op, enum machine_mode mode) 1193{ 1194 return (register_operand (op, mode) 1195 || (GET_CODE (op) == CONST_DOUBLE 1196 && (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode) 1197 && (unsigned) (CONST_DOUBLE_LOW (op) + 0x200) < 0x400 1198 && ((CONST_DOUBLE_HIGH (op) == -1 1199 && (CONST_DOUBLE_LOW (op) & 0x200) == 0x200) 1200 || (CONST_DOUBLE_HIGH (op) == 0 1201 && (CONST_DOUBLE_LOW (op) & 0x200) == 0))) 1202 || (GET_CODE (op) == CONST_INT 1203 && (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode) 1204 && (unsigned HOST_WIDE_INT) (INTVAL (op) + 0x200) < 0x400)); 1205} 1206 1207/* Return truth value of whether OP is an integer which fits the 1208 range constraining immediate operands in most three-address insns, 1209 which have a 13 bit immediate field. */ 1210 1211int 1212small_int (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) 1213{ 1214 return (GET_CODE (op) == CONST_INT && SMALL_INT (op)); 1215} 1216 1217int 1218small_int_or_double (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) 1219{ 1220 return ((GET_CODE (op) == CONST_INT && SMALL_INT (op)) 1221 || (GET_CODE (op) == CONST_DOUBLE 1222 && CONST_DOUBLE_HIGH (op) == 0 1223 && SPARC_SIMM13_P (CONST_DOUBLE_LOW (op)))); 1224} 1225 1226/* Recognize operand values for the umul instruction. That instruction sign 1227 extends immediate values just like all other sparc instructions, but 1228 interprets the extended result as an unsigned number. */ 1229 1230int 1231uns_small_int (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) 1232{ 1233#if HOST_BITS_PER_WIDE_INT > 32 1234 /* All allowed constants will fit a CONST_INT. */ 1235 return (GET_CODE (op) == CONST_INT 1236 && ((INTVAL (op) >= 0 && INTVAL (op) < 0x1000) 1237 || (INTVAL (op) >= 0xFFFFF000 1238 && INTVAL (op) <= 0xFFFFFFFF))); 1239#else 1240 return ((GET_CODE (op) == CONST_INT && (unsigned) INTVAL (op) < 0x1000) 1241 || (GET_CODE (op) == CONST_DOUBLE 1242 && CONST_DOUBLE_HIGH (op) == 0 1243 && (unsigned) CONST_DOUBLE_LOW (op) - 0xFFFFF000 < 0x1000)); 1244#endif 1245} 1246 1247int 1248uns_arith_operand (rtx op, enum machine_mode mode) 1249{ 1250 return register_operand (op, mode) || uns_small_int (op, mode); 1251} 1252 1253/* Return truth value of statement that OP is a call-clobbered register. */ 1254int 1255clobbered_register (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) 1256{ 1257 return (GET_CODE (op) == REG && call_used_regs[REGNO (op)]); 1258} 1259 1260/* Return 1 if OP is a valid operand for the source of a move insn. */ 1261 1262int 1263input_operand (rtx op, enum machine_mode mode) 1264{ 1265 /* If both modes are non-void they must be the same. */ 1266 if (mode != VOIDmode && GET_MODE (op) != VOIDmode && mode != GET_MODE (op)) 1267 return 0; 1268 1269 /* Accept CONSTANT_P_RTX, since it will be gone by CSE1 and result in 0/1. */ 1270 if (GET_CODE (op) == CONSTANT_P_RTX) 1271 return 1; 1272 1273 /* Allow any one instruction integer constant, and all CONST_INT 1274 variants when we are working in DImode and !arch64. */ 1275 if (GET_MODE_CLASS (mode) == MODE_INT 1276 && ((GET_CODE (op) == CONST_INT 1277 && (SPARC_SETHI_P (INTVAL (op) & GET_MODE_MASK (mode)) 1278 || SPARC_SIMM13_P (INTVAL (op)) 1279 || (mode == DImode 1280 && ! TARGET_ARCH64))) 1281 || (TARGET_ARCH64 1282 && GET_CODE (op) == CONST_DOUBLE 1283 && ((CONST_DOUBLE_HIGH (op) == 0 1284 && SPARC_SETHI_P (CONST_DOUBLE_LOW (op))) 1285 || 1286#if HOST_BITS_PER_WIDE_INT == 64 1287 (CONST_DOUBLE_HIGH (op) == 0 1288 && SPARC_SIMM13_P (CONST_DOUBLE_LOW (op))) 1289#else 1290 (SPARC_SIMM13_P (CONST_DOUBLE_LOW (op)) 1291 && (((CONST_DOUBLE_LOW (op) & 0x80000000) == 0 1292 && CONST_DOUBLE_HIGH (op) == 0) 1293 || (CONST_DOUBLE_HIGH (op) == -1 1294 && CONST_DOUBLE_LOW (op) & 0x80000000) != 0)) 1295#endif 1296 )))) 1297 return 1; 1298 1299 /* If !arch64 and this is a DImode const, allow it so that 1300 the splits can be generated. */ 1301 if (! TARGET_ARCH64 1302 && mode == DImode 1303 && GET_CODE (op) == CONST_DOUBLE) 1304 return 1; 1305 1306 if (register_operand (op, mode)) 1307 return 1; 1308 1309 if (GET_MODE_CLASS (mode) == MODE_FLOAT 1310 && GET_CODE (op) == CONST_DOUBLE) 1311 return 1; 1312 1313 /* If this is a SUBREG, look inside so that we handle 1314 paradoxical ones. */ 1315 if (GET_CODE (op) == SUBREG) 1316 op = SUBREG_REG (op); 1317 1318 /* Check for valid MEM forms. */ 1319 if (GET_CODE (op) == MEM) 1320 return memory_address_p (mode, XEXP (op, 0)); 1321 1322 return 0; 1323} 1324 1325/* Return 1 if OP is valid for the lhs of a compare insn. */ 1326 1327int 1328compare_operand (rtx op, enum machine_mode mode) 1329{ 1330 if (GET_CODE (op) == ZERO_EXTRACT) 1331 return (register_operand (XEXP (op, 0), mode) 1332 && small_int_or_double (XEXP (op, 1), mode) 1333 && small_int_or_double (XEXP (op, 2), mode) 1334 /* This matches cmp_zero_extract. */ 1335 && ((mode == SImode 1336 && ((GET_CODE (XEXP (op, 2)) == CONST_INT 1337 && INTVAL (XEXP (op, 2)) > 19) 1338 || (GET_CODE (XEXP (op, 2)) == CONST_DOUBLE 1339 && CONST_DOUBLE_LOW (XEXP (op, 2)) > 19))) 1340 /* This matches cmp_zero_extract_sp64. */ 1341 || (mode == DImode 1342 && TARGET_ARCH64 1343 && ((GET_CODE (XEXP (op, 2)) == CONST_INT 1344 && INTVAL (XEXP (op, 2)) > 51) 1345 || (GET_CODE (XEXP (op, 2)) == CONST_DOUBLE 1346 && CONST_DOUBLE_LOW (XEXP (op, 2)) > 51))))); 1347 else 1348 return register_operand (op, mode); 1349} 1350 1351 1352/* We know it can't be done in one insn when we get here, 1353 the movsi expander guarantees this. */ 1354void 1355sparc_emit_set_const32 (rtx op0, rtx op1) 1356{ 1357 enum machine_mode mode = GET_MODE (op0); 1358 rtx temp; 1359 1360 if (GET_CODE (op1) == CONST_INT) 1361 { 1362 HOST_WIDE_INT value = INTVAL (op1); 1363 1364 if (SPARC_SETHI_P (value & GET_MODE_MASK (mode)) 1365 || SPARC_SIMM13_P (value)) 1366 abort (); 1367 } 1368 1369 /* Full 2-insn decomposition is needed. */ 1370 if (reload_in_progress || reload_completed) 1371 temp = op0; 1372 else 1373 temp = gen_reg_rtx (mode); 1374 1375 if (GET_CODE (op1) == CONST_INT) 1376 { 1377 /* Emit them as real moves instead of a HIGH/LO_SUM, 1378 this way CSE can see everything and reuse intermediate 1379 values if it wants. */ 1380 if (TARGET_ARCH64 1381 && HOST_BITS_PER_WIDE_INT != 64 1382 && (INTVAL (op1) & 0x80000000) != 0) 1383 emit_insn (gen_rtx_SET 1384 (VOIDmode, temp, 1385 immed_double_const (INTVAL (op1) & ~(HOST_WIDE_INT)0x3ff, 1386 0, DImode))); 1387 else 1388 emit_insn (gen_rtx_SET (VOIDmode, temp, 1389 GEN_INT (INTVAL (op1) 1390 & ~(HOST_WIDE_INT)0x3ff))); 1391 1392 emit_insn (gen_rtx_SET (VOIDmode, 1393 op0, 1394 gen_rtx_IOR (mode, temp, 1395 GEN_INT (INTVAL (op1) & 0x3ff)))); 1396 } 1397 else 1398 { 1399 /* A symbol, emit in the traditional way. */ 1400 emit_insn (gen_rtx_SET (VOIDmode, temp, 1401 gen_rtx_HIGH (mode, op1))); 1402 emit_insn (gen_rtx_SET (VOIDmode, 1403 op0, gen_rtx_LO_SUM (mode, temp, op1))); 1404 1405 } 1406} 1407 1408 1409/* Load OP1, a symbolic 64-bit constant, into OP0, a DImode register. 1410 If TEMP is non-zero, we are forbidden to use any other scratch 1411 registers. Otherwise, we are allowed to generate them as needed. 1412 1413 Note that TEMP may have TImode if the code model is TARGET_CM_MEDANY 1414 or TARGET_CM_EMBMEDANY (see the reload_indi and reload_outdi patterns). */ 1415void 1416sparc_emit_set_symbolic_const64 (rtx op0, rtx op1, rtx temp) 1417{ 1418 rtx temp1, temp2, temp3, temp4, temp5; 1419 rtx ti_temp = 0; 1420 1421 if (temp && GET_MODE (temp) == TImode) 1422 { 1423 ti_temp = temp; 1424 temp = gen_rtx_REG (DImode, REGNO (temp)); 1425 } 1426 1427 /* SPARC-V9 code-model support. */ 1428 switch (sparc_cmodel) 1429 { 1430 case CM_MEDLOW: 1431 /* The range spanned by all instructions in the object is less 1432 than 2^31 bytes (2GB) and the distance from any instruction 1433 to the location of the label _GLOBAL_OFFSET_TABLE_ is less 1434 than 2^31 bytes (2GB). 1435 1436 The executable must be in the low 4TB of the virtual address 1437 space. 1438 1439 sethi %hi(symbol), %temp1 1440 or %temp1, %lo(symbol), %reg */ 1441 if (temp) 1442 temp1 = temp; /* op0 is allowed. */ 1443 else 1444 temp1 = gen_reg_rtx (DImode); 1445 1446 emit_insn (gen_rtx_SET (VOIDmode, temp1, gen_rtx_HIGH (DImode, op1))); 1447 emit_insn (gen_rtx_SET (VOIDmode, op0, gen_rtx_LO_SUM (DImode, temp1, op1))); 1448 break; 1449 1450 case CM_MEDMID: 1451 /* The range spanned by all instructions in the object is less 1452 than 2^31 bytes (2GB) and the distance from any instruction 1453 to the location of the label _GLOBAL_OFFSET_TABLE_ is less 1454 than 2^31 bytes (2GB). 1455 1456 The executable must be in the low 16TB of the virtual address 1457 space. 1458 1459 sethi %h44(symbol), %temp1 1460 or %temp1, %m44(symbol), %temp2 1461 sllx %temp2, 12, %temp3 1462 or %temp3, %l44(symbol), %reg */ 1463 if (temp) 1464 { 1465 temp1 = op0; 1466 temp2 = op0; 1467 temp3 = temp; /* op0 is allowed. */ 1468 } 1469 else 1470 { 1471 temp1 = gen_reg_rtx (DImode); 1472 temp2 = gen_reg_rtx (DImode); 1473 temp3 = gen_reg_rtx (DImode); 1474 } 1475 1476 emit_insn (gen_seth44 (temp1, op1)); 1477 emit_insn (gen_setm44 (temp2, temp1, op1)); 1478 emit_insn (gen_rtx_SET (VOIDmode, temp3, 1479 gen_rtx_ASHIFT (DImode, temp2, GEN_INT (12)))); 1480 emit_insn (gen_setl44 (op0, temp3, op1)); 1481 break; 1482 1483 case CM_MEDANY: 1484 /* The range spanned by all instructions in the object is less 1485 than 2^31 bytes (2GB) and the distance from any instruction 1486 to the location of the label _GLOBAL_OFFSET_TABLE_ is less 1487 than 2^31 bytes (2GB). 1488 1489 The executable can be placed anywhere in the virtual address 1490 space. 1491 1492 sethi %hh(symbol), %temp1 1493 sethi %lm(symbol), %temp2 1494 or %temp1, %hm(symbol), %temp3 1495 sllx %temp3, 32, %temp4 1496 or %temp4, %temp2, %temp5 1497 or %temp5, %lo(symbol), %reg */ 1498 if (temp) 1499 { 1500 /* It is possible that one of the registers we got for operands[2] 1501 might coincide with that of operands[0] (which is why we made 1502 it TImode). Pick the other one to use as our scratch. */ 1503 if (rtx_equal_p (temp, op0)) 1504 { 1505 if (ti_temp) 1506 temp = gen_rtx_REG (DImode, REGNO (temp) + 1); 1507 else 1508 abort(); 1509 } 1510 temp1 = op0; 1511 temp2 = temp; /* op0 is _not_ allowed, see above. */ 1512 temp3 = op0; 1513 temp4 = op0; 1514 temp5 = op0; 1515 } 1516 else 1517 { 1518 temp1 = gen_reg_rtx (DImode); 1519 temp2 = gen_reg_rtx (DImode); 1520 temp3 = gen_reg_rtx (DImode); 1521 temp4 = gen_reg_rtx (DImode); 1522 temp5 = gen_reg_rtx (DImode); 1523 } 1524 1525 emit_insn (gen_sethh (temp1, op1)); 1526 emit_insn (gen_setlm (temp2, op1)); 1527 emit_insn (gen_sethm (temp3, temp1, op1)); 1528 emit_insn (gen_rtx_SET (VOIDmode, temp4, 1529 gen_rtx_ASHIFT (DImode, temp3, GEN_INT (32)))); 1530 emit_insn (gen_rtx_SET (VOIDmode, temp5, 1531 gen_rtx_PLUS (DImode, temp4, temp2))); 1532 emit_insn (gen_setlo (op0, temp5, op1)); 1533 break; 1534 1535 case CM_EMBMEDANY: 1536 /* Old old old backwards compatibility kruft here. 1537 Essentially it is MEDLOW with a fixed 64-bit 1538 virtual base added to all data segment addresses. 1539 Text-segment stuff is computed like MEDANY, we can't 1540 reuse the code above because the relocation knobs 1541 look different. 1542 1543 Data segment: sethi %hi(symbol), %temp1 1544 add %temp1, EMBMEDANY_BASE_REG, %temp2 1545 or %temp2, %lo(symbol), %reg */ 1546 if (data_segment_operand (op1, GET_MODE (op1))) 1547 { 1548 if (temp) 1549 { 1550 temp1 = temp; /* op0 is allowed. */ 1551 temp2 = op0; 1552 } 1553 else 1554 { 1555 temp1 = gen_reg_rtx (DImode); 1556 temp2 = gen_reg_rtx (DImode); 1557 } 1558 1559 emit_insn (gen_embmedany_sethi (temp1, op1)); 1560 emit_insn (gen_embmedany_brsum (temp2, temp1)); 1561 emit_insn (gen_embmedany_losum (op0, temp2, op1)); 1562 } 1563 1564 /* Text segment: sethi %uhi(symbol), %temp1 1565 sethi %hi(symbol), %temp2 1566 or %temp1, %ulo(symbol), %temp3 1567 sllx %temp3, 32, %temp4 1568 or %temp4, %temp2, %temp5 1569 or %temp5, %lo(symbol), %reg */ 1570 else 1571 { 1572 if (temp) 1573 { 1574 /* It is possible that one of the registers we got for operands[2] 1575 might coincide with that of operands[0] (which is why we made 1576 it TImode). Pick the other one to use as our scratch. */ 1577 if (rtx_equal_p (temp, op0)) 1578 { 1579 if (ti_temp) 1580 temp = gen_rtx_REG (DImode, REGNO (temp) + 1); 1581 else 1582 abort(); 1583 } 1584 temp1 = op0; 1585 temp2 = temp; /* op0 is _not_ allowed, see above. */ 1586 temp3 = op0; 1587 temp4 = op0; 1588 temp5 = op0; 1589 } 1590 else 1591 { 1592 temp1 = gen_reg_rtx (DImode); 1593 temp2 = gen_reg_rtx (DImode); 1594 temp3 = gen_reg_rtx (DImode); 1595 temp4 = gen_reg_rtx (DImode); 1596 temp5 = gen_reg_rtx (DImode); 1597 } 1598 1599 emit_insn (gen_embmedany_textuhi (temp1, op1)); 1600 emit_insn (gen_embmedany_texthi (temp2, op1)); 1601 emit_insn (gen_embmedany_textulo (temp3, temp1, op1)); 1602 emit_insn (gen_rtx_SET (VOIDmode, temp4, 1603 gen_rtx_ASHIFT (DImode, temp3, GEN_INT (32)))); 1604 emit_insn (gen_rtx_SET (VOIDmode, temp5, 1605 gen_rtx_PLUS (DImode, temp4, temp2))); 1606 emit_insn (gen_embmedany_textlo (op0, temp5, op1)); 1607 } 1608 break; 1609 1610 default: 1611 abort(); 1612 } 1613} 1614 1615/* These avoid problems when cross compiling. If we do not 1616 go through all this hair then the optimizer will see 1617 invalid REG_EQUAL notes or in some cases none at all. */ 1618static void sparc_emit_set_safe_HIGH64 (rtx, HOST_WIDE_INT); 1619static rtx gen_safe_SET64 (rtx, HOST_WIDE_INT); 1620static rtx gen_safe_OR64 (rtx, HOST_WIDE_INT); 1621static rtx gen_safe_XOR64 (rtx, HOST_WIDE_INT); 1622 1623#if HOST_BITS_PER_WIDE_INT == 64 1624#define GEN_HIGHINT64(__x) GEN_INT ((__x) & ~(HOST_WIDE_INT)0x3ff) 1625#define GEN_INT64(__x) GEN_INT (__x) 1626#else 1627#define GEN_HIGHINT64(__x) \ 1628 immed_double_const ((__x) & ~(HOST_WIDE_INT)0x3ff, 0, DImode) 1629#define GEN_INT64(__x) \ 1630 immed_double_const ((__x) & 0xffffffff, \ 1631 ((__x) & 0x80000000 ? -1 : 0), DImode) 1632#endif 1633 1634/* The optimizer is not to assume anything about exactly 1635 which bits are set for a HIGH, they are unspecified. 1636 Unfortunately this leads to many missed optimizations 1637 during CSE. We mask out the non-HIGH bits, and matches 1638 a plain movdi, to alleviate this problem. */ 1639static void 1640sparc_emit_set_safe_HIGH64 (rtx dest, HOST_WIDE_INT val) 1641{ 1642 emit_insn (gen_rtx_SET (VOIDmode, dest, GEN_HIGHINT64 (val))); 1643} 1644 1645static rtx 1646gen_safe_SET64 (rtx dest, HOST_WIDE_INT val) 1647{ 1648 return gen_rtx_SET (VOIDmode, dest, GEN_INT64 (val)); 1649} 1650 1651static rtx 1652gen_safe_OR64 (rtx src, HOST_WIDE_INT val) 1653{ 1654 return gen_rtx_IOR (DImode, src, GEN_INT64 (val)); 1655} 1656 1657static rtx 1658gen_safe_XOR64 (rtx src, HOST_WIDE_INT val) 1659{ 1660 return gen_rtx_XOR (DImode, src, GEN_INT64 (val)); 1661} 1662 1663/* Worker routines for 64-bit constant formation on arch64. 1664 One of the key things to be doing in these emissions is 1665 to create as many temp REGs as possible. This makes it 1666 possible for half-built constants to be used later when 1667 such values are similar to something required later on. 1668 Without doing this, the optimizer cannot see such 1669 opportunities. */ 1670 1671static void sparc_emit_set_const64_quick1 (rtx, rtx, 1672 unsigned HOST_WIDE_INT, int); 1673 1674static void 1675sparc_emit_set_const64_quick1 (rtx op0, rtx temp, 1676 unsigned HOST_WIDE_INT low_bits, int is_neg) 1677{ 1678 unsigned HOST_WIDE_INT high_bits; 1679 1680 if (is_neg) 1681 high_bits = (~low_bits) & 0xffffffff; 1682 else 1683 high_bits = low_bits; 1684 1685 sparc_emit_set_safe_HIGH64 (temp, high_bits); 1686 if (!is_neg) 1687 { 1688 emit_insn (gen_rtx_SET (VOIDmode, op0, 1689 gen_safe_OR64 (temp, (high_bits & 0x3ff)))); 1690 } 1691 else 1692 { 1693 /* If we are XOR'ing with -1, then we should emit a one's complement 1694 instead. This way the combiner will notice logical operations 1695 such as ANDN later on and substitute. */ 1696 if ((low_bits & 0x3ff) == 0x3ff) 1697 { 1698 emit_insn (gen_rtx_SET (VOIDmode, op0, 1699 gen_rtx_NOT (DImode, temp))); 1700 } 1701 else 1702 { 1703 emit_insn (gen_rtx_SET (VOIDmode, op0, 1704 gen_safe_XOR64 (temp, 1705 (-(HOST_WIDE_INT)0x400 1706 | (low_bits & 0x3ff))))); 1707 } 1708 } 1709} 1710 1711static void sparc_emit_set_const64_quick2 (rtx, rtx, unsigned HOST_WIDE_INT, 1712 unsigned HOST_WIDE_INT, int); 1713 1714static void 1715sparc_emit_set_const64_quick2 (rtx op0, rtx temp, 1716 unsigned HOST_WIDE_INT high_bits, 1717 unsigned HOST_WIDE_INT low_immediate, 1718 int shift_count) 1719{ 1720 rtx temp2 = op0; 1721 1722 if ((high_bits & 0xfffffc00) != 0) 1723 { 1724 sparc_emit_set_safe_HIGH64 (temp, high_bits); 1725 if ((high_bits & ~0xfffffc00) != 0) 1726 emit_insn (gen_rtx_SET (VOIDmode, op0, 1727 gen_safe_OR64 (temp, (high_bits & 0x3ff)))); 1728 else 1729 temp2 = temp; 1730 } 1731 else 1732 { 1733 emit_insn (gen_safe_SET64 (temp, high_bits)); 1734 temp2 = temp; 1735 } 1736 1737 /* Now shift it up into place. */ 1738 emit_insn (gen_rtx_SET (VOIDmode, op0, 1739 gen_rtx_ASHIFT (DImode, temp2, 1740 GEN_INT (shift_count)))); 1741 1742 /* If there is a low immediate part piece, finish up by 1743 putting that in as well. */ 1744 if (low_immediate != 0) 1745 emit_insn (gen_rtx_SET (VOIDmode, op0, 1746 gen_safe_OR64 (op0, low_immediate))); 1747} 1748 1749static void sparc_emit_set_const64_longway (rtx, rtx, unsigned HOST_WIDE_INT, 1750 unsigned HOST_WIDE_INT); 1751 1752/* Full 64-bit constant decomposition. Even though this is the 1753 'worst' case, we still optimize a few things away. */ 1754static void 1755sparc_emit_set_const64_longway (rtx op0, rtx temp, 1756 unsigned HOST_WIDE_INT high_bits, 1757 unsigned HOST_WIDE_INT low_bits) 1758{ 1759 rtx sub_temp; 1760 1761 if (reload_in_progress || reload_completed) 1762 sub_temp = op0; 1763 else 1764 sub_temp = gen_reg_rtx (DImode); 1765 1766 if ((high_bits & 0xfffffc00) != 0) 1767 { 1768 sparc_emit_set_safe_HIGH64 (temp, high_bits); 1769 if ((high_bits & ~0xfffffc00) != 0) 1770 emit_insn (gen_rtx_SET (VOIDmode, 1771 sub_temp, 1772 gen_safe_OR64 (temp, (high_bits & 0x3ff)))); 1773 else 1774 sub_temp = temp; 1775 } 1776 else 1777 { 1778 emit_insn (gen_safe_SET64 (temp, high_bits)); 1779 sub_temp = temp; 1780 } 1781 1782 if (!reload_in_progress && !reload_completed) 1783 { 1784 rtx temp2 = gen_reg_rtx (DImode); 1785 rtx temp3 = gen_reg_rtx (DImode); 1786 rtx temp4 = gen_reg_rtx (DImode); 1787 1788 emit_insn (gen_rtx_SET (VOIDmode, temp4, 1789 gen_rtx_ASHIFT (DImode, sub_temp, 1790 GEN_INT (32)))); 1791 1792 sparc_emit_set_safe_HIGH64 (temp2, low_bits); 1793 if ((low_bits & ~0xfffffc00) != 0) 1794 { 1795 emit_insn (gen_rtx_SET (VOIDmode, temp3, 1796 gen_safe_OR64 (temp2, (low_bits & 0x3ff)))); 1797 emit_insn (gen_rtx_SET (VOIDmode, op0, 1798 gen_rtx_PLUS (DImode, temp4, temp3))); 1799 } 1800 else 1801 { 1802 emit_insn (gen_rtx_SET (VOIDmode, op0, 1803 gen_rtx_PLUS (DImode, temp4, temp2))); 1804 } 1805 } 1806 else 1807 { 1808 rtx low1 = GEN_INT ((low_bits >> (32 - 12)) & 0xfff); 1809 rtx low2 = GEN_INT ((low_bits >> (32 - 12 - 12)) & 0xfff); 1810 rtx low3 = GEN_INT ((low_bits >> (32 - 12 - 12 - 8)) & 0x0ff); 1811 int to_shift = 12; 1812 1813 /* We are in the middle of reload, so this is really 1814 painful. However we do still make an attempt to 1815 avoid emitting truly stupid code. */ 1816 if (low1 != const0_rtx) 1817 { 1818 emit_insn (gen_rtx_SET (VOIDmode, op0, 1819 gen_rtx_ASHIFT (DImode, sub_temp, 1820 GEN_INT (to_shift)))); 1821 emit_insn (gen_rtx_SET (VOIDmode, op0, 1822 gen_rtx_IOR (DImode, op0, low1))); 1823 sub_temp = op0; 1824 to_shift = 12; 1825 } 1826 else 1827 { 1828 to_shift += 12; 1829 } 1830 if (low2 != const0_rtx) 1831 { 1832 emit_insn (gen_rtx_SET (VOIDmode, op0, 1833 gen_rtx_ASHIFT (DImode, sub_temp, 1834 GEN_INT (to_shift)))); 1835 emit_insn (gen_rtx_SET (VOIDmode, op0, 1836 gen_rtx_IOR (DImode, op0, low2))); 1837 sub_temp = op0; 1838 to_shift = 8; 1839 } 1840 else 1841 { 1842 to_shift += 8; 1843 } 1844 emit_insn (gen_rtx_SET (VOIDmode, op0, 1845 gen_rtx_ASHIFT (DImode, sub_temp, 1846 GEN_INT (to_shift)))); 1847 if (low3 != const0_rtx) 1848 emit_insn (gen_rtx_SET (VOIDmode, op0, 1849 gen_rtx_IOR (DImode, op0, low3))); 1850 /* phew... */ 1851 } 1852} 1853 1854/* Analyze a 64-bit constant for certain properties. */ 1855static void analyze_64bit_constant (unsigned HOST_WIDE_INT, 1856 unsigned HOST_WIDE_INT, 1857 int *, int *, int *); 1858 1859static void 1860analyze_64bit_constant (unsigned HOST_WIDE_INT high_bits, 1861 unsigned HOST_WIDE_INT low_bits, 1862 int *hbsp, int *lbsp, int *abbasp) 1863{ 1864 int lowest_bit_set, highest_bit_set, all_bits_between_are_set; 1865 int i; 1866 1867 lowest_bit_set = highest_bit_set = -1; 1868 i = 0; 1869 do 1870 { 1871 if ((lowest_bit_set == -1) 1872 && ((low_bits >> i) & 1)) 1873 lowest_bit_set = i; 1874 if ((highest_bit_set == -1) 1875 && ((high_bits >> (32 - i - 1)) & 1)) 1876 highest_bit_set = (64 - i - 1); 1877 } 1878 while (++i < 32 1879 && ((highest_bit_set == -1) 1880 || (lowest_bit_set == -1))); 1881 if (i == 32) 1882 { 1883 i = 0; 1884 do 1885 { 1886 if ((lowest_bit_set == -1) 1887 && ((high_bits >> i) & 1)) 1888 lowest_bit_set = i + 32; 1889 if ((highest_bit_set == -1) 1890 && ((low_bits >> (32 - i - 1)) & 1)) 1891 highest_bit_set = 32 - i - 1; 1892 } 1893 while (++i < 32 1894 && ((highest_bit_set == -1) 1895 || (lowest_bit_set == -1))); 1896 } 1897 /* If there are no bits set this should have gone out 1898 as one instruction! */ 1899 if (lowest_bit_set == -1 1900 || highest_bit_set == -1) 1901 abort (); 1902 all_bits_between_are_set = 1; 1903 for (i = lowest_bit_set; i <= highest_bit_set; i++) 1904 { 1905 if (i < 32) 1906 { 1907 if ((low_bits & (1 << i)) != 0) 1908 continue; 1909 } 1910 else 1911 { 1912 if ((high_bits & (1 << (i - 32))) != 0) 1913 continue; 1914 } 1915 all_bits_between_are_set = 0; 1916 break; 1917 } 1918 *hbsp = highest_bit_set; 1919 *lbsp = lowest_bit_set; 1920 *abbasp = all_bits_between_are_set; 1921} 1922 1923static int const64_is_2insns (unsigned HOST_WIDE_INT, unsigned HOST_WIDE_INT); 1924 1925static int 1926const64_is_2insns (unsigned HOST_WIDE_INT high_bits, 1927 unsigned HOST_WIDE_INT low_bits) 1928{ 1929 int highest_bit_set, lowest_bit_set, all_bits_between_are_set; 1930 1931 if (high_bits == 0 1932 || high_bits == 0xffffffff) 1933 return 1; 1934 1935 analyze_64bit_constant (high_bits, low_bits, 1936 &highest_bit_set, &lowest_bit_set, 1937 &all_bits_between_are_set); 1938 1939 if ((highest_bit_set == 63 1940 || lowest_bit_set == 0) 1941 && all_bits_between_are_set != 0) 1942 return 1; 1943 1944 if ((highest_bit_set - lowest_bit_set) < 21) 1945 return 1; 1946 1947 return 0; 1948} 1949 1950static unsigned HOST_WIDE_INT create_simple_focus_bits (unsigned HOST_WIDE_INT, 1951 unsigned HOST_WIDE_INT, 1952 int, int); 1953 1954static unsigned HOST_WIDE_INT 1955create_simple_focus_bits (unsigned HOST_WIDE_INT high_bits, 1956 unsigned HOST_WIDE_INT low_bits, 1957 int lowest_bit_set, int shift) 1958{ 1959 HOST_WIDE_INT hi, lo; 1960 1961 if (lowest_bit_set < 32) 1962 { 1963 lo = (low_bits >> lowest_bit_set) << shift; 1964 hi = ((high_bits << (32 - lowest_bit_set)) << shift); 1965 } 1966 else 1967 { 1968 lo = 0; 1969 hi = ((high_bits >> (lowest_bit_set - 32)) << shift); 1970 } 1971 if (hi & lo) 1972 abort (); 1973 return (hi | lo); 1974} 1975 1976/* Here we are sure to be arch64 and this is an integer constant 1977 being loaded into a register. Emit the most efficient 1978 insn sequence possible. Detection of all the 1-insn cases 1979 has been done already. */ 1980void 1981sparc_emit_set_const64 (rtx op0, rtx op1) 1982{ 1983 unsigned HOST_WIDE_INT high_bits, low_bits; 1984 int lowest_bit_set, highest_bit_set; 1985 int all_bits_between_are_set; 1986 rtx temp = 0; 1987 1988 /* Sanity check that we know what we are working with. */ 1989 if (! TARGET_ARCH64) 1990 abort (); 1991 1992 if (GET_CODE (op0) != SUBREG) 1993 { 1994 if (GET_CODE (op0) != REG 1995 || (REGNO (op0) >= SPARC_FIRST_FP_REG 1996 && REGNO (op0) <= SPARC_LAST_V9_FP_REG)) 1997 abort (); 1998 } 1999 2000 if (reload_in_progress || reload_completed) 2001 temp = op0; 2002 2003 if (GET_CODE (op1) != CONST_DOUBLE 2004 && GET_CODE (op1) != CONST_INT) 2005 { 2006 sparc_emit_set_symbolic_const64 (op0, op1, temp); 2007 return; 2008 } 2009 2010 if (! temp) 2011 temp = gen_reg_rtx (DImode); 2012 2013 if (GET_CODE (op1) == CONST_DOUBLE) 2014 { 2015#if HOST_BITS_PER_WIDE_INT == 64 2016 high_bits = (CONST_DOUBLE_LOW (op1) >> 32) & 0xffffffff; 2017 low_bits = CONST_DOUBLE_LOW (op1) & 0xffffffff; 2018#else 2019 high_bits = CONST_DOUBLE_HIGH (op1); 2020 low_bits = CONST_DOUBLE_LOW (op1); 2021#endif 2022 } 2023 else 2024 { 2025#if HOST_BITS_PER_WIDE_INT == 64 2026 high_bits = ((INTVAL (op1) >> 32) & 0xffffffff); 2027 low_bits = (INTVAL (op1) & 0xffffffff); 2028#else 2029 high_bits = ((INTVAL (op1) < 0) ? 2030 0xffffffff : 2031 0x00000000); 2032 low_bits = INTVAL (op1); 2033#endif 2034 } 2035 2036 /* low_bits bits 0 --> 31 2037 high_bits bits 32 --> 63 */ 2038 2039 analyze_64bit_constant (high_bits, low_bits, 2040 &highest_bit_set, &lowest_bit_set, 2041 &all_bits_between_are_set); 2042 2043 /* First try for a 2-insn sequence. */ 2044 2045 /* These situations are preferred because the optimizer can 2046 * do more things with them: 2047 * 1) mov -1, %reg 2048 * sllx %reg, shift, %reg 2049 * 2) mov -1, %reg 2050 * srlx %reg, shift, %reg 2051 * 3) mov some_small_const, %reg 2052 * sllx %reg, shift, %reg 2053 */ 2054 if (((highest_bit_set == 63 2055 || lowest_bit_set == 0) 2056 && all_bits_between_are_set != 0) 2057 || ((highest_bit_set - lowest_bit_set) < 12)) 2058 { 2059 HOST_WIDE_INT the_const = -1; 2060 int shift = lowest_bit_set; 2061 2062 if ((highest_bit_set != 63 2063 && lowest_bit_set != 0) 2064 || all_bits_between_are_set == 0) 2065 { 2066 the_const = 2067 create_simple_focus_bits (high_bits, low_bits, 2068 lowest_bit_set, 0); 2069 } 2070 else if (lowest_bit_set == 0) 2071 shift = -(63 - highest_bit_set); 2072 2073 if (! SPARC_SIMM13_P (the_const)) 2074 abort (); 2075 2076 emit_insn (gen_safe_SET64 (temp, the_const)); 2077 if (shift > 0) 2078 emit_insn (gen_rtx_SET (VOIDmode, 2079 op0, 2080 gen_rtx_ASHIFT (DImode, 2081 temp, 2082 GEN_INT (shift)))); 2083 else if (shift < 0) 2084 emit_insn (gen_rtx_SET (VOIDmode, 2085 op0, 2086 gen_rtx_LSHIFTRT (DImode, 2087 temp, 2088 GEN_INT (-shift)))); 2089 else 2090 abort (); 2091 return; 2092 } 2093 2094 /* Now a range of 22 or less bits set somewhere. 2095 * 1) sethi %hi(focus_bits), %reg 2096 * sllx %reg, shift, %reg 2097 * 2) sethi %hi(focus_bits), %reg 2098 * srlx %reg, shift, %reg 2099 */ 2100 if ((highest_bit_set - lowest_bit_set) < 21) 2101 { 2102 unsigned HOST_WIDE_INT focus_bits = 2103 create_simple_focus_bits (high_bits, low_bits, 2104 lowest_bit_set, 10); 2105 2106 if (! SPARC_SETHI_P (focus_bits)) 2107 abort (); 2108 2109 sparc_emit_set_safe_HIGH64 (temp, focus_bits); 2110 2111 /* If lowest_bit_set == 10 then a sethi alone could have done it. */ 2112 if (lowest_bit_set < 10) 2113 emit_insn (gen_rtx_SET (VOIDmode, 2114 op0, 2115 gen_rtx_LSHIFTRT (DImode, temp, 2116 GEN_INT (10 - lowest_bit_set)))); 2117 else if (lowest_bit_set > 10) 2118 emit_insn (gen_rtx_SET (VOIDmode, 2119 op0, 2120 gen_rtx_ASHIFT (DImode, temp, 2121 GEN_INT (lowest_bit_set - 10)))); 2122 else 2123 abort (); 2124 return; 2125 } 2126 2127 /* 1) sethi %hi(low_bits), %reg 2128 * or %reg, %lo(low_bits), %reg 2129 * 2) sethi %hi(~low_bits), %reg 2130 * xor %reg, %lo(-0x400 | (low_bits & 0x3ff)), %reg 2131 */ 2132 if (high_bits == 0 2133 || high_bits == 0xffffffff) 2134 { 2135 sparc_emit_set_const64_quick1 (op0, temp, low_bits, 2136 (high_bits == 0xffffffff)); 2137 return; 2138 } 2139 2140 /* Now, try 3-insn sequences. */ 2141 2142 /* 1) sethi %hi(high_bits), %reg 2143 * or %reg, %lo(high_bits), %reg 2144 * sllx %reg, 32, %reg 2145 */ 2146 if (low_bits == 0) 2147 { 2148 sparc_emit_set_const64_quick2 (op0, temp, high_bits, 0, 32); 2149 return; 2150 } 2151 2152 /* We may be able to do something quick 2153 when the constant is negated, so try that. */ 2154 if (const64_is_2insns ((~high_bits) & 0xffffffff, 2155 (~low_bits) & 0xfffffc00)) 2156 { 2157 /* NOTE: The trailing bits get XOR'd so we need the 2158 non-negated bits, not the negated ones. */ 2159 unsigned HOST_WIDE_INT trailing_bits = low_bits & 0x3ff; 2160 2161 if ((((~high_bits) & 0xffffffff) == 0 2162 && ((~low_bits) & 0x80000000) == 0) 2163 || (((~high_bits) & 0xffffffff) == 0xffffffff 2164 && ((~low_bits) & 0x80000000) != 0)) 2165 { 2166 int fast_int = (~low_bits & 0xffffffff); 2167 2168 if ((SPARC_SETHI_P (fast_int) 2169 && (~high_bits & 0xffffffff) == 0) 2170 || SPARC_SIMM13_P (fast_int)) 2171 emit_insn (gen_safe_SET64 (temp, fast_int)); 2172 else 2173 sparc_emit_set_const64 (temp, GEN_INT64 (fast_int)); 2174 } 2175 else 2176 { 2177 rtx negated_const; 2178#if HOST_BITS_PER_WIDE_INT == 64 2179 negated_const = GEN_INT (((~low_bits) & 0xfffffc00) | 2180 (((HOST_WIDE_INT)((~high_bits) & 0xffffffff))<<32)); 2181#else 2182 negated_const = immed_double_const ((~low_bits) & 0xfffffc00, 2183 (~high_bits) & 0xffffffff, 2184 DImode); 2185#endif 2186 sparc_emit_set_const64 (temp, negated_const); 2187 } 2188 2189 /* If we are XOR'ing with -1, then we should emit a one's complement 2190 instead. This way the combiner will notice logical operations 2191 such as ANDN later on and substitute. */ 2192 if (trailing_bits == 0x3ff) 2193 { 2194 emit_insn (gen_rtx_SET (VOIDmode, op0, 2195 gen_rtx_NOT (DImode, temp))); 2196 } 2197 else 2198 { 2199 emit_insn (gen_rtx_SET (VOIDmode, 2200 op0, 2201 gen_safe_XOR64 (temp, 2202 (-0x400 | trailing_bits)))); 2203 } 2204 return; 2205 } 2206 2207 /* 1) sethi %hi(xxx), %reg 2208 * or %reg, %lo(xxx), %reg 2209 * sllx %reg, yyy, %reg 2210 * 2211 * ??? This is just a generalized version of the low_bits==0 2212 * thing above, FIXME... 2213 */ 2214 if ((highest_bit_set - lowest_bit_set) < 32) 2215 { 2216 unsigned HOST_WIDE_INT focus_bits = 2217 create_simple_focus_bits (high_bits, low_bits, 2218 lowest_bit_set, 0); 2219 2220 /* We can't get here in this state. */ 2221 if (highest_bit_set < 32 2222 || lowest_bit_set >= 32) 2223 abort (); 2224 2225 /* So what we know is that the set bits straddle the 2226 middle of the 64-bit word. */ 2227 sparc_emit_set_const64_quick2 (op0, temp, 2228 focus_bits, 0, 2229 lowest_bit_set); 2230 return; 2231 } 2232 2233 /* 1) sethi %hi(high_bits), %reg 2234 * or %reg, %lo(high_bits), %reg 2235 * sllx %reg, 32, %reg 2236 * or %reg, low_bits, %reg 2237 */ 2238 if (SPARC_SIMM13_P(low_bits) 2239 && ((int)low_bits > 0)) 2240 { 2241 sparc_emit_set_const64_quick2 (op0, temp, high_bits, low_bits, 32); 2242 return; 2243 } 2244 2245 /* The easiest way when all else fails, is full decomposition. */ 2246#if 0 2247 printf ("sparc_emit_set_const64: Hard constant [%08lx%08lx] neg[%08lx%08lx]\n", 2248 high_bits, low_bits, ~high_bits, ~low_bits); 2249#endif 2250 sparc_emit_set_const64_longway (op0, temp, high_bits, low_bits); 2251} 2252 2253/* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE, 2254 return the mode to be used for the comparison. For floating-point, 2255 CCFP[E]mode is used. CC_NOOVmode should be used when the first operand 2256 is a PLUS, MINUS, NEG, or ASHIFT. CCmode should be used when no special 2257 processing is needed. */ 2258 2259enum machine_mode 2260select_cc_mode (enum rtx_code op, rtx x, rtx y ATTRIBUTE_UNUSED) 2261{ 2262 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT) 2263 { 2264 switch (op) 2265 { 2266 case EQ: 2267 case NE: 2268 case UNORDERED: 2269 case ORDERED: 2270 case UNLT: 2271 case UNLE: 2272 case UNGT: 2273 case UNGE: 2274 case UNEQ: 2275 case LTGT: 2276 return CCFPmode; 2277 2278 case LT: 2279 case LE: 2280 case GT: 2281 case GE: 2282 return CCFPEmode; 2283 2284 default: 2285 abort (); 2286 } 2287 } 2288 else if (GET_CODE (x) == PLUS || GET_CODE (x) == MINUS 2289 || GET_CODE (x) == NEG || GET_CODE (x) == ASHIFT) 2290 { 2291 if (TARGET_ARCH64 && GET_MODE (x) == DImode) 2292 return CCX_NOOVmode; 2293 else 2294 return CC_NOOVmode; 2295 } 2296 else 2297 { 2298 if (TARGET_ARCH64 && GET_MODE (x) == DImode) 2299 return CCXmode; 2300 else 2301 return CCmode; 2302 } 2303} 2304 2305/* X and Y are two things to compare using CODE. Emit the compare insn and 2306 return the rtx for the cc reg in the proper mode. */ 2307 2308rtx 2309gen_compare_reg (enum rtx_code code, rtx x, rtx y) 2310{ 2311 enum machine_mode mode = SELECT_CC_MODE (code, x, y); 2312 rtx cc_reg; 2313 2314 /* ??? We don't have movcc patterns so we cannot generate pseudo regs for the 2315 fcc regs (cse can't tell they're really call clobbered regs and will 2316 remove a duplicate comparison even if there is an intervening function 2317 call - it will then try to reload the cc reg via an int reg which is why 2318 we need the movcc patterns). It is possible to provide the movcc 2319 patterns by using the ldxfsr/stxfsr v9 insns. I tried it: you need two 2320 registers (say %g1,%g5) and it takes about 6 insns. A better fix would be 2321 to tell cse that CCFPE mode registers (even pseudos) are call 2322 clobbered. */ 2323 2324 /* ??? This is an experiment. Rather than making changes to cse which may 2325 or may not be easy/clean, we do our own cse. This is possible because 2326 we will generate hard registers. Cse knows they're call clobbered (it 2327 doesn't know the same thing about pseudos). If we guess wrong, no big 2328 deal, but if we win, great! */ 2329 2330 if (TARGET_V9 && GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT) 2331#if 1 /* experiment */ 2332 { 2333 int reg; 2334 /* We cycle through the registers to ensure they're all exercised. */ 2335 static int next_fcc_reg = 0; 2336 /* Previous x,y for each fcc reg. */ 2337 static rtx prev_args[4][2]; 2338 2339 /* Scan prev_args for x,y. */ 2340 for (reg = 0; reg < 4; reg++) 2341 if (prev_args[reg][0] == x && prev_args[reg][1] == y) 2342 break; 2343 if (reg == 4) 2344 { 2345 reg = next_fcc_reg; 2346 prev_args[reg][0] = x; 2347 prev_args[reg][1] = y; 2348 next_fcc_reg = (next_fcc_reg + 1) & 3; 2349 } 2350 cc_reg = gen_rtx_REG (mode, reg + SPARC_FIRST_V9_FCC_REG); 2351 } 2352#else 2353 cc_reg = gen_reg_rtx (mode); 2354#endif /* ! experiment */ 2355 else if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT) 2356 cc_reg = gen_rtx_REG (mode, SPARC_FCC_REG); 2357 else 2358 cc_reg = gen_rtx_REG (mode, SPARC_ICC_REG); 2359 2360 emit_insn (gen_rtx_SET (VOIDmode, cc_reg, 2361 gen_rtx_COMPARE (mode, x, y))); 2362 2363 return cc_reg; 2364} 2365 2366/* This function is used for v9 only. 2367 CODE is the code for an Scc's comparison. 2368 OPERANDS[0] is the target of the Scc insn. 2369 OPERANDS[1] is the value we compare against const0_rtx (which hasn't 2370 been generated yet). 2371 2372 This function is needed to turn 2373 2374 (set (reg:SI 110) 2375 (gt (reg:CCX 100 %icc) 2376 (const_int 0))) 2377 into 2378 (set (reg:SI 110) 2379 (gt:DI (reg:CCX 100 %icc) 2380 (const_int 0))) 2381 2382 IE: The instruction recognizer needs to see the mode of the comparison to 2383 find the right instruction. We could use "gt:DI" right in the 2384 define_expand, but leaving it out allows us to handle DI, SI, etc. 2385 2386 We refer to the global sparc compare operands sparc_compare_op0 and 2387 sparc_compare_op1. */ 2388 2389int 2390gen_v9_scc (enum rtx_code compare_code, register rtx *operands) 2391{ 2392 rtx temp, op0, op1; 2393 2394 if (! TARGET_ARCH64 2395 && (GET_MODE (sparc_compare_op0) == DImode 2396 || GET_MODE (operands[0]) == DImode)) 2397 return 0; 2398 2399 op0 = sparc_compare_op0; 2400 op1 = sparc_compare_op1; 2401 2402 /* Try to use the movrCC insns. */ 2403 if (TARGET_ARCH64 2404 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT 2405 && op1 == const0_rtx 2406 && v9_regcmp_p (compare_code)) 2407 { 2408 /* Special case for op0 != 0. This can be done with one instruction if 2409 operands[0] == sparc_compare_op0. */ 2410 2411 if (compare_code == NE 2412 && GET_MODE (operands[0]) == DImode 2413 && rtx_equal_p (op0, operands[0])) 2414 { 2415 emit_insn (gen_rtx_SET (VOIDmode, operands[0], 2416 gen_rtx_IF_THEN_ELSE (DImode, 2417 gen_rtx_fmt_ee (compare_code, DImode, 2418 op0, const0_rtx), 2419 const1_rtx, 2420 operands[0]))); 2421 return 1; 2422 } 2423 2424 if (reg_overlap_mentioned_p (operands[0], op0)) 2425 { 2426 /* Handle the case where operands[0] == sparc_compare_op0. 2427 We "early clobber" the result. */ 2428 op0 = gen_reg_rtx (GET_MODE (sparc_compare_op0)); 2429 emit_move_insn (op0, sparc_compare_op0); 2430 } 2431 2432 emit_insn (gen_rtx_SET (VOIDmode, operands[0], const0_rtx)); 2433 if (GET_MODE (op0) != DImode) 2434 { 2435 temp = gen_reg_rtx (DImode); 2436 convert_move (temp, op0, 0); 2437 } 2438 else 2439 temp = op0; 2440 emit_insn (gen_rtx_SET (VOIDmode, operands[0], 2441 gen_rtx_IF_THEN_ELSE (GET_MODE (operands[0]), 2442 gen_rtx_fmt_ee (compare_code, DImode, 2443 temp, const0_rtx), 2444 const1_rtx, 2445 operands[0]))); 2446 return 1; 2447 } 2448 else 2449 { 2450 operands[1] = gen_compare_reg (compare_code, op0, op1); 2451 2452 switch (GET_MODE (operands[1])) 2453 { 2454 case CCmode : 2455 case CCXmode : 2456 case CCFPEmode : 2457 case CCFPmode : 2458 break; 2459 default : 2460 abort (); 2461 } 2462 emit_insn (gen_rtx_SET (VOIDmode, operands[0], const0_rtx)); 2463 emit_insn (gen_rtx_SET (VOIDmode, operands[0], 2464 gen_rtx_IF_THEN_ELSE (GET_MODE (operands[0]), 2465 gen_rtx_fmt_ee (compare_code, 2466 GET_MODE (operands[1]), 2467 operands[1], const0_rtx), 2468 const1_rtx, operands[0]))); 2469 return 1; 2470 } 2471} 2472 2473/* Emit a conditional jump insn for the v9 architecture using comparison code 2474 CODE and jump target LABEL. 2475 This function exists to take advantage of the v9 brxx insns. */ 2476 2477void 2478emit_v9_brxx_insn (enum rtx_code code, rtx op0, rtx label) 2479{ 2480 emit_jump_insn (gen_rtx_SET (VOIDmode, 2481 pc_rtx, 2482 gen_rtx_IF_THEN_ELSE (VOIDmode, 2483 gen_rtx_fmt_ee (code, GET_MODE (op0), 2484 op0, const0_rtx), 2485 gen_rtx_LABEL_REF (VOIDmode, label), 2486 pc_rtx))); 2487} 2488 2489/* Generate a DFmode part of a hard TFmode register. 2490 REG is the TFmode hard register, LOW is 1 for the 2491 low 64bit of the register and 0 otherwise. 2492 */ 2493rtx 2494gen_df_reg (rtx reg, int low) 2495{ 2496 int regno = REGNO (reg); 2497 2498 if ((WORDS_BIG_ENDIAN == 0) ^ (low != 0)) 2499 regno += (TARGET_ARCH64 && regno < 32) ? 1 : 2; 2500 return gen_rtx_REG (DFmode, regno); 2501} 2502 2503/* Generate a call to FUNC with OPERANDS. Operand 0 is the return value. 2504 Unlike normal calls, TFmode operands are passed by reference. It is 2505 assumed that no more than 3 operands are required. */ 2506 2507static void 2508emit_soft_tfmode_libcall (const char *func_name, int nargs, rtx *operands) 2509{ 2510 rtx ret_slot = NULL, arg[3], func_sym; 2511 int i; 2512 2513 /* We only expect to be called for conversions, unary, and binary ops. */ 2514 if (nargs < 2 || nargs > 3) 2515 abort (); 2516 2517 for (i = 0; i < nargs; ++i) 2518 { 2519 rtx this_arg = operands[i]; 2520 rtx this_slot; 2521 2522 /* TFmode arguments and return values are passed by reference. */ 2523 if (GET_MODE (this_arg) == TFmode) 2524 { 2525 int force_stack_temp; 2526 2527 force_stack_temp = 0; 2528 if (TARGET_BUGGY_QP_LIB && i == 0) 2529 force_stack_temp = 1; 2530 2531 if (GET_CODE (this_arg) == MEM 2532 && ! force_stack_temp) 2533 this_arg = XEXP (this_arg, 0); 2534 else if (CONSTANT_P (this_arg) 2535 && ! force_stack_temp) 2536 { 2537 this_slot = force_const_mem (TFmode, this_arg); 2538 this_arg = XEXP (this_slot, 0); 2539 } 2540 else 2541 { 2542 this_slot = assign_stack_temp (TFmode, GET_MODE_SIZE (TFmode), 0); 2543 2544 /* Operand 0 is the return value. We'll copy it out later. */ 2545 if (i > 0) 2546 emit_move_insn (this_slot, this_arg); 2547 else 2548 ret_slot = this_slot; 2549 2550 this_arg = XEXP (this_slot, 0); 2551 } 2552 } 2553 2554 arg[i] = this_arg; 2555 } 2556 2557 func_sym = gen_rtx_SYMBOL_REF (Pmode, func_name); 2558 2559 if (GET_MODE (operands[0]) == TFmode) 2560 { 2561 if (nargs == 2) 2562 emit_library_call (func_sym, LCT_NORMAL, VOIDmode, 2, 2563 arg[0], GET_MODE (arg[0]), 2564 arg[1], GET_MODE (arg[1])); 2565 else 2566 emit_library_call (func_sym, LCT_NORMAL, VOIDmode, 3, 2567 arg[0], GET_MODE (arg[0]), 2568 arg[1], GET_MODE (arg[1]), 2569 arg[2], GET_MODE (arg[2])); 2570 2571 if (ret_slot) 2572 emit_move_insn (operands[0], ret_slot); 2573 } 2574 else 2575 { 2576 rtx ret; 2577 2578 if (nargs != 2) 2579 abort (); 2580 2581 ret = emit_library_call_value (func_sym, operands[0], LCT_NORMAL, 2582 GET_MODE (operands[0]), 1, 2583 arg[1], GET_MODE (arg[1])); 2584 2585 if (ret != operands[0]) 2586 emit_move_insn (operands[0], ret); 2587 } 2588} 2589 2590/* Expand soft-float TFmode calls to sparc abi routines. */ 2591 2592static void 2593emit_soft_tfmode_binop (enum rtx_code code, rtx *operands) 2594{ 2595 const char *func; 2596 2597 switch (code) 2598 { 2599 case PLUS: 2600 func = "_Qp_add"; 2601 break; 2602 case MINUS: 2603 func = "_Qp_sub"; 2604 break; 2605 case MULT: 2606 func = "_Qp_mul"; 2607 break; 2608 case DIV: 2609 func = "_Qp_div"; 2610 break; 2611 default: 2612 abort (); 2613 } 2614 2615 emit_soft_tfmode_libcall (func, 3, operands); 2616} 2617 2618static void 2619emit_soft_tfmode_unop (enum rtx_code code, rtx *operands) 2620{ 2621 const char *func; 2622 2623 switch (code) 2624 { 2625 case SQRT: 2626 func = "_Qp_sqrt"; 2627 break; 2628 default: 2629 abort (); 2630 } 2631 2632 emit_soft_tfmode_libcall (func, 2, operands); 2633} 2634 2635static void 2636emit_soft_tfmode_cvt (enum rtx_code code, rtx *operands) 2637{ 2638 const char *func; 2639 2640 switch (code) 2641 { 2642 case FLOAT_EXTEND: 2643 switch (GET_MODE (operands[1])) 2644 { 2645 case SFmode: 2646 func = "_Qp_stoq"; 2647 break; 2648 case DFmode: 2649 func = "_Qp_dtoq"; 2650 break; 2651 default: 2652 abort (); 2653 } 2654 break; 2655 2656 case FLOAT_TRUNCATE: 2657 switch (GET_MODE (operands[0])) 2658 { 2659 case SFmode: 2660 func = "_Qp_qtos"; 2661 break; 2662 case DFmode: 2663 func = "_Qp_qtod"; 2664 break; 2665 default: 2666 abort (); 2667 } 2668 break; 2669 2670 case FLOAT: 2671 switch (GET_MODE (operands[1])) 2672 { 2673 case SImode: 2674 func = "_Qp_itoq"; 2675 break; 2676 case DImode: 2677 func = "_Qp_xtoq"; 2678 break; 2679 default: 2680 abort (); 2681 } 2682 break; 2683 2684 case UNSIGNED_FLOAT: 2685 switch (GET_MODE (operands[1])) 2686 { 2687 case SImode: 2688 func = "_Qp_uitoq"; 2689 break; 2690 case DImode: 2691 func = "_Qp_uxtoq"; 2692 break; 2693 default: 2694 abort (); 2695 } 2696 break; 2697 2698 case FIX: 2699 switch (GET_MODE (operands[0])) 2700 { 2701 case SImode: 2702 func = "_Qp_qtoi"; 2703 break; 2704 case DImode: 2705 func = "_Qp_qtox"; 2706 break; 2707 default: 2708 abort (); 2709 } 2710 break; 2711 2712 case UNSIGNED_FIX: 2713 switch (GET_MODE (operands[0])) 2714 { 2715 case SImode: 2716 func = "_Qp_qtoui"; 2717 break; 2718 case DImode: 2719 func = "_Qp_qtoux"; 2720 break; 2721 default: 2722 abort (); 2723 } 2724 break; 2725 2726 default: 2727 abort (); 2728 } 2729 2730 emit_soft_tfmode_libcall (func, 2, operands); 2731} 2732 2733/* Expand a hard-float tfmode operation. All arguments must be in 2734 registers. */ 2735 2736static void 2737emit_hard_tfmode_operation (enum rtx_code code, rtx *operands) 2738{ 2739 rtx op, dest; 2740 2741 if (GET_RTX_CLASS (code) == '1') 2742 { 2743 operands[1] = force_reg (GET_MODE (operands[1]), operands[1]); 2744 op = gen_rtx_fmt_e (code, GET_MODE (operands[0]), operands[1]); 2745 } 2746 else 2747 { 2748 operands[1] = force_reg (GET_MODE (operands[1]), operands[1]); 2749 operands[2] = force_reg (GET_MODE (operands[2]), operands[2]); 2750 op = gen_rtx_fmt_ee (code, GET_MODE (operands[0]), 2751 operands[1], operands[2]); 2752 } 2753 2754 if (register_operand (operands[0], VOIDmode)) 2755 dest = operands[0]; 2756 else 2757 dest = gen_reg_rtx (GET_MODE (operands[0])); 2758 2759 emit_insn (gen_rtx_SET (VOIDmode, dest, op)); 2760 2761 if (dest != operands[0]) 2762 emit_move_insn (operands[0], dest); 2763} 2764 2765void 2766emit_tfmode_binop (enum rtx_code code, rtx *operands) 2767{ 2768 if (TARGET_HARD_QUAD) 2769 emit_hard_tfmode_operation (code, operands); 2770 else 2771 emit_soft_tfmode_binop (code, operands); 2772} 2773 2774void 2775emit_tfmode_unop (enum rtx_code code, rtx *operands) 2776{ 2777 if (TARGET_HARD_QUAD) 2778 emit_hard_tfmode_operation (code, operands); 2779 else 2780 emit_soft_tfmode_unop (code, operands); 2781} 2782 2783void 2784emit_tfmode_cvt (enum rtx_code code, rtx *operands) 2785{ 2786 if (TARGET_HARD_QUAD) 2787 emit_hard_tfmode_operation (code, operands); 2788 else 2789 emit_soft_tfmode_cvt (code, operands); 2790} 2791 2792/* Return nonzero if a return peephole merging return with 2793 setting of output register is ok. */ 2794int 2795leaf_return_peephole_ok (void) 2796{ 2797 return (actual_fsize == 0); 2798} 2799 2800/* Return nonzero if a branch/jump/call instruction will be emitting 2801 nop into its delay slot. */ 2802 2803int 2804empty_delay_slot (rtx insn) 2805{ 2806 rtx seq; 2807 2808 /* If no previous instruction (should not happen), return true. */ 2809 if (PREV_INSN (insn) == NULL) 2810 return 1; 2811 2812 seq = NEXT_INSN (PREV_INSN (insn)); 2813 if (GET_CODE (PATTERN (seq)) == SEQUENCE) 2814 return 0; 2815 2816 return 1; 2817} 2818 2819/* Return nonzero if TRIAL can go into the function epilogue's 2820 delay slot. SLOT is the slot we are trying to fill. */ 2821 2822int 2823eligible_for_epilogue_delay (rtx trial, int slot) 2824{ 2825 rtx pat, src; 2826 2827 if (slot >= 1) 2828 return 0; 2829 2830 if (GET_CODE (trial) != INSN || GET_CODE (PATTERN (trial)) != SET) 2831 return 0; 2832 2833 if (get_attr_length (trial) != 1) 2834 return 0; 2835 2836 /* If there are any call-saved registers, we should scan TRIAL if it 2837 does not reference them. For now just make it easy. */ 2838 if (num_gfregs) 2839 return 0; 2840 2841 /* If the function uses __builtin_eh_return, the eh_return machinery 2842 occupies the delay slot. */ 2843 if (current_function_calls_eh_return) 2844 return 0; 2845 2846 /* In the case of a true leaf function, anything can go into the delay slot. 2847 A delay slot only exists however if the frame size is zero, otherwise 2848 we will put an insn to adjust the stack after the return. */ 2849 if (current_function_uses_only_leaf_regs) 2850 { 2851 if (leaf_return_peephole_ok ()) 2852 return ((get_attr_in_uncond_branch_delay (trial) 2853 == IN_BRANCH_DELAY_TRUE)); 2854 return 0; 2855 } 2856 2857 pat = PATTERN (trial); 2858 2859 /* Otherwise, only operations which can be done in tandem with 2860 a `restore' or `return' insn can go into the delay slot. */ 2861 if (GET_CODE (SET_DEST (pat)) != REG 2862 || REGNO (SET_DEST (pat)) < 24) 2863 return 0; 2864 2865 /* If this instruction sets up floating point register and we have a return 2866 instruction, it can probably go in. But restore will not work 2867 with FP_REGS. */ 2868 if (REGNO (SET_DEST (pat)) >= 32) 2869 { 2870 if (TARGET_V9 && ! epilogue_renumber (&pat, 1) 2871 && (get_attr_in_uncond_branch_delay (trial) == IN_BRANCH_DELAY_TRUE)) 2872 return 1; 2873 return 0; 2874 } 2875 2876 /* The set of insns matched here must agree precisely with the set of 2877 patterns paired with a RETURN in sparc.md. */ 2878 2879 src = SET_SRC (pat); 2880 2881 /* This matches "*return_[qhs]i" or even "*return_di" on TARGET_ARCH64. */ 2882 if (GET_MODE_CLASS (GET_MODE (src)) != MODE_FLOAT 2883 && arith_operand (src, GET_MODE (src))) 2884 { 2885 if (TARGET_ARCH64) 2886 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (DImode); 2887 else 2888 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (SImode); 2889 } 2890 2891 /* This matches "*return_di". */ 2892 else if (GET_MODE_CLASS (GET_MODE (src)) != MODE_FLOAT 2893 && arith_double_operand (src, GET_MODE (src))) 2894 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (DImode); 2895 2896 /* This matches "*return_sf_no_fpu". */ 2897 else if (! TARGET_FPU && restore_operand (SET_DEST (pat), SFmode) 2898 && register_operand (src, SFmode)) 2899 return 1; 2900 2901 /* If we have return instruction, anything that does not use 2902 local or output registers and can go into a delay slot wins. */ 2903 else if (TARGET_V9 && ! epilogue_renumber (&pat, 1) 2904 && (get_attr_in_uncond_branch_delay (trial) == IN_BRANCH_DELAY_TRUE)) 2905 return 1; 2906 2907 /* This matches "*return_addsi". */ 2908 else if (GET_CODE (src) == PLUS 2909 && arith_operand (XEXP (src, 0), SImode) 2910 && arith_operand (XEXP (src, 1), SImode) 2911 && (register_operand (XEXP (src, 0), SImode) 2912 || register_operand (XEXP (src, 1), SImode))) 2913 return 1; 2914 2915 /* This matches "*return_adddi". */ 2916 else if (GET_CODE (src) == PLUS 2917 && arith_double_operand (XEXP (src, 0), DImode) 2918 && arith_double_operand (XEXP (src, 1), DImode) 2919 && (register_operand (XEXP (src, 0), DImode) 2920 || register_operand (XEXP (src, 1), DImode))) 2921 return 1; 2922 2923 /* This can match "*return_losum_[sd]i". 2924 Catch only some cases, so that return_losum* don't have 2925 to be too big. */ 2926 else if (GET_CODE (src) == LO_SUM 2927 && ! TARGET_CM_MEDMID 2928 && ((register_operand (XEXP (src, 0), SImode) 2929 && immediate_operand (XEXP (src, 1), SImode)) 2930 || (TARGET_ARCH64 2931 && register_operand (XEXP (src, 0), DImode) 2932 && immediate_operand (XEXP (src, 1), DImode)))) 2933 return 1; 2934 2935 /* sll{,x} reg,1,reg2 is add reg,reg,reg2 as well. */ 2936 else if (GET_CODE (src) == ASHIFT 2937 && (register_operand (XEXP (src, 0), SImode) 2938 || register_operand (XEXP (src, 0), DImode)) 2939 && XEXP (src, 1) == const1_rtx) 2940 return 1; 2941 2942 return 0; 2943} 2944 2945/* Return nonzero if TRIAL can go into the call delay slot. */ 2946int 2947tls_call_delay (rtx trial) 2948{ 2949 rtx pat; 2950 2951 /* Binutils allows 2952 call __tls_get_addr, %tgd_call (foo) 2953 add %l7, %o0, %o0, %tgd_add (foo) 2954 while Sun as/ld does not. */ 2955 if (TARGET_GNU_TLS || !TARGET_TLS) 2956 return 1; 2957 2958 pat = PATTERN (trial); 2959 2960 /* We must reject tgd_add{32|64}, i.e. 2961 (set (reg) (plus (reg) (unspec [(reg) (symbol_ref)] UNSPEC_TLSGD))) 2962 and tldm_add{32|64}, i.e. 2963 (set (reg) (plus (reg) (unspec [(reg) (symbol_ref)] UNSPEC_TLSLDM))) 2964 for Sun as/ld. */ 2965 if (GET_CODE (pat) == SET 2966 && GET_CODE (SET_SRC (pat)) == PLUS) 2967 { 2968 rtx unspec = XEXP (SET_SRC (pat), 1); 2969 2970 if (GET_CODE (unspec) == UNSPEC 2971 && (XINT (unspec, 1) == UNSPEC_TLSGD 2972 || XINT (unspec, 1) == UNSPEC_TLSLDM)) 2973 return 0; 2974 } 2975 2976 return 1; 2977} 2978 2979/* Return nonzero if TRIAL can go into the sibling call 2980 delay slot. */ 2981 2982int 2983eligible_for_sibcall_delay (rtx trial) 2984{ 2985 rtx pat, src; 2986 2987 if (GET_CODE (trial) != INSN || GET_CODE (PATTERN (trial)) != SET) 2988 return 0; 2989 2990 if (get_attr_length (trial) != 1) 2991 return 0; 2992 2993 pat = PATTERN (trial); 2994 2995 if (current_function_uses_only_leaf_regs) 2996 { 2997 /* If the tail call is done using the call instruction, 2998 we have to restore %o7 in the delay slot. */ 2999 if ((TARGET_ARCH64 && ! TARGET_CM_MEDLOW) || flag_pic) 3000 return 0; 3001 3002 /* %g1 is used to build the function address */ 3003 if (reg_mentioned_p (gen_rtx_REG (Pmode, 1), pat)) 3004 return 0; 3005 3006 return 1; 3007 } 3008 3009 /* Otherwise, only operations which can be done in tandem with 3010 a `restore' insn can go into the delay slot. */ 3011 if (GET_CODE (SET_DEST (pat)) != REG 3012 || REGNO (SET_DEST (pat)) < 24 3013 || REGNO (SET_DEST (pat)) >= 32) 3014 return 0; 3015 3016 /* If it mentions %o7, it can't go in, because sibcall will clobber it 3017 in most cases. */ 3018 if (reg_mentioned_p (gen_rtx_REG (Pmode, 15), pat)) 3019 return 0; 3020 3021 src = SET_SRC (pat); 3022 3023 if (GET_MODE_CLASS (GET_MODE (src)) != MODE_FLOAT 3024 && arith_operand (src, GET_MODE (src))) 3025 { 3026 if (TARGET_ARCH64) 3027 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (DImode); 3028 else 3029 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (SImode); 3030 } 3031 3032 else if (GET_MODE_CLASS (GET_MODE (src)) != MODE_FLOAT 3033 && arith_double_operand (src, GET_MODE (src))) 3034 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (DImode); 3035 3036 else if (! TARGET_FPU && restore_operand (SET_DEST (pat), SFmode) 3037 && register_operand (src, SFmode)) 3038 return 1; 3039 3040 else if (GET_CODE (src) == PLUS 3041 && arith_operand (XEXP (src, 0), SImode) 3042 && arith_operand (XEXP (src, 1), SImode) 3043 && (register_operand (XEXP (src, 0), SImode) 3044 || register_operand (XEXP (src, 1), SImode))) 3045 return 1; 3046 3047 else if (GET_CODE (src) == PLUS 3048 && arith_double_operand (XEXP (src, 0), DImode) 3049 && arith_double_operand (XEXP (src, 1), DImode) 3050 && (register_operand (XEXP (src, 0), DImode) 3051 || register_operand (XEXP (src, 1), DImode))) 3052 return 1; 3053 3054 else if (GET_CODE (src) == LO_SUM 3055 && ! TARGET_CM_MEDMID 3056 && ((register_operand (XEXP (src, 0), SImode) 3057 && immediate_operand (XEXP (src, 1), SImode)) 3058 || (TARGET_ARCH64 3059 && register_operand (XEXP (src, 0), DImode) 3060 && immediate_operand (XEXP (src, 1), DImode)))) 3061 return 1; 3062 3063 else if (GET_CODE (src) == ASHIFT 3064 && (register_operand (XEXP (src, 0), SImode) 3065 || register_operand (XEXP (src, 0), DImode)) 3066 && XEXP (src, 1) == const1_rtx) 3067 return 1; 3068 3069 return 0; 3070} 3071 3072static int 3073check_return_regs (rtx x) 3074{ 3075 switch (GET_CODE (x)) 3076 { 3077 case REG: 3078 return IN_OR_GLOBAL_P (x); 3079 3080 case CONST_INT: 3081 case CONST_DOUBLE: 3082 case CONST: 3083 case SYMBOL_REF: 3084 case LABEL_REF: 3085 return 1; 3086 3087 case SET: 3088 case IOR: 3089 case AND: 3090 case XOR: 3091 case PLUS: 3092 case MINUS: 3093 if (check_return_regs (XEXP (x, 1)) == 0) 3094 return 0; 3095 case NOT: 3096 case NEG: 3097 case MEM: 3098 return check_return_regs (XEXP (x, 0)); 3099 3100 default: 3101 return 0; 3102 } 3103 3104} 3105 3106int 3107short_branch (int uid1, int uid2) 3108{ 3109 int delta = INSN_ADDRESSES (uid1) - INSN_ADDRESSES (uid2); 3110 3111 /* Leave a few words of "slop". */ 3112 if (delta >= -1023 && delta <= 1022) 3113 return 1; 3114 3115 return 0; 3116} 3117 3118/* Return nonzero if REG is not used after INSN. 3119 We assume REG is a reload reg, and therefore does 3120 not live past labels or calls or jumps. */ 3121int 3122reg_unused_after (rtx reg, rtx insn) 3123{ 3124 enum rtx_code code, prev_code = UNKNOWN; 3125 3126 while ((insn = NEXT_INSN (insn))) 3127 { 3128 if (prev_code == CALL_INSN && call_used_regs[REGNO (reg)]) 3129 return 1; 3130 3131 code = GET_CODE (insn); 3132 if (GET_CODE (insn) == CODE_LABEL) 3133 return 1; 3134 3135 if (GET_RTX_CLASS (code) == 'i') 3136 { 3137 rtx set = single_set (insn); 3138 int in_src = set && reg_overlap_mentioned_p (reg, SET_SRC (set)); 3139 if (set && in_src) 3140 return 0; 3141 if (set && reg_overlap_mentioned_p (reg, SET_DEST (set))) 3142 return 1; 3143 if (set == 0 && reg_overlap_mentioned_p (reg, PATTERN (insn))) 3144 return 0; 3145 } 3146 prev_code = code; 3147 } 3148 return 1; 3149} 3150 3151/* Determine if it's legal to put X into the constant pool. This 3152 is not possible if X contains the address of a symbol that is 3153 not constant (TLS) or not known at final link time (PIC). */ 3154 3155static bool 3156sparc_cannot_force_const_mem (rtx x) 3157{ 3158 switch (GET_CODE (x)) 3159 { 3160 case CONST_INT: 3161 case CONST_DOUBLE: 3162 /* Accept all non-symbolic constants. */ 3163 return false; 3164 3165 case LABEL_REF: 3166 /* Labels are OK iff we are non-PIC. */ 3167 return flag_pic != 0; 3168 3169 case SYMBOL_REF: 3170 /* 'Naked' TLS symbol references are never OK, 3171 non-TLS symbols are OK iff we are non-PIC. */ 3172 if (SYMBOL_REF_TLS_MODEL (x)) 3173 return true; 3174 else 3175 return flag_pic != 0; 3176 3177 case CONST: 3178 return sparc_cannot_force_const_mem (XEXP (x, 0)); 3179 case PLUS: 3180 case MINUS: 3181 return sparc_cannot_force_const_mem (XEXP (x, 0)) 3182 || sparc_cannot_force_const_mem (XEXP (x, 1)); 3183 case UNSPEC: 3184 return true; 3185 default: 3186 abort (); 3187 } 3188} 3189 3190/* The table we use to reference PIC data. */ 3191static GTY(()) rtx global_offset_table; 3192 3193/* The function we use to get at it. */ 3194static GTY(()) rtx get_pc_symbol; 3195static GTY(()) char get_pc_symbol_name[256]; 3196 3197/* Ensure that we are not using patterns that are not OK with PIC. */ 3198 3199int 3200check_pic (int i) 3201{ 3202 switch (flag_pic) 3203 { 3204 case 1: 3205 if (GET_CODE (recog_data.operand[i]) == SYMBOL_REF 3206 || (GET_CODE (recog_data.operand[i]) == CONST 3207 && ! (GET_CODE (XEXP (recog_data.operand[i], 0)) == MINUS 3208 && (XEXP (XEXP (recog_data.operand[i], 0), 0) 3209 == global_offset_table) 3210 && (GET_CODE (XEXP (XEXP (recog_data.operand[i], 0), 1)) 3211 == CONST)))) 3212 abort (); 3213 case 2: 3214 default: 3215 return 1; 3216 } 3217} 3218 3219/* Return true if X is an address which needs a temporary register when 3220 reloaded while generating PIC code. */ 3221 3222int 3223pic_address_needs_scratch (rtx x) 3224{ 3225 /* An address which is a symbolic plus a non SMALL_INT needs a temp reg. */ 3226 if (GET_CODE (x) == CONST && GET_CODE (XEXP (x, 0)) == PLUS 3227 && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF 3228 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT 3229 && ! SMALL_INT (XEXP (XEXP (x, 0), 1))) 3230 return 1; 3231 3232 return 0; 3233} 3234 3235/* Determine if a given RTX is a valid constant. We already know this 3236 satisfies CONSTANT_P. */ 3237 3238bool 3239legitimate_constant_p (rtx x) 3240{ 3241 rtx inner; 3242 3243 switch (GET_CODE (x)) 3244 { 3245 case SYMBOL_REF: 3246 /* TLS symbols are not constant. */ 3247 if (SYMBOL_REF_TLS_MODEL (x)) 3248 return false; 3249 break; 3250 3251 case CONST: 3252 inner = XEXP (x, 0); 3253 3254 /* Offsets of TLS symbols are never valid. 3255 Discourage CSE from creating them. */ 3256 if (GET_CODE (inner) == PLUS 3257 && tls_symbolic_operand (XEXP (inner, 0))) 3258 return false; 3259 break; 3260 3261 case CONST_DOUBLE: 3262 if (GET_MODE (x) == VOIDmode) 3263 return true; 3264 3265 /* Floating point constants are generally not ok. 3266 The only exception is 0.0 in VIS. */ 3267 if (TARGET_VIS 3268 && (GET_MODE (x) == SFmode 3269 || GET_MODE (x) == DFmode 3270 || GET_MODE (x) == TFmode) 3271 && fp_zero_operand (x, GET_MODE (x))) 3272 return true; 3273 3274 return false; 3275 3276 default: 3277 break; 3278 } 3279 3280 return true; 3281} 3282 3283/* Determine if a given RTX is a valid constant address. */ 3284 3285bool 3286constant_address_p (rtx x) 3287{ 3288 switch (GET_CODE (x)) 3289 { 3290 case LABEL_REF: 3291 case CONST_INT: 3292 case HIGH: 3293 return true; 3294 3295 case CONST: 3296 if (flag_pic && pic_address_needs_scratch (x)) 3297 return false; 3298 return legitimate_constant_p (x); 3299 3300 case SYMBOL_REF: 3301 return !flag_pic && legitimate_constant_p (x); 3302 3303 default: 3304 return false; 3305 } 3306} 3307 3308/* Nonzero if the constant value X is a legitimate general operand 3309 when generating PIC code. It is given that flag_pic is on and 3310 that X satisfies CONSTANT_P or is a CONST_DOUBLE. */ 3311 3312bool 3313legitimate_pic_operand_p (rtx x) 3314{ 3315 if (pic_address_needs_scratch (x)) 3316 return false; 3317 if (tls_symbolic_operand (x) 3318 || (GET_CODE (x) == CONST 3319 && GET_CODE (XEXP (x, 0)) == PLUS 3320 && tls_symbolic_operand (XEXP (XEXP (x, 0), 0)))) 3321 return false; 3322 return true; 3323} 3324 3325/* Return nonzero if ADDR is a valid memory address. 3326 STRICT specifies whether strict register checking applies. */ 3327 3328int 3329legitimate_address_p (enum machine_mode mode, rtx addr, int strict) 3330{ 3331 rtx rs1 = NULL, rs2 = NULL, imm1 = NULL; 3332 3333 if (REG_P (addr) || GET_CODE (addr) == SUBREG) 3334 rs1 = addr; 3335 else if (GET_CODE (addr) == PLUS) 3336 { 3337 rs1 = XEXP (addr, 0); 3338 rs2 = XEXP (addr, 1); 3339 3340 /* Canonicalize. REG comes first, if there are no regs, 3341 LO_SUM comes first. */ 3342 if (!REG_P (rs1) 3343 && GET_CODE (rs1) != SUBREG 3344 && (REG_P (rs2) 3345 || GET_CODE (rs2) == SUBREG 3346 || (GET_CODE (rs2) == LO_SUM && GET_CODE (rs1) != LO_SUM))) 3347 { 3348 rs1 = XEXP (addr, 1); 3349 rs2 = XEXP (addr, 0); 3350 } 3351 3352 if ((flag_pic == 1 3353 && rs1 == pic_offset_table_rtx 3354 && !REG_P (rs2) 3355 && GET_CODE (rs2) != SUBREG 3356 && GET_CODE (rs2) != LO_SUM 3357 && GET_CODE (rs2) != MEM 3358 && !tls_symbolic_operand (rs2) 3359 && (! symbolic_operand (rs2, VOIDmode) || mode == Pmode) 3360 && (GET_CODE (rs2) != CONST_INT || SMALL_INT (rs2))) 3361 || ((REG_P (rs1) 3362 || GET_CODE (rs1) == SUBREG) 3363 && RTX_OK_FOR_OFFSET_P (rs2))) 3364 { 3365 imm1 = rs2; 3366 rs2 = NULL; 3367 } 3368 else if ((REG_P (rs1) || GET_CODE (rs1) == SUBREG) 3369 && (REG_P (rs2) || GET_CODE (rs2) == SUBREG)) 3370 { 3371 /* We prohibit REG + REG for TFmode when there are no quad move insns 3372 and we consequently need to split. We do this because REG+REG 3373 is not an offsettable address. If we get the situation in reload 3374 where source and destination of a movtf pattern are both MEMs with 3375 REG+REG address, then only one of them gets converted to an 3376 offsettable address. */ 3377 if (mode == TFmode 3378 && ! (TARGET_FPU && TARGET_ARCH64 && TARGET_HARD_QUAD)) 3379 return 0; 3380 3381 /* We prohibit REG + REG on ARCH32 if not optimizing for 3382 DFmode/DImode because then mem_min_alignment is likely to be zero 3383 after reload and the forced split would lack a matching splitter 3384 pattern. */ 3385 if (TARGET_ARCH32 && !optimize 3386 && (mode == DFmode || mode == DImode)) 3387 return 0; 3388 } 3389 else if (USE_AS_OFFSETABLE_LO10 3390 && GET_CODE (rs1) == LO_SUM 3391 && TARGET_ARCH64 3392 && ! TARGET_CM_MEDMID 3393 && RTX_OK_FOR_OLO10_P (rs2)) 3394 { 3395 rs2 = NULL; 3396 imm1 = XEXP (rs1, 1); 3397 rs1 = XEXP (rs1, 0); 3398 if (! CONSTANT_P (imm1) || tls_symbolic_operand (rs1)) 3399 return 0; 3400 } 3401 } 3402 else if (GET_CODE (addr) == LO_SUM) 3403 { 3404 rs1 = XEXP (addr, 0); 3405 imm1 = XEXP (addr, 1); 3406 3407 if (! CONSTANT_P (imm1) || tls_symbolic_operand (rs1)) 3408 return 0; 3409 3410 /* We can't allow TFmode in 32-bit mode, because an offset greater 3411 than the alignment (8) may cause the LO_SUM to overflow. */ 3412 if (mode == TFmode && TARGET_ARCH32) 3413 return 0; 3414 } 3415 else if (GET_CODE (addr) == CONST_INT && SMALL_INT (addr)) 3416 return 1; 3417 else 3418 return 0; 3419 3420 if (GET_CODE (rs1) == SUBREG) 3421 rs1 = SUBREG_REG (rs1); 3422 if (!REG_P (rs1)) 3423 return 0; 3424 3425 if (rs2) 3426 { 3427 if (GET_CODE (rs2) == SUBREG) 3428 rs2 = SUBREG_REG (rs2); 3429 if (!REG_P (rs2)) 3430 return 0; 3431 } 3432 3433 if (strict) 3434 { 3435 if (!REGNO_OK_FOR_BASE_P (REGNO (rs1)) 3436 || (rs2 && !REGNO_OK_FOR_BASE_P (REGNO (rs2)))) 3437 return 0; 3438 } 3439 else 3440 { 3441 if ((REGNO (rs1) >= 32 3442 && REGNO (rs1) != FRAME_POINTER_REGNUM 3443 && REGNO (rs1) < FIRST_PSEUDO_REGISTER) 3444 || (rs2 3445 && (REGNO (rs2) >= 32 3446 && REGNO (rs2) != FRAME_POINTER_REGNUM 3447 && REGNO (rs2) < FIRST_PSEUDO_REGISTER))) 3448 return 0; 3449 } 3450 return 1; 3451} 3452 3453/* Construct the SYMBOL_REF for the tls_get_offset function. */ 3454 3455static GTY(()) rtx sparc_tls_symbol; 3456static rtx 3457sparc_tls_get_addr (void) 3458{ 3459 if (!sparc_tls_symbol) 3460 sparc_tls_symbol = gen_rtx_SYMBOL_REF (Pmode, "__tls_get_addr"); 3461 3462 return sparc_tls_symbol; 3463} 3464 3465static rtx 3466sparc_tls_got (void) 3467{ 3468 rtx temp; 3469 if (flag_pic) 3470 { 3471 current_function_uses_pic_offset_table = 1; 3472 return pic_offset_table_rtx; 3473 } 3474 3475 if (!global_offset_table) 3476 global_offset_table = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_"); 3477 temp = gen_reg_rtx (Pmode); 3478 emit_move_insn (temp, global_offset_table); 3479 return temp; 3480} 3481 3482 3483/* ADDR contains a thread-local SYMBOL_REF. Generate code to compute 3484 this (thread-local) address. */ 3485 3486rtx 3487legitimize_tls_address (rtx addr) 3488{ 3489 rtx temp1, temp2, temp3, ret, o0, got, insn; 3490 3491 if (no_new_pseudos) 3492 abort (); 3493 3494 if (GET_CODE (addr) == SYMBOL_REF) 3495 switch (SYMBOL_REF_TLS_MODEL (addr)) 3496 { 3497 case TLS_MODEL_GLOBAL_DYNAMIC: 3498 start_sequence (); 3499 temp1 = gen_reg_rtx (SImode); 3500 temp2 = gen_reg_rtx (SImode); 3501 ret = gen_reg_rtx (Pmode); 3502 o0 = gen_rtx_REG (Pmode, 8); 3503 got = sparc_tls_got (); 3504 emit_insn (gen_tgd_hi22 (temp1, addr)); 3505 emit_insn (gen_tgd_lo10 (temp2, temp1, addr)); 3506 if (TARGET_ARCH32) 3507 { 3508 emit_insn (gen_tgd_add32 (o0, got, temp2, addr)); 3509 insn = emit_call_insn (gen_tgd_call32 (o0, sparc_tls_get_addr (), 3510 addr, const1_rtx)); 3511 } 3512 else 3513 { 3514 emit_insn (gen_tgd_add64 (o0, got, temp2, addr)); 3515 insn = emit_call_insn (gen_tgd_call64 (o0, sparc_tls_get_addr (), 3516 addr, const1_rtx)); 3517 } 3518 CALL_INSN_FUNCTION_USAGE (insn) 3519 = gen_rtx_EXPR_LIST (VOIDmode, gen_rtx_USE (VOIDmode, o0), 3520 CALL_INSN_FUNCTION_USAGE (insn)); 3521 insn = get_insns (); 3522 end_sequence (); 3523 emit_libcall_block (insn, ret, o0, addr); 3524 break; 3525 3526 case TLS_MODEL_LOCAL_DYNAMIC: 3527 start_sequence (); 3528 temp1 = gen_reg_rtx (SImode); 3529 temp2 = gen_reg_rtx (SImode); 3530 temp3 = gen_reg_rtx (Pmode); 3531 ret = gen_reg_rtx (Pmode); 3532 o0 = gen_rtx_REG (Pmode, 8); 3533 got = sparc_tls_got (); 3534 emit_insn (gen_tldm_hi22 (temp1)); 3535 emit_insn (gen_tldm_lo10 (temp2, temp1)); 3536 if (TARGET_ARCH32) 3537 { 3538 emit_insn (gen_tldm_add32 (o0, got, temp2)); 3539 insn = emit_call_insn (gen_tldm_call32 (o0, sparc_tls_get_addr (), 3540 const1_rtx)); 3541 } 3542 else 3543 { 3544 emit_insn (gen_tldm_add64 (o0, got, temp2)); 3545 insn = emit_call_insn (gen_tldm_call64 (o0, sparc_tls_get_addr (), 3546 const1_rtx)); 3547 } 3548 CALL_INSN_FUNCTION_USAGE (insn) 3549 = gen_rtx_EXPR_LIST (VOIDmode, gen_rtx_USE (VOIDmode, o0), 3550 CALL_INSN_FUNCTION_USAGE (insn)); 3551 insn = get_insns (); 3552 end_sequence (); 3553 emit_libcall_block (insn, temp3, o0, 3554 gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx), 3555 UNSPEC_TLSLD_BASE)); 3556 temp1 = gen_reg_rtx (SImode); 3557 temp2 = gen_reg_rtx (SImode); 3558 emit_insn (gen_tldo_hix22 (temp1, addr)); 3559 emit_insn (gen_tldo_lox10 (temp2, temp1, addr)); 3560 if (TARGET_ARCH32) 3561 emit_insn (gen_tldo_add32 (ret, temp3, temp2, addr)); 3562 else 3563 emit_insn (gen_tldo_add64 (ret, temp3, temp2, addr)); 3564 break; 3565 3566 case TLS_MODEL_INITIAL_EXEC: 3567 temp1 = gen_reg_rtx (SImode); 3568 temp2 = gen_reg_rtx (SImode); 3569 temp3 = gen_reg_rtx (Pmode); 3570 got = sparc_tls_got (); 3571 emit_insn (gen_tie_hi22 (temp1, addr)); 3572 emit_insn (gen_tie_lo10 (temp2, temp1, addr)); 3573 if (TARGET_ARCH32) 3574 emit_insn (gen_tie_ld32 (temp3, got, temp2, addr)); 3575 else 3576 emit_insn (gen_tie_ld64 (temp3, got, temp2, addr)); 3577 if (TARGET_SUN_TLS) 3578 { 3579 ret = gen_reg_rtx (Pmode); 3580 if (TARGET_ARCH32) 3581 emit_insn (gen_tie_add32 (ret, gen_rtx_REG (Pmode, 7), 3582 temp3, addr)); 3583 else 3584 emit_insn (gen_tie_add64 (ret, gen_rtx_REG (Pmode, 7), 3585 temp3, addr)); 3586 } 3587 else 3588 ret = gen_rtx_PLUS (Pmode, gen_rtx_REG (Pmode, 7), temp3); 3589 break; 3590 3591 case TLS_MODEL_LOCAL_EXEC: 3592 temp1 = gen_reg_rtx (Pmode); 3593 temp2 = gen_reg_rtx (Pmode); 3594 if (TARGET_ARCH32) 3595 { 3596 emit_insn (gen_tle_hix22_sp32 (temp1, addr)); 3597 emit_insn (gen_tle_lox10_sp32 (temp2, temp1, addr)); 3598 } 3599 else 3600 { 3601 emit_insn (gen_tle_hix22_sp64 (temp1, addr)); 3602 emit_insn (gen_tle_lox10_sp64 (temp2, temp1, addr)); 3603 } 3604 ret = gen_rtx_PLUS (Pmode, gen_rtx_REG (Pmode, 7), temp2); 3605 break; 3606 3607 default: 3608 abort (); 3609 } 3610 3611 else 3612 abort (); /* for now ... */ 3613 3614 return ret; 3615} 3616 3617 3618/* Legitimize PIC addresses. If the address is already position-independent, 3619 we return ORIG. Newly generated position-independent addresses go into a 3620 reg. This is REG if nonzero, otherwise we allocate register(s) as 3621 necessary. */ 3622 3623rtx 3624legitimize_pic_address (rtx orig, enum machine_mode mode ATTRIBUTE_UNUSED, 3625 rtx reg) 3626{ 3627 if (GET_CODE (orig) == SYMBOL_REF) 3628 { 3629 rtx pic_ref, address; 3630 rtx insn; 3631 3632 if (reg == 0) 3633 { 3634 if (reload_in_progress || reload_completed) 3635 abort (); 3636 else 3637 reg = gen_reg_rtx (Pmode); 3638 } 3639 3640 if (flag_pic == 2) 3641 { 3642 /* If not during reload, allocate another temp reg here for loading 3643 in the address, so that these instructions can be optimized 3644 properly. */ 3645 rtx temp_reg = ((reload_in_progress || reload_completed) 3646 ? reg : gen_reg_rtx (Pmode)); 3647 3648 /* Must put the SYMBOL_REF inside an UNSPEC here so that cse 3649 won't get confused into thinking that these two instructions 3650 are loading in the true address of the symbol. If in the 3651 future a PIC rtx exists, that should be used instead. */ 3652 if (Pmode == SImode) 3653 { 3654 emit_insn (gen_movsi_high_pic (temp_reg, orig)); 3655 emit_insn (gen_movsi_lo_sum_pic (temp_reg, temp_reg, orig)); 3656 } 3657 else 3658 { 3659 emit_insn (gen_movdi_high_pic (temp_reg, orig)); 3660 emit_insn (gen_movdi_lo_sum_pic (temp_reg, temp_reg, orig)); 3661 } 3662 address = temp_reg; 3663 } 3664 else 3665 address = orig; 3666 3667 pic_ref = gen_rtx_MEM (Pmode, 3668 gen_rtx_PLUS (Pmode, 3669 pic_offset_table_rtx, address)); 3670 current_function_uses_pic_offset_table = 1; 3671 RTX_UNCHANGING_P (pic_ref) = 1; 3672 insn = emit_move_insn (reg, pic_ref); 3673 /* Put a REG_EQUAL note on this insn, so that it can be optimized 3674 by loop. */ 3675 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUAL, orig, 3676 REG_NOTES (insn)); 3677 return reg; 3678 } 3679 else if (GET_CODE (orig) == CONST) 3680 { 3681 rtx base, offset; 3682 3683 if (GET_CODE (XEXP (orig, 0)) == PLUS 3684 && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx) 3685 return orig; 3686 3687 if (reg == 0) 3688 { 3689 if (reload_in_progress || reload_completed) 3690 abort (); 3691 else 3692 reg = gen_reg_rtx (Pmode); 3693 } 3694 3695 if (GET_CODE (XEXP (orig, 0)) == PLUS) 3696 { 3697 base = legitimize_pic_address (XEXP (XEXP (orig, 0), 0), Pmode, reg); 3698 offset = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode, 3699 base == reg ? 0 : reg); 3700 } 3701 else 3702 abort (); 3703 3704 if (GET_CODE (offset) == CONST_INT) 3705 { 3706 if (SMALL_INT (offset)) 3707 return plus_constant (base, INTVAL (offset)); 3708 else if (! reload_in_progress && ! reload_completed) 3709 offset = force_reg (Pmode, offset); 3710 else 3711 /* If we reach here, then something is seriously wrong. */ 3712 abort (); 3713 } 3714 return gen_rtx_PLUS (Pmode, base, offset); 3715 } 3716 else if (GET_CODE (orig) == LABEL_REF) 3717 /* ??? Why do we do this? */ 3718 /* Now movsi_pic_label_ref uses it, but we ought to be checking that 3719 the register is live instead, in case it is eliminated. */ 3720 current_function_uses_pic_offset_table = 1; 3721 3722 return orig; 3723} 3724 3725/* Try machine-dependent ways of modifying an illegitimate address X 3726 to be legitimate. If we find one, return the new, valid address. 3727 3728 OLDX is the address as it was before break_out_memory_refs was called. 3729 In some cases it is useful to look at this to decide what needs to be done. 3730 3731 MODE is the mode of the operand pointed to by X. */ 3732 3733rtx 3734legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED, enum machine_mode mode) 3735{ 3736 rtx orig_x = x; 3737 3738 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == MULT) 3739 x = gen_rtx_PLUS (Pmode, XEXP (x, 1), 3740 force_operand (XEXP (x, 0), NULL_RTX)); 3741 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == MULT) 3742 x = gen_rtx_PLUS (Pmode, XEXP (x, 0), 3743 force_operand (XEXP (x, 1), NULL_RTX)); 3744 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == PLUS) 3745 x = gen_rtx_PLUS (Pmode, force_operand (XEXP (x, 0), NULL_RTX), 3746 XEXP (x, 1)); 3747 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == PLUS) 3748 x = gen_rtx_PLUS (Pmode, XEXP (x, 0), 3749 force_operand (XEXP (x, 1), NULL_RTX)); 3750 3751 if (x != orig_x && legitimate_address_p (mode, x, FALSE)) 3752 return x; 3753 3754 if (tls_symbolic_operand (x)) 3755 x = legitimize_tls_address (x); 3756 else if (flag_pic) 3757 x = legitimize_pic_address (x, mode, 0); 3758 else if (GET_CODE (x) == PLUS && CONSTANT_ADDRESS_P (XEXP (x, 1))) 3759 x = gen_rtx_PLUS (Pmode, XEXP (x, 0), 3760 copy_to_mode_reg (Pmode, XEXP (x, 1))); 3761 else if (GET_CODE (x) == PLUS && CONSTANT_ADDRESS_P (XEXP (x, 0))) 3762 x = gen_rtx_PLUS (Pmode, XEXP (x, 1), 3763 copy_to_mode_reg (Pmode, XEXP (x, 0))); 3764 else if (GET_CODE (x) == SYMBOL_REF 3765 || GET_CODE (x) == CONST 3766 || GET_CODE (x) == LABEL_REF) 3767 x = copy_to_suggested_reg (x, NULL_RTX, Pmode); 3768 return x; 3769} 3770 3771/* Emit special PIC prologues. */ 3772 3773void 3774load_pic_register (void) 3775{ 3776 /* Labels to get the PC in the prologue of this function. */ 3777 int orig_flag_pic = flag_pic; 3778 3779 if (! flag_pic) 3780 abort (); 3781 3782 /* If we haven't emitted the special get_pc helper function, do so now. */ 3783 if (get_pc_symbol_name[0] == 0) 3784 { 3785 int align; 3786 3787 ASM_GENERATE_INTERNAL_LABEL (get_pc_symbol_name, "LGETPC", 0); 3788 text_section (); 3789 3790 align = floor_log2 (FUNCTION_BOUNDARY / BITS_PER_UNIT); 3791 if (align > 0) 3792 ASM_OUTPUT_ALIGN (asm_out_file, align); 3793 (*targetm.asm_out.internal_label) (asm_out_file, "LGETPC", 0); 3794 fputs ("\tretl\n\tadd\t%o7, %l7, %l7\n", asm_out_file); 3795 } 3796 3797 /* Initialize every time through, since we can't easily 3798 know this to be permanent. */ 3799 global_offset_table = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_"); 3800 get_pc_symbol = gen_rtx_SYMBOL_REF (Pmode, get_pc_symbol_name); 3801 flag_pic = 0; 3802 3803 emit_insn (gen_get_pc (pic_offset_table_rtx, global_offset_table, 3804 get_pc_symbol)); 3805 3806 flag_pic = orig_flag_pic; 3807 3808 /* Need to emit this whether or not we obey regdecls, 3809 since setjmp/longjmp can cause life info to screw up. 3810 ??? In the case where we don't obey regdecls, this is not sufficient 3811 since we may not fall out the bottom. */ 3812 emit_insn (gen_rtx_USE (VOIDmode, pic_offset_table_rtx)); 3813} 3814 3815/* Return 1 if RTX is a MEM which is known to be aligned to at 3816 least a DESIRED byte boundary. */ 3817 3818int 3819mem_min_alignment (rtx mem, int desired) 3820{ 3821 rtx addr, base, offset; 3822 3823 /* If it's not a MEM we can't accept it. */ 3824 if (GET_CODE (mem) != MEM) 3825 return 0; 3826 3827 addr = XEXP (mem, 0); 3828 base = offset = NULL_RTX; 3829 if (GET_CODE (addr) == PLUS) 3830 { 3831 if (GET_CODE (XEXP (addr, 0)) == REG) 3832 { 3833 base = XEXP (addr, 0); 3834 3835 /* What we are saying here is that if the base 3836 REG is aligned properly, the compiler will make 3837 sure any REG based index upon it will be so 3838 as well. */ 3839 if (GET_CODE (XEXP (addr, 1)) == CONST_INT) 3840 offset = XEXP (addr, 1); 3841 else 3842 offset = const0_rtx; 3843 } 3844 } 3845 else if (GET_CODE (addr) == REG) 3846 { 3847 base = addr; 3848 offset = const0_rtx; 3849 } 3850 3851 if (base != NULL_RTX) 3852 { 3853 int regno = REGNO (base); 3854 3855 if (regno != HARD_FRAME_POINTER_REGNUM && regno != STACK_POINTER_REGNUM) 3856 { 3857 /* Check if the compiler has recorded some information 3858 about the alignment of the base REG. If reload has 3859 completed, we already matched with proper alignments. 3860 If not running global_alloc, reload might give us 3861 unaligned pointer to local stack though. */ 3862 if (((cfun != 0 3863 && REGNO_POINTER_ALIGN (regno) >= desired * BITS_PER_UNIT) 3864 || (optimize && reload_completed)) 3865 && (INTVAL (offset) & (desired - 1)) == 0) 3866 return 1; 3867 } 3868 else 3869 { 3870 if (((INTVAL (offset) - SPARC_STACK_BIAS) & (desired - 1)) == 0) 3871 return 1; 3872 } 3873 } 3874 else if (! TARGET_UNALIGNED_DOUBLES 3875 || CONSTANT_P (addr) 3876 || GET_CODE (addr) == LO_SUM) 3877 { 3878 /* Anything else we know is properly aligned unless TARGET_UNALIGNED_DOUBLES 3879 is true, in which case we can only assume that an access is aligned if 3880 it is to a constant address, or the address involves a LO_SUM. */ 3881 return 1; 3882 } 3883 3884 /* An obviously unaligned address. */ 3885 return 0; 3886} 3887 3888 3889/* Vectors to keep interesting information about registers where it can easily 3890 be got. We used to use the actual mode value as the bit number, but there 3891 are more than 32 modes now. Instead we use two tables: one indexed by 3892 hard register number, and one indexed by mode. */ 3893 3894/* The purpose of sparc_mode_class is to shrink the range of modes so that 3895 they all fit (as bit numbers) in a 32 bit word (again). Each real mode is 3896 mapped into one sparc_mode_class mode. */ 3897 3898enum sparc_mode_class { 3899 S_MODE, D_MODE, T_MODE, O_MODE, 3900 SF_MODE, DF_MODE, TF_MODE, OF_MODE, 3901 CC_MODE, CCFP_MODE 3902}; 3903 3904/* Modes for single-word and smaller quantities. */ 3905#define S_MODES ((1 << (int) S_MODE) | (1 << (int) SF_MODE)) 3906 3907/* Modes for double-word and smaller quantities. */ 3908#define D_MODES (S_MODES | (1 << (int) D_MODE) | (1 << DF_MODE)) 3909 3910/* Modes for quad-word and smaller quantities. */ 3911#define T_MODES (D_MODES | (1 << (int) T_MODE) | (1 << (int) TF_MODE)) 3912 3913/* Modes for 8-word and smaller quantities. */ 3914#define O_MODES (T_MODES | (1 << (int) O_MODE) | (1 << (int) OF_MODE)) 3915 3916/* Modes for single-float quantities. We must allow any single word or 3917 smaller quantity. This is because the fix/float conversion instructions 3918 take integer inputs/outputs from the float registers. */ 3919#define SF_MODES (S_MODES) 3920 3921/* Modes for double-float and smaller quantities. */ 3922#define DF_MODES (S_MODES | D_MODES) 3923 3924/* Modes for double-float only quantities. */ 3925#define DF_MODES_NO_S ((1 << (int) D_MODE) | (1 << (int) DF_MODE)) 3926 3927/* Modes for quad-float only quantities. */ 3928#define TF_ONLY_MODES (1 << (int) TF_MODE) 3929 3930/* Modes for quad-float and smaller quantities. */ 3931#define TF_MODES (DF_MODES | TF_ONLY_MODES) 3932 3933/* Modes for quad-float and double-float quantities. */ 3934#define TF_MODES_NO_S (DF_MODES_NO_S | TF_ONLY_MODES) 3935 3936/* Modes for quad-float pair only quantities. */ 3937#define OF_ONLY_MODES (1 << (int) OF_MODE) 3938 3939/* Modes for quad-float pairs and smaller quantities. */ 3940#define OF_MODES (TF_MODES | OF_ONLY_MODES) 3941 3942#define OF_MODES_NO_S (TF_MODES_NO_S | OF_ONLY_MODES) 3943 3944/* Modes for condition codes. */ 3945#define CC_MODES (1 << (int) CC_MODE) 3946#define CCFP_MODES (1 << (int) CCFP_MODE) 3947 3948/* Value is 1 if register/mode pair is acceptable on sparc. 3949 The funny mixture of D and T modes is because integer operations 3950 do not specially operate on tetra quantities, so non-quad-aligned 3951 registers can hold quadword quantities (except %o4 and %i4 because 3952 they cross fixed registers). */ 3953 3954/* This points to either the 32 bit or the 64 bit version. */ 3955const int *hard_regno_mode_classes; 3956 3957static const int hard_32bit_mode_classes[] = { 3958 S_MODES, S_MODES, T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES, 3959 T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES, D_MODES, S_MODES, 3960 T_MODES, S_MODES, T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES, 3961 T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES, D_MODES, S_MODES, 3962 3963 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES, 3964 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES, 3965 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES, 3966 OF_MODES, SF_MODES, DF_MODES, SF_MODES, TF_MODES, SF_MODES, DF_MODES, SF_MODES, 3967 3968 /* FP regs f32 to f63. Only the even numbered registers actually exist, 3969 and none can hold SFmode/SImode values. */ 3970 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, 3971 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, 3972 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, 3973 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, TF_MODES_NO_S, 0, DF_MODES_NO_S, 0, 3974 3975 /* %fcc[0123] */ 3976 CCFP_MODES, CCFP_MODES, CCFP_MODES, CCFP_MODES, 3977 3978 /* %icc */ 3979 CC_MODES 3980}; 3981 3982static const int hard_64bit_mode_classes[] = { 3983 D_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, 3984 O_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, 3985 T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, 3986 O_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, 3987 3988 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES, 3989 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES, 3990 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES, 3991 OF_MODES, SF_MODES, DF_MODES, SF_MODES, TF_MODES, SF_MODES, DF_MODES, SF_MODES, 3992 3993 /* FP regs f32 to f63. Only the even numbered registers actually exist, 3994 and none can hold SFmode/SImode values. */ 3995 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, 3996 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, 3997 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, 3998 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, TF_MODES_NO_S, 0, DF_MODES_NO_S, 0, 3999 4000 /* %fcc[0123] */ 4001 CCFP_MODES, CCFP_MODES, CCFP_MODES, CCFP_MODES, 4002 4003 /* %icc */ 4004 CC_MODES 4005}; 4006 4007int sparc_mode_class [NUM_MACHINE_MODES]; 4008 4009enum reg_class sparc_regno_reg_class[FIRST_PSEUDO_REGISTER]; 4010 4011static void 4012sparc_init_modes (void) 4013{ 4014 int i; 4015 4016 for (i = 0; i < NUM_MACHINE_MODES; i++) 4017 { 4018 switch (GET_MODE_CLASS (i)) 4019 { 4020 case MODE_INT: 4021 case MODE_PARTIAL_INT: 4022 case MODE_COMPLEX_INT: 4023 if (GET_MODE_SIZE (i) <= 4) 4024 sparc_mode_class[i] = 1 << (int) S_MODE; 4025 else if (GET_MODE_SIZE (i) == 8) 4026 sparc_mode_class[i] = 1 << (int) D_MODE; 4027 else if (GET_MODE_SIZE (i) == 16) 4028 sparc_mode_class[i] = 1 << (int) T_MODE; 4029 else if (GET_MODE_SIZE (i) == 32) 4030 sparc_mode_class[i] = 1 << (int) O_MODE; 4031 else 4032 sparc_mode_class[i] = 0; 4033 break; 4034 case MODE_FLOAT: 4035 case MODE_COMPLEX_FLOAT: 4036 if (GET_MODE_SIZE (i) <= 4) 4037 sparc_mode_class[i] = 1 << (int) SF_MODE; 4038 else if (GET_MODE_SIZE (i) == 8) 4039 sparc_mode_class[i] = 1 << (int) DF_MODE; 4040 else if (GET_MODE_SIZE (i) == 16) 4041 sparc_mode_class[i] = 1 << (int) TF_MODE; 4042 else if (GET_MODE_SIZE (i) == 32) 4043 sparc_mode_class[i] = 1 << (int) OF_MODE; 4044 else 4045 sparc_mode_class[i] = 0; 4046 break; 4047 case MODE_CC: 4048 if (i == (int) CCFPmode || i == (int) CCFPEmode) 4049 sparc_mode_class[i] = 1 << (int) CCFP_MODE; 4050 else 4051 sparc_mode_class[i] = 1 << (int) CC_MODE; 4052 break; 4053 default: 4054 sparc_mode_class[i] = 0; 4055 break; 4056 } 4057 } 4058 4059 if (TARGET_ARCH64) 4060 hard_regno_mode_classes = hard_64bit_mode_classes; 4061 else 4062 hard_regno_mode_classes = hard_32bit_mode_classes; 4063 4064 /* Initialize the array used by REGNO_REG_CLASS. */ 4065 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) 4066 { 4067 if (i < 16 && TARGET_V8PLUS) 4068 sparc_regno_reg_class[i] = I64_REGS; 4069 else if (i < 32 || i == FRAME_POINTER_REGNUM) 4070 sparc_regno_reg_class[i] = GENERAL_REGS; 4071 else if (i < 64) 4072 sparc_regno_reg_class[i] = FP_REGS; 4073 else if (i < 96) 4074 sparc_regno_reg_class[i] = EXTRA_FP_REGS; 4075 else if (i < 100) 4076 sparc_regno_reg_class[i] = FPCC_REGS; 4077 else 4078 sparc_regno_reg_class[i] = NO_REGS; 4079 } 4080} 4081 4082/* Save non call used registers from LOW to HIGH at BASE+OFFSET. 4083 N_REGS is the number of 4-byte regs saved thus far. This applies even to 4084 v9 int regs as it simplifies the code. */ 4085 4086static int 4087save_regs (FILE *file, int low, int high, const char *base, 4088 int offset, int n_regs, HOST_WIDE_INT real_offset) 4089{ 4090 int i; 4091 4092 if (TARGET_ARCH64 && high <= 32) 4093 { 4094 for (i = low; i < high; i++) 4095 { 4096 if (regs_ever_live[i] && ! call_used_regs[i]) 4097 { 4098 fprintf (file, "\tstx\t%s, [%s+%d]\n", 4099 reg_names[i], base, offset + 4 * n_regs); 4100 if (dwarf2out_do_frame ()) 4101 dwarf2out_reg_save ("", i, real_offset + 4 * n_regs); 4102 n_regs += 2; 4103 } 4104 } 4105 } 4106 else 4107 { 4108 for (i = low; i < high; i += 2) 4109 { 4110 if (regs_ever_live[i] && ! call_used_regs[i]) 4111 { 4112 if (regs_ever_live[i+1] && ! call_used_regs[i+1]) 4113 { 4114 fprintf (file, "\tstd\t%s, [%s+%d]\n", 4115 reg_names[i], base, offset + 4 * n_regs); 4116 if (dwarf2out_do_frame ()) 4117 { 4118 char *l = dwarf2out_cfi_label (); 4119 dwarf2out_reg_save (l, i, real_offset + 4 * n_regs); 4120 dwarf2out_reg_save (l, i+1, real_offset + 4 * n_regs + 4); 4121 } 4122 n_regs += 2; 4123 } 4124 else 4125 { 4126 fprintf (file, "\tst\t%s, [%s+%d]\n", 4127 reg_names[i], base, offset + 4 * n_regs); 4128 if (dwarf2out_do_frame ()) 4129 dwarf2out_reg_save ("", i, real_offset + 4 * n_regs); 4130 n_regs += 2; 4131 } 4132 } 4133 else 4134 { 4135 if (regs_ever_live[i+1] && ! call_used_regs[i+1]) 4136 { 4137 fprintf (file, "\tst\t%s, [%s+%d]\n", 4138 reg_names[i+1], base, offset + 4 * n_regs + 4); 4139 if (dwarf2out_do_frame ()) 4140 dwarf2out_reg_save ("", i + 1, real_offset + 4 * n_regs + 4); 4141 n_regs += 2; 4142 } 4143 } 4144 } 4145 } 4146 return n_regs; 4147} 4148 4149/* Restore non call used registers from LOW to HIGH at BASE+OFFSET. 4150 4151 N_REGS is the number of 4-byte regs saved thus far. This applies even to 4152 v9 int regs as it simplifies the code. */ 4153 4154static int 4155restore_regs (FILE *file, int low, int high, const char *base, 4156 int offset, int n_regs) 4157{ 4158 int i; 4159 4160 if (TARGET_ARCH64 && high <= 32) 4161 { 4162 for (i = low; i < high; i++) 4163 { 4164 if (regs_ever_live[i] && ! call_used_regs[i]) 4165 fprintf (file, "\tldx\t[%s+%d], %s\n", 4166 base, offset + 4 * n_regs, reg_names[i]), 4167 n_regs += 2; 4168 } 4169 } 4170 else 4171 { 4172 for (i = low; i < high; i += 2) 4173 { 4174 if (regs_ever_live[i] && ! call_used_regs[i]) 4175 if (regs_ever_live[i+1] && ! call_used_regs[i+1]) 4176 fprintf (file, "\tldd\t[%s+%d], %s\n", 4177 base, offset + 4 * n_regs, reg_names[i]), 4178 n_regs += 2; 4179 else 4180 fprintf (file, "\tld\t[%s+%d], %s\n", 4181 base, offset + 4 * n_regs, reg_names[i]), 4182 n_regs += 2; 4183 else if (regs_ever_live[i+1] && ! call_used_regs[i+1]) 4184 fprintf (file, "\tld\t[%s+%d], %s\n", 4185 base, offset + 4 * n_regs + 4, reg_names[i+1]), 4186 n_regs += 2; 4187 } 4188 } 4189 return n_regs; 4190} 4191 4192/* Compute the frame size required by the function. This function is called 4193 during the reload pass and also by output_function_prologue(). */ 4194 4195HOST_WIDE_INT 4196compute_frame_size (HOST_WIDE_INT size, int leaf_function) 4197{ 4198 int n_regs = 0, i; 4199 int outgoing_args_size = (current_function_outgoing_args_size 4200 + REG_PARM_STACK_SPACE (current_function_decl)); 4201 4202 /* N_REGS is the number of 4-byte regs saved thus far. This applies 4203 even to v9 int regs to be consistent with save_regs/restore_regs. */ 4204 4205 if (TARGET_ARCH64) 4206 { 4207 for (i = 0; i < 8; i++) 4208 if (regs_ever_live[i] && ! call_used_regs[i]) 4209 n_regs += 2; 4210 } 4211 else 4212 { 4213 for (i = 0; i < 8; i += 2) 4214 if ((regs_ever_live[i] && ! call_used_regs[i]) 4215 || (regs_ever_live[i+1] && ! call_used_regs[i+1])) 4216 n_regs += 2; 4217 } 4218 4219 for (i = 32; i < (TARGET_V9 ? 96 : 64); i += 2) 4220 if ((regs_ever_live[i] && ! call_used_regs[i]) 4221 || (regs_ever_live[i+1] && ! call_used_regs[i+1])) 4222 n_regs += 2; 4223 4224 /* Set up values for use in `function_epilogue'. */ 4225 num_gfregs = n_regs; 4226 4227 if (leaf_function && n_regs == 0 4228 && size == 0 && current_function_outgoing_args_size == 0) 4229 { 4230 actual_fsize = apparent_fsize = 0; 4231 } 4232 else 4233 { 4234 /* We subtract STARTING_FRAME_OFFSET, remember it's negative. */ 4235 apparent_fsize = (size - STARTING_FRAME_OFFSET + 7) & -8; 4236 apparent_fsize += n_regs * 4; 4237 actual_fsize = apparent_fsize + ((outgoing_args_size + 7) & -8); 4238 } 4239 4240 /* Make sure nothing can clobber our register windows. 4241 If a SAVE must be done, or there is a stack-local variable, 4242 the register window area must be allocated. 4243 ??? For v8 we apparently need an additional 8 bytes of reserved space. */ 4244 if (leaf_function == 0 || size > 0) 4245 actual_fsize += (16 * UNITS_PER_WORD) + (TARGET_ARCH64 ? 0 : 8); 4246 4247 return SPARC_STACK_ALIGN (actual_fsize); 4248} 4249 4250/* Build big number NUM in register REG and output the result to FILE. 4251 REG is guaranteed to be the only clobbered register. The function 4252 will very likely emit several instructions, so it must not be called 4253 from within a delay slot. */ 4254 4255static void 4256build_big_number (FILE *file, HOST_WIDE_INT num, const char *reg) 4257{ 4258#if HOST_BITS_PER_WIDE_INT == 64 4259 HOST_WIDE_INT high_bits = (num >> 32) & 0xffffffff; 4260 4261 if (high_bits == 0 4262#else 4263 if (num >= 0 4264#endif 4265 || ! TARGET_ARCH64) 4266 { 4267 /* We don't use the 'set' macro because it appears to be broken 4268 in the Solaris 7 assembler. */ 4269 fprintf (file, "\tsethi\t%%hi("HOST_WIDE_INT_PRINT_DEC"), %s\n", 4270 num, reg); 4271 if ((num & 0x3ff) != 0) 4272 fprintf (file, "\tor\t%s, %%lo("HOST_WIDE_INT_PRINT_DEC"), %s\n", 4273 reg, num, reg); 4274 } 4275#if HOST_BITS_PER_WIDE_INT == 64 4276 else if (high_bits == 0xffffffff) /* && TARGET_ARCH64 */ 4277#else 4278 else /* num < 0 && TARGET_ARCH64 */ 4279#endif 4280 { 4281 /* Sethi does not sign extend, so we must use a little trickery 4282 to use it for negative numbers. Invert the constant before 4283 loading it in, then use xor immediate to invert the loaded bits 4284 (along with the upper 32 bits) to the desired constant. This 4285 works because the sethi and immediate fields overlap. */ 4286 HOST_WIDE_INT inv = ~num; 4287 HOST_WIDE_INT low = -0x400 + (num & 0x3ff); 4288 4289 fprintf (file, "\tsethi\t%%hi("HOST_WIDE_INT_PRINT_DEC"), %s\n", 4290 inv, reg); 4291 fprintf (file, "\txor\t%s, "HOST_WIDE_INT_PRINT_DEC", %s\n", 4292 reg, low, reg); 4293 } 4294#if HOST_BITS_PER_WIDE_INT == 64 4295 else /* TARGET_ARCH64 */ 4296 { 4297 /* We don't use the 'setx' macro because if requires a scratch register. 4298 This is the translation of sparc_emit_set_const64_longway into asm. 4299 Hopefully we will soon have prologue/epilogue emitted as RTL. */ 4300 HOST_WIDE_INT low1 = (num >> (32 - 12)) & 0xfff; 4301 HOST_WIDE_INT low2 = (num >> (32 - 12 - 12)) & 0xfff; 4302 HOST_WIDE_INT low3 = (num >> (32 - 12 - 12 - 8)) & 0x0ff; 4303 int to_shift = 12; 4304 4305 /* We don't use the 'set' macro because it appears to be broken 4306 in the Solaris 7 assembler. */ 4307 fprintf (file, "\tsethi\t%%hi("HOST_WIDE_INT_PRINT_DEC"), %s\n", 4308 high_bits, reg); 4309 if ((high_bits & 0x3ff) != 0) 4310 fprintf (file, "\tor\t%s, %%lo("HOST_WIDE_INT_PRINT_DEC"), %s\n", 4311 reg, high_bits, reg); 4312 4313 if (low1 != 0) 4314 { 4315 fprintf (file, "\tsllx\t%s, %d, %s\n", reg, to_shift, reg); 4316 fprintf (file, "\tor\t%s, "HOST_WIDE_INT_PRINT_DEC", %s\n", 4317 reg, low1, reg); 4318 to_shift = 12; 4319 } 4320 else 4321 { 4322 to_shift += 12; 4323 } 4324 if (low2 != 0) 4325 { 4326 fprintf (file, "\tsllx\t%s, %d, %s\n", reg, to_shift, reg); 4327 fprintf (file, "\tor\t%s, "HOST_WIDE_INT_PRINT_DEC", %s\n", 4328 reg, low2, reg); 4329 to_shift = 8; 4330 } 4331 else 4332 { 4333 to_shift += 8; 4334 } 4335 fprintf (file, "\tsllx\t%s, %d, %s\n", reg, to_shift, reg); 4336 if (low3 != 0) 4337 fprintf (file, "\tor\t%s, "HOST_WIDE_INT_PRINT_DEC", %s\n", 4338 reg, low3, reg); 4339 } 4340#endif 4341} 4342 4343/* Output any necessary .register pseudo-ops. */ 4344void 4345sparc_output_scratch_registers (FILE *file ATTRIBUTE_UNUSED) 4346{ 4347#ifdef HAVE_AS_REGISTER_PSEUDO_OP 4348 int i; 4349 4350 if (TARGET_ARCH32) 4351 return; 4352 4353 /* Check if %g[2367] were used without 4354 .register being printed for them already. */ 4355 for (i = 2; i < 8; i++) 4356 { 4357 if (regs_ever_live [i] 4358 && ! sparc_hard_reg_printed [i]) 4359 { 4360 sparc_hard_reg_printed [i] = 1; 4361 fprintf (file, "\t.register\t%%g%d, #scratch\n", i); 4362 } 4363 if (i == 3) i = 5; 4364 } 4365#endif 4366} 4367 4368/* This function generates the assembly code for function entry. 4369 FILE is a stdio stream to output the code to. 4370 SIZE is an int: how many units of temporary storage to allocate. 4371 Refer to the array `regs_ever_live' to determine which registers 4372 to save; `regs_ever_live[I]' is nonzero if register number I 4373 is ever used in the function. This macro is responsible for 4374 knowing which registers should not be saved even if used. */ 4375 4376/* On SPARC, move-double insns between fpu and cpu need an 8-byte block 4377 of memory. If any fpu reg is used in the function, we allocate 4378 such a block here, at the bottom of the frame, just in case it's needed. 4379 4380 If this function is a leaf procedure, then we may choose not 4381 to do a "save" insn. The decision about whether or not 4382 to do this is made in regclass.c. */ 4383 4384static void 4385sparc_output_function_prologue (FILE *file, HOST_WIDE_INT size) 4386{ 4387 if (TARGET_FLAT) 4388 sparc_flat_function_prologue (file, size); 4389 else 4390 sparc_nonflat_function_prologue (file, size, 4391 current_function_uses_only_leaf_regs); 4392} 4393 4394/* Output code for the function prologue. */ 4395 4396static void 4397sparc_nonflat_function_prologue (FILE *file, HOST_WIDE_INT size, 4398 int leaf_function) 4399{ 4400 sparc_output_scratch_registers (file); 4401 4402 /* Need to use actual_fsize, since we are also allocating 4403 space for our callee (and our own register save area). */ 4404 actual_fsize = compute_frame_size (size, leaf_function); 4405 4406 if (leaf_function) 4407 { 4408 frame_base_name = "%sp"; 4409 frame_base_offset = actual_fsize + SPARC_STACK_BIAS; 4410 } 4411 else 4412 { 4413 frame_base_name = "%fp"; 4414 frame_base_offset = SPARC_STACK_BIAS; 4415 } 4416 4417 /* This is only for the human reader. */ 4418 fprintf (file, "\t%s#PROLOGUE# 0\n", ASM_COMMENT_START); 4419 4420 if (actual_fsize == 0) 4421 /* do nothing. */ ; 4422 else if (! leaf_function) 4423 { 4424 if (actual_fsize <= 4096) 4425 fprintf (file, "\tsave\t%%sp, -"HOST_WIDE_INT_PRINT_DEC", %%sp\n", 4426 actual_fsize); 4427 else if (actual_fsize <= 8192) 4428 { 4429 fprintf (file, "\tsave\t%%sp, -4096, %%sp\n"); 4430 fprintf (file, "\tadd\t%%sp, -"HOST_WIDE_INT_PRINT_DEC", %%sp\n", 4431 actual_fsize - 4096); 4432 } 4433 else 4434 { 4435 build_big_number (file, -actual_fsize, "%g1"); 4436 fprintf (file, "\tsave\t%%sp, %%g1, %%sp\n"); 4437 } 4438 } 4439 else /* leaf function */ 4440 { 4441 if (actual_fsize <= 4096) 4442 fprintf (file, "\tadd\t%%sp, -"HOST_WIDE_INT_PRINT_DEC", %%sp\n", 4443 actual_fsize); 4444 else if (actual_fsize <= 8192) 4445 { 4446 fprintf (file, "\tadd\t%%sp, -4096, %%sp\n"); 4447 fprintf (file, "\tadd\t%%sp, -"HOST_WIDE_INT_PRINT_DEC", %%sp\n", 4448 actual_fsize - 4096); 4449 } 4450 else 4451 { 4452 build_big_number (file, -actual_fsize, "%g1"); 4453 fprintf (file, "\tadd\t%%sp, %%g1, %%sp\n"); 4454 } 4455 } 4456 4457 if (dwarf2out_do_frame () && actual_fsize) 4458 { 4459 char *label = dwarf2out_cfi_label (); 4460 4461 /* The canonical frame address refers to the top of the frame. */ 4462 dwarf2out_def_cfa (label, (leaf_function ? STACK_POINTER_REGNUM 4463 : HARD_FRAME_POINTER_REGNUM), 4464 frame_base_offset); 4465 4466 if (! leaf_function) 4467 { 4468 /* Note the register window save. This tells the unwinder that 4469 it needs to restore the window registers from the previous 4470 frame's window save area at 0(cfa). */ 4471 dwarf2out_window_save (label); 4472 4473 /* The return address (-8) is now in %i7. */ 4474 dwarf2out_return_reg (label, 31); 4475 } 4476 } 4477 4478 /* If doing anything with PIC, do it now. */ 4479 if (! flag_pic) 4480 fprintf (file, "\t%s#PROLOGUE# 1\n", ASM_COMMENT_START); 4481 4482 /* Call saved registers are saved just above the outgoing argument area. */ 4483 if (num_gfregs) 4484 { 4485 HOST_WIDE_INT offset, real_offset; 4486 int n_regs; 4487 const char *base; 4488 4489 real_offset = -apparent_fsize; 4490 offset = -apparent_fsize + frame_base_offset; 4491 if (offset < -4096 || offset + num_gfregs * 4 > 4096) 4492 { 4493 /* ??? This might be optimized a little as %g1 might already have a 4494 value close enough that a single add insn will do. */ 4495 /* ??? Although, all of this is probably only a temporary fix 4496 because if %g1 can hold a function result, then 4497 output_function_epilogue will lose (the result will get 4498 clobbered). */ 4499 build_big_number (file, offset, "%g1"); 4500 fprintf (file, "\tadd\t%s, %%g1, %%g1\n", frame_base_name); 4501 base = "%g1"; 4502 offset = 0; 4503 } 4504 else 4505 { 4506 base = frame_base_name; 4507 } 4508 4509 n_regs = save_regs (file, 0, 8, base, offset, 0, real_offset); 4510 save_regs (file, 32, TARGET_V9 ? 96 : 64, base, offset, n_regs, 4511 real_offset); 4512 } 4513} 4514 4515/* Output code to restore any call saved registers. */ 4516 4517static void 4518output_restore_regs (FILE *file, int leaf_function ATTRIBUTE_UNUSED) 4519{ 4520 HOST_WIDE_INT offset; 4521 int n_regs; 4522 const char *base; 4523 4524 offset = -apparent_fsize + frame_base_offset; 4525 if (offset < -4096 || offset + num_gfregs * 4 > 4096 - 8 /*double*/) 4526 { 4527 build_big_number (file, offset, "%g1"); 4528 fprintf (file, "\tadd\t%s, %%g1, %%g1\n", frame_base_name); 4529 base = "%g1"; 4530 offset = 0; 4531 } 4532 else 4533 { 4534 base = frame_base_name; 4535 } 4536 4537 n_regs = restore_regs (file, 0, 8, base, offset, 0); 4538 restore_regs (file, 32, TARGET_V9 ? 96 : 64, base, offset, n_regs); 4539} 4540 4541/* This function generates the assembly code for function exit, 4542 on machines that need it. 4543 4544 The function epilogue should not depend on the current stack pointer! 4545 It should use the frame pointer only. This is mandatory because 4546 of alloca; we also take advantage of it to omit stack adjustments 4547 before returning. */ 4548 4549static void 4550sparc_output_function_epilogue (FILE *file, HOST_WIDE_INT size) 4551{ 4552 if (TARGET_FLAT) 4553 sparc_flat_function_epilogue (file, size); 4554 else 4555 sparc_nonflat_function_epilogue (file, size, 4556 current_function_uses_only_leaf_regs); 4557} 4558 4559/* Output code for the function epilogue. */ 4560 4561static void 4562sparc_nonflat_function_epilogue (FILE *file, 4563 HOST_WIDE_INT size ATTRIBUTE_UNUSED, 4564 int leaf_function) 4565{ 4566 const char *ret; 4567 4568 if (current_function_epilogue_delay_list == 0) 4569 { 4570 /* If code does not drop into the epilogue, we need 4571 do nothing except output pending case vectors. 4572 4573 We have to still output a dummy nop for the sake of 4574 sane backtraces. Otherwise, if the last two instructions 4575 of a function were call foo; dslot; this can make the return 4576 PC of foo (ie. address of call instruction plus 8) point to 4577 the first instruction in the next function. */ 4578 rtx insn, last_real_insn; 4579 4580 insn = get_last_insn (); 4581 4582 last_real_insn = prev_real_insn (insn); 4583 if (last_real_insn 4584 && GET_CODE (last_real_insn) == INSN 4585 && GET_CODE (PATTERN (last_real_insn)) == SEQUENCE) 4586 last_real_insn = XVECEXP (PATTERN (last_real_insn), 0, 0); 4587 4588 if (last_real_insn && GET_CODE (last_real_insn) == CALL_INSN) 4589 fputs("\tnop\n", file); 4590 4591 if (GET_CODE (insn) == NOTE) 4592 insn = prev_nonnote_insn (insn); 4593 if (insn && GET_CODE (insn) == BARRIER) 4594 goto output_vectors; 4595 } 4596 4597 if (num_gfregs) 4598 output_restore_regs (file, leaf_function); 4599 4600 /* Work out how to skip the caller's unimp instruction if required. */ 4601 if (leaf_function) 4602 ret = (SKIP_CALLERS_UNIMP_P ? "jmp\t%o7+12" : "retl"); 4603 else 4604 ret = (SKIP_CALLERS_UNIMP_P ? "jmp\t%i7+12" : "ret"); 4605 4606 if (! leaf_function) 4607 { 4608 if (current_function_calls_eh_return) 4609 { 4610 if (current_function_epilogue_delay_list) 4611 abort (); 4612 if (SKIP_CALLERS_UNIMP_P) 4613 abort (); 4614 4615 fputs ("\trestore\n\tretl\n\tadd\t%sp, %g1, %sp\n", file); 4616 } 4617 /* If we wound up with things in our delay slot, flush them here. */ 4618 else if (current_function_epilogue_delay_list) 4619 { 4620 rtx delay = PATTERN (XEXP (current_function_epilogue_delay_list, 0)); 4621 4622 if (TARGET_V9 && ! epilogue_renumber (&delay, 1)) 4623 { 4624 epilogue_renumber (&delay, 0); 4625 fputs (SKIP_CALLERS_UNIMP_P 4626 ? "\treturn\t%i7+12\n" 4627 : "\treturn\t%i7+8\n", file); 4628 final_scan_insn (XEXP (current_function_epilogue_delay_list, 0), 4629 file, 1, 0, 0, NULL); 4630 } 4631 else 4632 { 4633 rtx insn, src; 4634 4635 if (GET_CODE (delay) != SET) 4636 abort(); 4637 4638 src = SET_SRC (delay); 4639 if (GET_CODE (src) == ASHIFT) 4640 { 4641 if (XEXP (src, 1) != const1_rtx) 4642 abort(); 4643 SET_SRC (delay) 4644 = gen_rtx_PLUS (GET_MODE (src), XEXP (src, 0), 4645 XEXP (src, 0)); 4646 } 4647 4648 insn = gen_rtx_PARALLEL (VOIDmode, 4649 gen_rtvec (2, delay, 4650 gen_rtx_RETURN (VOIDmode))); 4651 insn = emit_jump_insn (insn); 4652 4653 sparc_emitting_epilogue = true; 4654 final_scan_insn (insn, file, 1, 0, 1, NULL); 4655 sparc_emitting_epilogue = false; 4656 } 4657 } 4658 else if (TARGET_V9 && ! SKIP_CALLERS_UNIMP_P) 4659 fputs ("\treturn\t%i7+8\n\tnop\n", file); 4660 else 4661 fprintf (file, "\t%s\n\trestore\n", ret); 4662 } 4663 /* All of the following cases are for leaf functions. */ 4664 else if (current_function_calls_eh_return) 4665 abort (); 4666 else if (current_function_epilogue_delay_list) 4667 { 4668 /* eligible_for_epilogue_delay_slot ensures that if this is a 4669 leaf function, then we will only have insn in the delay slot 4670 if the frame size is zero, thus no adjust for the stack is 4671 needed here. */ 4672 if (actual_fsize != 0) 4673 abort (); 4674 fprintf (file, "\t%s\n", ret); 4675 final_scan_insn (XEXP (current_function_epilogue_delay_list, 0), 4676 file, 1, 0, 1, NULL); 4677 } 4678 /* Output 'nop' instead of 'sub %sp,-0,%sp' when no frame, so as to 4679 avoid generating confusing assembly language output. */ 4680 else if (actual_fsize == 0) 4681 fprintf (file, "\t%s\n\tnop\n", ret); 4682 else if (actual_fsize <= 4096) 4683 fprintf (file, "\t%s\n\tsub\t%%sp, -"HOST_WIDE_INT_PRINT_DEC", %%sp\n", 4684 ret, actual_fsize); 4685 else if (actual_fsize <= 8192) 4686 fprintf (file, "\tsub\t%%sp, -4096, %%sp\n\t%s\n\tsub\t%%sp, -"HOST_WIDE_INT_PRINT_DEC", %%sp\n", 4687 ret, actual_fsize - 4096); 4688 else 4689 { 4690 build_big_number (file, actual_fsize, "%g1"); 4691 fprintf (file, "\t%s\n\tadd\t%%sp, %%g1, %%sp\n", ret); 4692 } 4693 4694 output_vectors: 4695 sparc_output_deferred_case_vectors (); 4696} 4697 4698/* Output a sibling call. */ 4699 4700const char * 4701output_sibcall (rtx insn, rtx call_operand) 4702{ 4703 int leaf_regs = current_function_uses_only_leaf_regs; 4704 rtx operands[3]; 4705 int delay_slot = dbr_sequence_length () > 0; 4706 4707 if (num_gfregs) 4708 { 4709 /* Call to restore global regs might clobber 4710 the delay slot. Instead of checking for this 4711 output the delay slot now. */ 4712 if (delay_slot) 4713 { 4714 rtx delay = NEXT_INSN (insn); 4715 4716 if (! delay) 4717 abort (); 4718 4719 final_scan_insn (delay, asm_out_file, 1, 0, 1, NULL); 4720 PATTERN (delay) = gen_blockage (); 4721 INSN_CODE (delay) = -1; 4722 delay_slot = 0; 4723 } 4724 output_restore_regs (asm_out_file, leaf_regs); 4725 } 4726 4727 operands[0] = call_operand; 4728 4729 if (leaf_regs) 4730 { 4731#ifdef HAVE_AS_RELAX_OPTION 4732 /* If as and ld are relaxing tail call insns into branch always, 4733 use or %o7,%g0,X; call Y; or X,%g0,%o7 always, so that it can 4734 be optimized. With sethi/jmpl as nor ld has no easy way how to 4735 find out if somebody does not branch between the sethi and jmpl. */ 4736 int spare_slot = 0; 4737#else 4738 int spare_slot = ((TARGET_ARCH32 || TARGET_CM_MEDLOW) && ! flag_pic); 4739#endif 4740 HOST_WIDE_INT size = 0; 4741 4742 if ((actual_fsize || ! spare_slot) && delay_slot) 4743 { 4744 rtx delay = NEXT_INSN (insn); 4745 4746 if (! delay) 4747 abort (); 4748 4749 final_scan_insn (delay, asm_out_file, 1, 0, 1, NULL); 4750 PATTERN (delay) = gen_blockage (); 4751 INSN_CODE (delay) = -1; 4752 delay_slot = 0; 4753 } 4754 if (actual_fsize) 4755 { 4756 if (actual_fsize <= 4096) 4757 size = actual_fsize; 4758 else if (actual_fsize <= 8192) 4759 { 4760 fputs ("\tsub\t%sp, -4096, %sp\n", asm_out_file); 4761 size = actual_fsize - 4096; 4762 } 4763 else 4764 { 4765 build_big_number (asm_out_file, actual_fsize, "%g1"); 4766 fputs ("\tadd\t%%sp, %%g1, %%sp\n", asm_out_file); 4767 } 4768 } 4769 if (spare_slot) 4770 { 4771 output_asm_insn ("sethi\t%%hi(%a0), %%g1", operands); 4772 output_asm_insn ("jmpl\t%%g1 + %%lo(%a0), %%g0", operands); 4773 if (size) 4774 fprintf (asm_out_file, "\t sub\t%%sp, -"HOST_WIDE_INT_PRINT_DEC", %%sp\n", size); 4775 else if (! delay_slot) 4776 fputs ("\t nop\n", asm_out_file); 4777 } 4778 else 4779 { 4780 if (size) 4781 fprintf (asm_out_file, "\tsub\t%%sp, -"HOST_WIDE_INT_PRINT_DEC", %%sp\n", size); 4782 /* Use or with rs2 %%g0 instead of mov, so that as/ld can optimize 4783 it into branch if possible. */ 4784 output_asm_insn ("or\t%%o7, %%g0, %%g1", operands); 4785 output_asm_insn ("call\t%a0, 0", operands); 4786 output_asm_insn (" or\t%%g1, %%g0, %%o7", operands); 4787 } 4788 return ""; 4789 } 4790 4791 output_asm_insn ("call\t%a0, 0", operands); 4792 if (delay_slot) 4793 { 4794 rtx delay = NEXT_INSN (insn), pat; 4795 4796 if (! delay) 4797 abort (); 4798 4799 pat = PATTERN (delay); 4800 if (GET_CODE (pat) != SET) 4801 abort (); 4802 4803 operands[0] = SET_DEST (pat); 4804 pat = SET_SRC (pat); 4805 switch (GET_CODE (pat)) 4806 { 4807 case PLUS: 4808 operands[1] = XEXP (pat, 0); 4809 operands[2] = XEXP (pat, 1); 4810 output_asm_insn (" restore %r1, %2, %Y0", operands); 4811 break; 4812 case LO_SUM: 4813 operands[1] = XEXP (pat, 0); 4814 operands[2] = XEXP (pat, 1); 4815 output_asm_insn (" restore %r1, %%lo(%a2), %Y0", operands); 4816 break; 4817 case ASHIFT: 4818 operands[1] = XEXP (pat, 0); 4819 output_asm_insn (" restore %r1, %r1, %Y0", operands); 4820 break; 4821 default: 4822 operands[1] = pat; 4823 output_asm_insn (" restore %%g0, %1, %Y0", operands); 4824 break; 4825 } 4826 PATTERN (delay) = gen_blockage (); 4827 INSN_CODE (delay) = -1; 4828 } 4829 else 4830 fputs ("\t restore\n", asm_out_file); 4831 return ""; 4832} 4833 4834/* Functions for handling argument passing. 4835 4836 For v8 the first six args are normally in registers and the rest are 4837 pushed. Any arg that starts within the first 6 words is at least 4838 partially passed in a register unless its data type forbids. 4839 4840 For v9, the argument registers are laid out as an array of 16 elements 4841 and arguments are added sequentially. The first 6 int args and up to the 4842 first 16 fp args (depending on size) are passed in regs. 4843 4844 Slot Stack Integral Float Float in structure Double Long Double 4845 ---- ----- -------- ----- ------------------ ------ ----------- 4846 15 [SP+248] %f31 %f30,%f31 %d30 4847 14 [SP+240] %f29 %f28,%f29 %d28 %q28 4848 13 [SP+232] %f27 %f26,%f27 %d26 4849 12 [SP+224] %f25 %f24,%f25 %d24 %q24 4850 11 [SP+216] %f23 %f22,%f23 %d22 4851 10 [SP+208] %f21 %f20,%f21 %d20 %q20 4852 9 [SP+200] %f19 %f18,%f19 %d18 4853 8 [SP+192] %f17 %f16,%f17 %d16 %q16 4854 7 [SP+184] %f15 %f14,%f15 %d14 4855 6 [SP+176] %f13 %f12,%f13 %d12 %q12 4856 5 [SP+168] %o5 %f11 %f10,%f11 %d10 4857 4 [SP+160] %o4 %f9 %f8,%f9 %d8 %q8 4858 3 [SP+152] %o3 %f7 %f6,%f7 %d6 4859 2 [SP+144] %o2 %f5 %f4,%f5 %d4 %q4 4860 1 [SP+136] %o1 %f3 %f2,%f3 %d2 4861 0 [SP+128] %o0 %f1 %f0,%f1 %d0 %q0 4862 4863 Here SP = %sp if -mno-stack-bias or %sp+stack_bias otherwise. 4864 4865 Integral arguments are always passed as 64 bit quantities appropriately 4866 extended. 4867 4868 Passing of floating point values is handled as follows. 4869 If a prototype is in scope: 4870 If the value is in a named argument (i.e. not a stdarg function or a 4871 value not part of the `...') then the value is passed in the appropriate 4872 fp reg. 4873 If the value is part of the `...' and is passed in one of the first 6 4874 slots then the value is passed in the appropriate int reg. 4875 If the value is part of the `...' and is not passed in one of the first 6 4876 slots then the value is passed in memory. 4877 If a prototype is not in scope: 4878 If the value is one of the first 6 arguments the value is passed in the 4879 appropriate integer reg and the appropriate fp reg. 4880 If the value is not one of the first 6 arguments the value is passed in 4881 the appropriate fp reg and in memory. 4882 */ 4883 4884/* Maximum number of int regs for args. */ 4885#define SPARC_INT_ARG_MAX 6 4886/* Maximum number of fp regs for args. */ 4887#define SPARC_FP_ARG_MAX 16 4888 4889#define ROUND_ADVANCE(SIZE) (((SIZE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) 4890 4891/* Handle the INIT_CUMULATIVE_ARGS macro. 4892 Initialize a variable CUM of type CUMULATIVE_ARGS 4893 for a call to a function whose data type is FNTYPE. 4894 For a library call, FNTYPE is 0. */ 4895 4896void 4897init_cumulative_args (struct sparc_args *cum, tree fntype, 4898 rtx libname ATTRIBUTE_UNUSED, 4899 tree fndecl ATTRIBUTE_UNUSED) 4900{ 4901 cum->words = 0; 4902 cum->prototype_p = fntype && TYPE_ARG_TYPES (fntype); 4903 cum->libcall_p = fntype == 0; 4904} 4905 4906/* Scan the record type TYPE and return the following predicates: 4907 - INTREGS_P: the record contains at least one field or sub-field 4908 that is eligible for promotion in integer registers. 4909 - FP_REGS_P: the record contains at least one field or sub-field 4910 that is eligible for promotion in floating-point registers. 4911 - PACKED_P: the record contains at least one field that is packed. 4912 4913 Sub-fields are not taken into account for the PACKED_P predicate. */ 4914 4915static void 4916scan_record_type (tree type, int *intregs_p, int *fpregs_p, int *packed_p) 4917{ 4918 tree field; 4919 4920 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field)) 4921 { 4922 if (TREE_CODE (field) == FIELD_DECL) 4923 { 4924 if (TREE_CODE (TREE_TYPE (field)) == RECORD_TYPE) 4925 scan_record_type (TREE_TYPE (field), intregs_p, fpregs_p, 0); 4926 else if (FLOAT_TYPE_P (TREE_TYPE (field)) && TARGET_FPU) 4927 *fpregs_p = 1; 4928 else 4929 *intregs_p = 1; 4930 4931 if (packed_p && DECL_PACKED (field)) 4932 *packed_p = 1; 4933 } 4934 } 4935} 4936 4937/* Compute the slot number to pass an argument in. 4938 Return the slot number or -1 if passing on the stack. 4939 4940 CUM is a variable of type CUMULATIVE_ARGS which gives info about 4941 the preceding args and about the function being called. 4942 MODE is the argument's machine mode. 4943 TYPE is the data type of the argument (as a tree). 4944 This is null for libcalls where that information may 4945 not be available. 4946 NAMED is nonzero if this argument is a named parameter 4947 (otherwise it is an extra parameter matching an ellipsis). 4948 INCOMING_P is zero for FUNCTION_ARG, nonzero for FUNCTION_INCOMING_ARG. 4949 *PREGNO records the register number to use if scalar type. 4950 *PPADDING records the amount of padding needed in words. */ 4951 4952static int 4953function_arg_slotno (const struct sparc_args *cum, enum machine_mode mode, 4954 tree type, int named, int incoming_p, 4955 int *pregno, int *ppadding) 4956{ 4957 int regbase = (incoming_p 4958 ? SPARC_INCOMING_INT_ARG_FIRST 4959 : SPARC_OUTGOING_INT_ARG_FIRST); 4960 int slotno = cum->words; 4961 int regno; 4962 4963 *ppadding = 0; 4964 4965 if (type != 0 && TREE_ADDRESSABLE (type)) 4966 return -1; 4967 if (TARGET_ARCH32 4968 && type != 0 && mode == BLKmode 4969 && TYPE_ALIGN (type) % PARM_BOUNDARY != 0) 4970 return -1; 4971 4972 switch (mode) 4973 { 4974 case VOIDmode : 4975 /* MODE is VOIDmode when generating the actual call. 4976 See emit_call_1. */ 4977 return -1; 4978 4979 case TImode : case CTImode : 4980 if (TARGET_ARCH64 && (slotno & 1) != 0) 4981 slotno++, *ppadding = 1; 4982 /* fallthrough */ 4983 4984 case QImode : case CQImode : 4985 case HImode : case CHImode : 4986 case SImode : case CSImode : 4987 case DImode : case CDImode : 4988 if (slotno >= SPARC_INT_ARG_MAX) 4989 return -1; 4990 regno = regbase + slotno; 4991 break; 4992 4993 case TFmode : case TCmode : 4994 if (TARGET_ARCH64 && (slotno & 1) != 0) 4995 slotno++, *ppadding = 1; 4996 /* fallthrough */ 4997 4998 case SFmode : case SCmode : 4999 case DFmode : case DCmode : 5000 if (TARGET_ARCH32) 5001 { 5002 if (slotno >= SPARC_INT_ARG_MAX) 5003 return -1; 5004 regno = regbase + slotno; 5005 } 5006 else 5007 { 5008 if (TARGET_FPU && named) 5009 { 5010 if (slotno >= SPARC_FP_ARG_MAX) 5011 return -1; 5012 regno = SPARC_FP_ARG_FIRST + slotno * 2; 5013 if (mode == SFmode) 5014 regno++; 5015 } 5016 else 5017 { 5018 if (slotno >= SPARC_INT_ARG_MAX) 5019 return -1; 5020 regno = regbase + slotno; 5021 } 5022 } 5023 break; 5024 5025 case BLKmode : 5026 /* For sparc64, objects requiring 16 byte alignment get it. */ 5027 if (TARGET_ARCH64) 5028 { 5029 if (type && TYPE_ALIGN (type) == 128 && (slotno & 1) != 0) 5030 slotno++, *ppadding = 1; 5031 } 5032 5033 if (TARGET_ARCH32 5034 || (type && TREE_CODE (type) == UNION_TYPE)) 5035 { 5036 if (slotno >= SPARC_INT_ARG_MAX) 5037 return -1; 5038 regno = regbase + slotno; 5039 } 5040 else 5041 { 5042 int intregs_p = 0, fpregs_p = 0, packed_p = 0; 5043 5044 /* First see what kinds of registers we would need. */ 5045 scan_record_type (type, &intregs_p, &fpregs_p, &packed_p); 5046 5047 /* The ABI obviously doesn't specify how packed structures 5048 are passed. These are defined to be passed in int regs 5049 if possible, otherwise memory. */ 5050 if (packed_p || !named) 5051 fpregs_p = 0, intregs_p = 1; 5052 5053 /* If all arg slots are filled, then must pass on stack. */ 5054 if (fpregs_p && slotno >= SPARC_FP_ARG_MAX) 5055 return -1; 5056 /* If there are only int args and all int arg slots are filled, 5057 then must pass on stack. */ 5058 if (!fpregs_p && intregs_p && slotno >= SPARC_INT_ARG_MAX) 5059 return -1; 5060 /* Note that even if all int arg slots are filled, fp members may 5061 still be passed in regs if such regs are available. 5062 *PREGNO isn't set because there may be more than one, it's up 5063 to the caller to compute them. */ 5064 return slotno; 5065 } 5066 break; 5067 5068 default : 5069 abort (); 5070 } 5071 5072 *pregno = regno; 5073 return slotno; 5074} 5075 5076/* Handle recursive register counting for structure field layout. */ 5077 5078struct function_arg_record_value_parms 5079{ 5080 rtx ret; /* return expression being built. */ 5081 int slotno; /* slot number of the argument. */ 5082 int named; /* whether the argument is named. */ 5083 int regbase; /* regno of the base register. */ 5084 int stack; /* 1 if part of the argument is on the stack. */ 5085 int intoffset; /* offset of the first pending integer field. */ 5086 unsigned int nregs; /* number of words passed in registers. */ 5087}; 5088 5089static void function_arg_record_value_3 5090 (HOST_WIDE_INT, struct function_arg_record_value_parms *); 5091static void function_arg_record_value_2 5092 (tree, HOST_WIDE_INT, struct function_arg_record_value_parms *, bool); 5093static void function_arg_record_value_1 5094 (tree, HOST_WIDE_INT, struct function_arg_record_value_parms *, bool); 5095static rtx function_arg_record_value (tree, enum machine_mode, int, int, int); 5096static rtx function_arg_union_value (int, enum machine_mode, int, int); 5097 5098/* A subroutine of function_arg_record_value. Traverse the structure 5099 recursively and determine how many registers will be required. */ 5100 5101static void 5102function_arg_record_value_1 (tree type, HOST_WIDE_INT startbitpos, 5103 struct function_arg_record_value_parms *parms, 5104 bool packed_p) 5105{ 5106 tree field; 5107 5108 /* We need to compute how many registers are needed so we can 5109 allocate the PARALLEL but before we can do that we need to know 5110 whether there are any packed fields. The ABI obviously doesn't 5111 specify how structures are passed in this case, so they are 5112 defined to be passed in int regs if possible, otherwise memory, 5113 regardless of whether there are fp values present. */ 5114 5115 if (! packed_p) 5116 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field)) 5117 { 5118 if (TREE_CODE (field) == FIELD_DECL && DECL_PACKED (field)) 5119 { 5120 packed_p = true; 5121 break; 5122 } 5123 } 5124 5125 /* Compute how many registers we need. */ 5126 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field)) 5127 { 5128 if (TREE_CODE (field) == FIELD_DECL) 5129 { 5130 HOST_WIDE_INT bitpos = startbitpos; 5131 5132 if (DECL_SIZE (field) != 0 5133 && host_integerp (bit_position (field), 1)) 5134 bitpos += int_bit_position (field); 5135 5136 /* ??? FIXME: else assume zero offset. */ 5137 5138 if (TREE_CODE (TREE_TYPE (field)) == RECORD_TYPE) 5139 function_arg_record_value_1 (TREE_TYPE (field), 5140 bitpos, 5141 parms, 5142 packed_p); 5143 else if (FLOAT_TYPE_P (TREE_TYPE (field)) 5144 && TARGET_FPU 5145 && parms->named 5146 && ! packed_p) 5147 { 5148 if (parms->intoffset != -1) 5149 { 5150 unsigned int startbit, endbit; 5151 int intslots, this_slotno; 5152 5153 startbit = parms->intoffset & -BITS_PER_WORD; 5154 endbit = (bitpos + BITS_PER_WORD - 1) & -BITS_PER_WORD; 5155 5156 intslots = (endbit - startbit) / BITS_PER_WORD; 5157 this_slotno = parms->slotno + parms->intoffset 5158 / BITS_PER_WORD; 5159 5160 if (intslots > 0 && intslots > SPARC_INT_ARG_MAX - this_slotno) 5161 { 5162 intslots = MAX (0, SPARC_INT_ARG_MAX - this_slotno); 5163 /* We need to pass this field on the stack. */ 5164 parms->stack = 1; 5165 } 5166 5167 parms->nregs += intslots; 5168 parms->intoffset = -1; 5169 } 5170 5171 /* There's no need to check this_slotno < SPARC_FP_ARG MAX. 5172 If it wasn't true we wouldn't be here. */ 5173 parms->nregs += 1; 5174 if (TREE_CODE (TREE_TYPE (field)) == COMPLEX_TYPE) 5175 parms->nregs += 1; 5176 } 5177 else 5178 { 5179 if (parms->intoffset == -1) 5180 parms->intoffset = bitpos; 5181 } 5182 } 5183 } 5184} 5185 5186/* A subroutine of function_arg_record_value. Assign the bits of the 5187 structure between parms->intoffset and bitpos to integer registers. */ 5188 5189static void 5190function_arg_record_value_3 (HOST_WIDE_INT bitpos, 5191 struct function_arg_record_value_parms *parms) 5192{ 5193 enum machine_mode mode; 5194 unsigned int regno; 5195 unsigned int startbit, endbit; 5196 int this_slotno, intslots, intoffset; 5197 rtx reg; 5198 5199 if (parms->intoffset == -1) 5200 return; 5201 5202 intoffset = parms->intoffset; 5203 parms->intoffset = -1; 5204 5205 startbit = intoffset & -BITS_PER_WORD; 5206 endbit = (bitpos + BITS_PER_WORD - 1) & -BITS_PER_WORD; 5207 intslots = (endbit - startbit) / BITS_PER_WORD; 5208 this_slotno = parms->slotno + intoffset / BITS_PER_WORD; 5209 5210 intslots = MIN (intslots, SPARC_INT_ARG_MAX - this_slotno); 5211 if (intslots <= 0) 5212 return; 5213 5214 /* If this is the trailing part of a word, only load that much into 5215 the register. Otherwise load the whole register. Note that in 5216 the latter case we may pick up unwanted bits. It's not a problem 5217 at the moment but may wish to revisit. */ 5218 5219 if (intoffset % BITS_PER_WORD != 0) 5220 mode = mode_for_size (BITS_PER_WORD - intoffset % BITS_PER_WORD, 5221 MODE_INT, 0); 5222 else 5223 mode = word_mode; 5224 5225 intoffset /= BITS_PER_UNIT; 5226 do 5227 { 5228 regno = parms->regbase + this_slotno; 5229 reg = gen_rtx_REG (mode, regno); 5230 XVECEXP (parms->ret, 0, parms->stack + parms->nregs) 5231 = gen_rtx_EXPR_LIST (VOIDmode, reg, GEN_INT (intoffset)); 5232 5233 this_slotno += 1; 5234 intoffset = (intoffset | (UNITS_PER_WORD-1)) + 1; 5235 mode = word_mode; 5236 parms->nregs += 1; 5237 intslots -= 1; 5238 } 5239 while (intslots > 0); 5240} 5241 5242/* A subroutine of function_arg_record_value. Traverse the structure 5243 recursively and assign bits to floating point registers. Track which 5244 bits in between need integer registers; invoke function_arg_record_value_3 5245 to make that happen. */ 5246 5247static void 5248function_arg_record_value_2 (tree type, HOST_WIDE_INT startbitpos, 5249 struct function_arg_record_value_parms *parms, 5250 bool packed_p) 5251{ 5252 tree field; 5253 5254 if (! packed_p) 5255 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field)) 5256 { 5257 if (TREE_CODE (field) == FIELD_DECL && DECL_PACKED (field)) 5258 { 5259 packed_p = true; 5260 break; 5261 } 5262 } 5263 5264 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field)) 5265 { 5266 if (TREE_CODE (field) == FIELD_DECL) 5267 { 5268 HOST_WIDE_INT bitpos = startbitpos; 5269 5270 if (DECL_SIZE (field) != 0 5271 && host_integerp (bit_position (field), 1)) 5272 bitpos += int_bit_position (field); 5273 5274 /* ??? FIXME: else assume zero offset. */ 5275 5276 if (TREE_CODE (TREE_TYPE (field)) == RECORD_TYPE) 5277 function_arg_record_value_2 (TREE_TYPE (field), 5278 bitpos, 5279 parms, 5280 packed_p); 5281 else if (FLOAT_TYPE_P (TREE_TYPE (field)) 5282 && TARGET_FPU 5283 && parms->named 5284 && ! packed_p) 5285 { 5286 int this_slotno = parms->slotno + bitpos / BITS_PER_WORD; 5287 int regno; 5288 enum machine_mode mode = DECL_MODE (field); 5289 rtx reg; 5290 5291 function_arg_record_value_3 (bitpos, parms); 5292 regno = SPARC_FP_ARG_FIRST + this_slotno * 2 5293 + ((mode == SFmode || mode == SCmode) 5294 && (bitpos & 32) != 0); 5295 switch (mode) 5296 { 5297 case SCmode: mode = SFmode; break; 5298 case DCmode: mode = DFmode; break; 5299 case TCmode: mode = TFmode; break; 5300 default: break; 5301 } 5302 reg = gen_rtx_REG (mode, regno); 5303 XVECEXP (parms->ret, 0, parms->stack + parms->nregs) 5304 = gen_rtx_EXPR_LIST (VOIDmode, reg, 5305 GEN_INT (bitpos / BITS_PER_UNIT)); 5306 parms->nregs += 1; 5307 if (TREE_CODE (TREE_TYPE (field)) == COMPLEX_TYPE) 5308 { 5309 regno += GET_MODE_SIZE (mode) / 4; 5310 reg = gen_rtx_REG (mode, regno); 5311 XVECEXP (parms->ret, 0, parms->stack + parms->nregs) 5312 = gen_rtx_EXPR_LIST (VOIDmode, reg, 5313 GEN_INT ((bitpos + GET_MODE_BITSIZE (mode)) 5314 / BITS_PER_UNIT)); 5315 parms->nregs += 1; 5316 } 5317 } 5318 else 5319 { 5320 if (parms->intoffset == -1) 5321 parms->intoffset = bitpos; 5322 } 5323 } 5324 } 5325} 5326 5327/* Used by function_arg and function_value to implement the complex 5328 conventions of the 64-bit ABI for passing and returning structures. 5329 Return an expression valid as a return value for the two macros 5330 FUNCTION_ARG and FUNCTION_VALUE. 5331 5332 TYPE is the data type of the argument (as a tree). 5333 This is null for libcalls where that information may 5334 not be available. 5335 MODE is the argument's machine mode. 5336 SLOTNO is the index number of the argument's slot in the parameter array. 5337 NAMED is nonzero if this argument is a named parameter 5338 (otherwise it is an extra parameter matching an ellipsis). 5339 REGBASE is the regno of the base register for the parameter array. */ 5340 5341static rtx 5342function_arg_record_value (tree type, enum machine_mode mode, 5343 int slotno, int named, int regbase) 5344{ 5345 HOST_WIDE_INT typesize = int_size_in_bytes (type); 5346 struct function_arg_record_value_parms parms; 5347 unsigned int nregs; 5348 5349 parms.ret = NULL_RTX; 5350 parms.slotno = slotno; 5351 parms.named = named; 5352 parms.regbase = regbase; 5353 parms.stack = 0; 5354 5355 /* Compute how many registers we need. */ 5356 parms.nregs = 0; 5357 parms.intoffset = 0; 5358 function_arg_record_value_1 (type, 0, &parms, false); 5359 5360 /* Take into account pending integer fields. */ 5361 if (parms.intoffset != -1) 5362 { 5363 unsigned int startbit, endbit; 5364 int intslots, this_slotno; 5365 5366 startbit = parms.intoffset & -BITS_PER_WORD; 5367 endbit = (typesize*BITS_PER_UNIT + BITS_PER_WORD - 1) & -BITS_PER_WORD; 5368 intslots = (endbit - startbit) / BITS_PER_WORD; 5369 this_slotno = slotno + parms.intoffset / BITS_PER_WORD; 5370 5371 if (intslots > 0 && intslots > SPARC_INT_ARG_MAX - this_slotno) 5372 { 5373 intslots = MAX (0, SPARC_INT_ARG_MAX - this_slotno); 5374 /* We need to pass this field on the stack. */ 5375 parms.stack = 1; 5376 } 5377 5378 parms.nregs += intslots; 5379 } 5380 nregs = parms.nregs; 5381 5382 /* Allocate the vector and handle some annoying special cases. */ 5383 if (nregs == 0) 5384 { 5385 /* ??? Empty structure has no value? Duh? */ 5386 if (typesize <= 0) 5387 { 5388 /* Though there's nothing really to store, return a word register 5389 anyway so the rest of gcc doesn't go nuts. Returning a PARALLEL 5390 leads to breakage due to the fact that there are zero bytes to 5391 load. */ 5392 return gen_rtx_REG (mode, regbase); 5393 } 5394 else 5395 { 5396 /* ??? C++ has structures with no fields, and yet a size. Give up 5397 for now and pass everything back in integer registers. */ 5398 nregs = (typesize + UNITS_PER_WORD - 1) / UNITS_PER_WORD; 5399 } 5400 if (nregs + slotno > SPARC_INT_ARG_MAX) 5401 nregs = SPARC_INT_ARG_MAX - slotno; 5402 } 5403 if (nregs == 0) 5404 abort (); 5405 5406 parms.ret = gen_rtx_PARALLEL (mode, rtvec_alloc (parms.stack + nregs)); 5407 5408 /* If at least one field must be passed on the stack, generate 5409 (parallel [(expr_list (nil) ...) ...]) so that all fields will 5410 also be passed on the stack. We can't do much better because the 5411 semantics of FUNCTION_ARG_PARTIAL_NREGS doesn't handle the case 5412 of structures for which the fields passed exclusively in registers 5413 are not at the beginning of the structure. */ 5414 if (parms.stack) 5415 XVECEXP (parms.ret, 0, 0) 5416 = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx); 5417 5418 /* Fill in the entries. */ 5419 parms.nregs = 0; 5420 parms.intoffset = 0; 5421 function_arg_record_value_2 (type, 0, &parms, false); 5422 function_arg_record_value_3 (typesize * BITS_PER_UNIT, &parms); 5423 5424 if (parms.nregs != nregs) 5425 abort (); 5426 5427 return parms.ret; 5428} 5429 5430/* Used by function_arg and function_value to implement the conventions 5431 of the 64-bit ABI for passing and returning unions. 5432 Return an expression valid as a return value for the two macros 5433 FUNCTION_ARG and FUNCTION_VALUE. 5434 5435 SIZE is the size in bytes of the union. 5436 MODE is the argument's machine mode. 5437 REGNO is the hard register the union will be passed in. */ 5438 5439static rtx 5440function_arg_union_value (int size, enum machine_mode mode, int slotno, 5441 int regno) 5442{ 5443 int nwords = ROUND_ADVANCE (size), i; 5444 rtx regs; 5445 5446 /* See comment in previous function for empty structures. */ 5447 if (nwords == 0) 5448 return gen_rtx_REG (mode, regno); 5449 5450 if (slotno == SPARC_INT_ARG_MAX - 1) 5451 nwords = 1; 5452 5453 /* Unions are passed left-justified. */ 5454 regs = gen_rtx_PARALLEL (mode, rtvec_alloc (nwords)); 5455 5456 for (i = 0; i < nwords; i++) 5457 XVECEXP (regs, 0, i) 5458 = gen_rtx_EXPR_LIST (VOIDmode, 5459 gen_rtx_REG (word_mode, regno + i), 5460 GEN_INT (UNITS_PER_WORD * i)); 5461 5462 return regs; 5463} 5464 5465/* Handle the FUNCTION_ARG macro. 5466 Determine where to put an argument to a function. 5467 Value is zero to push the argument on the stack, 5468 or a hard register in which to store the argument. 5469 5470 CUM is a variable of type CUMULATIVE_ARGS which gives info about 5471 the preceding args and about the function being called. 5472 MODE is the argument's machine mode. 5473 TYPE is the data type of the argument (as a tree). 5474 This is null for libcalls where that information may 5475 not be available. 5476 NAMED is nonzero if this argument is a named parameter 5477 (otherwise it is an extra parameter matching an ellipsis). 5478 INCOMING_P is zero for FUNCTION_ARG, nonzero for FUNCTION_INCOMING_ARG. */ 5479 5480rtx 5481function_arg (const struct sparc_args *cum, enum machine_mode mode, 5482 tree type, int named, int incoming_p) 5483{ 5484 int regbase = (incoming_p 5485 ? SPARC_INCOMING_INT_ARG_FIRST 5486 : SPARC_OUTGOING_INT_ARG_FIRST); 5487 int slotno, regno, padding; 5488 rtx reg; 5489 5490 slotno = function_arg_slotno (cum, mode, type, named, incoming_p, 5491 ®no, &padding); 5492 5493 if (slotno == -1) 5494 return 0; 5495 5496 if (TARGET_ARCH32) 5497 { 5498 reg = gen_rtx_REG (mode, regno); 5499 return reg; 5500 } 5501 5502 if (type && TREE_CODE (type) == RECORD_TYPE) 5503 { 5504 /* Structures up to 16 bytes in size are passed in arg slots on the 5505 stack and are promoted to registers where possible. */ 5506 5507 if (int_size_in_bytes (type) > 16) 5508 abort (); /* shouldn't get here */ 5509 5510 return function_arg_record_value (type, mode, slotno, named, regbase); 5511 } 5512 else if (type && TREE_CODE (type) == UNION_TYPE) 5513 { 5514 HOST_WIDE_INT size = int_size_in_bytes (type); 5515 5516 if (size > 16) 5517 abort (); /* shouldn't get here */ 5518 5519 return function_arg_union_value (size, mode, slotno, regno); 5520 } 5521 /* v9 fp args in reg slots beyond the int reg slots get passed in regs 5522 but also have the slot allocated for them. 5523 If no prototype is in scope fp values in register slots get passed 5524 in two places, either fp regs and int regs or fp regs and memory. */ 5525 else if ((GET_MODE_CLASS (mode) == MODE_FLOAT 5526 || GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT) 5527 && SPARC_FP_REG_P (regno)) 5528 { 5529 reg = gen_rtx_REG (mode, regno); 5530 if (cum->prototype_p || cum->libcall_p) 5531 { 5532 /* "* 2" because fp reg numbers are recorded in 4 byte 5533 quantities. */ 5534#if 0 5535 /* ??? This will cause the value to be passed in the fp reg and 5536 in the stack. When a prototype exists we want to pass the 5537 value in the reg but reserve space on the stack. That's an 5538 optimization, and is deferred [for a bit]. */ 5539 if ((regno - SPARC_FP_ARG_FIRST) >= SPARC_INT_ARG_MAX * 2) 5540 return gen_rtx_PARALLEL (mode, 5541 gen_rtvec (2, 5542 gen_rtx_EXPR_LIST (VOIDmode, 5543 NULL_RTX, const0_rtx), 5544 gen_rtx_EXPR_LIST (VOIDmode, 5545 reg, const0_rtx))); 5546 else 5547#else 5548 /* ??? It seems that passing back a register even when past 5549 the area declared by REG_PARM_STACK_SPACE will allocate 5550 space appropriately, and will not copy the data onto the 5551 stack, exactly as we desire. 5552 5553 This is due to locate_and_pad_parm being called in 5554 expand_call whenever reg_parm_stack_space > 0, which 5555 while beneficial to our example here, would seem to be 5556 in error from what had been intended. Ho hum... -- r~ */ 5557#endif 5558 return reg; 5559 } 5560 else 5561 { 5562 rtx v0, v1; 5563 5564 if ((regno - SPARC_FP_ARG_FIRST) < SPARC_INT_ARG_MAX * 2) 5565 { 5566 int intreg; 5567 5568 /* On incoming, we don't need to know that the value 5569 is passed in %f0 and %i0, and it confuses other parts 5570 causing needless spillage even on the simplest cases. */ 5571 if (incoming_p) 5572 return reg; 5573 5574 intreg = (SPARC_OUTGOING_INT_ARG_FIRST 5575 + (regno - SPARC_FP_ARG_FIRST) / 2); 5576 5577 v0 = gen_rtx_EXPR_LIST (VOIDmode, reg, const0_rtx); 5578 v1 = gen_rtx_EXPR_LIST (VOIDmode, gen_rtx_REG (mode, intreg), 5579 const0_rtx); 5580 return gen_rtx_PARALLEL (mode, gen_rtvec (2, v0, v1)); 5581 } 5582 else 5583 { 5584 v0 = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx); 5585 v1 = gen_rtx_EXPR_LIST (VOIDmode, reg, const0_rtx); 5586 return gen_rtx_PARALLEL (mode, gen_rtvec (2, v0, v1)); 5587 } 5588 } 5589 } 5590 else 5591 { 5592 /* Scalar or complex int. */ 5593 reg = gen_rtx_REG (mode, regno); 5594 } 5595 5596 return reg; 5597} 5598 5599/* Handle the FUNCTION_ARG_PARTIAL_NREGS macro. 5600 For an arg passed partly in registers and partly in memory, 5601 this is the number of registers used. 5602 For args passed entirely in registers or entirely in memory, zero. 5603 5604 Any arg that starts in the first 6 regs but won't entirely fit in them 5605 needs partial registers on v8. On v9, structures with integer 5606 values in arg slots 5,6 will be passed in %o5 and SP+176, and complex fp 5607 values that begin in the last fp reg [where "last fp reg" varies with the 5608 mode] will be split between that reg and memory. */ 5609 5610int 5611function_arg_partial_nregs (const struct sparc_args *cum, 5612 enum machine_mode mode, tree type, int named) 5613{ 5614 int slotno, regno, padding; 5615 5616 /* We pass 0 for incoming_p here, it doesn't matter. */ 5617 slotno = function_arg_slotno (cum, mode, type, named, 0, ®no, &padding); 5618 5619 if (slotno == -1) 5620 return 0; 5621 5622 if (TARGET_ARCH32) 5623 { 5624 if ((slotno + (mode == BLKmode 5625 ? ROUND_ADVANCE (int_size_in_bytes (type)) 5626 : ROUND_ADVANCE (GET_MODE_SIZE (mode)))) 5627 > NPARM_REGS (SImode)) 5628 return NPARM_REGS (SImode) - slotno; 5629 return 0; 5630 } 5631 else 5632 { 5633 if (type && AGGREGATE_TYPE_P (type)) 5634 { 5635 int size = int_size_in_bytes (type); 5636 int align = TYPE_ALIGN (type); 5637 5638 if (align == 16) 5639 slotno += slotno & 1; 5640 if (size > 8 && size <= 16 5641 && slotno == SPARC_INT_ARG_MAX - 1) 5642 return 1; 5643 } 5644 else if (GET_MODE_CLASS (mode) == MODE_COMPLEX_INT 5645 || (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT 5646 && ! (TARGET_FPU && named))) 5647 { 5648 /* The complex types are passed as packed types. */ 5649 if (GET_MODE_SIZE (mode) <= UNITS_PER_WORD) 5650 return 0; 5651 5652 if (GET_MODE_ALIGNMENT (mode) == 128) 5653 { 5654 slotno += slotno & 1; 5655 5656 /* ??? The mode needs 3 slots? */ 5657 if (slotno == SPARC_INT_ARG_MAX - 2) 5658 return 1; 5659 } 5660 else 5661 { 5662 if (slotno == SPARC_INT_ARG_MAX - 1) 5663 return 1; 5664 } 5665 } 5666 else if (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT) 5667 { 5668 if (GET_MODE_ALIGNMENT (mode) == 128) 5669 slotno += slotno & 1; 5670 if ((slotno + GET_MODE_SIZE (mode) / UNITS_PER_WORD) 5671 > SPARC_FP_ARG_MAX) 5672 return 1; 5673 } 5674 return 0; 5675 } 5676} 5677 5678/* Handle the FUNCTION_ARG_PASS_BY_REFERENCE macro. 5679 !v9: The SPARC ABI stipulates passing struct arguments (of any size) and 5680 quad-precision floats by invisible reference. 5681 v9: Aggregates greater than 16 bytes are passed by reference. 5682 For Pascal, also pass arrays by reference. */ 5683 5684int 5685function_arg_pass_by_reference (const struct sparc_args *cum ATTRIBUTE_UNUSED, 5686 enum machine_mode mode, tree type, 5687 int named ATTRIBUTE_UNUSED) 5688{ 5689 if (TARGET_ARCH32) 5690 { 5691 return ((type && AGGREGATE_TYPE_P (type)) 5692 || mode == SCmode 5693 || GET_MODE_SIZE (mode) > 8); 5694 } 5695 else 5696 { 5697 return ((type && TREE_CODE (type) == ARRAY_TYPE) 5698 /* Consider complex values as aggregates, so care 5699 for CTImode and TCmode. */ 5700 || GET_MODE_SIZE (mode) > 16 5701 || (type 5702 && AGGREGATE_TYPE_P (type) 5703 && (unsigned HOST_WIDE_INT) int_size_in_bytes (type) > 16)); 5704 } 5705} 5706 5707/* Handle the FUNCTION_ARG_ADVANCE macro. 5708 Update the data in CUM to advance over an argument 5709 of mode MODE and data type TYPE. 5710 TYPE is null for libcalls where that information may not be available. */ 5711 5712void 5713function_arg_advance (struct sparc_args *cum, enum machine_mode mode, 5714 tree type, int named) 5715{ 5716 int slotno, regno, padding; 5717 5718 /* We pass 0 for incoming_p here, it doesn't matter. */ 5719 slotno = function_arg_slotno (cum, mode, type, named, 0, ®no, &padding); 5720 5721 /* If register required leading padding, add it. */ 5722 if (slotno != -1) 5723 cum->words += padding; 5724 5725 if (TARGET_ARCH32) 5726 { 5727 cum->words += (mode != BLKmode 5728 ? ROUND_ADVANCE (GET_MODE_SIZE (mode)) 5729 : ROUND_ADVANCE (int_size_in_bytes (type))); 5730 } 5731 else 5732 { 5733 if (type && AGGREGATE_TYPE_P (type)) 5734 { 5735 int size = int_size_in_bytes (type); 5736 5737 if (size <= 8) 5738 ++cum->words; 5739 else if (size <= 16) 5740 cum->words += 2; 5741 else /* passed by reference */ 5742 ++cum->words; 5743 } 5744 else 5745 { 5746 cum->words += (mode != BLKmode 5747 ? ROUND_ADVANCE (GET_MODE_SIZE (mode)) 5748 : ROUND_ADVANCE (int_size_in_bytes (type))); 5749 } 5750 } 5751} 5752 5753/* Handle the FUNCTION_ARG_PADDING macro. 5754 For the 64 bit ABI structs are always stored left shifted in their 5755 argument slot. */ 5756 5757enum direction 5758function_arg_padding (enum machine_mode mode, tree type) 5759{ 5760 if (TARGET_ARCH64 && type != 0 && AGGREGATE_TYPE_P (type)) 5761 return upward; 5762 5763 /* Fall back to the default. */ 5764 return DEFAULT_FUNCTION_ARG_PADDING (mode, type); 5765} 5766 5767/* Handle FUNCTION_VALUE, FUNCTION_OUTGOING_VALUE, and LIBCALL_VALUE macros. 5768 For v9, function return values are subject to the same rules as arguments, 5769 except that up to 32-bytes may be returned in registers. */ 5770 5771rtx 5772function_value (tree type, enum machine_mode mode, int incoming_p) 5773{ 5774 int regno; 5775 5776 if (TARGET_ARCH64 && type) 5777 { 5778 int regbase = (incoming_p 5779 ? SPARC_OUTGOING_INT_ARG_FIRST 5780 : SPARC_INCOMING_INT_ARG_FIRST); 5781 5782 if (TREE_CODE (type) == RECORD_TYPE) 5783 { 5784 /* Structures up to 32 bytes in size are passed in registers, 5785 promoted to fp registers where possible. */ 5786 5787 if (int_size_in_bytes (type) > 32) 5788 abort (); /* shouldn't get here */ 5789 5790 return function_arg_record_value (type, mode, 0, 1, regbase); 5791 } 5792 else if (TREE_CODE (type) == UNION_TYPE) 5793 { 5794 HOST_WIDE_INT size = int_size_in_bytes (type); 5795 5796 if (size > 32) 5797 abort (); /* shouldn't get here */ 5798 5799 return function_arg_union_value (size, mode, 0, regbase); 5800 } 5801 else if (AGGREGATE_TYPE_P (type)) 5802 { 5803 /* All other aggregate types are passed in an integer register 5804 in a mode corresponding to the size of the type. */ 5805 HOST_WIDE_INT bytes = int_size_in_bytes (type); 5806 5807 if (bytes > 32) 5808 abort (); 5809 5810 mode = mode_for_size (bytes * BITS_PER_UNIT, MODE_INT, 0); 5811 5812 /* ??? We probably should have made the same ABI change in 5813 3.4.0 as the one we made for unions. The latter was 5814 required by the SCD though, while the former is not 5815 specified, so we favored compatibility and efficiency. 5816 5817 Now we're stuck for aggregates larger than 16 bytes, 5818 because OImode vanished in the meantime. Let's not 5819 try to be unduly clever, and simply follow the ABI 5820 for unions in that case. */ 5821 if (mode == BLKmode) 5822 return function_arg_union_value (bytes, mode, 0, regbase); 5823 } 5824 else if (GET_MODE_CLASS (mode) == MODE_INT 5825 && GET_MODE_SIZE (mode) < UNITS_PER_WORD) 5826 mode = word_mode; 5827 } 5828 5829 if (incoming_p) 5830 regno = BASE_RETURN_VALUE_REG (mode); 5831 else 5832 regno = BASE_OUTGOING_VALUE_REG (mode); 5833 5834 return gen_rtx_REG (mode, regno); 5835} 5836 5837/* Do what is necessary for `va_start'. We look at the current function 5838 to determine if stdarg or varargs is used and return the address of 5839 the first unnamed parameter. */ 5840 5841rtx 5842sparc_builtin_saveregs (void) 5843{ 5844 int first_reg = current_function_args_info.words; 5845 rtx address; 5846 int regno; 5847 5848 for (regno = first_reg; regno < NPARM_REGS (word_mode); regno++) 5849 emit_move_insn (gen_rtx_MEM (word_mode, 5850 gen_rtx_PLUS (Pmode, 5851 frame_pointer_rtx, 5852 GEN_INT (FIRST_PARM_OFFSET (0) 5853 + (UNITS_PER_WORD 5854 * regno)))), 5855 gen_rtx_REG (word_mode, 5856 BASE_INCOMING_ARG_REG (word_mode) + regno)); 5857 5858 address = gen_rtx_PLUS (Pmode, 5859 frame_pointer_rtx, 5860 GEN_INT (FIRST_PARM_OFFSET (0) 5861 + UNITS_PER_WORD * first_reg)); 5862 5863 return address; 5864} 5865 5866/* Implement `va_start' for varargs and stdarg. */ 5867 5868void 5869sparc_va_start (tree valist, rtx nextarg) 5870{ 5871 nextarg = expand_builtin_saveregs (); 5872 std_expand_builtin_va_start (valist, nextarg); 5873} 5874 5875/* Implement `va_arg'. */ 5876 5877rtx 5878sparc_va_arg (tree valist, tree type) 5879{ 5880 HOST_WIDE_INT size, rsize, align; 5881 tree addr, incr; 5882 rtx addr_rtx; 5883 int indirect = 0; 5884 5885 /* Round up sizeof(type) to a word. */ 5886 size = int_size_in_bytes (type); 5887 rsize = (size + UNITS_PER_WORD - 1) & -UNITS_PER_WORD; 5888 align = 0; 5889 5890 if (TARGET_ARCH64) 5891 { 5892 if (TYPE_ALIGN (type) >= 2 * (unsigned) BITS_PER_WORD) 5893 align = 2 * UNITS_PER_WORD; 5894 5895 /* Consider complex values as aggregates, so care 5896 for CTImode and TCmode. */ 5897 if ((unsigned HOST_WIDE_INT) size > 16) 5898 { 5899 indirect = 1; 5900 size = rsize = UNITS_PER_WORD; 5901 align = 0; 5902 } 5903 else if (AGGREGATE_TYPE_P (type)) 5904 { 5905 /* SPARC-V9 ABI states that structures up to 16 bytes in size 5906 are given whole slots as needed. */ 5907 if (size == 0) 5908 size = rsize = UNITS_PER_WORD; 5909 else 5910 size = rsize; 5911 } 5912 } 5913 else 5914 { 5915 if (AGGREGATE_TYPE_P (type) 5916 || TYPE_MODE (type) == SCmode 5917 || GET_MODE_SIZE (TYPE_MODE (type)) > 8) 5918 { 5919 indirect = 1; 5920 size = rsize = UNITS_PER_WORD; 5921 } 5922 } 5923 5924 incr = valist; 5925 if (align) 5926 { 5927 incr = fold (build (PLUS_EXPR, ptr_type_node, incr, 5928 build_int_2 (align - 1, 0))); 5929 incr = fold (build (BIT_AND_EXPR, ptr_type_node, incr, 5930 build_int_2 (-align, -1))); 5931 } 5932 5933 addr = incr = save_expr (incr); 5934 if (BYTES_BIG_ENDIAN && size < rsize) 5935 { 5936 addr = fold (build (PLUS_EXPR, ptr_type_node, incr, 5937 build_int_2 (rsize - size, 0))); 5938 } 5939 incr = fold (build (PLUS_EXPR, ptr_type_node, incr, 5940 build_int_2 (rsize, 0))); 5941 5942 incr = build (MODIFY_EXPR, ptr_type_node, valist, incr); 5943 TREE_SIDE_EFFECTS (incr) = 1; 5944 expand_expr (incr, const0_rtx, VOIDmode, EXPAND_NORMAL); 5945 5946 addr_rtx = expand_expr (addr, NULL, Pmode, EXPAND_NORMAL); 5947 5948 /* If the address isn't aligned properly for the type, 5949 we may need to copy to a temporary. 5950 FIXME: This is inefficient. Usually we can do this 5951 in registers. */ 5952 if (align == 0 5953 && TYPE_ALIGN (type) > BITS_PER_WORD 5954 && !indirect) 5955 { 5956 /* FIXME: We really need to specify that the temporary is live 5957 for the whole function because expand_builtin_va_arg wants 5958 the alias set to be get_varargs_alias_set (), but in this 5959 case the alias set is that for TYPE and if the memory gets 5960 reused it will be reused with alias set TYPE. */ 5961 rtx tmp = assign_temp (type, 0, 1, 0); 5962 rtx dest_addr; 5963 5964 addr_rtx = force_reg (Pmode, addr_rtx); 5965 addr_rtx = gen_rtx_MEM (BLKmode, addr_rtx); 5966 set_mem_alias_set (addr_rtx, get_varargs_alias_set ()); 5967 set_mem_align (addr_rtx, BITS_PER_WORD); 5968 tmp = shallow_copy_rtx (tmp); 5969 PUT_MODE (tmp, BLKmode); 5970 set_mem_alias_set (tmp, 0); 5971 5972 dest_addr = emit_block_move (tmp, addr_rtx, GEN_INT (rsize), 5973 BLOCK_OP_NORMAL); 5974 if (dest_addr != NULL_RTX) 5975 addr_rtx = dest_addr; 5976 else 5977 addr_rtx = XCEXP (tmp, 0, MEM); 5978 } 5979 5980 if (indirect) 5981 { 5982 addr_rtx = force_reg (Pmode, addr_rtx); 5983 addr_rtx = gen_rtx_MEM (Pmode, addr_rtx); 5984 set_mem_alias_set (addr_rtx, get_varargs_alias_set ()); 5985 } 5986 5987 return addr_rtx; 5988} 5989 5990/* Return the string to output an unconditional branch to LABEL, which is 5991 the operand number of the label. 5992 5993 DEST is the destination insn (i.e. the label), INSN is the source. */ 5994 5995const char * 5996output_ubranch (rtx dest, int label, rtx insn) 5997{ 5998 static char string[64]; 5999 bool noop = false; 6000 char *p; 6001 6002 /* TurboSPARC is reported to have problems with 6003 with 6004 foo: b,a foo 6005 i.e. an empty loop with the annul bit set. The workaround is to use 6006 foo: b foo; nop 6007 instead. */ 6008 6009 if (! TARGET_V9 && flag_delayed_branch 6010 && (INSN_ADDRESSES (INSN_UID (dest)) 6011 == INSN_ADDRESSES (INSN_UID (insn)))) 6012 { 6013 strcpy (string, "b\t"); 6014 noop = true; 6015 } 6016 else 6017 { 6018 bool v9_form = false; 6019 6020 if (TARGET_V9 && INSN_ADDRESSES_SET_P ()) 6021 { 6022 int delta = (INSN_ADDRESSES (INSN_UID (dest)) 6023 - INSN_ADDRESSES (INSN_UID (insn))); 6024 /* Leave some instructions for "slop". */ 6025 if (delta >= -260000 && delta < 260000) 6026 v9_form = true; 6027 } 6028 6029 if (v9_form) 6030 strcpy (string, "ba%*,pt\t%%xcc, "); 6031 else 6032 strcpy (string, "b%*\t"); 6033 } 6034 6035 p = strchr (string, '\0'); 6036 *p++ = '%'; 6037 *p++ = 'l'; 6038 *p++ = '0' + label; 6039 *p++ = '%'; 6040 if (noop) 6041 *p++ = '#'; 6042 else 6043 *p++ = '('; 6044 *p = '\0'; 6045 6046 return string; 6047} 6048 6049/* Return the string to output a conditional branch to LABEL, which is 6050 the operand number of the label. OP is the conditional expression. 6051 XEXP (OP, 0) is assumed to be a condition code register (integer or 6052 floating point) and its mode specifies what kind of comparison we made. 6053 6054 DEST is the destination insn (i.e. the label), INSN is the source. 6055 6056 REVERSED is nonzero if we should reverse the sense of the comparison. 6057 6058 ANNUL is nonzero if we should generate an annulling branch. 6059 6060 NOOP is nonzero if we have to follow this branch by a noop. */ 6061 6062char * 6063output_cbranch (rtx op, rtx dest, int label, int reversed, int annul, 6064 int noop, rtx insn) 6065{ 6066 static char string[50]; 6067 enum rtx_code code = GET_CODE (op); 6068 rtx cc_reg = XEXP (op, 0); 6069 enum machine_mode mode = GET_MODE (cc_reg); 6070 const char *labelno, *branch; 6071 int spaces = 8, far; 6072 char *p; 6073 6074 /* v9 branches are limited to +-1MB. If it is too far away, 6075 change 6076 6077 bne,pt %xcc, .LC30 6078 6079 to 6080 6081 be,pn %xcc, .+12 6082 nop 6083 ba .LC30 6084 6085 and 6086 6087 fbne,a,pn %fcc2, .LC29 6088 6089 to 6090 6091 fbe,pt %fcc2, .+16 6092 nop 6093 ba .LC29 */ 6094 6095 far = TARGET_V9 && (get_attr_length (insn) >= 3); 6096 if (reversed ^ far) 6097 { 6098 /* Reversal of FP compares takes care -- an ordered compare 6099 becomes an unordered compare and vice versa. */ 6100 if (mode == CCFPmode || mode == CCFPEmode) 6101 code = reverse_condition_maybe_unordered (code); 6102 else 6103 code = reverse_condition (code); 6104 } 6105 6106 /* Start by writing the branch condition. */ 6107 if (mode == CCFPmode || mode == CCFPEmode) 6108 { 6109 switch (code) 6110 { 6111 case NE: 6112 branch = "fbne"; 6113 break; 6114 case EQ: 6115 branch = "fbe"; 6116 break; 6117 case GE: 6118 branch = "fbge"; 6119 break; 6120 case GT: 6121 branch = "fbg"; 6122 break; 6123 case LE: 6124 branch = "fble"; 6125 break; 6126 case LT: 6127 branch = "fbl"; 6128 break; 6129 case UNORDERED: 6130 branch = "fbu"; 6131 break; 6132 case ORDERED: 6133 branch = "fbo"; 6134 break; 6135 case UNGT: 6136 branch = "fbug"; 6137 break; 6138 case UNLT: 6139 branch = "fbul"; 6140 break; 6141 case UNEQ: 6142 branch = "fbue"; 6143 break; 6144 case UNGE: 6145 branch = "fbuge"; 6146 break; 6147 case UNLE: 6148 branch = "fbule"; 6149 break; 6150 case LTGT: 6151 branch = "fblg"; 6152 break; 6153 6154 default: 6155 abort (); 6156 } 6157 6158 /* ??? !v9: FP branches cannot be preceded by another floating point 6159 insn. Because there is currently no concept of pre-delay slots, 6160 we can fix this only by always emitting a nop before a floating 6161 point branch. */ 6162 6163 string[0] = '\0'; 6164 if (! TARGET_V9) 6165 strcpy (string, "nop\n\t"); 6166 strcat (string, branch); 6167 } 6168 else 6169 { 6170 switch (code) 6171 { 6172 case NE: 6173 branch = "bne"; 6174 break; 6175 case EQ: 6176 branch = "be"; 6177 break; 6178 case GE: 6179 if (mode == CC_NOOVmode || mode == CCX_NOOVmode) 6180 branch = "bpos"; 6181 else 6182 branch = "bge"; 6183 break; 6184 case GT: 6185 branch = "bg"; 6186 break; 6187 case LE: 6188 branch = "ble"; 6189 break; 6190 case LT: 6191 if (mode == CC_NOOVmode || mode == CCX_NOOVmode) 6192 branch = "bneg"; 6193 else 6194 branch = "bl"; 6195 break; 6196 case GEU: 6197 branch = "bgeu"; 6198 break; 6199 case GTU: 6200 branch = "bgu"; 6201 break; 6202 case LEU: 6203 branch = "bleu"; 6204 break; 6205 case LTU: 6206 branch = "blu"; 6207 break; 6208 6209 default: 6210 abort (); 6211 } 6212 strcpy (string, branch); 6213 } 6214 spaces -= strlen (branch); 6215 p = strchr (string, '\0'); 6216 6217 /* Now add the annulling, the label, and a possible noop. */ 6218 if (annul && ! far) 6219 { 6220 strcpy (p, ",a"); 6221 p += 2; 6222 spaces -= 2; 6223 } 6224 6225 if (TARGET_V9) 6226 { 6227 rtx note; 6228 int v8 = 0; 6229 6230 if (! far && insn && INSN_ADDRESSES_SET_P ()) 6231 { 6232 int delta = (INSN_ADDRESSES (INSN_UID (dest)) 6233 - INSN_ADDRESSES (INSN_UID (insn))); 6234 /* Leave some instructions for "slop". */ 6235 if (delta < -260000 || delta >= 260000) 6236 v8 = 1; 6237 } 6238 6239 if (mode == CCFPmode || mode == CCFPEmode) 6240 { 6241 static char v9_fcc_labelno[] = "%%fccX, "; 6242 /* Set the char indicating the number of the fcc reg to use. */ 6243 v9_fcc_labelno[5] = REGNO (cc_reg) - SPARC_FIRST_V9_FCC_REG + '0'; 6244 labelno = v9_fcc_labelno; 6245 if (v8) 6246 { 6247 if (REGNO (cc_reg) == SPARC_FCC_REG) 6248 labelno = ""; 6249 else 6250 abort (); 6251 } 6252 } 6253 else if (mode == CCXmode || mode == CCX_NOOVmode) 6254 { 6255 labelno = "%%xcc, "; 6256 if (v8) 6257 abort (); 6258 } 6259 else 6260 { 6261 labelno = "%%icc, "; 6262 if (v8) 6263 labelno = ""; 6264 } 6265 6266 if (*labelno && insn && (note = find_reg_note (insn, REG_BR_PROB, NULL_RTX))) 6267 { 6268 strcpy (p, 6269 ((INTVAL (XEXP (note, 0)) >= REG_BR_PROB_BASE / 2) ^ far) 6270 ? ",pt" : ",pn"); 6271 p += 3; 6272 spaces -= 3; 6273 } 6274 } 6275 else 6276 labelno = ""; 6277 6278 if (spaces > 0) 6279 *p++ = '\t'; 6280 else 6281 *p++ = ' '; 6282 strcpy (p, labelno); 6283 p = strchr (p, '\0'); 6284 if (far) 6285 { 6286 strcpy (p, ".+12\n\tnop\n\tb\t"); 6287 if (annul || noop) 6288 p[3] = '6'; 6289 p += 13; 6290 } 6291 *p++ = '%'; 6292 *p++ = 'l'; 6293 /* Set the char indicating the number of the operand containing the 6294 label_ref. */ 6295 *p++ = label + '0'; 6296 *p = '\0'; 6297 if (noop) 6298 strcpy (p, "\n\tnop"); 6299 6300 return string; 6301} 6302 6303/* Emit a library call comparison between floating point X and Y. 6304 COMPARISON is the rtl operator to compare with (EQ, NE, GT, etc.). 6305 TARGET_ARCH64 uses _Qp_* functions, which use pointers to TFmode 6306 values as arguments instead of the TFmode registers themselves, 6307 that's why we cannot call emit_float_lib_cmp. */ 6308void 6309sparc_emit_float_lib_cmp (rtx x, rtx y, enum rtx_code comparison) 6310{ 6311 const char *qpfunc; 6312 rtx slot0, slot1, result, tem, tem2; 6313 enum machine_mode mode; 6314 6315 switch (comparison) 6316 { 6317 case EQ: 6318 qpfunc = (TARGET_ARCH64) ? "_Qp_feq" : "_Q_feq"; 6319 break; 6320 6321 case NE: 6322 qpfunc = (TARGET_ARCH64) ? "_Qp_fne" : "_Q_fne"; 6323 break; 6324 6325 case GT: 6326 qpfunc = (TARGET_ARCH64) ? "_Qp_fgt" : "_Q_fgt"; 6327 break; 6328 6329 case GE: 6330 qpfunc = (TARGET_ARCH64) ? "_Qp_fge" : "_Q_fge"; 6331 break; 6332 6333 case LT: 6334 qpfunc = (TARGET_ARCH64) ? "_Qp_flt" : "_Q_flt"; 6335 break; 6336 6337 case LE: 6338 qpfunc = (TARGET_ARCH64) ? "_Qp_fle" : "_Q_fle"; 6339 break; 6340 6341 case ORDERED: 6342 case UNORDERED: 6343 case UNGT: 6344 case UNLT: 6345 case UNEQ: 6346 case UNGE: 6347 case UNLE: 6348 case LTGT: 6349 qpfunc = (TARGET_ARCH64) ? "_Qp_cmp" : "_Q_cmp"; 6350 break; 6351 6352 default: 6353 abort(); 6354 break; 6355 } 6356 6357 if (TARGET_ARCH64) 6358 { 6359 if (GET_CODE (x) != MEM) 6360 { 6361 slot0 = assign_stack_temp (TFmode, GET_MODE_SIZE(TFmode), 0); 6362 emit_insn (gen_rtx_SET (VOIDmode, slot0, x)); 6363 } 6364 else 6365 slot0 = x; 6366 6367 if (GET_CODE (y) != MEM) 6368 { 6369 slot1 = assign_stack_temp (TFmode, GET_MODE_SIZE(TFmode), 0); 6370 emit_insn (gen_rtx_SET (VOIDmode, slot1, y)); 6371 } 6372 else 6373 slot1 = y; 6374 6375 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, qpfunc), LCT_NORMAL, 6376 DImode, 2, 6377 XEXP (slot0, 0), Pmode, 6378 XEXP (slot1, 0), Pmode); 6379 6380 mode = DImode; 6381 } 6382 else 6383 { 6384 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, qpfunc), LCT_NORMAL, 6385 SImode, 2, 6386 x, TFmode, y, TFmode); 6387 6388 mode = SImode; 6389 } 6390 6391 6392 /* Immediately move the result of the libcall into a pseudo 6393 register so reload doesn't clobber the value if it needs 6394 the return register for a spill reg. */ 6395 result = gen_reg_rtx (mode); 6396 emit_move_insn (result, hard_libcall_value (mode)); 6397 6398 switch (comparison) 6399 { 6400 default: 6401 emit_cmp_insn (result, const0_rtx, NE, NULL_RTX, mode, 0); 6402 break; 6403 case ORDERED: 6404 case UNORDERED: 6405 emit_cmp_insn (result, GEN_INT(3), comparison == UNORDERED ? EQ : NE, 6406 NULL_RTX, mode, 0); 6407 break; 6408 case UNGT: 6409 case UNGE: 6410 emit_cmp_insn (result, const1_rtx, 6411 comparison == UNGT ? GT : NE, NULL_RTX, mode, 0); 6412 break; 6413 case UNLE: 6414 emit_cmp_insn (result, const2_rtx, NE, NULL_RTX, mode, 0); 6415 break; 6416 case UNLT: 6417 tem = gen_reg_rtx (mode); 6418 if (TARGET_ARCH32) 6419 emit_insn (gen_andsi3 (tem, result, const1_rtx)); 6420 else 6421 emit_insn (gen_anddi3 (tem, result, const1_rtx)); 6422 emit_cmp_insn (tem, const0_rtx, NE, NULL_RTX, mode, 0); 6423 break; 6424 case UNEQ: 6425 case LTGT: 6426 tem = gen_reg_rtx (mode); 6427 if (TARGET_ARCH32) 6428 emit_insn (gen_addsi3 (tem, result, const1_rtx)); 6429 else 6430 emit_insn (gen_adddi3 (tem, result, const1_rtx)); 6431 tem2 = gen_reg_rtx (mode); 6432 if (TARGET_ARCH32) 6433 emit_insn (gen_andsi3 (tem2, tem, const2_rtx)); 6434 else 6435 emit_insn (gen_anddi3 (tem2, tem, const2_rtx)); 6436 emit_cmp_insn (tem2, const0_rtx, comparison == UNEQ ? EQ : NE, 6437 NULL_RTX, mode, 0); 6438 break; 6439 } 6440} 6441 6442/* Generate an unsigned DImode to FP conversion. This is the same code 6443 optabs would emit if we didn't have TFmode patterns. */ 6444 6445void 6446sparc_emit_floatunsdi (rtx *operands) 6447{ 6448 rtx neglab, donelab, i0, i1, f0, in, out; 6449 enum machine_mode mode; 6450 6451 out = operands[0]; 6452 in = force_reg (DImode, operands[1]); 6453 mode = GET_MODE (out); 6454 neglab = gen_label_rtx (); 6455 donelab = gen_label_rtx (); 6456 i0 = gen_reg_rtx (DImode); 6457 i1 = gen_reg_rtx (DImode); 6458 f0 = gen_reg_rtx (mode); 6459 6460 emit_cmp_and_jump_insns (in, const0_rtx, LT, const0_rtx, DImode, 0, neglab); 6461 6462 emit_insn (gen_rtx_SET (VOIDmode, out, gen_rtx_FLOAT (mode, in))); 6463 emit_jump_insn (gen_jump (donelab)); 6464 emit_barrier (); 6465 6466 emit_label (neglab); 6467 6468 emit_insn (gen_lshrdi3 (i0, in, const1_rtx)); 6469 emit_insn (gen_anddi3 (i1, in, const1_rtx)); 6470 emit_insn (gen_iordi3 (i0, i0, i1)); 6471 emit_insn (gen_rtx_SET (VOIDmode, f0, gen_rtx_FLOAT (mode, i0))); 6472 emit_insn (gen_rtx_SET (VOIDmode, out, gen_rtx_PLUS (mode, f0, f0))); 6473 6474 emit_label (donelab); 6475} 6476 6477/* Return the string to output a conditional branch to LABEL, testing 6478 register REG. LABEL is the operand number of the label; REG is the 6479 operand number of the reg. OP is the conditional expression. The mode 6480 of REG says what kind of comparison we made. 6481 6482 DEST is the destination insn (i.e. the label), INSN is the source. 6483 6484 REVERSED is nonzero if we should reverse the sense of the comparison. 6485 6486 ANNUL is nonzero if we should generate an annulling branch. 6487 6488 NOOP is nonzero if we have to follow this branch by a noop. */ 6489 6490char * 6491output_v9branch (rtx op, rtx dest, int reg, int label, int reversed, 6492 int annul, int noop, rtx insn) 6493{ 6494 static char string[50]; 6495 enum rtx_code code = GET_CODE (op); 6496 enum machine_mode mode = GET_MODE (XEXP (op, 0)); 6497 rtx note; 6498 int far; 6499 char *p; 6500 6501 /* branch on register are limited to +-128KB. If it is too far away, 6502 change 6503 6504 brnz,pt %g1, .LC30 6505 6506 to 6507 6508 brz,pn %g1, .+12 6509 nop 6510 ba,pt %xcc, .LC30 6511 6512 and 6513 6514 brgez,a,pn %o1, .LC29 6515 6516 to 6517 6518 brlz,pt %o1, .+16 6519 nop 6520 ba,pt %xcc, .LC29 */ 6521 6522 far = get_attr_length (insn) >= 3; 6523 6524 /* If not floating-point or if EQ or NE, we can just reverse the code. */ 6525 if (reversed ^ far) 6526 code = reverse_condition (code); 6527 6528 /* Only 64 bit versions of these instructions exist. */ 6529 if (mode != DImode) 6530 abort (); 6531 6532 /* Start by writing the branch condition. */ 6533 6534 switch (code) 6535 { 6536 case NE: 6537 strcpy (string, "brnz"); 6538 break; 6539 6540 case EQ: 6541 strcpy (string, "brz"); 6542 break; 6543 6544 case GE: 6545 strcpy (string, "brgez"); 6546 break; 6547 6548 case LT: 6549 strcpy (string, "brlz"); 6550 break; 6551 6552 case LE: 6553 strcpy (string, "brlez"); 6554 break; 6555 6556 case GT: 6557 strcpy (string, "brgz"); 6558 break; 6559 6560 default: 6561 abort (); 6562 } 6563 6564 p = strchr (string, '\0'); 6565 6566 /* Now add the annulling, reg, label, and nop. */ 6567 if (annul && ! far) 6568 { 6569 strcpy (p, ",a"); 6570 p += 2; 6571 } 6572 6573 if (insn && (note = find_reg_note (insn, REG_BR_PROB, NULL_RTX))) 6574 { 6575 strcpy (p, 6576 ((INTVAL (XEXP (note, 0)) >= REG_BR_PROB_BASE / 2) ^ far) 6577 ? ",pt" : ",pn"); 6578 p += 3; 6579 } 6580 6581 *p = p < string + 8 ? '\t' : ' '; 6582 p++; 6583 *p++ = '%'; 6584 *p++ = '0' + reg; 6585 *p++ = ','; 6586 *p++ = ' '; 6587 if (far) 6588 { 6589 int veryfar = 1, delta; 6590 6591 if (INSN_ADDRESSES_SET_P ()) 6592 { 6593 delta = (INSN_ADDRESSES (INSN_UID (dest)) 6594 - INSN_ADDRESSES (INSN_UID (insn))); 6595 /* Leave some instructions for "slop". */ 6596 if (delta >= -260000 && delta < 260000) 6597 veryfar = 0; 6598 } 6599 6600 strcpy (p, ".+12\n\tnop\n\t"); 6601 if (annul || noop) 6602 p[3] = '6'; 6603 p += 11; 6604 if (veryfar) 6605 { 6606 strcpy (p, "b\t"); 6607 p += 2; 6608 } 6609 else 6610 { 6611 strcpy (p, "ba,pt\t%%xcc, "); 6612 p += 13; 6613 } 6614 } 6615 *p++ = '%'; 6616 *p++ = 'l'; 6617 *p++ = '0' + label; 6618 *p = '\0'; 6619 6620 if (noop) 6621 strcpy (p, "\n\tnop"); 6622 6623 return string; 6624} 6625 6626/* Return 1, if any of the registers of the instruction are %l[0-7] or %o[0-7]. 6627 Such instructions cannot be used in the delay slot of return insn on v9. 6628 If TEST is 0, also rename all %i[0-7] registers to their %o[0-7] counterparts. 6629 */ 6630 6631static int 6632epilogue_renumber (register rtx *where, int test) 6633{ 6634 register const char *fmt; 6635 register int i; 6636 register enum rtx_code code; 6637 6638 if (*where == 0) 6639 return 0; 6640 6641 code = GET_CODE (*where); 6642 6643 switch (code) 6644 { 6645 case REG: 6646 if (REGNO (*where) >= 8 && REGNO (*where) < 24) /* oX or lX */ 6647 return 1; 6648 if (! test && REGNO (*where) >= 24 && REGNO (*where) < 32) 6649 *where = gen_rtx (REG, GET_MODE (*where), OUTGOING_REGNO (REGNO(*where))); 6650 case SCRATCH: 6651 case CC0: 6652 case PC: 6653 case CONST_INT: 6654 case CONST_DOUBLE: 6655 return 0; 6656 6657 /* Do not replace the frame pointer with the stack pointer because 6658 it can cause the delayed instruction to load below the stack. 6659 This occurs when instructions like: 6660 6661 (set (reg/i:SI 24 %i0) 6662 (mem/f:SI (plus:SI (reg/f:SI 30 %fp) 6663 (const_int -20 [0xffffffec])) 0)) 6664 6665 are in the return delayed slot. */ 6666 case PLUS: 6667 if (GET_CODE (XEXP (*where, 0)) == REG 6668 && REGNO (XEXP (*where, 0)) == HARD_FRAME_POINTER_REGNUM 6669 && (GET_CODE (XEXP (*where, 1)) != CONST_INT 6670 || INTVAL (XEXP (*where, 1)) < SPARC_STACK_BIAS)) 6671 return 1; 6672 break; 6673 6674 case MEM: 6675 if (SPARC_STACK_BIAS 6676 && GET_CODE (XEXP (*where, 0)) == REG 6677 && REGNO (XEXP (*where, 0)) == HARD_FRAME_POINTER_REGNUM) 6678 return 1; 6679 break; 6680 6681 default: 6682 break; 6683 } 6684 6685 fmt = GET_RTX_FORMAT (code); 6686 6687 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) 6688 { 6689 if (fmt[i] == 'E') 6690 { 6691 register int j; 6692 for (j = XVECLEN (*where, i) - 1; j >= 0; j--) 6693 if (epilogue_renumber (&(XVECEXP (*where, i, j)), test)) 6694 return 1; 6695 } 6696 else if (fmt[i] == 'e' 6697 && epilogue_renumber (&(XEXP (*where, i)), test)) 6698 return 1; 6699 } 6700 return 0; 6701} 6702 6703/* Leaf functions and non-leaf functions have different needs. */ 6704 6705static const int 6706reg_leaf_alloc_order[] = REG_LEAF_ALLOC_ORDER; 6707 6708static const int 6709reg_nonleaf_alloc_order[] = REG_ALLOC_ORDER; 6710 6711static const int *const reg_alloc_orders[] = { 6712 reg_leaf_alloc_order, 6713 reg_nonleaf_alloc_order}; 6714 6715void 6716order_regs_for_local_alloc (void) 6717{ 6718 static int last_order_nonleaf = 1; 6719 6720 if (regs_ever_live[15] != last_order_nonleaf) 6721 { 6722 last_order_nonleaf = !last_order_nonleaf; 6723 memcpy ((char *) reg_alloc_order, 6724 (const char *) reg_alloc_orders[last_order_nonleaf], 6725 FIRST_PSEUDO_REGISTER * sizeof (int)); 6726 } 6727} 6728 6729/* Return 1 if REG and MEM are legitimate enough to allow the various 6730 mem<-->reg splits to be run. */ 6731 6732int 6733sparc_splitdi_legitimate (rtx reg, rtx mem) 6734{ 6735 /* Punt if we are here by mistake. */ 6736 if (! reload_completed) 6737 abort (); 6738 6739 /* We must have an offsettable memory reference. */ 6740 if (! offsettable_memref_p (mem)) 6741 return 0; 6742 6743 /* If we have legitimate args for ldd/std, we do not want 6744 the split to happen. */ 6745 if ((REGNO (reg) % 2) == 0 6746 && mem_min_alignment (mem, 8)) 6747 return 0; 6748 6749 /* Success. */ 6750 return 1; 6751} 6752 6753/* Return 1 if x and y are some kind of REG and they refer to 6754 different hard registers. This test is guaranteed to be 6755 run after reload. */ 6756 6757int 6758sparc_absnegfloat_split_legitimate (rtx x, rtx y) 6759{ 6760 if (GET_CODE (x) != REG) 6761 return 0; 6762 if (GET_CODE (y) != REG) 6763 return 0; 6764 if (REGNO (x) == REGNO (y)) 6765 return 0; 6766 return 1; 6767} 6768 6769/* Return 1 if REGNO (reg1) is even and REGNO (reg1) == REGNO (reg2) - 1. 6770 This makes them candidates for using ldd and std insns. 6771 6772 Note reg1 and reg2 *must* be hard registers. */ 6773 6774int 6775registers_ok_for_ldd_peep (rtx reg1, rtx reg2) 6776{ 6777 /* We might have been passed a SUBREG. */ 6778 if (GET_CODE (reg1) != REG || GET_CODE (reg2) != REG) 6779 return 0; 6780 6781 if (REGNO (reg1) % 2 != 0) 6782 return 0; 6783 6784 /* Integer ldd is deprecated in SPARC V9 */ 6785 if (TARGET_V9 && REGNO (reg1) < 32) 6786 return 0; 6787 6788 return (REGNO (reg1) == REGNO (reg2) - 1); 6789} 6790 6791/* Return 1 if the addresses in mem1 and mem2 are suitable for use in 6792 an ldd or std insn. 6793 6794 This can only happen when addr1 and addr2, the addresses in mem1 6795 and mem2, are consecutive memory locations (addr1 + 4 == addr2). 6796 addr1 must also be aligned on a 64-bit boundary. 6797 6798 Also iff dependent_reg_rtx is not null it should not be used to 6799 compute the address for mem1, i.e. we cannot optimize a sequence 6800 like: 6801 ld [%o0], %o0 6802 ld [%o0 + 4], %o1 6803 to 6804 ldd [%o0], %o0 6805 nor: 6806 ld [%g3 + 4], %g3 6807 ld [%g3], %g2 6808 to 6809 ldd [%g3], %g2 6810 6811 But, note that the transformation from: 6812 ld [%g2 + 4], %g3 6813 ld [%g2], %g2 6814 to 6815 ldd [%g2], %g2 6816 is perfectly fine. Thus, the peephole2 patterns always pass us 6817 the destination register of the first load, never the second one. 6818 6819 For stores we don't have a similar problem, so dependent_reg_rtx is 6820 NULL_RTX. */ 6821 6822int 6823mems_ok_for_ldd_peep (rtx mem1, rtx mem2, rtx dependent_reg_rtx) 6824{ 6825 rtx addr1, addr2; 6826 unsigned int reg1; 6827 HOST_WIDE_INT offset1; 6828 6829 /* The mems cannot be volatile. */ 6830 if (MEM_VOLATILE_P (mem1) || MEM_VOLATILE_P (mem2)) 6831 return 0; 6832 6833 /* MEM1 should be aligned on a 64-bit boundary. */ 6834 if (MEM_ALIGN (mem1) < 64) 6835 return 0; 6836 6837 addr1 = XEXP (mem1, 0); 6838 addr2 = XEXP (mem2, 0); 6839 6840 /* Extract a register number and offset (if used) from the first addr. */ 6841 if (GET_CODE (addr1) == PLUS) 6842 { 6843 /* If not a REG, return zero. */ 6844 if (GET_CODE (XEXP (addr1, 0)) != REG) 6845 return 0; 6846 else 6847 { 6848 reg1 = REGNO (XEXP (addr1, 0)); 6849 /* The offset must be constant! */ 6850 if (GET_CODE (XEXP (addr1, 1)) != CONST_INT) 6851 return 0; 6852 offset1 = INTVAL (XEXP (addr1, 1)); 6853 } 6854 } 6855 else if (GET_CODE (addr1) != REG) 6856 return 0; 6857 else 6858 { 6859 reg1 = REGNO (addr1); 6860 /* This was a simple (mem (reg)) expression. Offset is 0. */ 6861 offset1 = 0; 6862 } 6863 6864 /* Make sure the second address is a (mem (plus (reg) (const_int). */ 6865 if (GET_CODE (addr2) != PLUS) 6866 return 0; 6867 6868 if (GET_CODE (XEXP (addr2, 0)) != REG 6869 || GET_CODE (XEXP (addr2, 1)) != CONST_INT) 6870 return 0; 6871 6872 if (reg1 != REGNO (XEXP (addr2, 0))) 6873 return 0; 6874 6875 if (dependent_reg_rtx != NULL_RTX && reg1 == REGNO (dependent_reg_rtx)) 6876 return 0; 6877 6878 /* The first offset must be evenly divisible by 8 to ensure the 6879 address is 64 bit aligned. */ 6880 if (offset1 % 8 != 0) 6881 return 0; 6882 6883 /* The offset for the second addr must be 4 more than the first addr. */ 6884 if (INTVAL (XEXP (addr2, 1)) != offset1 + 4) 6885 return 0; 6886 6887 /* All the tests passed. addr1 and addr2 are valid for ldd and std 6888 instructions. */ 6889 return 1; 6890} 6891 6892/* Return 1 if reg is a pseudo, or is the first register in 6893 a hard register pair. This makes it a candidate for use in 6894 ldd and std insns. */ 6895 6896int 6897register_ok_for_ldd (rtx reg) 6898{ 6899 /* We might have been passed a SUBREG. */ 6900 if (GET_CODE (reg) != REG) 6901 return 0; 6902 6903 if (REGNO (reg) < FIRST_PSEUDO_REGISTER) 6904 return (REGNO (reg) % 2 == 0); 6905 else 6906 return 1; 6907} 6908 6909/* Print operand X (an rtx) in assembler syntax to file FILE. 6910 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified. 6911 For `%' followed by punctuation, CODE is the punctuation and X is null. */ 6912 6913void 6914print_operand (FILE *file, rtx x, int code) 6915{ 6916 switch (code) 6917 { 6918 case '#': 6919 /* Output a 'nop' if there's nothing for the delay slot. */ 6920 if (dbr_sequence_length () == 0) 6921 fputs ("\n\t nop", file); 6922 return; 6923 case '*': 6924 /* Output an annul flag if there's nothing for the delay slot and we 6925 are optimizing. This is always used with '(' below. */ 6926 /* Sun OS 4.1.1 dbx can't handle an annulled unconditional branch; 6927 this is a dbx bug. So, we only do this when optimizing. */ 6928 /* On UltraSPARC, a branch in a delay slot causes a pipeline flush. 6929 Always emit a nop in case the next instruction is a branch. */ 6930 if (dbr_sequence_length () == 0 6931 && (optimize && (int)sparc_cpu < PROCESSOR_V9)) 6932 fputs (",a", file); 6933 return; 6934 case '(': 6935 /* Output a 'nop' if there's nothing for the delay slot and we are 6936 not optimizing. This is always used with '*' above. */ 6937 if (dbr_sequence_length () == 0 6938 && ! (optimize && (int)sparc_cpu < PROCESSOR_V9)) 6939 fputs ("\n\t nop", file); 6940 return; 6941 case '_': 6942 /* Output the Embedded Medium/Anywhere code model base register. */ 6943 fputs (EMBMEDANY_BASE_REG, file); 6944 return; 6945 case '@': 6946 /* Print out what we are using as the frame pointer. This might 6947 be %fp, or might be %sp+offset. */ 6948 /* ??? What if offset is too big? Perhaps the caller knows it isn't? */ 6949 fprintf (file, "%s+"HOST_WIDE_INT_PRINT_DEC, frame_base_name, frame_base_offset); 6950 return; 6951 case '&': 6952 /* Print some local dynamic TLS name. */ 6953 assemble_name (file, get_some_local_dynamic_name ()); 6954 return; 6955 case 'Y': 6956 /* Adjust the operand to take into account a RESTORE operation. */ 6957 if (GET_CODE (x) == CONST_INT) 6958 break; 6959 else if (GET_CODE (x) != REG) 6960 output_operand_lossage ("invalid %%Y operand"); 6961 else if (REGNO (x) < 8) 6962 fputs (reg_names[REGNO (x)], file); 6963 else if (REGNO (x) >= 24 && REGNO (x) < 32) 6964 fputs (reg_names[REGNO (x)-16], file); 6965 else 6966 output_operand_lossage ("invalid %%Y operand"); 6967 return; 6968 case 'L': 6969 /* Print out the low order register name of a register pair. */ 6970 if (WORDS_BIG_ENDIAN) 6971 fputs (reg_names[REGNO (x)+1], file); 6972 else 6973 fputs (reg_names[REGNO (x)], file); 6974 return; 6975 case 'H': 6976 /* Print out the high order register name of a register pair. */ 6977 if (WORDS_BIG_ENDIAN) 6978 fputs (reg_names[REGNO (x)], file); 6979 else 6980 fputs (reg_names[REGNO (x)+1], file); 6981 return; 6982 case 'R': 6983 /* Print out the second register name of a register pair or quad. 6984 I.e., R (%o0) => %o1. */ 6985 fputs (reg_names[REGNO (x)+1], file); 6986 return; 6987 case 'S': 6988 /* Print out the third register name of a register quad. 6989 I.e., S (%o0) => %o2. */ 6990 fputs (reg_names[REGNO (x)+2], file); 6991 return; 6992 case 'T': 6993 /* Print out the fourth register name of a register quad. 6994 I.e., T (%o0) => %o3. */ 6995 fputs (reg_names[REGNO (x)+3], file); 6996 return; 6997 case 'x': 6998 /* Print a condition code register. */ 6999 if (REGNO (x) == SPARC_ICC_REG) 7000 { 7001 /* We don't handle CC[X]_NOOVmode because they're not supposed 7002 to occur here. */ 7003 if (GET_MODE (x) == CCmode) 7004 fputs ("%icc", file); 7005 else if (GET_MODE (x) == CCXmode) 7006 fputs ("%xcc", file); 7007 else 7008 abort (); 7009 } 7010 else 7011 /* %fccN register */ 7012 fputs (reg_names[REGNO (x)], file); 7013 return; 7014 case 'm': 7015 /* Print the operand's address only. */ 7016 output_address (XEXP (x, 0)); 7017 return; 7018 case 'r': 7019 /* In this case we need a register. Use %g0 if the 7020 operand is const0_rtx. */ 7021 if (x == const0_rtx 7022 || (GET_MODE (x) != VOIDmode && x == CONST0_RTX (GET_MODE (x)))) 7023 { 7024 fputs ("%g0", file); 7025 return; 7026 } 7027 else 7028 break; 7029 7030 case 'A': 7031 switch (GET_CODE (x)) 7032 { 7033 case IOR: fputs ("or", file); break; 7034 case AND: fputs ("and", file); break; 7035 case XOR: fputs ("xor", file); break; 7036 default: output_operand_lossage ("invalid %%A operand"); 7037 } 7038 return; 7039 7040 case 'B': 7041 switch (GET_CODE (x)) 7042 { 7043 case IOR: fputs ("orn", file); break; 7044 case AND: fputs ("andn", file); break; 7045 case XOR: fputs ("xnor", file); break; 7046 default: output_operand_lossage ("invalid %%B operand"); 7047 } 7048 return; 7049 7050 /* These are used by the conditional move instructions. */ 7051 case 'c' : 7052 case 'C': 7053 { 7054 enum rtx_code rc = GET_CODE (x); 7055 7056 if (code == 'c') 7057 { 7058 enum machine_mode mode = GET_MODE (XEXP (x, 0)); 7059 if (mode == CCFPmode || mode == CCFPEmode) 7060 rc = reverse_condition_maybe_unordered (GET_CODE (x)); 7061 else 7062 rc = reverse_condition (GET_CODE (x)); 7063 } 7064 switch (rc) 7065 { 7066 case NE: fputs ("ne", file); break; 7067 case EQ: fputs ("e", file); break; 7068 case GE: fputs ("ge", file); break; 7069 case GT: fputs ("g", file); break; 7070 case LE: fputs ("le", file); break; 7071 case LT: fputs ("l", file); break; 7072 case GEU: fputs ("geu", file); break; 7073 case GTU: fputs ("gu", file); break; 7074 case LEU: fputs ("leu", file); break; 7075 case LTU: fputs ("lu", file); break; 7076 case LTGT: fputs ("lg", file); break; 7077 case UNORDERED: fputs ("u", file); break; 7078 case ORDERED: fputs ("o", file); break; 7079 case UNLT: fputs ("ul", file); break; 7080 case UNLE: fputs ("ule", file); break; 7081 case UNGT: fputs ("ug", file); break; 7082 case UNGE: fputs ("uge", file); break; 7083 case UNEQ: fputs ("ue", file); break; 7084 default: output_operand_lossage (code == 'c' 7085 ? "invalid %%c operand" 7086 : "invalid %%C operand"); 7087 } 7088 return; 7089 } 7090 7091 /* These are used by the movr instruction pattern. */ 7092 case 'd': 7093 case 'D': 7094 { 7095 enum rtx_code rc = (code == 'd' 7096 ? reverse_condition (GET_CODE (x)) 7097 : GET_CODE (x)); 7098 switch (rc) 7099 { 7100 case NE: fputs ("ne", file); break; 7101 case EQ: fputs ("e", file); break; 7102 case GE: fputs ("gez", file); break; 7103 case LT: fputs ("lz", file); break; 7104 case LE: fputs ("lez", file); break; 7105 case GT: fputs ("gz", file); break; 7106 default: output_operand_lossage (code == 'd' 7107 ? "invalid %%d operand" 7108 : "invalid %%D operand"); 7109 } 7110 return; 7111 } 7112 7113 case 'b': 7114 { 7115 /* Print a sign-extended character. */ 7116 int i = trunc_int_for_mode (INTVAL (x), QImode); 7117 fprintf (file, "%d", i); 7118 return; 7119 } 7120 7121 case 'f': 7122 /* Operand must be a MEM; write its address. */ 7123 if (GET_CODE (x) != MEM) 7124 output_operand_lossage ("invalid %%f operand"); 7125 output_address (XEXP (x, 0)); 7126 return; 7127 7128 case 's': 7129 { 7130 /* Print a sign-extended 32-bit value. */ 7131 HOST_WIDE_INT i; 7132 if (GET_CODE(x) == CONST_INT) 7133 i = INTVAL (x); 7134 else if (GET_CODE(x) == CONST_DOUBLE) 7135 i = CONST_DOUBLE_LOW (x); 7136 else 7137 { 7138 output_operand_lossage ("invalid %%s operand"); 7139 return; 7140 } 7141 i = trunc_int_for_mode (i, SImode); 7142 fprintf (file, HOST_WIDE_INT_PRINT_DEC, i); 7143 return; 7144 } 7145 7146 case 0: 7147 /* Do nothing special. */ 7148 break; 7149 7150 default: 7151 /* Undocumented flag. */ 7152 output_operand_lossage ("invalid operand output code"); 7153 } 7154 7155 if (GET_CODE (x) == REG) 7156 fputs (reg_names[REGNO (x)], file); 7157 else if (GET_CODE (x) == MEM) 7158 { 7159 fputc ('[', file); 7160 /* Poor Sun assembler doesn't understand absolute addressing. */ 7161 if (CONSTANT_P (XEXP (x, 0))) 7162 fputs ("%g0+", file); 7163 output_address (XEXP (x, 0)); 7164 fputc (']', file); 7165 } 7166 else if (GET_CODE (x) == HIGH) 7167 { 7168 fputs ("%hi(", file); 7169 output_addr_const (file, XEXP (x, 0)); 7170 fputc (')', file); 7171 } 7172 else if (GET_CODE (x) == LO_SUM) 7173 { 7174 print_operand (file, XEXP (x, 0), 0); 7175 if (TARGET_CM_MEDMID) 7176 fputs ("+%l44(", file); 7177 else 7178 fputs ("+%lo(", file); 7179 output_addr_const (file, XEXP (x, 1)); 7180 fputc (')', file); 7181 } 7182 else if (GET_CODE (x) == CONST_DOUBLE 7183 && (GET_MODE (x) == VOIDmode 7184 || GET_MODE_CLASS (GET_MODE (x)) == MODE_INT)) 7185 { 7186 if (CONST_DOUBLE_HIGH (x) == 0) 7187 fprintf (file, "%u", (unsigned int) CONST_DOUBLE_LOW (x)); 7188 else if (CONST_DOUBLE_HIGH (x) == -1 7189 && CONST_DOUBLE_LOW (x) < 0) 7190 fprintf (file, "%d", (int) CONST_DOUBLE_LOW (x)); 7191 else 7192 output_operand_lossage ("long long constant not a valid immediate operand"); 7193 } 7194 else if (GET_CODE (x) == CONST_DOUBLE) 7195 output_operand_lossage ("floating point constant not a valid immediate operand"); 7196 else { output_addr_const (file, x); } 7197} 7198 7199/* Target hook for assembling integer objects. The sparc version has 7200 special handling for aligned DI-mode objects. */ 7201 7202static bool 7203sparc_assemble_integer (rtx x, unsigned int size, int aligned_p) 7204{ 7205 /* ??? We only output .xword's for symbols and only then in environments 7206 where the assembler can handle them. */ 7207 if (aligned_p && size == 8 7208 && (GET_CODE (x) != CONST_INT && GET_CODE (x) != CONST_DOUBLE)) 7209 { 7210 if (TARGET_V9) 7211 { 7212 assemble_integer_with_op ("\t.xword\t", x); 7213 return true; 7214 } 7215 else 7216 { 7217 assemble_aligned_integer (4, const0_rtx); 7218 assemble_aligned_integer (4, x); 7219 return true; 7220 } 7221 } 7222 return default_assemble_integer (x, size, aligned_p); 7223} 7224 7225/* Return the value of a code used in the .proc pseudo-op that says 7226 what kind of result this function returns. For non-C types, we pick 7227 the closest C type. */ 7228 7229#ifndef SHORT_TYPE_SIZE 7230#define SHORT_TYPE_SIZE (BITS_PER_UNIT * 2) 7231#endif 7232 7233#ifndef INT_TYPE_SIZE 7234#define INT_TYPE_SIZE BITS_PER_WORD 7235#endif 7236 7237#ifndef LONG_TYPE_SIZE 7238#define LONG_TYPE_SIZE BITS_PER_WORD 7239#endif 7240 7241#ifndef LONG_LONG_TYPE_SIZE 7242#define LONG_LONG_TYPE_SIZE (BITS_PER_WORD * 2) 7243#endif 7244 7245#ifndef FLOAT_TYPE_SIZE 7246#define FLOAT_TYPE_SIZE BITS_PER_WORD 7247#endif 7248 7249#ifndef DOUBLE_TYPE_SIZE 7250#define DOUBLE_TYPE_SIZE (BITS_PER_WORD * 2) 7251#endif 7252 7253#ifndef LONG_DOUBLE_TYPE_SIZE 7254#define LONG_DOUBLE_TYPE_SIZE (BITS_PER_WORD * 2) 7255#endif 7256 7257unsigned long 7258sparc_type_code (register tree type) 7259{ 7260 register unsigned long qualifiers = 0; 7261 register unsigned shift; 7262 7263 /* Only the first 30 bits of the qualifier are valid. We must refrain from 7264 setting more, since some assemblers will give an error for this. Also, 7265 we must be careful to avoid shifts of 32 bits or more to avoid getting 7266 unpredictable results. */ 7267 7268 for (shift = 6; shift < 30; shift += 2, type = TREE_TYPE (type)) 7269 { 7270 switch (TREE_CODE (type)) 7271 { 7272 case ERROR_MARK: 7273 return qualifiers; 7274 7275 case ARRAY_TYPE: 7276 qualifiers |= (3 << shift); 7277 break; 7278 7279 case FUNCTION_TYPE: 7280 case METHOD_TYPE: 7281 qualifiers |= (2 << shift); 7282 break; 7283 7284 case POINTER_TYPE: 7285 case REFERENCE_TYPE: 7286 case OFFSET_TYPE: 7287 qualifiers |= (1 << shift); 7288 break; 7289 7290 case RECORD_TYPE: 7291 return (qualifiers | 8); 7292 7293 case UNION_TYPE: 7294 case QUAL_UNION_TYPE: 7295 return (qualifiers | 9); 7296 7297 case ENUMERAL_TYPE: 7298 return (qualifiers | 10); 7299 7300 case VOID_TYPE: 7301 return (qualifiers | 16); 7302 7303 case INTEGER_TYPE: 7304 /* If this is a range type, consider it to be the underlying 7305 type. */ 7306 if (TREE_TYPE (type) != 0) 7307 break; 7308 7309 /* Carefully distinguish all the standard types of C, 7310 without messing up if the language is not C. We do this by 7311 testing TYPE_PRECISION and TREE_UNSIGNED. The old code used to 7312 look at both the names and the above fields, but that's redundant. 7313 Any type whose size is between two C types will be considered 7314 to be the wider of the two types. Also, we do not have a 7315 special code to use for "long long", so anything wider than 7316 long is treated the same. Note that we can't distinguish 7317 between "int" and "long" in this code if they are the same 7318 size, but that's fine, since neither can the assembler. */ 7319 7320 if (TYPE_PRECISION (type) <= CHAR_TYPE_SIZE) 7321 return (qualifiers | (TREE_UNSIGNED (type) ? 12 : 2)); 7322 7323 else if (TYPE_PRECISION (type) <= SHORT_TYPE_SIZE) 7324 return (qualifiers | (TREE_UNSIGNED (type) ? 13 : 3)); 7325 7326 else if (TYPE_PRECISION (type) <= INT_TYPE_SIZE) 7327 return (qualifiers | (TREE_UNSIGNED (type) ? 14 : 4)); 7328 7329 else 7330 return (qualifiers | (TREE_UNSIGNED (type) ? 15 : 5)); 7331 7332 case REAL_TYPE: 7333 /* If this is a range type, consider it to be the underlying 7334 type. */ 7335 if (TREE_TYPE (type) != 0) 7336 break; 7337 7338 /* Carefully distinguish all the standard types of C, 7339 without messing up if the language is not C. */ 7340 7341 if (TYPE_PRECISION (type) == FLOAT_TYPE_SIZE) 7342 return (qualifiers | 6); 7343 7344 else 7345 return (qualifiers | 7); 7346 7347 case COMPLEX_TYPE: /* GNU Fortran COMPLEX type. */ 7348 /* ??? We need to distinguish between double and float complex types, 7349 but I don't know how yet because I can't reach this code from 7350 existing front-ends. */ 7351 return (qualifiers | 7); /* Who knows? */ 7352 7353 case CHAR_TYPE: /* GNU Pascal CHAR type. Not used in C. */ 7354 case BOOLEAN_TYPE: /* GNU Fortran BOOLEAN type. */ 7355 case FILE_TYPE: /* GNU Pascal FILE type. */ 7356 case SET_TYPE: /* GNU Pascal SET type. */ 7357 case LANG_TYPE: /* ? */ 7358 return qualifiers; 7359 7360 default: 7361 abort (); /* Not a type! */ 7362 } 7363 } 7364 7365 return qualifiers; 7366} 7367 7368/* Nested function support. */ 7369 7370/* Emit RTL insns to initialize the variable parts of a trampoline. 7371 FNADDR is an RTX for the address of the function's pure code. 7372 CXT is an RTX for the static chain value for the function. 7373 7374 This takes 16 insns: 2 shifts & 2 ands (to split up addresses), 4 sethi 7375 (to load in opcodes), 4 iors (to merge address and opcodes), and 4 writes 7376 (to store insns). This is a bit excessive. Perhaps a different 7377 mechanism would be better here. 7378 7379 Emit enough FLUSH insns to synchronize the data and instruction caches. */ 7380 7381void 7382sparc_initialize_trampoline (rtx tramp, rtx fnaddr, rtx cxt) 7383{ 7384 /* SPARC 32-bit trampoline: 7385 7386 sethi %hi(fn), %g1 7387 sethi %hi(static), %g2 7388 jmp %g1+%lo(fn) 7389 or %g2, %lo(static), %g2 7390 7391 SETHI i,r = 00rr rrr1 00ii iiii iiii iiii iiii iiii 7392 JMPL r+i,d = 10dd ddd1 1100 0rrr rr1i iiii iiii iiii 7393 */ 7394 7395 emit_move_insn 7396 (gen_rtx_MEM (SImode, plus_constant (tramp, 0)), 7397 expand_binop (SImode, ior_optab, 7398 expand_shift (RSHIFT_EXPR, SImode, fnaddr, 7399 size_int (10), 0, 1), 7400 GEN_INT (trunc_int_for_mode (0x03000000, SImode)), 7401 NULL_RTX, 1, OPTAB_DIRECT)); 7402 7403 emit_move_insn 7404 (gen_rtx_MEM (SImode, plus_constant (tramp, 4)), 7405 expand_binop (SImode, ior_optab, 7406 expand_shift (RSHIFT_EXPR, SImode, cxt, 7407 size_int (10), 0, 1), 7408 GEN_INT (trunc_int_for_mode (0x05000000, SImode)), 7409 NULL_RTX, 1, OPTAB_DIRECT)); 7410 7411 emit_move_insn 7412 (gen_rtx_MEM (SImode, plus_constant (tramp, 8)), 7413 expand_binop (SImode, ior_optab, 7414 expand_and (SImode, fnaddr, GEN_INT (0x3ff), NULL_RTX), 7415 GEN_INT (trunc_int_for_mode (0x81c06000, SImode)), 7416 NULL_RTX, 1, OPTAB_DIRECT)); 7417 7418 emit_move_insn 7419 (gen_rtx_MEM (SImode, plus_constant (tramp, 12)), 7420 expand_binop (SImode, ior_optab, 7421 expand_and (SImode, cxt, GEN_INT (0x3ff), NULL_RTX), 7422 GEN_INT (trunc_int_for_mode (0x8410a000, SImode)), 7423 NULL_RTX, 1, OPTAB_DIRECT)); 7424 7425 /* On UltraSPARC a flush flushes an entire cache line. The trampoline is 7426 aligned on a 16 byte boundary so one flush clears it all. */ 7427 emit_insn (gen_flush (validize_mem (gen_rtx_MEM (SImode, tramp)))); 7428 if (sparc_cpu != PROCESSOR_ULTRASPARC 7429 && sparc_cpu != PROCESSOR_ULTRASPARC3) 7430 emit_insn (gen_flush (validize_mem (gen_rtx_MEM (SImode, 7431 plus_constant (tramp, 8))))); 7432 7433 /* Call __enable_execute_stack after writing onto the stack to make sure 7434 the stack address is accessible. */ 7435#ifdef ENABLE_EXECUTE_STACK 7436 emit_library_call (gen_rtx (SYMBOL_REF, Pmode, "__enable_execute_stack"), 7437 LCT_NORMAL, VOIDmode, 1, tramp, Pmode); 7438#endif 7439 7440} 7441 7442/* The 64-bit version is simpler because it makes more sense to load the 7443 values as "immediate" data out of the trampoline. It's also easier since 7444 we can read the PC without clobbering a register. */ 7445 7446void 7447sparc64_initialize_trampoline (rtx tramp, rtx fnaddr, rtx cxt) 7448{ 7449 /* SPARC 64-bit trampoline: 7450 7451 rd %pc, %g1 7452 ldx [%g1+24], %g5 7453 jmp %g5 7454 ldx [%g1+16], %g5 7455 +16 bytes data 7456 */ 7457 7458 emit_move_insn (gen_rtx_MEM (SImode, tramp), 7459 GEN_INT (trunc_int_for_mode (0x83414000, SImode))); 7460 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 4)), 7461 GEN_INT (trunc_int_for_mode (0xca586018, SImode))); 7462 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 8)), 7463 GEN_INT (trunc_int_for_mode (0x81c14000, SImode))); 7464 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 12)), 7465 GEN_INT (trunc_int_for_mode (0xca586010, SImode))); 7466 emit_move_insn (gen_rtx_MEM (DImode, plus_constant (tramp, 16)), cxt); 7467 emit_move_insn (gen_rtx_MEM (DImode, plus_constant (tramp, 24)), fnaddr); 7468 emit_insn (gen_flushdi (validize_mem (gen_rtx_MEM (DImode, tramp)))); 7469 7470 if (sparc_cpu != PROCESSOR_ULTRASPARC 7471 && sparc_cpu != PROCESSOR_ULTRASPARC3) 7472 emit_insn (gen_flushdi (validize_mem (gen_rtx_MEM (DImode, plus_constant (tramp, 8))))); 7473 7474 /* Call __enable_execute_stack after writing onto the stack to make sure 7475 the stack address is accessible. */ 7476#ifdef ENABLE_EXECUTE_STACK 7477 emit_library_call (gen_rtx (SYMBOL_REF, Pmode, "__enable_execute_stack"), 7478 LCT_NORMAL, VOIDmode, 1, tramp, Pmode); 7479#endif 7480} 7481 7482/* Subroutines to support a flat (single) register window calling 7483 convention. */ 7484 7485/* Single-register window sparc stack frames look like: 7486 7487 Before call After call 7488 +-----------------------+ +-----------------------+ 7489 high | | | | 7490 mem | caller's temps. | | caller's temps. | 7491 | | | | 7492 +-----------------------+ +-----------------------+ 7493 | | | | 7494 | arguments on stack. | | arguments on stack. | 7495 | | | | 7496 +-----------------------+FP+92->+-----------------------+ 7497 | 6 words to save | | 6 words to save | 7498 | arguments passed | | arguments passed | 7499 | in registers, even | | in registers, even | 7500 | if not passed. | | if not passed. | 7501 SP+68->+-----------------------+FP+68->+-----------------------+ 7502 | 1 word struct addr | | 1 word struct addr | 7503 +-----------------------+FP+64->+-----------------------+ 7504 | | | | 7505 | 16 word reg save area | | 16 word reg save area | 7506 | | | | 7507 SP->+-----------------------+ FP->+-----------------------+ 7508 | 4 word area for | 7509 | fp/alu reg moves | 7510 FP-16->+-----------------------+ 7511 | | 7512 | local variables | 7513 | | 7514 +-----------------------+ 7515 | | 7516 | fp register save | 7517 | | 7518 +-----------------------+ 7519 | | 7520 | gp register save | 7521 | | 7522 +-----------------------+ 7523 | | 7524 | alloca allocations | 7525 | | 7526 +-----------------------+ 7527 | | 7528 | arguments on stack | 7529 | | 7530 SP+92->+-----------------------+ 7531 | 6 words to save | 7532 | arguments passed | 7533 | in registers, even | 7534 low | if not passed. | 7535 memory SP+68->+-----------------------+ 7536 | 1 word struct addr | 7537 SP+64->+-----------------------+ 7538 | | 7539 I 16 word reg save area | 7540 | | 7541 SP->+-----------------------+ */ 7542 7543/* Structure to be filled in by sparc_flat_compute_frame_size with register 7544 save masks, and offsets for the current function. */ 7545 7546struct sparc_frame_info 7547{ 7548 HOST_WIDE_INT total_size; /* # bytes that the entire frame takes up. */ 7549 HOST_WIDE_INT var_size; /* # bytes that variables take up. */ 7550 int args_size; /* # bytes that outgoing arguments take up. */ 7551 int extra_size; /* # bytes of extra gunk. */ 7552 int gp_reg_size; /* # bytes needed to store gp regs. */ 7553 int fp_reg_size; /* # bytes needed to store fp regs. */ 7554 unsigned long gmask; /* Mask of saved gp registers. */ 7555 unsigned long fmask; /* Mask of saved fp registers. */ 7556 int reg_offset; /* Offset from new sp to store regs. */ 7557 int initialized; /* Nonzero if frame size already calculated. */ 7558}; 7559 7560/* Current frame information calculated by sparc_flat_compute_frame_size. */ 7561struct sparc_frame_info current_frame_info; 7562 7563/* Zero structure to initialize current_frame_info. */ 7564struct sparc_frame_info zero_frame_info; 7565 7566#define RETURN_ADDR_REGNUM 15 7567#define HARD_FRAME_POINTER_MASK (1 << (HARD_FRAME_POINTER_REGNUM)) 7568#define RETURN_ADDR_MASK (1 << (RETURN_ADDR_REGNUM)) 7569 7570/* Tell prologue and epilogue if register REGNO should be saved / restored. */ 7571 7572static bool 7573sparc_flat_must_save_register_p (int regno) 7574{ 7575 /* General case: call-saved registers live at some point. */ 7576 if (!call_used_regs[regno] && regs_ever_live[regno]) 7577 return true; 7578 7579 /* Frame pointer register (%i7) if needed. */ 7580 if (regno == HARD_FRAME_POINTER_REGNUM && frame_pointer_needed) 7581 return true; 7582 7583 /* PIC register (%l7) if needed. */ 7584 if (regno == (int) PIC_OFFSET_TABLE_REGNUM 7585 && flag_pic && current_function_uses_pic_offset_table) 7586 return true; 7587 7588 /* Return address register (%o7) if needed. */ 7589 if (regno == RETURN_ADDR_REGNUM 7590 && (regs_ever_live[RETURN_ADDR_REGNUM] 7591 /* When the PIC offset table is used, the PIC register 7592 is set by using a bare call that clobbers %o7. */ 7593 || (flag_pic && current_function_uses_pic_offset_table))) 7594 return true; 7595 7596 return false; 7597} 7598 7599/* Return the bytes needed to compute the frame pointer from the current 7600 stack pointer. */ 7601 7602HOST_WIDE_INT 7603sparc_flat_compute_frame_size (HOST_WIDE_INT size) 7604 /* # of var. bytes allocated. */ 7605{ 7606 int regno; 7607 HOST_WIDE_INT total_size; /* # bytes that the entire frame takes up. */ 7608 HOST_WIDE_INT var_size; /* # bytes that variables take up. */ 7609 int args_size; /* # bytes that outgoing arguments take up. */ 7610 int extra_size; /* # extra bytes. */ 7611 int gp_reg_size; /* # bytes needed to store gp regs. */ 7612 int fp_reg_size; /* # bytes needed to store fp regs. */ 7613 unsigned long gmask; /* Mask of saved gp registers. */ 7614 unsigned long fmask; /* Mask of saved fp registers. */ 7615 int reg_offset; /* Offset to register save area. */ 7616 int need_aligned_p; /* 1 if need the save area 8 byte aligned. */ 7617 7618 /* This is the size of the 16 word reg save area, 1 word struct addr 7619 area, and 4 word fp/alu register copy area. */ 7620 extra_size = -STARTING_FRAME_OFFSET + FIRST_PARM_OFFSET(0); 7621 var_size = size; 7622 gp_reg_size = 0; 7623 fp_reg_size = 0; 7624 gmask = 0; 7625 fmask = 0; 7626 reg_offset = 0; 7627 need_aligned_p = 0; 7628 7629 args_size = 0; 7630 if (!leaf_function_p ()) 7631 { 7632 /* Also include the size needed for the 6 parameter registers. */ 7633 args_size = current_function_outgoing_args_size + 24; 7634 } 7635 total_size = var_size + args_size; 7636 7637 /* Calculate space needed for gp registers. */ 7638 for (regno = 1; regno <= 31; regno++) 7639 { 7640 if (sparc_flat_must_save_register_p (regno)) 7641 { 7642 /* If we need to save two regs in a row, ensure there's room to bump 7643 up the address to align it to a doubleword boundary. */ 7644 if ((regno & 0x1) == 0 && sparc_flat_must_save_register_p (regno+1)) 7645 { 7646 if (gp_reg_size % 8 != 0) 7647 gp_reg_size += 4; 7648 gp_reg_size += 2 * UNITS_PER_WORD; 7649 gmask |= 3 << regno; 7650 regno++; 7651 need_aligned_p = 1; 7652 } 7653 else 7654 { 7655 gp_reg_size += UNITS_PER_WORD; 7656 gmask |= 1 << regno; 7657 } 7658 } 7659 } 7660 7661 /* Calculate space needed for fp registers. */ 7662 for (regno = 32; regno <= 63; regno++) 7663 { 7664 if (regs_ever_live[regno] && !call_used_regs[regno]) 7665 { 7666 fp_reg_size += UNITS_PER_WORD; 7667 fmask |= 1 << (regno - 32); 7668 } 7669 } 7670 7671 if (gmask || fmask) 7672 { 7673 int n; 7674 reg_offset = FIRST_PARM_OFFSET(0) + args_size; 7675 /* Ensure save area is 8 byte aligned if we need it. */ 7676 n = reg_offset % 8; 7677 if (need_aligned_p && n != 0) 7678 { 7679 total_size += 8 - n; 7680 reg_offset += 8 - n; 7681 } 7682 total_size += gp_reg_size + fp_reg_size; 7683 } 7684 7685 /* If we must allocate a stack frame at all, we must also allocate 7686 room for register window spillage, so as to be binary compatible 7687 with libraries and operating systems that do not use -mflat. */ 7688 if (total_size > 0) 7689 total_size += extra_size; 7690 else 7691 extra_size = 0; 7692 7693 total_size = SPARC_STACK_ALIGN (total_size); 7694 7695 /* Save other computed information. */ 7696 current_frame_info.total_size = total_size; 7697 current_frame_info.var_size = var_size; 7698 current_frame_info.args_size = args_size; 7699 current_frame_info.extra_size = extra_size; 7700 current_frame_info.gp_reg_size = gp_reg_size; 7701 current_frame_info.fp_reg_size = fp_reg_size; 7702 current_frame_info.gmask = gmask; 7703 current_frame_info.fmask = fmask; 7704 current_frame_info.reg_offset = reg_offset; 7705 current_frame_info.initialized = reload_completed; 7706 7707 /* Ok, we're done. */ 7708 return total_size; 7709} 7710 7711/* Save/restore registers in GMASK and FMASK at register BASE_REG plus offset 7712 OFFSET. 7713 7714 BASE_REG must be 8 byte aligned. This allows us to test OFFSET for 7715 appropriate alignment and use DOUBLEWORD_OP when we can. We assume 7716 [BASE_REG+OFFSET] will always be a valid address. 7717 7718 WORD_OP is either "st" for save, "ld" for restore. 7719 DOUBLEWORD_OP is either "std" for save, "ldd" for restore. */ 7720 7721static void 7722sparc_flat_save_restore (FILE *file, const char *base_reg, int offset, 7723 unsigned long gmask, unsigned long fmask, 7724 const char *word_op, const char *doubleword_op, 7725 HOST_WIDE_INT base_offset) 7726{ 7727 int regno; 7728 7729 if (gmask == 0 && fmask == 0) 7730 return; 7731 7732 /* Save registers starting from high to low. We've already saved the 7733 previous frame pointer and previous return address for the debugger's 7734 sake. The debugger allows us to not need a nop in the epilog if at least 7735 one register is reloaded in addition to return address. */ 7736 7737 if (gmask) 7738 { 7739 for (regno = 1; regno <= 31; regno++) 7740 { 7741 if ((gmask & (1L << regno)) != 0) 7742 { 7743 if ((regno & 0x1) == 0 && ((gmask & (1L << (regno+1))) != 0)) 7744 { 7745 /* We can save two registers in a row. If we're not at a 7746 double word boundary, move to one. 7747 sparc_flat_compute_frame_size ensures there's room to do 7748 this. */ 7749 if (offset % 8 != 0) 7750 offset += UNITS_PER_WORD; 7751 7752 if (word_op[0] == 's') 7753 { 7754 fprintf (file, "\t%s\t%s, [%s+%d]\n", 7755 doubleword_op, reg_names[regno], 7756 base_reg, offset); 7757 if (dwarf2out_do_frame ()) 7758 { 7759 char *l = dwarf2out_cfi_label (); 7760 dwarf2out_reg_save (l, regno, offset + base_offset); 7761 dwarf2out_reg_save 7762 (l, regno+1, offset+base_offset + UNITS_PER_WORD); 7763 } 7764 } 7765 else 7766 fprintf (file, "\t%s\t[%s+%d], %s\n", 7767 doubleword_op, base_reg, offset, 7768 reg_names[regno]); 7769 7770 offset += 2 * UNITS_PER_WORD; 7771 regno++; 7772 } 7773 else 7774 { 7775 if (word_op[0] == 's') 7776 { 7777 fprintf (file, "\t%s\t%s, [%s+%d]\n", 7778 word_op, reg_names[regno], 7779 base_reg, offset); 7780 if (dwarf2out_do_frame ()) 7781 dwarf2out_reg_save ("", regno, offset + base_offset); 7782 } 7783 else 7784 fprintf (file, "\t%s\t[%s+%d], %s\n", 7785 word_op, base_reg, offset, reg_names[regno]); 7786 7787 offset += UNITS_PER_WORD; 7788 } 7789 } 7790 } 7791 } 7792 7793 if (fmask) 7794 { 7795 for (regno = 32; regno <= 63; regno++) 7796 { 7797 if ((fmask & (1L << (regno - 32))) != 0) 7798 { 7799 if (word_op[0] == 's') 7800 { 7801 fprintf (file, "\t%s\t%s, [%s+%d]\n", 7802 word_op, reg_names[regno], 7803 base_reg, offset); 7804 if (dwarf2out_do_frame ()) 7805 dwarf2out_reg_save ("", regno, offset + base_offset); 7806 } 7807 else 7808 fprintf (file, "\t%s\t[%s+%d], %s\n", 7809 word_op, base_reg, offset, reg_names[regno]); 7810 7811 offset += UNITS_PER_WORD; 7812 } 7813 } 7814 } 7815} 7816 7817/* Set up the stack and frame (if desired) for the function. */ 7818 7819static void 7820sparc_flat_function_prologue (FILE *file, HOST_WIDE_INT size) 7821{ 7822 const char *sp_str = reg_names[STACK_POINTER_REGNUM]; 7823 unsigned long gmask = current_frame_info.gmask; 7824 7825 sparc_output_scratch_registers (file); 7826 7827 /* This is only for the human reader. */ 7828 fprintf (file, "\t%s#PROLOGUE# 0\n", ASM_COMMENT_START); 7829 fprintf (file, "\t%s# vars= "HOST_WIDE_INT_PRINT_DEC", " 7830 "regs= %d/%d, args= %d, extra= %d\n", 7831 ASM_COMMENT_START, 7832 current_frame_info.var_size, 7833 current_frame_info.gp_reg_size / 4, 7834 current_frame_info.fp_reg_size / 4, 7835 current_function_outgoing_args_size, 7836 current_frame_info.extra_size); 7837 7838 size = SPARC_STACK_ALIGN (size); 7839 size = (! current_frame_info.initialized 7840 ? sparc_flat_compute_frame_size (size) 7841 : current_frame_info.total_size); 7842 7843 /* These cases shouldn't happen. Catch them now. */ 7844 if (size == 0 && (gmask || current_frame_info.fmask)) 7845 abort (); 7846 7847 /* Allocate our stack frame by decrementing %sp. 7848 At present, the only algorithm gdb can use to determine if this is a 7849 flat frame is if we always set %i7 if we set %sp. This can be optimized 7850 in the future by putting in some sort of debugging information that says 7851 this is a `flat' function. However, there is still the case of debugging 7852 code without such debugging information (including cases where most fns 7853 have such info, but there is one that doesn't). So, always do this now 7854 so we don't get a lot of code out there that gdb can't handle. 7855 If the frame pointer isn't needn't then that's ok - gdb won't be able to 7856 distinguish us from a non-flat function but there won't (and shouldn't) 7857 be any differences anyway. The return pc is saved (if necessary) right 7858 after %i7 so gdb won't have to look too far to find it. */ 7859 if (size > 0) 7860 { 7861 int reg_offset = current_frame_info.reg_offset; 7862 const char *const fp_str = reg_names[HARD_FRAME_POINTER_REGNUM]; 7863 static const char *const t1_str = "%g1"; 7864 7865 /* Things get a little tricky if local variables take up more than ~4096 7866 bytes and outgoing arguments take up more than ~4096 bytes. When that 7867 happens, the register save area can't be accessed from either end of 7868 the frame. Handle this by decrementing %sp to the start of the gp 7869 register save area, save the regs, update %i7, and then set %sp to its 7870 final value. Given that we only have one scratch register to play 7871 with it is the cheapest solution, and it helps gdb out as it won't 7872 slow down recognition of flat functions. 7873 Don't change the order of insns emitted here without checking with 7874 the gdb folk first. */ 7875 7876 /* Is the entire register save area offsettable from %sp? */ 7877 if (reg_offset < 4096 - 64 * UNITS_PER_WORD) 7878 { 7879 if (size <= 4096) 7880 { 7881 fprintf (file, "\tadd\t%s, -"HOST_WIDE_INT_PRINT_DEC", %s\n", 7882 sp_str, size, sp_str); 7883 if (gmask & HARD_FRAME_POINTER_MASK) 7884 { 7885 fprintf (file, "\tst\t%s, [%s+%d]\n", 7886 fp_str, sp_str, reg_offset); 7887 fprintf (file, "\tsub\t%s, -"HOST_WIDE_INT_PRINT_DEC", %s" 7888 "\t%s# set up frame pointer\n", 7889 sp_str, size, fp_str, ASM_COMMENT_START); 7890 reg_offset += 4; 7891 } 7892 } 7893 else 7894 { 7895 build_big_number (file, size, t1_str); 7896 fprintf (file, "\tsub\t%s, %s, %s\n", sp_str, t1_str, sp_str); 7897 if (gmask & HARD_FRAME_POINTER_MASK) 7898 { 7899 fprintf (file, "\tst\t%s, [%s+%d]\n", 7900 fp_str, sp_str, reg_offset); 7901 fprintf (file, "\tadd\t%s, %s, %s\t%s# set up frame pointer\n", 7902 sp_str, t1_str, fp_str, ASM_COMMENT_START); 7903 reg_offset += 4; 7904 } 7905 } 7906 if (dwarf2out_do_frame ()) 7907 { 7908 char *l = dwarf2out_cfi_label (); 7909 if (gmask & HARD_FRAME_POINTER_MASK) 7910 { 7911 dwarf2out_reg_save (l, HARD_FRAME_POINTER_REGNUM, 7912 reg_offset - 4 - size); 7913 dwarf2out_def_cfa (l, HARD_FRAME_POINTER_REGNUM, 0); 7914 } 7915 else 7916 dwarf2out_def_cfa (l, STACK_POINTER_REGNUM, size); 7917 } 7918 if (gmask & RETURN_ADDR_MASK) 7919 { 7920 fprintf (file, "\tst\t%s, [%s+%d]\n", 7921 reg_names[RETURN_ADDR_REGNUM], sp_str, reg_offset); 7922 if (dwarf2out_do_frame ()) 7923 dwarf2out_return_save ("", reg_offset - size); 7924 reg_offset += 4; 7925 } 7926 sparc_flat_save_restore (file, sp_str, reg_offset, 7927 gmask & ~(HARD_FRAME_POINTER_MASK | RETURN_ADDR_MASK), 7928 current_frame_info.fmask, 7929 "st", "std", -size); 7930 } 7931 else 7932 { 7933 /* Subtract %sp in two steps, but make sure there is always a 7934 64-byte register save area, and %sp is properly aligned. */ 7935 7936 /* Amount to decrement %sp by, the first time. */ 7937 HOST_WIDE_INT size1 = ((size - reg_offset + 64) + 15) & -16; 7938 7939 /* Amount to decrement %sp by, the second time. */ 7940 HOST_WIDE_INT size2 = size - size1; 7941 7942 /* Offset to register save area from %sp after first decrement. */ 7943 int offset = (int)(size1 - (size - reg_offset)); 7944 7945 if (size1 <= 4096) 7946 { 7947 fprintf (file, "\tadd\t%s, -"HOST_WIDE_INT_PRINT_DEC", %s\n", 7948 sp_str, size1, sp_str); 7949 if (gmask & HARD_FRAME_POINTER_MASK) 7950 { 7951 fprintf (file, "\tst\t%s, [%s+%d]\n" 7952 "\tsub\t%s, -"HOST_WIDE_INT_PRINT_DEC", %s" 7953 "\t%s# set up frame pointer\n", 7954 fp_str, sp_str, offset, sp_str, size1, 7955 fp_str, ASM_COMMENT_START); 7956 offset += 4; 7957 } 7958 } 7959 else 7960 { 7961 build_big_number (file, size1, t1_str); 7962 fprintf (file, "\tsub\t%s, %s, %s\n", sp_str, t1_str, sp_str); 7963 if (gmask & HARD_FRAME_POINTER_MASK) 7964 { 7965 fprintf (file, "\tst\t%s, [%s+%d]\n" 7966 "\tadd\t%s, %s, %s\t%s# set up frame pointer\n", 7967 fp_str, sp_str, offset, sp_str, t1_str, 7968 fp_str, ASM_COMMENT_START); 7969 offset += 4; 7970 } 7971 } 7972 if (dwarf2out_do_frame ()) 7973 { 7974 char *l = dwarf2out_cfi_label (); 7975 if (gmask & HARD_FRAME_POINTER_MASK) 7976 { 7977 dwarf2out_reg_save (l, HARD_FRAME_POINTER_REGNUM, 7978 offset - 4 - size1); 7979 dwarf2out_def_cfa (l, HARD_FRAME_POINTER_REGNUM, 0); 7980 } 7981 else 7982 dwarf2out_def_cfa (l, STACK_POINTER_REGNUM, size1); 7983 } 7984 if (gmask & RETURN_ADDR_MASK) 7985 { 7986 fprintf (file, "\tst\t%s, [%s+%d]\n", 7987 reg_names[RETURN_ADDR_REGNUM], sp_str, offset); 7988 if (dwarf2out_do_frame ()) 7989 /* offset - size1 == reg_offset - size 7990 if reg_offset were updated above like offset. */ 7991 dwarf2out_return_save ("", offset - size1); 7992 offset += 4; 7993 } 7994 sparc_flat_save_restore (file, sp_str, offset, 7995 gmask & ~(HARD_FRAME_POINTER_MASK | RETURN_ADDR_MASK), 7996 current_frame_info.fmask, 7997 "st", "std", -size1); 7998 if (size2 <= 4096) 7999 fprintf (file, "\tadd\t%s, -"HOST_WIDE_INT_PRINT_DEC", %s\n", 8000 sp_str, size2, sp_str); 8001 else 8002 { 8003 build_big_number (file, size2, t1_str); 8004 fprintf (file, "\tsub\t%s, %s, %s\n", sp_str, t1_str, sp_str); 8005 } 8006 if (dwarf2out_do_frame ()) 8007 if (! (gmask & HARD_FRAME_POINTER_MASK)) 8008 dwarf2out_def_cfa ("", STACK_POINTER_REGNUM, size); 8009 } 8010 } 8011 8012 fprintf (file, "\t%s#PROLOGUE# 1\n", ASM_COMMENT_START); 8013} 8014 8015/* Do any necessary cleanup after a function to restore stack, frame, 8016 and regs. */ 8017 8018static void 8019sparc_flat_function_epilogue (FILE *file, HOST_WIDE_INT size) 8020{ 8021 rtx epilogue_delay = current_function_epilogue_delay_list; 8022 int noepilogue = FALSE; 8023 8024 /* This is only for the human reader. */ 8025 fprintf (file, "\t%s#EPILOGUE#\n", ASM_COMMENT_START); 8026 8027 /* The epilogue does not depend on any registers, but the stack 8028 registers, so we assume that if we have 1 pending nop, it can be 8029 ignored, and 2 it must be filled (2 nops occur for integer 8030 multiply and divide). */ 8031 8032 size = SPARC_STACK_ALIGN (size); 8033 size = (!current_frame_info.initialized 8034 ? sparc_flat_compute_frame_size (size) 8035 : current_frame_info.total_size); 8036 8037 if (size == 0 && epilogue_delay == 0) 8038 { 8039 rtx insn = get_last_insn (); 8040 8041 /* If the last insn was a BARRIER, we don't have to write any code 8042 because a jump (aka return) was put there. */ 8043 if (GET_CODE (insn) == NOTE) 8044 insn = prev_nonnote_insn (insn); 8045 if (insn && GET_CODE (insn) == BARRIER) 8046 noepilogue = TRUE; 8047 } 8048 8049 if (!noepilogue) 8050 { 8051 int reg_offset = current_frame_info.reg_offset; 8052 int reg_offset1; 8053 const char *const sp_str = reg_names[STACK_POINTER_REGNUM]; 8054 const char *const fp_str = reg_names[HARD_FRAME_POINTER_REGNUM]; 8055 static const char *const t1_str = "%g1"; 8056 8057 /* In the reload sequence, we don't need to fill the load delay 8058 slots for most of the loads, also see if we can fill the final 8059 delay slot if not otherwise filled by the reload sequence. */ 8060 8061 if (size > 4096) 8062 build_big_number (file, size, t1_str); 8063 8064 if (frame_pointer_needed) 8065 { 8066 if (size > 4096) 8067 fprintf (file,"\tsub\t%s, %s, %s\t\t%s# sp not trusted here\n", 8068 fp_str, t1_str, sp_str, ASM_COMMENT_START); 8069 else 8070 fprintf (file,"\tadd\t%s, -"HOST_WIDE_INT_PRINT_DEC", %s" 8071 "\t\t%s# sp not trusted here\n", 8072 fp_str, size, sp_str, ASM_COMMENT_START); 8073 } 8074 8075 /* Is the entire register save area offsettable from %sp? */ 8076 if (reg_offset < 4096 - 64 * UNITS_PER_WORD) 8077 { 8078 reg_offset1 = 0; 8079 } 8080 else 8081 { 8082 /* Restore %sp in two steps, but make sure there is always a 8083 64-byte register save area, and %sp is properly aligned. */ 8084 8085 /* Amount to increment %sp by, the first time. */ 8086 reg_offset1 = ((reg_offset - 64 - 16) + 15) & -16; 8087 8088 /* Offset to register save area from %sp. */ 8089 reg_offset = reg_offset1 - reg_offset; 8090 8091 if (reg_offset1 > 4096) 8092 { 8093 build_big_number (file, reg_offset1, t1_str); 8094 fprintf (file, "\tadd\t%s, %s, %s\n", sp_str, t1_str, sp_str); 8095 } 8096 else 8097 fprintf (file, "\tsub\t%s, -%d, %s\n", sp_str, reg_offset1, sp_str); 8098 } 8099 8100 /* We must restore the frame pointer and return address reg first 8101 because they are treated specially by the prologue output code. */ 8102 if (current_frame_info.gmask & HARD_FRAME_POINTER_MASK) 8103 { 8104 fprintf (file, "\tld\t[%s+%d], %s\n", 8105 sp_str, reg_offset, fp_str); 8106 reg_offset += 4; 8107 } 8108 if (current_frame_info.gmask & RETURN_ADDR_MASK) 8109 { 8110 fprintf (file, "\tld\t[%s+%d], %s\n", 8111 sp_str, reg_offset, reg_names[RETURN_ADDR_REGNUM]); 8112 reg_offset += 4; 8113 } 8114 8115 /* Restore any remaining saved registers. */ 8116 sparc_flat_save_restore (file, sp_str, reg_offset, 8117 current_frame_info.gmask & ~(HARD_FRAME_POINTER_MASK | RETURN_ADDR_MASK), 8118 current_frame_info.fmask, 8119 "ld", "ldd", 0); 8120 8121 /* If we had to increment %sp in two steps, record it so the second 8122 restoration in the epilogue finishes up. */ 8123 if (reg_offset1 > 0) 8124 { 8125 size -= reg_offset1; 8126 if (size > 4096) 8127 build_big_number (file, size, t1_str); 8128 } 8129 8130 if (current_function_returns_struct) 8131 fprintf (file, "\tjmp\t%%o7+12\n"); 8132 else 8133 fprintf (file, "\tretl\n"); 8134 8135 /* If the only register saved is the return address, we need a 8136 nop, unless we have an instruction to put into it. Otherwise 8137 we don't since reloading multiple registers doesn't reference 8138 the register being loaded. */ 8139 8140 if (epilogue_delay) 8141 { 8142 if (size) 8143 abort (); 8144 final_scan_insn (XEXP (epilogue_delay, 0), file, 1, -2, 1, NULL); 8145 } 8146 8147 else if (size > 4096) 8148 fprintf (file, "\tadd\t%s, %s, %s\n", sp_str, t1_str, sp_str); 8149 8150 else if (size > 0) 8151 fprintf (file, "\tsub\t%s, -"HOST_WIDE_INT_PRINT_DEC", %s\n", 8152 sp_str, size, sp_str); 8153 8154 else 8155 fprintf (file, "\tnop\n"); 8156 } 8157 8158 /* Reset state info for each function. */ 8159 current_frame_info = zero_frame_info; 8160 8161 sparc_output_deferred_case_vectors (); 8162} 8163 8164/* Define the number of delay slots needed for the function epilogue. 8165 8166 On the sparc, we need a slot if either no stack has been allocated, 8167 or the only register saved is the return register. */ 8168 8169int 8170sparc_flat_epilogue_delay_slots (void) 8171{ 8172 if (!current_frame_info.initialized) 8173 (void) sparc_flat_compute_frame_size (get_frame_size ()); 8174 8175 if (current_frame_info.total_size == 0) 8176 return 1; 8177 8178 return 0; 8179} 8180 8181/* Return true if TRIAL is a valid insn for the epilogue delay slot. 8182 Any single length instruction which doesn't reference the stack or frame 8183 pointer is OK. */ 8184 8185int 8186sparc_flat_eligible_for_epilogue_delay (rtx trial, int slot ATTRIBUTE_UNUSED) 8187{ 8188 rtx pat = PATTERN (trial); 8189 8190 if (get_attr_length (trial) != 1) 8191 return 0; 8192 8193 if (! reg_mentioned_p (stack_pointer_rtx, pat) 8194 && ! reg_mentioned_p (frame_pointer_rtx, pat)) 8195 return 1; 8196 8197 return 0; 8198} 8199 8200/* Adjust the cost of a scheduling dependency. Return the new cost of 8201 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */ 8202 8203static int 8204supersparc_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost) 8205{ 8206 enum attr_type insn_type; 8207 8208 if (! recog_memoized (insn)) 8209 return 0; 8210 8211 insn_type = get_attr_type (insn); 8212 8213 if (REG_NOTE_KIND (link) == 0) 8214 { 8215 /* Data dependency; DEP_INSN writes a register that INSN reads some 8216 cycles later. */ 8217 8218 /* if a load, then the dependence must be on the memory address; 8219 add an extra "cycle". Note that the cost could be two cycles 8220 if the reg was written late in an instruction group; we ca not tell 8221 here. */ 8222 if (insn_type == TYPE_LOAD || insn_type == TYPE_FPLOAD) 8223 return cost + 3; 8224 8225 /* Get the delay only if the address of the store is the dependence. */ 8226 if (insn_type == TYPE_STORE || insn_type == TYPE_FPSTORE) 8227 { 8228 rtx pat = PATTERN(insn); 8229 rtx dep_pat = PATTERN (dep_insn); 8230 8231 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET) 8232 return cost; /* This should not happen! */ 8233 8234 /* The dependency between the two instructions was on the data that 8235 is being stored. Assume that this implies that the address of the 8236 store is not dependent. */ 8237 if (rtx_equal_p (SET_DEST (dep_pat), SET_SRC (pat))) 8238 return cost; 8239 8240 return cost + 3; /* An approximation. */ 8241 } 8242 8243 /* A shift instruction cannot receive its data from an instruction 8244 in the same cycle; add a one cycle penalty. */ 8245 if (insn_type == TYPE_SHIFT) 8246 return cost + 3; /* Split before cascade into shift. */ 8247 } 8248 else 8249 { 8250 /* Anti- or output- dependency; DEP_INSN reads/writes a register that 8251 INSN writes some cycles later. */ 8252 8253 /* These are only significant for the fpu unit; writing a fp reg before 8254 the fpu has finished with it stalls the processor. */ 8255 8256 /* Reusing an integer register causes no problems. */ 8257 if (insn_type == TYPE_IALU || insn_type == TYPE_SHIFT) 8258 return 0; 8259 } 8260 8261 return cost; 8262} 8263 8264static int 8265hypersparc_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost) 8266{ 8267 enum attr_type insn_type, dep_type; 8268 rtx pat = PATTERN(insn); 8269 rtx dep_pat = PATTERN (dep_insn); 8270 8271 if (recog_memoized (insn) < 0 || recog_memoized (dep_insn) < 0) 8272 return cost; 8273 8274 insn_type = get_attr_type (insn); 8275 dep_type = get_attr_type (dep_insn); 8276 8277 switch (REG_NOTE_KIND (link)) 8278 { 8279 case 0: 8280 /* Data dependency; DEP_INSN writes a register that INSN reads some 8281 cycles later. */ 8282 8283 switch (insn_type) 8284 { 8285 case TYPE_STORE: 8286 case TYPE_FPSTORE: 8287 /* Get the delay iff the address of the store is the dependence. */ 8288 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET) 8289 return cost; 8290 8291 if (rtx_equal_p (SET_DEST (dep_pat), SET_SRC (pat))) 8292 return cost; 8293 return cost + 3; 8294 8295 case TYPE_LOAD: 8296 case TYPE_SLOAD: 8297 case TYPE_FPLOAD: 8298 /* If a load, then the dependence must be on the memory address. If 8299 the addresses aren't equal, then it might be a false dependency */ 8300 if (dep_type == TYPE_STORE || dep_type == TYPE_FPSTORE) 8301 { 8302 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET 8303 || GET_CODE (SET_DEST (dep_pat)) != MEM 8304 || GET_CODE (SET_SRC (pat)) != MEM 8305 || ! rtx_equal_p (XEXP (SET_DEST (dep_pat), 0), 8306 XEXP (SET_SRC (pat), 0))) 8307 return cost + 2; 8308 8309 return cost + 8; 8310 } 8311 break; 8312 8313 case TYPE_BRANCH: 8314 /* Compare to branch latency is 0. There is no benefit from 8315 separating compare and branch. */ 8316 if (dep_type == TYPE_COMPARE) 8317 return 0; 8318 /* Floating point compare to branch latency is less than 8319 compare to conditional move. */ 8320 if (dep_type == TYPE_FPCMP) 8321 return cost - 1; 8322 break; 8323 default: 8324 break; 8325 } 8326 break; 8327 8328 case REG_DEP_ANTI: 8329 /* Anti-dependencies only penalize the fpu unit. */ 8330 if (insn_type == TYPE_IALU || insn_type == TYPE_SHIFT) 8331 return 0; 8332 break; 8333 8334 default: 8335 break; 8336 } 8337 8338 return cost; 8339} 8340 8341static int 8342sparc_adjust_cost(rtx insn, rtx link, rtx dep, int cost) 8343{ 8344 switch (sparc_cpu) 8345 { 8346 case PROCESSOR_SUPERSPARC: 8347 cost = supersparc_adjust_cost (insn, link, dep, cost); 8348 break; 8349 case PROCESSOR_HYPERSPARC: 8350 case PROCESSOR_SPARCLITE86X: 8351 cost = hypersparc_adjust_cost (insn, link, dep, cost); 8352 break; 8353 default: 8354 break; 8355 } 8356 return cost; 8357} 8358 8359static void 8360sparc_sched_init (FILE *dump ATTRIBUTE_UNUSED, 8361 int sched_verbose ATTRIBUTE_UNUSED, 8362 int max_ready ATTRIBUTE_UNUSED) 8363{ 8364} 8365 8366static int 8367sparc_use_dfa_pipeline_interface (void) 8368{ 8369 if ((1 << sparc_cpu) & 8370 ((1 << PROCESSOR_ULTRASPARC) | (1 << PROCESSOR_CYPRESS) | 8371 (1 << PROCESSOR_SUPERSPARC) | (1 << PROCESSOR_HYPERSPARC) | 8372 (1 << PROCESSOR_SPARCLITE86X) | (1 << PROCESSOR_TSC701) | 8373 (1 << PROCESSOR_ULTRASPARC3))) 8374 return 1; 8375 return 0; 8376} 8377 8378static int 8379sparc_use_sched_lookahead (void) 8380{ 8381 if (sparc_cpu == PROCESSOR_ULTRASPARC 8382 || sparc_cpu == PROCESSOR_ULTRASPARC3) 8383 return 4; 8384 if ((1 << sparc_cpu) & 8385 ((1 << PROCESSOR_SUPERSPARC) | (1 << PROCESSOR_HYPERSPARC) | 8386 (1 << PROCESSOR_SPARCLITE86X))) 8387 return 3; 8388 return 0; 8389} 8390 8391static int 8392sparc_issue_rate (void) 8393{ 8394 switch (sparc_cpu) 8395 { 8396 default: 8397 return 1; 8398 case PROCESSOR_V9: 8399 /* Assume V9 processors are capable of at least dual-issue. */ 8400 return 2; 8401 case PROCESSOR_SUPERSPARC: 8402 return 3; 8403 case PROCESSOR_HYPERSPARC: 8404 case PROCESSOR_SPARCLITE86X: 8405 return 2; 8406 case PROCESSOR_ULTRASPARC: 8407 case PROCESSOR_ULTRASPARC3: 8408 return 4; 8409 } 8410} 8411 8412static int 8413set_extends (rtx insn) 8414{ 8415 register rtx pat = PATTERN (insn); 8416 8417 switch (GET_CODE (SET_SRC (pat))) 8418 { 8419 /* Load and some shift instructions zero extend. */ 8420 case MEM: 8421 case ZERO_EXTEND: 8422 /* sethi clears the high bits */ 8423 case HIGH: 8424 /* LO_SUM is used with sethi. sethi cleared the high 8425 bits and the values used with lo_sum are positive */ 8426 case LO_SUM: 8427 /* Store flag stores 0 or 1 */ 8428 case LT: case LTU: 8429 case GT: case GTU: 8430 case LE: case LEU: 8431 case GE: case GEU: 8432 case EQ: 8433 case NE: 8434 return 1; 8435 case AND: 8436 { 8437 rtx op0 = XEXP (SET_SRC (pat), 0); 8438 rtx op1 = XEXP (SET_SRC (pat), 1); 8439 if (GET_CODE (op1) == CONST_INT) 8440 return INTVAL (op1) >= 0; 8441 if (GET_CODE (op0) != REG) 8442 return 0; 8443 if (sparc_check_64 (op0, insn) == 1) 8444 return 1; 8445 return (GET_CODE (op1) == REG && sparc_check_64 (op1, insn) == 1); 8446 } 8447 case IOR: 8448 case XOR: 8449 { 8450 rtx op0 = XEXP (SET_SRC (pat), 0); 8451 rtx op1 = XEXP (SET_SRC (pat), 1); 8452 if (GET_CODE (op0) != REG || sparc_check_64 (op0, insn) <= 0) 8453 return 0; 8454 if (GET_CODE (op1) == CONST_INT) 8455 return INTVAL (op1) >= 0; 8456 return (GET_CODE (op1) == REG && sparc_check_64 (op1, insn) == 1); 8457 } 8458 case LSHIFTRT: 8459 return GET_MODE (SET_SRC (pat)) == SImode; 8460 /* Positive integers leave the high bits zero. */ 8461 case CONST_DOUBLE: 8462 return ! (CONST_DOUBLE_LOW (SET_SRC (pat)) & 0x80000000); 8463 case CONST_INT: 8464 return ! (INTVAL (SET_SRC (pat)) & 0x80000000); 8465 case ASHIFTRT: 8466 case SIGN_EXTEND: 8467 return - (GET_MODE (SET_SRC (pat)) == SImode); 8468 case REG: 8469 return sparc_check_64 (SET_SRC (pat), insn); 8470 default: 8471 return 0; 8472 } 8473} 8474 8475/* We _ought_ to have only one kind per function, but... */ 8476static GTY(()) rtx sparc_addr_diff_list; 8477static GTY(()) rtx sparc_addr_list; 8478 8479void 8480sparc_defer_case_vector (rtx lab, rtx vec, int diff) 8481{ 8482 vec = gen_rtx_EXPR_LIST (VOIDmode, lab, vec); 8483 if (diff) 8484 sparc_addr_diff_list 8485 = gen_rtx_EXPR_LIST (VOIDmode, vec, sparc_addr_diff_list); 8486 else 8487 sparc_addr_list = gen_rtx_EXPR_LIST (VOIDmode, vec, sparc_addr_list); 8488} 8489 8490static void 8491sparc_output_addr_vec (rtx vec) 8492{ 8493 rtx lab = XEXP (vec, 0), body = XEXP (vec, 1); 8494 int idx, vlen = XVECLEN (body, 0); 8495 8496#ifdef ASM_OUTPUT_ADDR_VEC_START 8497 ASM_OUTPUT_ADDR_VEC_START (asm_out_file); 8498#endif 8499 8500#ifdef ASM_OUTPUT_CASE_LABEL 8501 ASM_OUTPUT_CASE_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (lab), 8502 NEXT_INSN (lab)); 8503#else 8504 (*targetm.asm_out.internal_label) (asm_out_file, "L", CODE_LABEL_NUMBER (lab)); 8505#endif 8506 8507 for (idx = 0; idx < vlen; idx++) 8508 { 8509 ASM_OUTPUT_ADDR_VEC_ELT 8510 (asm_out_file, CODE_LABEL_NUMBER (XEXP (XVECEXP (body, 0, idx), 0))); 8511 } 8512 8513#ifdef ASM_OUTPUT_ADDR_VEC_END 8514 ASM_OUTPUT_ADDR_VEC_END (asm_out_file); 8515#endif 8516} 8517 8518static void 8519sparc_output_addr_diff_vec (rtx vec) 8520{ 8521 rtx lab = XEXP (vec, 0), body = XEXP (vec, 1); 8522 rtx base = XEXP (XEXP (body, 0), 0); 8523 int idx, vlen = XVECLEN (body, 1); 8524 8525#ifdef ASM_OUTPUT_ADDR_VEC_START 8526 ASM_OUTPUT_ADDR_VEC_START (asm_out_file); 8527#endif 8528 8529#ifdef ASM_OUTPUT_CASE_LABEL 8530 ASM_OUTPUT_CASE_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (lab), 8531 NEXT_INSN (lab)); 8532#else 8533 (*targetm.asm_out.internal_label) (asm_out_file, "L", CODE_LABEL_NUMBER (lab)); 8534#endif 8535 8536 for (idx = 0; idx < vlen; idx++) 8537 { 8538 ASM_OUTPUT_ADDR_DIFF_ELT 8539 (asm_out_file, 8540 body, 8541 CODE_LABEL_NUMBER (XEXP (XVECEXP (body, 1, idx), 0)), 8542 CODE_LABEL_NUMBER (base)); 8543 } 8544 8545#ifdef ASM_OUTPUT_ADDR_VEC_END 8546 ASM_OUTPUT_ADDR_VEC_END (asm_out_file); 8547#endif 8548} 8549 8550static void 8551sparc_output_deferred_case_vectors (void) 8552{ 8553 rtx t; 8554 int align; 8555 8556 if (sparc_addr_list == NULL_RTX 8557 && sparc_addr_diff_list == NULL_RTX) 8558 return; 8559 8560 /* Align to cache line in the function's code section. */ 8561 function_section (current_function_decl); 8562 8563 align = floor_log2 (FUNCTION_BOUNDARY / BITS_PER_UNIT); 8564 if (align > 0) 8565 ASM_OUTPUT_ALIGN (asm_out_file, align); 8566 8567 for (t = sparc_addr_list; t ; t = XEXP (t, 1)) 8568 sparc_output_addr_vec (XEXP (t, 0)); 8569 for (t = sparc_addr_diff_list; t ; t = XEXP (t, 1)) 8570 sparc_output_addr_diff_vec (XEXP (t, 0)); 8571 8572 sparc_addr_list = sparc_addr_diff_list = NULL_RTX; 8573} 8574 8575/* Return 0 if the high 32 bits of X (the low word of X, if DImode) are 8576 unknown. Return 1 if the high bits are zero, -1 if the register is 8577 sign extended. */ 8578int 8579sparc_check_64 (rtx x, rtx insn) 8580{ 8581 /* If a register is set only once it is safe to ignore insns this 8582 code does not know how to handle. The loop will either recognize 8583 the single set and return the correct value or fail to recognize 8584 it and return 0. */ 8585 int set_once = 0; 8586 rtx y = x; 8587 8588 if (GET_CODE (x) != REG) 8589 abort (); 8590 8591 if (GET_MODE (x) == DImode) 8592 y = gen_rtx_REG (SImode, REGNO (x) + WORDS_BIG_ENDIAN); 8593 8594 if (flag_expensive_optimizations 8595 && REG_N_SETS (REGNO (y)) == 1) 8596 set_once = 1; 8597 8598 if (insn == 0) 8599 { 8600 if (set_once) 8601 insn = get_last_insn_anywhere (); 8602 else 8603 return 0; 8604 } 8605 8606 while ((insn = PREV_INSN (insn))) 8607 { 8608 switch (GET_CODE (insn)) 8609 { 8610 case JUMP_INSN: 8611 case NOTE: 8612 break; 8613 case CODE_LABEL: 8614 case CALL_INSN: 8615 default: 8616 if (! set_once) 8617 return 0; 8618 break; 8619 case INSN: 8620 { 8621 rtx pat = PATTERN (insn); 8622 if (GET_CODE (pat) != SET) 8623 return 0; 8624 if (rtx_equal_p (x, SET_DEST (pat))) 8625 return set_extends (insn); 8626 if (y && rtx_equal_p (y, SET_DEST (pat))) 8627 return set_extends (insn); 8628 if (reg_overlap_mentioned_p (SET_DEST (pat), y)) 8629 return 0; 8630 } 8631 } 8632 } 8633 return 0; 8634} 8635 8636/* Returns assembly code to perform a DImode shift using 8637 a 64-bit global or out register on SPARC-V8+. */ 8638char * 8639sparc_v8plus_shift (rtx *operands, rtx insn, const char *opcode) 8640{ 8641 static char asm_code[60]; 8642 8643 /* The scratch register is only required when the destination 8644 register is not a 64-bit global or out register. */ 8645 if (which_alternative != 2) 8646 operands[3] = operands[0]; 8647 8648 /* We can only shift by constants <= 63. */ 8649 if (GET_CODE (operands[2]) == CONST_INT) 8650 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f); 8651 8652 if (GET_CODE (operands[1]) == CONST_INT) 8653 { 8654 output_asm_insn ("mov\t%1, %3", operands); 8655 } 8656 else 8657 { 8658 output_asm_insn ("sllx\t%H1, 32, %3", operands); 8659 if (sparc_check_64 (operands[1], insn) <= 0) 8660 output_asm_insn ("srl\t%L1, 0, %L1", operands); 8661 output_asm_insn ("or\t%L1, %3, %3", operands); 8662 } 8663 8664 strcpy(asm_code, opcode); 8665 8666 if (which_alternative != 2) 8667 return strcat (asm_code, "\t%0, %2, %L0\n\tsrlx\t%L0, 32, %H0"); 8668 else 8669 return strcat (asm_code, "\t%3, %2, %3\n\tsrlx\t%3, 32, %H0\n\tmov\t%3, %L0"); 8670} 8671 8672/* Output rtl to increment the profiler label LABELNO 8673 for profiling a function entry. */ 8674 8675void 8676sparc_profile_hook (int labelno) 8677{ 8678 char buf[32]; 8679 rtx lab, fun; 8680 8681 ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno); 8682 lab = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf)); 8683 fun = gen_rtx_SYMBOL_REF (Pmode, MCOUNT_FUNCTION); 8684 8685 emit_library_call (fun, LCT_NORMAL, VOIDmode, 1, lab, Pmode); 8686} 8687 8688#ifdef OBJECT_FORMAT_ELF 8689static void 8690sparc_elf_asm_named_section (const char *name, unsigned int flags) 8691{ 8692 if (flags & SECTION_MERGE) 8693 { 8694 /* entsize cannot be expressed in this section attributes 8695 encoding style. */ 8696 default_elf_asm_named_section (name, flags); 8697 return; 8698 } 8699 8700 fprintf (asm_out_file, "\t.section\t\"%s\"", name); 8701 8702 if (!(flags & SECTION_DEBUG)) 8703 fputs (",#alloc", asm_out_file); 8704 if (flags & SECTION_WRITE) 8705 fputs (",#write", asm_out_file); 8706 if (flags & SECTION_TLS) 8707 fputs (",#tls", asm_out_file); 8708 if (flags & SECTION_CODE) 8709 fputs (",#execinstr", asm_out_file); 8710 8711 /* ??? Handle SECTION_BSS. */ 8712 8713 fputc ('\n', asm_out_file); 8714} 8715#endif /* OBJECT_FORMAT_ELF */ 8716 8717/* We do not allow sibling calls if -mflat, nor 8718 we do not allow indirect calls to be optimized into sibling calls. 8719 8720 Also, on sparc 32-bit we cannot emit a sibling call when the 8721 current function returns a structure. This is because the "unimp 8722 after call" convention would cause the callee to return to the 8723 wrong place. The generic code already disallows cases where the 8724 function being called returns a structure. 8725 8726 It may seem strange how this last case could occur. Usually there 8727 is code after the call which jumps to epilogue code which dumps the 8728 return value into the struct return area. That ought to invalidate 8729 the sibling call right? Well, in the c++ case we can end up passing 8730 the pointer to the struct return area to a constructor (which returns 8731 void) and then nothing else happens. Such a sibling call would look 8732 valid without the added check here. */ 8733static bool 8734sparc_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED) 8735{ 8736 return (decl 8737 && ! TARGET_FLAT 8738 && (TARGET_ARCH64 || ! current_function_returns_struct)); 8739} 8740 8741/* libfunc renaming. */ 8742#include "config/gofast.h" 8743 8744static void 8745sparc_init_libfuncs (void) 8746{ 8747 if (TARGET_ARCH32) 8748 { 8749 /* Use the subroutines that Sun's library provides for integer 8750 multiply and divide. The `*' prevents an underscore from 8751 being prepended by the compiler. .umul is a little faster 8752 than .mul. */ 8753 set_optab_libfunc (smul_optab, SImode, "*.umul"); 8754 set_optab_libfunc (sdiv_optab, SImode, "*.div"); 8755 set_optab_libfunc (udiv_optab, SImode, "*.udiv"); 8756 set_optab_libfunc (smod_optab, SImode, "*.rem"); 8757 set_optab_libfunc (umod_optab, SImode, "*.urem"); 8758 8759 /* TFmode arithmetic. These names are part of the SPARC 32bit ABI. */ 8760 set_optab_libfunc (add_optab, TFmode, "_Q_add"); 8761 set_optab_libfunc (sub_optab, TFmode, "_Q_sub"); 8762 set_optab_libfunc (neg_optab, TFmode, "_Q_neg"); 8763 set_optab_libfunc (smul_optab, TFmode, "_Q_mul"); 8764 set_optab_libfunc (sdiv_optab, TFmode, "_Q_div"); 8765 8766 /* We can define the TFmode sqrt optab only if TARGET_FPU. This 8767 is because with soft-float, the SFmode and DFmode sqrt 8768 instructions will be absent, and the compiler will notice and 8769 try to use the TFmode sqrt instruction for calls to the 8770 builtin function sqrt, but this fails. */ 8771 if (TARGET_FPU) 8772 set_optab_libfunc (sqrt_optab, TFmode, "_Q_sqrt"); 8773 8774 set_optab_libfunc (eq_optab, TFmode, "_Q_feq"); 8775 set_optab_libfunc (ne_optab, TFmode, "_Q_fne"); 8776 set_optab_libfunc (gt_optab, TFmode, "_Q_fgt"); 8777 set_optab_libfunc (ge_optab, TFmode, "_Q_fge"); 8778 set_optab_libfunc (lt_optab, TFmode, "_Q_flt"); 8779 set_optab_libfunc (le_optab, TFmode, "_Q_fle"); 8780 8781 set_conv_libfunc (sext_optab, TFmode, SFmode, "_Q_stoq"); 8782 set_conv_libfunc (sext_optab, TFmode, DFmode, "_Q_dtoq"); 8783 set_conv_libfunc (trunc_optab, SFmode, TFmode, "_Q_qtos"); 8784 set_conv_libfunc (trunc_optab, DFmode, TFmode, "_Q_qtod"); 8785 8786 set_conv_libfunc (sfix_optab, SImode, TFmode, "_Q_qtoi"); 8787 set_conv_libfunc (ufix_optab, SImode, TFmode, "_Q_qtou"); 8788 set_conv_libfunc (sfloat_optab, TFmode, SImode, "_Q_itoq"); 8789 8790 if (DITF_CONVERSION_LIBFUNCS) 8791 { 8792 set_conv_libfunc (sfix_optab, DImode, TFmode, "_Q_qtoll"); 8793 set_conv_libfunc (ufix_optab, DImode, TFmode, "_Q_qtoull"); 8794 set_conv_libfunc (sfloat_optab, TFmode, DImode, "_Q_lltoq"); 8795 } 8796 8797 if (SUN_CONVERSION_LIBFUNCS) 8798 { 8799 set_conv_libfunc (sfix_optab, DImode, SFmode, "__ftoll"); 8800 set_conv_libfunc (ufix_optab, DImode, SFmode, "__ftoull"); 8801 set_conv_libfunc (sfix_optab, DImode, DFmode, "__dtoll"); 8802 set_conv_libfunc (ufix_optab, DImode, DFmode, "__dtoull"); 8803 } 8804 } 8805 if (TARGET_ARCH64) 8806 { 8807 /* In the SPARC 64bit ABI, SImode multiply and divide functions 8808 do not exist in the library. Make sure the compiler does not 8809 emit calls to them by accident. (It should always use the 8810 hardware instructions.) */ 8811 set_optab_libfunc (smul_optab, SImode, 0); 8812 set_optab_libfunc (sdiv_optab, SImode, 0); 8813 set_optab_libfunc (udiv_optab, SImode, 0); 8814 set_optab_libfunc (smod_optab, SImode, 0); 8815 set_optab_libfunc (umod_optab, SImode, 0); 8816 8817 if (SUN_INTEGER_MULTIPLY_64) 8818 { 8819 set_optab_libfunc (smul_optab, DImode, "__mul64"); 8820 set_optab_libfunc (sdiv_optab, DImode, "__div64"); 8821 set_optab_libfunc (udiv_optab, DImode, "__udiv64"); 8822 set_optab_libfunc (smod_optab, DImode, "__rem64"); 8823 set_optab_libfunc (umod_optab, DImode, "__urem64"); 8824 } 8825 8826 if (SUN_CONVERSION_LIBFUNCS) 8827 { 8828 set_conv_libfunc (sfix_optab, DImode, SFmode, "__ftol"); 8829 set_conv_libfunc (ufix_optab, DImode, SFmode, "__ftoul"); 8830 set_conv_libfunc (sfix_optab, DImode, DFmode, "__dtol"); 8831 set_conv_libfunc (ufix_optab, DImode, DFmode, "__dtoul"); 8832 } 8833 } 8834 8835 gofast_maybe_init_libfuncs (); 8836} 8837 8838/* ??? Similar to the standard section selection, but force reloc-y-ness 8839 if SUNOS4_SHARED_LIBRARIES. Unclear why this helps (as opposed to 8840 pretending PIC always on), but that's what the old code did. */ 8841 8842static void 8843sparc_aout_select_section (tree t, int reloc, unsigned HOST_WIDE_INT align) 8844{ 8845 default_select_section (t, reloc | SUNOS4_SHARED_LIBRARIES, align); 8846} 8847 8848/* Use text section for a constant unless we need more alignment than 8849 that offers. */ 8850 8851static void 8852sparc_aout_select_rtx_section (enum machine_mode mode, rtx x, 8853 unsigned HOST_WIDE_INT align) 8854{ 8855 if (align <= MAX_TEXT_ALIGN 8856 && ! (flag_pic && (symbolic_operand (x, mode) 8857 || SUNOS4_SHARED_LIBRARIES))) 8858 readonly_data_section (); 8859 else 8860 data_section (); 8861} 8862 8863int 8864sparc_extra_constraint_check (rtx op, int c, int strict) 8865{ 8866 int reload_ok_mem; 8867 8868 if (TARGET_ARCH64 8869 && (c == 'T' || c == 'U')) 8870 return 0; 8871 8872 switch (c) 8873 { 8874 case 'Q': 8875 return fp_sethi_p (op); 8876 8877 case 'R': 8878 return fp_mov_p (op); 8879 8880 case 'S': 8881 return fp_high_losum_p (op); 8882 8883 case 'U': 8884 if (! strict 8885 || (GET_CODE (op) == REG 8886 && (REGNO (op) < FIRST_PSEUDO_REGISTER 8887 || reg_renumber[REGNO (op)] >= 0))) 8888 return register_ok_for_ldd (op); 8889 8890 return 0; 8891 8892 case 'W': 8893 case 'T': 8894 break; 8895 8896 default: 8897 return 0; 8898 } 8899 8900 /* Our memory extra constraints have to emulate the 8901 behavior of 'm' and 'o' in order for reload to work 8902 correctly. */ 8903 if (GET_CODE (op) == MEM) 8904 { 8905 reload_ok_mem = 0; 8906 if ((TARGET_ARCH64 || mem_min_alignment (op, 8)) 8907 && (! strict 8908 || strict_memory_address_p (Pmode, XEXP (op, 0)))) 8909 reload_ok_mem = 1; 8910 } 8911 else 8912 { 8913 reload_ok_mem = (reload_in_progress 8914 && GET_CODE (op) == REG 8915 && REGNO (op) >= FIRST_PSEUDO_REGISTER 8916 && reg_renumber [REGNO (op)] < 0); 8917 } 8918 8919 return reload_ok_mem; 8920} 8921 8922/* ??? This duplicates information provided to the compiler by the 8923 ??? scheduler description. Some day, teach genautomata to output 8924 ??? the latencies and then CSE will just use that. */ 8925 8926static bool 8927sparc_rtx_costs (rtx x, int code, int outer_code, int *total) 8928{ 8929 switch (code) 8930 { 8931 case PLUS: case MINUS: case ABS: case NEG: 8932 case FLOAT: case UNSIGNED_FLOAT: 8933 case FIX: case UNSIGNED_FIX: 8934 case FLOAT_EXTEND: case FLOAT_TRUNCATE: 8935 if (FLOAT_MODE_P (GET_MODE (x))) 8936 { 8937 switch (sparc_cpu) 8938 { 8939 case PROCESSOR_ULTRASPARC: 8940 case PROCESSOR_ULTRASPARC3: 8941 *total = COSTS_N_INSNS (4); 8942 return true; 8943 8944 case PROCESSOR_SUPERSPARC: 8945 *total = COSTS_N_INSNS (3); 8946 return true; 8947 8948 case PROCESSOR_CYPRESS: 8949 *total = COSTS_N_INSNS (5); 8950 return true; 8951 8952 case PROCESSOR_HYPERSPARC: 8953 case PROCESSOR_SPARCLITE86X: 8954 default: 8955 *total = COSTS_N_INSNS (1); 8956 return true; 8957 } 8958 } 8959 8960 *total = COSTS_N_INSNS (1); 8961 return true; 8962 8963 case SQRT: 8964 switch (sparc_cpu) 8965 { 8966 case PROCESSOR_ULTRASPARC: 8967 if (GET_MODE (x) == SFmode) 8968 *total = COSTS_N_INSNS (13); 8969 else 8970 *total = COSTS_N_INSNS (23); 8971 return true; 8972 8973 case PROCESSOR_ULTRASPARC3: 8974 if (GET_MODE (x) == SFmode) 8975 *total = COSTS_N_INSNS (20); 8976 else 8977 *total = COSTS_N_INSNS (29); 8978 return true; 8979 8980 case PROCESSOR_SUPERSPARC: 8981 *total = COSTS_N_INSNS (12); 8982 return true; 8983 8984 case PROCESSOR_CYPRESS: 8985 *total = COSTS_N_INSNS (63); 8986 return true; 8987 8988 case PROCESSOR_HYPERSPARC: 8989 case PROCESSOR_SPARCLITE86X: 8990 *total = COSTS_N_INSNS (17); 8991 return true; 8992 8993 default: 8994 *total = COSTS_N_INSNS (30); 8995 return true; 8996 } 8997 8998 case COMPARE: 8999 if (FLOAT_MODE_P (GET_MODE (x))) 9000 { 9001 switch (sparc_cpu) 9002 { 9003 case PROCESSOR_ULTRASPARC: 9004 case PROCESSOR_ULTRASPARC3: 9005 *total = COSTS_N_INSNS (1); 9006 return true; 9007 9008 case PROCESSOR_SUPERSPARC: 9009 *total = COSTS_N_INSNS (3); 9010 return true; 9011 9012 case PROCESSOR_CYPRESS: 9013 *total = COSTS_N_INSNS (5); 9014 return true; 9015 9016 case PROCESSOR_HYPERSPARC: 9017 case PROCESSOR_SPARCLITE86X: 9018 default: 9019 *total = COSTS_N_INSNS (1); 9020 return true; 9021 } 9022 } 9023 9024 /* ??? Maybe mark integer compares as zero cost on 9025 ??? all UltraSPARC processors because the result 9026 ??? can be bypassed to a branch in the same group. */ 9027 9028 *total = COSTS_N_INSNS (1); 9029 return true; 9030 9031 case MULT: 9032 if (FLOAT_MODE_P (GET_MODE (x))) 9033 { 9034 switch (sparc_cpu) 9035 { 9036 case PROCESSOR_ULTRASPARC: 9037 case PROCESSOR_ULTRASPARC3: 9038 *total = COSTS_N_INSNS (4); 9039 return true; 9040 9041 case PROCESSOR_SUPERSPARC: 9042 *total = COSTS_N_INSNS (3); 9043 return true; 9044 9045 case PROCESSOR_CYPRESS: 9046 *total = COSTS_N_INSNS (7); 9047 return true; 9048 9049 case PROCESSOR_HYPERSPARC: 9050 case PROCESSOR_SPARCLITE86X: 9051 *total = COSTS_N_INSNS (1); 9052 return true; 9053 9054 default: 9055 *total = COSTS_N_INSNS (5); 9056 return true; 9057 } 9058 } 9059 9060 /* The latency is actually variable for Ultra-I/II 9061 And if one of the inputs have a known constant 9062 value, we could calculate this precisely. 9063 9064 However, for that to be useful we would need to 9065 add some machine description changes which would 9066 make sure small constants ended up in rs1 of the 9067 multiply instruction. This is because the multiply 9068 latency is determined by the number of clear (or 9069 set if the value is negative) bits starting from 9070 the most significant bit of the first input. 9071 9072 The algorithm for computing num_cycles of a multiply 9073 on Ultra-I/II is: 9074 9075 if (rs1 < 0) 9076 highest_bit = highest_clear_bit(rs1); 9077 else 9078 highest_bit = highest_set_bit(rs1); 9079 if (num_bits < 3) 9080 highest_bit = 3; 9081 num_cycles = 4 + ((highest_bit - 3) / 2); 9082 9083 If we did that we would have to also consider register 9084 allocation issues that would result from forcing such 9085 a value into a register. 9086 9087 There are other similar tricks we could play if we 9088 knew, for example, that one input was an array index. 9089 9090 Since we do not play any such tricks currently the 9091 safest thing to do is report the worst case latency. */ 9092 if (sparc_cpu == PROCESSOR_ULTRASPARC) 9093 { 9094 *total = (GET_MODE (x) == DImode 9095 ? COSTS_N_INSNS (34) : COSTS_N_INSNS (19)); 9096 return true; 9097 } 9098 9099 /* Multiply latency on Ultra-III, fortunately, is constant. */ 9100 if (sparc_cpu == PROCESSOR_ULTRASPARC3) 9101 { 9102 *total = COSTS_N_INSNS (6); 9103 return true; 9104 } 9105 9106 if (sparc_cpu == PROCESSOR_HYPERSPARC 9107 || sparc_cpu == PROCESSOR_SPARCLITE86X) 9108 { 9109 *total = COSTS_N_INSNS (17); 9110 return true; 9111 } 9112 9113 *total = (TARGET_HARD_MUL ? COSTS_N_INSNS (5) : COSTS_N_INSNS (25)); 9114 return true; 9115 9116 case DIV: 9117 case UDIV: 9118 case MOD: 9119 case UMOD: 9120 if (FLOAT_MODE_P (GET_MODE (x))) 9121 { 9122 switch (sparc_cpu) 9123 { 9124 case PROCESSOR_ULTRASPARC: 9125 if (GET_MODE (x) == SFmode) 9126 *total = COSTS_N_INSNS (13); 9127 else 9128 *total = COSTS_N_INSNS (23); 9129 return true; 9130 9131 case PROCESSOR_ULTRASPARC3: 9132 if (GET_MODE (x) == SFmode) 9133 *total = COSTS_N_INSNS (17); 9134 else 9135 *total = COSTS_N_INSNS (20); 9136 return true; 9137 9138 case PROCESSOR_SUPERSPARC: 9139 if (GET_MODE (x) == SFmode) 9140 *total = COSTS_N_INSNS (6); 9141 else 9142 *total = COSTS_N_INSNS (9); 9143 return true; 9144 9145 case PROCESSOR_HYPERSPARC: 9146 case PROCESSOR_SPARCLITE86X: 9147 if (GET_MODE (x) == SFmode) 9148 *total = COSTS_N_INSNS (8); 9149 else 9150 *total = COSTS_N_INSNS (12); 9151 return true; 9152 9153 default: 9154 *total = COSTS_N_INSNS (7); 9155 return true; 9156 } 9157 } 9158 9159 if (sparc_cpu == PROCESSOR_ULTRASPARC) 9160 *total = (GET_MODE (x) == DImode 9161 ? COSTS_N_INSNS (68) : COSTS_N_INSNS (37)); 9162 else if (sparc_cpu == PROCESSOR_ULTRASPARC3) 9163 *total = (GET_MODE (x) == DImode 9164 ? COSTS_N_INSNS (71) : COSTS_N_INSNS (40)); 9165 else 9166 *total = COSTS_N_INSNS (25); 9167 return true; 9168 9169 case IF_THEN_ELSE: 9170 /* Conditional moves. */ 9171 switch (sparc_cpu) 9172 { 9173 case PROCESSOR_ULTRASPARC: 9174 *total = COSTS_N_INSNS (2); 9175 return true; 9176 9177 case PROCESSOR_ULTRASPARC3: 9178 if (FLOAT_MODE_P (GET_MODE (x))) 9179 *total = COSTS_N_INSNS (3); 9180 else 9181 *total = COSTS_N_INSNS (2); 9182 return true; 9183 9184 default: 9185 *total = COSTS_N_INSNS (1); 9186 return true; 9187 } 9188 9189 case MEM: 9190 /* If outer-code is SIGN/ZERO extension we have to subtract 9191 out COSTS_N_INSNS (1) from whatever we return in determining 9192 the cost. */ 9193 switch (sparc_cpu) 9194 { 9195 case PROCESSOR_ULTRASPARC: 9196 if (outer_code == ZERO_EXTEND) 9197 *total = COSTS_N_INSNS (1); 9198 else 9199 *total = COSTS_N_INSNS (2); 9200 return true; 9201 9202 case PROCESSOR_ULTRASPARC3: 9203 if (outer_code == ZERO_EXTEND) 9204 { 9205 if (GET_MODE (x) == QImode 9206 || GET_MODE (x) == HImode 9207 || outer_code == SIGN_EXTEND) 9208 *total = COSTS_N_INSNS (2); 9209 else 9210 *total = COSTS_N_INSNS (1); 9211 } 9212 else 9213 { 9214 /* This handles sign extension (3 cycles) 9215 and everything else (2 cycles). */ 9216 *total = COSTS_N_INSNS (2); 9217 } 9218 return true; 9219 9220 case PROCESSOR_SUPERSPARC: 9221 if (FLOAT_MODE_P (GET_MODE (x)) 9222 || outer_code == ZERO_EXTEND 9223 || outer_code == SIGN_EXTEND) 9224 *total = COSTS_N_INSNS (0); 9225 else 9226 *total = COSTS_N_INSNS (1); 9227 return true; 9228 9229 case PROCESSOR_TSC701: 9230 if (outer_code == ZERO_EXTEND 9231 || outer_code == SIGN_EXTEND) 9232 *total = COSTS_N_INSNS (2); 9233 else 9234 *total = COSTS_N_INSNS (3); 9235 return true; 9236 9237 case PROCESSOR_CYPRESS: 9238 if (outer_code == ZERO_EXTEND 9239 || outer_code == SIGN_EXTEND) 9240 *total = COSTS_N_INSNS (1); 9241 else 9242 *total = COSTS_N_INSNS (2); 9243 return true; 9244 9245 case PROCESSOR_HYPERSPARC: 9246 case PROCESSOR_SPARCLITE86X: 9247 default: 9248 if (outer_code == ZERO_EXTEND 9249 || outer_code == SIGN_EXTEND) 9250 *total = COSTS_N_INSNS (0); 9251 else 9252 *total = COSTS_N_INSNS (1); 9253 return true; 9254 } 9255 9256 case CONST_INT: 9257 if (INTVAL (x) < 0x1000 && INTVAL (x) >= -0x1000) 9258 { 9259 *total = 0; 9260 return true; 9261 } 9262 /* FALLTHRU */ 9263 9264 case HIGH: 9265 *total = 2; 9266 return true; 9267 9268 case CONST: 9269 case LABEL_REF: 9270 case SYMBOL_REF: 9271 *total = 4; 9272 return true; 9273 9274 case CONST_DOUBLE: 9275 if (GET_MODE (x) == DImode 9276 && ((XINT (x, 3) == 0 9277 && (unsigned HOST_WIDE_INT) XINT (x, 2) < 0x1000) 9278 || (XINT (x, 3) == -1 9279 && XINT (x, 2) < 0 9280 && XINT (x, 2) >= -0x1000))) 9281 *total = 0; 9282 else 9283 *total = 8; 9284 return true; 9285 9286 default: 9287 return false; 9288 } 9289} 9290 9291/* Output the assembler code for a thunk function. THUNK_DECL is the 9292 declaration for the thunk function itself, FUNCTION is the decl for 9293 the target function. DELTA is an immediate constant offset to be 9294 added to THIS. If VCALL_OFFSET is nonzero, the word at address 9295 (*THIS + VCALL_OFFSET) should be additionally added to THIS. */ 9296 9297static void 9298sparc_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED, 9299 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset, 9300 tree function) 9301{ 9302 rtx this, insn, funexp; 9303 9304 reload_completed = 1; 9305 epilogue_completed = 1; 9306 no_new_pseudos = 1; 9307 current_function_uses_only_leaf_regs = 1; 9308 9309 emit_note (NOTE_INSN_PROLOGUE_END); 9310 9311 /* Find the "this" pointer. Normally in %o0, but in ARCH64 if the function 9312 returns a structure, the structure return pointer is there instead. */ 9313 if (TARGET_ARCH64 && aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function)) 9314 this = gen_rtx_REG (Pmode, SPARC_INCOMING_INT_ARG_FIRST + 1); 9315 else 9316 this = gen_rtx_REG (Pmode, SPARC_INCOMING_INT_ARG_FIRST); 9317 9318 /* Add DELTA. When possible use a plain add, otherwise load it into 9319 a register first. */ 9320 if (delta) 9321 { 9322 rtx delta_rtx = GEN_INT (delta); 9323 9324 if (! SPARC_SIMM13_P (delta)) 9325 { 9326 rtx scratch = gen_rtx_REG (Pmode, 1); 9327 emit_move_insn (scratch, delta_rtx); 9328 delta_rtx = scratch; 9329 } 9330 9331 /* THIS += DELTA. */ 9332 emit_insn (gen_add2_insn (this, delta_rtx)); 9333 } 9334 9335 /* Add the word at address (*THIS + VCALL_OFFSET). */ 9336 if (vcall_offset) 9337 { 9338 rtx vcall_offset_rtx = GEN_INT (vcall_offset); 9339 rtx scratch = gen_rtx_REG (Pmode, 1); 9340 9341 if (vcall_offset >= 0) 9342 abort (); 9343 9344 /* SCRATCH = *THIS. */ 9345 emit_move_insn (scratch, gen_rtx_MEM (Pmode, this)); 9346 9347 /* Prepare for adding VCALL_OFFSET. The difficulty is that we 9348 may not have any available scratch register at this point. */ 9349 if (SPARC_SIMM13_P (vcall_offset)) 9350 ; 9351 /* This is the case if ARCH64 (unless -ffixed-g5 is passed). */ 9352 else if (! fixed_regs[5] 9353 /* The below sequence is made up of at least 2 insns, 9354 while the default method may need only one. */ 9355 && vcall_offset < -8192) 9356 { 9357 rtx scratch2 = gen_rtx_REG (Pmode, 5); 9358 emit_move_insn (scratch2, vcall_offset_rtx); 9359 vcall_offset_rtx = scratch2; 9360 } 9361 else 9362 { 9363 rtx increment = GEN_INT (-4096); 9364 9365 /* VCALL_OFFSET is a negative number whose typical range can be 9366 estimated as -32768..0 in 32-bit mode. In almost all cases 9367 it is therefore cheaper to emit multiple add insns than 9368 spilling and loading the constant into a register (at least 9369 6 insns). */ 9370 while (! SPARC_SIMM13_P (vcall_offset)) 9371 { 9372 emit_insn (gen_add2_insn (scratch, increment)); 9373 vcall_offset += 4096; 9374 } 9375 vcall_offset_rtx = GEN_INT (vcall_offset); /* cannot be 0 */ 9376 } 9377 9378 /* SCRATCH = *(*THIS + VCALL_OFFSET). */ 9379 emit_move_insn (scratch, gen_rtx_MEM (Pmode, 9380 gen_rtx_PLUS (Pmode, 9381 scratch, 9382 vcall_offset_rtx))); 9383 9384 /* THIS += *(*THIS + VCALL_OFFSET). */ 9385 emit_insn (gen_add2_insn (this, scratch)); 9386 } 9387 9388 /* Generate a tail call to the target function. */ 9389 if (! TREE_USED (function)) 9390 { 9391 assemble_external (function); 9392 TREE_USED (function) = 1; 9393 } 9394 funexp = XEXP (DECL_RTL (function), 0); 9395 funexp = gen_rtx_MEM (FUNCTION_MODE, funexp); 9396 insn = emit_call_insn (gen_sibcall (funexp)); 9397 SIBLING_CALL_P (insn) = 1; 9398 emit_barrier (); 9399 9400 /* Run just enough of rest_of_compilation to get the insns emitted. 9401 There's not really enough bulk here to make other passes such as 9402 instruction scheduling worth while. Note that use_thunk calls 9403 assemble_start_function and assemble_end_function. */ 9404 insn = get_insns (); 9405 insn_locators_initialize (); 9406 shorten_branches (insn); 9407 final_start_function (insn, file, 1); 9408 final (insn, file, 1, 0); 9409 final_end_function (); 9410 9411 reload_completed = 0; 9412 epilogue_completed = 0; 9413 no_new_pseudos = 0; 9414} 9415 9416/* Return true if sparc_output_mi_thunk would be able to output the 9417 assembler code for the thunk function specified by the arguments 9418 it is passed, and false otherwise. */ 9419static bool 9420sparc_can_output_mi_thunk (tree thunk_fndecl ATTRIBUTE_UNUSED, 9421 HOST_WIDE_INT delta ATTRIBUTE_UNUSED, 9422 HOST_WIDE_INT vcall_offset, 9423 tree function ATTRIBUTE_UNUSED) 9424{ 9425 /* Bound the loop used in the default method above. */ 9426 return (vcall_offset >= -32768 || ! fixed_regs[5]); 9427} 9428 9429/* How to allocate a 'struct machine_function'. */ 9430 9431static struct machine_function * 9432sparc_init_machine_status (void) 9433{ 9434 return ggc_alloc_cleared (sizeof (struct machine_function)); 9435} 9436 9437/* Locate some local-dynamic symbol still in use by this function 9438 so that we can print its name in local-dynamic base patterns. */ 9439 9440static const char * 9441get_some_local_dynamic_name (void) 9442{ 9443 rtx insn; 9444 9445 if (cfun->machine->some_ld_name) 9446 return cfun->machine->some_ld_name; 9447 9448 for (insn = get_insns (); insn ; insn = NEXT_INSN (insn)) 9449 if (INSN_P (insn) 9450 && for_each_rtx (&PATTERN (insn), get_some_local_dynamic_name_1, 0)) 9451 return cfun->machine->some_ld_name; 9452 9453 abort (); 9454} 9455 9456static int 9457get_some_local_dynamic_name_1 (rtx *px, void *data ATTRIBUTE_UNUSED) 9458{ 9459 rtx x = *px; 9460 9461 if (x 9462 && GET_CODE (x) == SYMBOL_REF 9463 && SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_DYNAMIC) 9464 { 9465 cfun->machine->some_ld_name = XSTR (x, 0); 9466 return 1; 9467 } 9468 9469 return 0; 9470} 9471 9472/* This is called from dwarf2out.c via ASM_OUTPUT_DWARF_DTPREL. 9473 We need to emit DTP-relative relocations. */ 9474 9475void 9476sparc_output_dwarf_dtprel (FILE *file, int size, rtx x) 9477{ 9478 switch (size) 9479 { 9480 case 4: 9481 fputs ("\t.word\t%r_tls_dtpoff32(", file); 9482 break; 9483 case 8: 9484 fputs ("\t.xword\t%r_tls_dtpoff64(", file); 9485 break; 9486 default: 9487 abort (); 9488 } 9489 output_addr_const (file, x); 9490 fputs (")", file); 9491} 9492 9493#include "gt-sparc.h" 9494