sparc.c revision 117395
1/* Subroutines for insn-output.c for Sun SPARC. 2 Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 3 1999, 2000, 2001, 2002 Free Software Foundation, Inc. 4 Contributed by Michael Tiemann (tiemann@cygnus.com) 5 64 bit SPARC V9 support by Michael Tiemann, Jim Wilson, and Doug Evans, 6 at Cygnus Support. 7 8This file is part of GNU CC. 9 10GNU CC is free software; you can redistribute it and/or modify 11it under the terms of the GNU General Public License as published by 12the Free Software Foundation; either version 2, or (at your option) 13any later version. 14 15GNU CC is distributed in the hope that it will be useful, 16but WITHOUT ANY WARRANTY; without even the implied warranty of 17MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18GNU General Public License for more details. 19 20You should have received a copy of the GNU General Public License 21along with GNU CC; see the file COPYING. If not, write to 22the Free Software Foundation, 59 Temple Place - Suite 330, 23Boston, MA 02111-1307, USA. */ 24 25#include "config.h" 26#include "system.h" 27#include "tree.h" 28#include "rtl.h" 29#include "regs.h" 30#include "hard-reg-set.h" 31#include "real.h" 32#include "insn-config.h" 33#include "conditions.h" 34#include "output.h" 35#include "insn-attr.h" 36#include "flags.h" 37#include "function.h" 38#include "expr.h" 39#include "optabs.h" 40#include "libfuncs.h" 41#include "recog.h" 42#include "toplev.h" 43#include "ggc.h" 44#include "tm_p.h" 45#include "debug.h" 46#include "target.h" 47#include "target-def.h" 48 49/* 1 if the caller has placed an "unimp" insn immediately after the call. 50 This is used in v8 code when calling a function that returns a structure. 51 v9 doesn't have this. Be careful to have this test be the same as that 52 used on the call. */ 53 54#define SKIP_CALLERS_UNIMP_P \ 55(!TARGET_ARCH64 && current_function_returns_struct \ 56 && ! integer_zerop (DECL_SIZE (DECL_RESULT (current_function_decl))) \ 57 && (TREE_CODE (DECL_SIZE (DECL_RESULT (current_function_decl))) \ 58 == INTEGER_CST)) 59 60/* Global variables for machine-dependent things. */ 61 62/* Size of frame. Need to know this to emit return insns from leaf procedures. 63 ACTUAL_FSIZE is set by compute_frame_size() which is called during the 64 reload pass. This is important as the value is later used in insn 65 scheduling (to see what can go in a delay slot). 66 APPARENT_FSIZE is the size of the stack less the register save area and less 67 the outgoing argument area. It is used when saving call preserved regs. */ 68static int apparent_fsize; 69static int actual_fsize; 70 71/* Number of live general or floating point registers needed to be 72 saved (as 4-byte quantities). */ 73static int num_gfregs; 74 75/* Save the operands last given to a compare for use when we 76 generate a scc or bcc insn. */ 77rtx sparc_compare_op0, sparc_compare_op1; 78 79/* Coordinate with the md file wrt special insns created by 80 sparc_nonflat_function_epilogue. */ 81bool sparc_emitting_epilogue; 82 83/* Vector to say how input registers are mapped to output registers. 84 HARD_FRAME_POINTER_REGNUM cannot be remapped by this function to 85 eliminate it. You must use -fomit-frame-pointer to get that. */ 86char leaf_reg_remap[] = 87{ 0, 1, 2, 3, 4, 5, 6, 7, 88 -1, -1, -1, -1, -1, -1, 14, -1, 89 -1, -1, -1, -1, -1, -1, -1, -1, 90 8, 9, 10, 11, 12, 13, -1, 15, 91 92 32, 33, 34, 35, 36, 37, 38, 39, 93 40, 41, 42, 43, 44, 45, 46, 47, 94 48, 49, 50, 51, 52, 53, 54, 55, 95 56, 57, 58, 59, 60, 61, 62, 63, 96 64, 65, 66, 67, 68, 69, 70, 71, 97 72, 73, 74, 75, 76, 77, 78, 79, 98 80, 81, 82, 83, 84, 85, 86, 87, 99 88, 89, 90, 91, 92, 93, 94, 95, 100 96, 97, 98, 99, 100}; 101 102/* Vector, indexed by hard register number, which contains 1 103 for a register that is allowable in a candidate for leaf 104 function treatment. */ 105char sparc_leaf_regs[] = 106{ 1, 1, 1, 1, 1, 1, 1, 1, 107 0, 0, 0, 0, 0, 0, 1, 0, 108 0, 0, 0, 0, 0, 0, 0, 0, 109 1, 1, 1, 1, 1, 1, 0, 1, 110 1, 1, 1, 1, 1, 1, 1, 1, 111 1, 1, 1, 1, 1, 1, 1, 1, 112 1, 1, 1, 1, 1, 1, 1, 1, 113 1, 1, 1, 1, 1, 1, 1, 1, 114 1, 1, 1, 1, 1, 1, 1, 1, 115 1, 1, 1, 1, 1, 1, 1, 1, 116 1, 1, 1, 1, 1, 1, 1, 1, 117 1, 1, 1, 1, 1, 1, 1, 1, 118 1, 1, 1, 1, 1}; 119 120/* Name of where we pretend to think the frame pointer points. 121 Normally, this is "%fp", but if we are in a leaf procedure, 122 this is "%sp+something". We record "something" separately as it may be 123 too big for reg+constant addressing. */ 124 125static const char *frame_base_name; 126static int frame_base_offset; 127 128static void sparc_init_modes PARAMS ((void)); 129static int save_regs PARAMS ((FILE *, int, int, const char *, 130 int, int, int)); 131static int restore_regs PARAMS ((FILE *, int, int, const char *, int, int)); 132static void build_big_number PARAMS ((FILE *, int, const char *)); 133static int function_arg_slotno PARAMS ((const CUMULATIVE_ARGS *, 134 enum machine_mode, tree, int, int, 135 int *, int *)); 136 137static int supersparc_adjust_cost PARAMS ((rtx, rtx, rtx, int)); 138static int hypersparc_adjust_cost PARAMS ((rtx, rtx, rtx, int)); 139 140static void sparc_output_addr_vec PARAMS ((rtx)); 141static void sparc_output_addr_diff_vec PARAMS ((rtx)); 142static void sparc_output_deferred_case_vectors PARAMS ((void)); 143static int check_return_regs PARAMS ((rtx)); 144static int epilogue_renumber PARAMS ((rtx *, int)); 145static bool sparc_assemble_integer PARAMS ((rtx, unsigned int, int)); 146static int set_extends PARAMS ((rtx)); 147static void output_restore_regs PARAMS ((FILE *, int)); 148static void sparc_output_function_prologue PARAMS ((FILE *, HOST_WIDE_INT)); 149static void sparc_output_function_epilogue PARAMS ((FILE *, HOST_WIDE_INT)); 150static void sparc_flat_function_epilogue PARAMS ((FILE *, HOST_WIDE_INT)); 151static void sparc_flat_function_prologue PARAMS ((FILE *, HOST_WIDE_INT)); 152static void sparc_nonflat_function_epilogue PARAMS ((FILE *, HOST_WIDE_INT, 153 int)); 154static void sparc_nonflat_function_prologue PARAMS ((FILE *, HOST_WIDE_INT, 155 int)); 156#ifdef OBJECT_FORMAT_ELF 157static void sparc_elf_asm_named_section PARAMS ((const char *, unsigned int)); 158#endif 159static void sparc_aout_select_section PARAMS ((tree, int, 160 unsigned HOST_WIDE_INT)) 161 ATTRIBUTE_UNUSED; 162static void sparc_aout_select_rtx_section PARAMS ((enum machine_mode, rtx, 163 unsigned HOST_WIDE_INT)) 164 ATTRIBUTE_UNUSED; 165 166static int sparc_adjust_cost PARAMS ((rtx, rtx, rtx, int)); 167static int sparc_issue_rate PARAMS ((void)); 168static void sparc_sched_init PARAMS ((FILE *, int, int)); 169static int sparc_use_dfa_pipeline_interface PARAMS ((void)); 170static int sparc_use_sched_lookahead PARAMS ((void)); 171 172static void emit_soft_tfmode_libcall PARAMS ((const char *, int, rtx *)); 173static void emit_soft_tfmode_binop PARAMS ((enum rtx_code, rtx *)); 174static void emit_soft_tfmode_unop PARAMS ((enum rtx_code, rtx *)); 175static void emit_soft_tfmode_cvt PARAMS ((enum rtx_code, rtx *)); 176static void emit_hard_tfmode_operation PARAMS ((enum rtx_code, rtx *)); 177 178static void sparc_encode_section_info PARAMS ((tree, int)); 179static void sparc_output_mi_thunk PARAMS ((FILE *, tree, HOST_WIDE_INT, 180 HOST_WIDE_INT, tree)); 181 182/* Option handling. */ 183 184/* Code model option as passed by user. */ 185const char *sparc_cmodel_string; 186/* Parsed value. */ 187enum cmodel sparc_cmodel; 188 189char sparc_hard_reg_printed[8]; 190 191struct sparc_cpu_select sparc_select[] = 192{ 193 /* switch name, tune arch */ 194 { (char *)0, "default", 1, 1 }, 195 { (char *)0, "-mcpu=", 1, 1 }, 196 { (char *)0, "-mtune=", 1, 0 }, 197 { 0, 0, 0, 0 } 198}; 199 200/* CPU type. This is set from TARGET_CPU_DEFAULT and -m{cpu,tune}=xxx. */ 201enum processor_type sparc_cpu; 202 203/* Initialize the GCC target structure. */ 204 205/* The sparc default is to use .half rather than .short for aligned 206 HI objects. Use .word instead of .long on non-ELF systems. */ 207#undef TARGET_ASM_ALIGNED_HI_OP 208#define TARGET_ASM_ALIGNED_HI_OP "\t.half\t" 209#ifndef OBJECT_FORMAT_ELF 210#undef TARGET_ASM_ALIGNED_SI_OP 211#define TARGET_ASM_ALIGNED_SI_OP "\t.word\t" 212#endif 213 214#undef TARGET_ASM_UNALIGNED_HI_OP 215#define TARGET_ASM_UNALIGNED_HI_OP "\t.uahalf\t" 216#undef TARGET_ASM_UNALIGNED_SI_OP 217#define TARGET_ASM_UNALIGNED_SI_OP "\t.uaword\t" 218#undef TARGET_ASM_UNALIGNED_DI_OP 219#define TARGET_ASM_UNALIGNED_DI_OP "\t.uaxword\t" 220 221/* The target hook has to handle DI-mode values. */ 222#undef TARGET_ASM_INTEGER 223#define TARGET_ASM_INTEGER sparc_assemble_integer 224 225#undef TARGET_ASM_FUNCTION_PROLOGUE 226#define TARGET_ASM_FUNCTION_PROLOGUE sparc_output_function_prologue 227#undef TARGET_ASM_FUNCTION_EPILOGUE 228#define TARGET_ASM_FUNCTION_EPILOGUE sparc_output_function_epilogue 229 230#undef TARGET_SCHED_ADJUST_COST 231#define TARGET_SCHED_ADJUST_COST sparc_adjust_cost 232#undef TARGET_SCHED_ISSUE_RATE 233#define TARGET_SCHED_ISSUE_RATE sparc_issue_rate 234#undef TARGET_SCHED_INIT 235#define TARGET_SCHED_INIT sparc_sched_init 236#undef TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE 237#define TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE sparc_use_dfa_pipeline_interface 238#undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD 239#define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD sparc_use_sched_lookahead 240 241#undef TARGET_ENCODE_SECTION_INFO 242#define TARGET_ENCODE_SECTION_INFO sparc_encode_section_info 243 244#undef TARGET_ASM_OUTPUT_MI_THUNK 245#define TARGET_ASM_OUTPUT_MI_THUNK sparc_output_mi_thunk 246#undef TARGET_ASM_CAN_OUTPUT_MI_THUNK 247#define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall 248 249struct gcc_target targetm = TARGET_INITIALIZER; 250 251/* Validate and override various options, and do some machine dependent 252 initialization. */ 253 254void 255sparc_override_options () 256{ 257 static struct code_model { 258 const char *const name; 259 const int value; 260 } const cmodels[] = { 261 { "32", CM_32 }, 262 { "medlow", CM_MEDLOW }, 263 { "medmid", CM_MEDMID }, 264 { "medany", CM_MEDANY }, 265 { "embmedany", CM_EMBMEDANY }, 266 { 0, 0 } 267 }; 268 const struct code_model *cmodel; 269 /* Map TARGET_CPU_DEFAULT to value for -m{arch,tune}=. */ 270 static struct cpu_default { 271 const int cpu; 272 const char *const name; 273 } const cpu_default[] = { 274 /* There must be one entry here for each TARGET_CPU value. */ 275 { TARGET_CPU_sparc, "cypress" }, 276 { TARGET_CPU_sparclet, "tsc701" }, 277 { TARGET_CPU_sparclite, "f930" }, 278 { TARGET_CPU_v8, "v8" }, 279 { TARGET_CPU_hypersparc, "hypersparc" }, 280 { TARGET_CPU_sparclite86x, "sparclite86x" }, 281 { TARGET_CPU_supersparc, "supersparc" }, 282 { TARGET_CPU_v9, "v9" }, 283 { TARGET_CPU_ultrasparc, "ultrasparc" }, 284 { TARGET_CPU_ultrasparc3, "ultrasparc3" }, 285 { 0, 0 } 286 }; 287 const struct cpu_default *def; 288 /* Table of values for -m{cpu,tune}=. */ 289 static struct cpu_table { 290 const char *const name; 291 const enum processor_type processor; 292 const int disable; 293 const int enable; 294 } const cpu_table[] = { 295 { "v7", PROCESSOR_V7, MASK_ISA, 0 }, 296 { "cypress", PROCESSOR_CYPRESS, MASK_ISA, 0 }, 297 { "v8", PROCESSOR_V8, MASK_ISA, MASK_V8 }, 298 /* TI TMS390Z55 supersparc */ 299 { "supersparc", PROCESSOR_SUPERSPARC, MASK_ISA, MASK_V8 }, 300 { "sparclite", PROCESSOR_SPARCLITE, MASK_ISA, MASK_SPARCLITE }, 301 /* The Fujitsu MB86930 is the original sparclite chip, with no fpu. 302 The Fujitsu MB86934 is the recent sparclite chip, with an fpu. */ 303 { "f930", PROCESSOR_F930, MASK_ISA|MASK_FPU, MASK_SPARCLITE }, 304 { "f934", PROCESSOR_F934, MASK_ISA, MASK_SPARCLITE|MASK_FPU }, 305 { "hypersparc", PROCESSOR_HYPERSPARC, MASK_ISA, MASK_V8|MASK_FPU }, 306 { "sparclite86x", PROCESSOR_SPARCLITE86X, MASK_ISA|MASK_FPU, 307 MASK_SPARCLITE }, 308 { "sparclet", PROCESSOR_SPARCLET, MASK_ISA, MASK_SPARCLET }, 309 /* TEMIC sparclet */ 310 { "tsc701", PROCESSOR_TSC701, MASK_ISA, MASK_SPARCLET }, 311 { "v9", PROCESSOR_V9, MASK_ISA, MASK_V9 }, 312 /* TI ultrasparc I, II, IIi */ 313 { "ultrasparc", PROCESSOR_ULTRASPARC, MASK_ISA, MASK_V9 314 /* Although insns using %y are deprecated, it is a clear win on current 315 ultrasparcs. */ 316 |MASK_DEPRECATED_V8_INSNS}, 317 /* TI ultrasparc III */ 318 /* ??? Check if %y issue still holds true in ultra3. */ 319 { "ultrasparc3", PROCESSOR_ULTRASPARC3, MASK_ISA, MASK_V9|MASK_DEPRECATED_V8_INSNS}, 320 { 0, 0, 0, 0 } 321 }; 322 const struct cpu_table *cpu; 323 const struct sparc_cpu_select *sel; 324 int fpu; 325 326#ifndef SPARC_BI_ARCH 327 /* Check for unsupported architecture size. */ 328 if (! TARGET_64BIT != DEFAULT_ARCH32_P) 329 error ("%s is not supported by this configuration", 330 DEFAULT_ARCH32_P ? "-m64" : "-m32"); 331#endif 332 333 /* We force all 64bit archs to use 128 bit long double */ 334 if (TARGET_64BIT && ! TARGET_LONG_DOUBLE_128) 335 { 336 error ("-mlong-double-64 not allowed with -m64"); 337 target_flags |= MASK_LONG_DOUBLE_128; 338 } 339 340 /* Code model selection. */ 341 sparc_cmodel = SPARC_DEFAULT_CMODEL; 342 343#ifdef SPARC_BI_ARCH 344 if (TARGET_ARCH32) 345 sparc_cmodel = CM_32; 346#endif 347 348 if (sparc_cmodel_string != NULL) 349 { 350 if (TARGET_ARCH64) 351 { 352 for (cmodel = &cmodels[0]; cmodel->name; cmodel++) 353 if (strcmp (sparc_cmodel_string, cmodel->name) == 0) 354 break; 355 if (cmodel->name == NULL) 356 error ("bad value (%s) for -mcmodel= switch", sparc_cmodel_string); 357 else 358 sparc_cmodel = cmodel->value; 359 } 360 else 361 error ("-mcmodel= is not supported on 32 bit systems"); 362 } 363 364 fpu = TARGET_FPU; /* save current -mfpu status */ 365 366 /* Set the default CPU. */ 367 for (def = &cpu_default[0]; def->name; ++def) 368 if (def->cpu == TARGET_CPU_DEFAULT) 369 break; 370 if (! def->name) 371 abort (); 372 sparc_select[0].string = def->name; 373 374 for (sel = &sparc_select[0]; sel->name; ++sel) 375 { 376 if (sel->string) 377 { 378 for (cpu = &cpu_table[0]; cpu->name; ++cpu) 379 if (! strcmp (sel->string, cpu->name)) 380 { 381 if (sel->set_tune_p) 382 sparc_cpu = cpu->processor; 383 384 if (sel->set_arch_p) 385 { 386 target_flags &= ~cpu->disable; 387 target_flags |= cpu->enable; 388 } 389 break; 390 } 391 392 if (! cpu->name) 393 error ("bad value (%s) for %s switch", sel->string, sel->name); 394 } 395 } 396 397 /* If -mfpu or -mno-fpu was explicitly used, don't override with 398 the processor default. Clear MASK_FPU_SET to avoid confusing 399 the reverse mapping from switch values to names. */ 400 if (TARGET_FPU_SET) 401 { 402 target_flags = (target_flags & ~MASK_FPU) | fpu; 403 target_flags &= ~MASK_FPU_SET; 404 } 405 406 /* Don't allow -mvis if FPU is disabled. */ 407 if (! TARGET_FPU) 408 target_flags &= ~MASK_VIS; 409 410 /* -mvis assumes UltraSPARC+, so we are sure v9 instructions 411 are available. 412 -m64 also implies v9. */ 413 if (TARGET_VIS || TARGET_ARCH64) 414 { 415 target_flags |= MASK_V9; 416 target_flags &= ~(MASK_V8 | MASK_SPARCLET | MASK_SPARCLITE); 417 } 418 419 /* Use the deprecated v8 insns for sparc64 in 32 bit mode. */ 420 if (TARGET_V9 && TARGET_ARCH32) 421 target_flags |= MASK_DEPRECATED_V8_INSNS; 422 423 /* V8PLUS requires V9, makes no sense in 64 bit mode. */ 424 if (! TARGET_V9 || TARGET_ARCH64) 425 target_flags &= ~MASK_V8PLUS; 426 427 /* Don't use stack biasing in 32 bit mode. */ 428 if (TARGET_ARCH32) 429 target_flags &= ~MASK_STACK_BIAS; 430 431 /* Supply a default value for align_functions. */ 432 if (align_functions == 0 433 && (sparc_cpu == PROCESSOR_ULTRASPARC 434 || sparc_cpu == PROCESSOR_ULTRASPARC3)) 435 align_functions = 32; 436 437 /* Validate PCC_STRUCT_RETURN. */ 438 if (flag_pcc_struct_return == DEFAULT_PCC_STRUCT_RETURN) 439 flag_pcc_struct_return = (TARGET_ARCH64 ? 0 : 1); 440 441 /* Only use .uaxword when compiling for a 64-bit target. */ 442 if (!TARGET_ARCH64) 443 targetm.asm_out.unaligned_op.di = NULL; 444 445 /* Do various machine dependent initializations. */ 446 sparc_init_modes (); 447} 448 449/* Miscellaneous utilities. */ 450 451/* Nonzero if CODE, a comparison, is suitable for use in v9 conditional move 452 or branch on register contents instructions. */ 453 454int 455v9_regcmp_p (code) 456 enum rtx_code code; 457{ 458 return (code == EQ || code == NE || code == GE || code == LT 459 || code == LE || code == GT); 460} 461 462 463/* Operand constraints. */ 464 465/* Return nonzero only if OP is a register of mode MODE, 466 or const0_rtx. */ 467 468int 469reg_or_0_operand (op, mode) 470 rtx op; 471 enum machine_mode mode; 472{ 473 if (register_operand (op, mode)) 474 return 1; 475 if (op == const0_rtx) 476 return 1; 477 if (GET_MODE (op) == VOIDmode && GET_CODE (op) == CONST_DOUBLE 478 && CONST_DOUBLE_HIGH (op) == 0 479 && CONST_DOUBLE_LOW (op) == 0) 480 return 1; 481 if (fp_zero_operand (op, mode)) 482 return 1; 483 return 0; 484} 485 486/* Return nonzero only if OP is const1_rtx. */ 487 488int 489const1_operand (op, mode) 490 rtx op; 491 enum machine_mode mode ATTRIBUTE_UNUSED; 492{ 493 return op == const1_rtx; 494} 495 496/* Nonzero if OP is a floating point value with value 0.0. */ 497 498int 499fp_zero_operand (op, mode) 500 rtx op; 501 enum machine_mode mode; 502{ 503 if (GET_MODE_CLASS (GET_MODE (op)) != MODE_FLOAT) 504 return 0; 505 return op == CONST0_RTX (mode); 506} 507 508/* Nonzero if OP is a register operand in floating point register. */ 509 510int 511fp_register_operand (op, mode) 512 rtx op; 513 enum machine_mode mode; 514{ 515 if (! register_operand (op, mode)) 516 return 0; 517 if (GET_CODE (op) == SUBREG) 518 op = SUBREG_REG (op); 519 return GET_CODE (op) == REG && SPARC_FP_REG_P (REGNO (op)); 520} 521 522/* Nonzero if OP is a floating point constant which can 523 be loaded into an integer register using a single 524 sethi instruction. */ 525 526int 527fp_sethi_p (op) 528 rtx op; 529{ 530 if (GET_CODE (op) == CONST_DOUBLE) 531 { 532 REAL_VALUE_TYPE r; 533 long i; 534 535 REAL_VALUE_FROM_CONST_DOUBLE (r, op); 536 if (REAL_VALUES_EQUAL (r, dconst0) && 537 ! REAL_VALUE_MINUS_ZERO (r)) 538 return 0; 539 REAL_VALUE_TO_TARGET_SINGLE (r, i); 540 if (SPARC_SETHI_P (i)) 541 return 1; 542 } 543 544 return 0; 545} 546 547/* Nonzero if OP is a floating point constant which can 548 be loaded into an integer register using a single 549 mov instruction. */ 550 551int 552fp_mov_p (op) 553 rtx op; 554{ 555 if (GET_CODE (op) == CONST_DOUBLE) 556 { 557 REAL_VALUE_TYPE r; 558 long i; 559 560 REAL_VALUE_FROM_CONST_DOUBLE (r, op); 561 if (REAL_VALUES_EQUAL (r, dconst0) && 562 ! REAL_VALUE_MINUS_ZERO (r)) 563 return 0; 564 REAL_VALUE_TO_TARGET_SINGLE (r, i); 565 if (SPARC_SIMM13_P (i)) 566 return 1; 567 } 568 569 return 0; 570} 571 572/* Nonzero if OP is a floating point constant which can 573 be loaded into an integer register using a high/losum 574 instruction sequence. */ 575 576int 577fp_high_losum_p (op) 578 rtx op; 579{ 580 /* The constraints calling this should only be in 581 SFmode move insns, so any constant which cannot 582 be moved using a single insn will do. */ 583 if (GET_CODE (op) == CONST_DOUBLE) 584 { 585 REAL_VALUE_TYPE r; 586 long i; 587 588 REAL_VALUE_FROM_CONST_DOUBLE (r, op); 589 if (REAL_VALUES_EQUAL (r, dconst0) && 590 ! REAL_VALUE_MINUS_ZERO (r)) 591 return 0; 592 REAL_VALUE_TO_TARGET_SINGLE (r, i); 593 if (! SPARC_SETHI_P (i) 594 && ! SPARC_SIMM13_P (i)) 595 return 1; 596 } 597 598 return 0; 599} 600 601/* Nonzero if OP is an integer register. */ 602 603int 604intreg_operand (op, mode) 605 rtx op; 606 enum machine_mode mode ATTRIBUTE_UNUSED; 607{ 608 return (register_operand (op, SImode) 609 || (TARGET_ARCH64 && register_operand (op, DImode))); 610} 611 612/* Nonzero if OP is a floating point condition code register. */ 613 614int 615fcc_reg_operand (op, mode) 616 rtx op; 617 enum machine_mode mode; 618{ 619 /* This can happen when recog is called from combine. Op may be a MEM. 620 Fail instead of calling abort in this case. */ 621 if (GET_CODE (op) != REG) 622 return 0; 623 624 if (mode != VOIDmode && mode != GET_MODE (op)) 625 return 0; 626 if (mode == VOIDmode 627 && (GET_MODE (op) != CCFPmode && GET_MODE (op) != CCFPEmode)) 628 return 0; 629 630#if 0 /* ??? ==> 1 when %fcc0-3 are pseudos first. See gen_compare_reg(). */ 631 if (reg_renumber == 0) 632 return REGNO (op) >= FIRST_PSEUDO_REGISTER; 633 return REGNO_OK_FOR_CCFP_P (REGNO (op)); 634#else 635 return (unsigned) REGNO (op) - SPARC_FIRST_V9_FCC_REG < 4; 636#endif 637} 638 639/* Nonzero if OP is a floating point condition code fcc0 register. */ 640 641int 642fcc0_reg_operand (op, mode) 643 rtx op; 644 enum machine_mode mode; 645{ 646 /* This can happen when recog is called from combine. Op may be a MEM. 647 Fail instead of calling abort in this case. */ 648 if (GET_CODE (op) != REG) 649 return 0; 650 651 if (mode != VOIDmode && mode != GET_MODE (op)) 652 return 0; 653 if (mode == VOIDmode 654 && (GET_MODE (op) != CCFPmode && GET_MODE (op) != CCFPEmode)) 655 return 0; 656 657 return REGNO (op) == SPARC_FCC_REG; 658} 659 660/* Nonzero if OP is an integer or floating point condition code register. */ 661 662int 663icc_or_fcc_reg_operand (op, mode) 664 rtx op; 665 enum machine_mode mode; 666{ 667 if (GET_CODE (op) == REG && REGNO (op) == SPARC_ICC_REG) 668 { 669 if (mode != VOIDmode && mode != GET_MODE (op)) 670 return 0; 671 if (mode == VOIDmode 672 && GET_MODE (op) != CCmode && GET_MODE (op) != CCXmode) 673 return 0; 674 return 1; 675 } 676 677 return fcc_reg_operand (op, mode); 678} 679 680/* Nonzero if OP can appear as the dest of a RESTORE insn. */ 681int 682restore_operand (op, mode) 683 rtx op; 684 enum machine_mode mode; 685{ 686 return (GET_CODE (op) == REG && GET_MODE (op) == mode 687 && (REGNO (op) < 8 || (REGNO (op) >= 24 && REGNO (op) < 32))); 688} 689 690/* Call insn on SPARC can take a PC-relative constant address, or any regular 691 memory address. */ 692 693int 694call_operand (op, mode) 695 rtx op; 696 enum machine_mode mode; 697{ 698 if (GET_CODE (op) != MEM) 699 abort (); 700 op = XEXP (op, 0); 701 return (symbolic_operand (op, mode) || memory_address_p (Pmode, op)); 702} 703 704int 705call_operand_address (op, mode) 706 rtx op; 707 enum machine_mode mode; 708{ 709 return (symbolic_operand (op, mode) || memory_address_p (Pmode, op)); 710} 711 712/* Returns 1 if OP is either a symbol reference or a sum of a symbol 713 reference and a constant. */ 714 715int 716symbolic_operand (op, mode) 717 register rtx op; 718 enum machine_mode mode; 719{ 720 enum machine_mode omode = GET_MODE (op); 721 722 if (omode != mode && omode != VOIDmode && mode != VOIDmode) 723 return 0; 724 725 switch (GET_CODE (op)) 726 { 727 case SYMBOL_REF: 728 case LABEL_REF: 729 return 1; 730 731 case CONST: 732 op = XEXP (op, 0); 733 return ((GET_CODE (XEXP (op, 0)) == SYMBOL_REF 734 || GET_CODE (XEXP (op, 0)) == LABEL_REF) 735 && GET_CODE (XEXP (op, 1)) == CONST_INT); 736 737 default: 738 return 0; 739 } 740} 741 742/* Return truth value of statement that OP is a symbolic memory 743 operand of mode MODE. */ 744 745int 746symbolic_memory_operand (op, mode) 747 rtx op; 748 enum machine_mode mode ATTRIBUTE_UNUSED; 749{ 750 if (GET_CODE (op) == SUBREG) 751 op = SUBREG_REG (op); 752 if (GET_CODE (op) != MEM) 753 return 0; 754 op = XEXP (op, 0); 755 return (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == CONST 756 || GET_CODE (op) == HIGH || GET_CODE (op) == LABEL_REF); 757} 758 759/* Return truth value of statement that OP is a LABEL_REF of mode MODE. */ 760 761int 762label_ref_operand (op, mode) 763 rtx op; 764 enum machine_mode mode; 765{ 766 if (GET_CODE (op) != LABEL_REF) 767 return 0; 768 if (GET_MODE (op) != mode) 769 return 0; 770 return 1; 771} 772 773/* Return 1 if the operand is an argument used in generating pic references 774 in either the medium/low or medium/anywhere code models of sparc64. */ 775 776int 777sp64_medium_pic_operand (op, mode) 778 rtx op; 779 enum machine_mode mode ATTRIBUTE_UNUSED; 780{ 781 /* Check for (const (minus (symbol_ref:GOT) 782 (const (minus (label) (pc))))). */ 783 if (GET_CODE (op) != CONST) 784 return 0; 785 op = XEXP (op, 0); 786 if (GET_CODE (op) != MINUS) 787 return 0; 788 if (GET_CODE (XEXP (op, 0)) != SYMBOL_REF) 789 return 0; 790 /* ??? Ensure symbol is GOT. */ 791 if (GET_CODE (XEXP (op, 1)) != CONST) 792 return 0; 793 if (GET_CODE (XEXP (XEXP (op, 1), 0)) != MINUS) 794 return 0; 795 return 1; 796} 797 798/* Return 1 if the operand is a data segment reference. This includes 799 the readonly data segment, or in other words anything but the text segment. 800 This is needed in the medium/anywhere code model on v9. These values 801 are accessed with EMBMEDANY_BASE_REG. */ 802 803int 804data_segment_operand (op, mode) 805 rtx op; 806 enum machine_mode mode ATTRIBUTE_UNUSED; 807{ 808 switch (GET_CODE (op)) 809 { 810 case SYMBOL_REF : 811 return ! SYMBOL_REF_FLAG (op); 812 case PLUS : 813 /* Assume canonical format of symbol + constant. 814 Fall through. */ 815 case CONST : 816 return data_segment_operand (XEXP (op, 0), VOIDmode); 817 default : 818 return 0; 819 } 820} 821 822/* Return 1 if the operand is a text segment reference. 823 This is needed in the medium/anywhere code model on v9. */ 824 825int 826text_segment_operand (op, mode) 827 rtx op; 828 enum machine_mode mode ATTRIBUTE_UNUSED; 829{ 830 switch (GET_CODE (op)) 831 { 832 case LABEL_REF : 833 return 1; 834 case SYMBOL_REF : 835 return SYMBOL_REF_FLAG (op); 836 case PLUS : 837 /* Assume canonical format of symbol + constant. 838 Fall through. */ 839 case CONST : 840 return text_segment_operand (XEXP (op, 0), VOIDmode); 841 default : 842 return 0; 843 } 844} 845 846/* Return 1 if the operand is either a register or a memory operand that is 847 not symbolic. */ 848 849int 850reg_or_nonsymb_mem_operand (op, mode) 851 register rtx op; 852 enum machine_mode mode; 853{ 854 if (register_operand (op, mode)) 855 return 1; 856 857 if (memory_operand (op, mode) && ! symbolic_memory_operand (op, mode)) 858 return 1; 859 860 return 0; 861} 862 863int 864splittable_symbolic_memory_operand (op, mode) 865 rtx op; 866 enum machine_mode mode ATTRIBUTE_UNUSED; 867{ 868 if (GET_CODE (op) != MEM) 869 return 0; 870 if (! symbolic_operand (XEXP (op, 0), Pmode)) 871 return 0; 872 return 1; 873} 874 875int 876splittable_immediate_memory_operand (op, mode) 877 rtx op; 878 enum machine_mode mode ATTRIBUTE_UNUSED; 879{ 880 if (GET_CODE (op) != MEM) 881 return 0; 882 if (! immediate_operand (XEXP (op, 0), Pmode)) 883 return 0; 884 return 1; 885} 886 887/* Return truth value of whether OP is EQ or NE. */ 888 889int 890eq_or_neq (op, mode) 891 rtx op; 892 enum machine_mode mode ATTRIBUTE_UNUSED; 893{ 894 return (GET_CODE (op) == EQ || GET_CODE (op) == NE); 895} 896 897/* Return 1 if this is a comparison operator, but not an EQ, NE, GEU, 898 or LTU for non-floating-point. We handle those specially. */ 899 900int 901normal_comp_operator (op, mode) 902 rtx op; 903 enum machine_mode mode ATTRIBUTE_UNUSED; 904{ 905 enum rtx_code code = GET_CODE (op); 906 907 if (GET_RTX_CLASS (code) != '<') 908 return 0; 909 910 if (GET_MODE (XEXP (op, 0)) == CCFPmode 911 || GET_MODE (XEXP (op, 0)) == CCFPEmode) 912 return 1; 913 914 return (code != NE && code != EQ && code != GEU && code != LTU); 915} 916 917/* Return 1 if this is a comparison operator. This allows the use of 918 MATCH_OPERATOR to recognize all the branch insns. */ 919 920int 921noov_compare_op (op, mode) 922 register rtx op; 923 enum machine_mode mode ATTRIBUTE_UNUSED; 924{ 925 enum rtx_code code = GET_CODE (op); 926 927 if (GET_RTX_CLASS (code) != '<') 928 return 0; 929 930 if (GET_MODE (XEXP (op, 0)) == CC_NOOVmode 931 || GET_MODE (XEXP (op, 0)) == CCX_NOOVmode) 932 /* These are the only branches which work with CC_NOOVmode. */ 933 return (code == EQ || code == NE || code == GE || code == LT); 934 return 1; 935} 936 937/* Return 1 if this is a 64-bit comparison operator. This allows the use of 938 MATCH_OPERATOR to recognize all the branch insns. */ 939 940int 941noov_compare64_op (op, mode) 942 register rtx op; 943 enum machine_mode mode ATTRIBUTE_UNUSED; 944{ 945 enum rtx_code code = GET_CODE (op); 946 947 if (! TARGET_V9) 948 return 0; 949 950 if (GET_RTX_CLASS (code) != '<') 951 return 0; 952 953 if (GET_MODE (XEXP (op, 0)) == CCX_NOOVmode) 954 /* These are the only branches which work with CCX_NOOVmode. */ 955 return (code == EQ || code == NE || code == GE || code == LT); 956 return (GET_MODE (XEXP (op, 0)) == CCXmode); 957} 958 959/* Nonzero if OP is a comparison operator suitable for use in v9 960 conditional move or branch on register contents instructions. */ 961 962int 963v9_regcmp_op (op, mode) 964 register rtx op; 965 enum machine_mode mode ATTRIBUTE_UNUSED; 966{ 967 enum rtx_code code = GET_CODE (op); 968 969 if (GET_RTX_CLASS (code) != '<') 970 return 0; 971 972 return v9_regcmp_p (code); 973} 974 975/* Return 1 if this is a SIGN_EXTEND or ZERO_EXTEND operation. */ 976 977int 978extend_op (op, mode) 979 rtx op; 980 enum machine_mode mode ATTRIBUTE_UNUSED; 981{ 982 return GET_CODE (op) == SIGN_EXTEND || GET_CODE (op) == ZERO_EXTEND; 983} 984 985/* Return nonzero if OP is an operator of mode MODE which can set 986 the condition codes explicitly. We do not include PLUS and MINUS 987 because these require CC_NOOVmode, which we handle explicitly. */ 988 989int 990cc_arithop (op, mode) 991 rtx op; 992 enum machine_mode mode ATTRIBUTE_UNUSED; 993{ 994 if (GET_CODE (op) == AND 995 || GET_CODE (op) == IOR 996 || GET_CODE (op) == XOR) 997 return 1; 998 999 return 0; 1000} 1001 1002/* Return nonzero if OP is an operator of mode MODE which can bitwise 1003 complement its second operand and set the condition codes explicitly. */ 1004 1005int 1006cc_arithopn (op, mode) 1007 rtx op; 1008 enum machine_mode mode ATTRIBUTE_UNUSED; 1009{ 1010 /* XOR is not here because combine canonicalizes (xor (not ...) ...) 1011 and (xor ... (not ...)) to (not (xor ...)). */ 1012 return (GET_CODE (op) == AND 1013 || GET_CODE (op) == IOR); 1014} 1015 1016/* Return true if OP is a register, or is a CONST_INT that can fit in a 1017 signed 13 bit immediate field. This is an acceptable SImode operand for 1018 most 3 address instructions. */ 1019 1020int 1021arith_operand (op, mode) 1022 rtx op; 1023 enum machine_mode mode; 1024{ 1025 if (register_operand (op, mode)) 1026 return 1; 1027 if (GET_CODE (op) != CONST_INT) 1028 return 0; 1029 return SMALL_INT32 (op); 1030} 1031 1032/* Return true if OP is a constant 4096 */ 1033 1034int 1035arith_4096_operand (op, mode) 1036 rtx op; 1037 enum machine_mode mode ATTRIBUTE_UNUSED; 1038{ 1039 if (GET_CODE (op) != CONST_INT) 1040 return 0; 1041 else 1042 return INTVAL (op) == 4096; 1043} 1044 1045/* Return true if OP is suitable as second operand for add/sub */ 1046 1047int 1048arith_add_operand (op, mode) 1049 rtx op; 1050 enum machine_mode mode; 1051{ 1052 return arith_operand (op, mode) || arith_4096_operand (op, mode); 1053} 1054 1055/* Return true if OP is a CONST_INT or a CONST_DOUBLE which can fit in the 1056 immediate field of OR and XOR instructions. Used for 64-bit 1057 constant formation patterns. */ 1058int 1059const64_operand (op, mode) 1060 rtx op; 1061 enum machine_mode mode ATTRIBUTE_UNUSED; 1062{ 1063 return ((GET_CODE (op) == CONST_INT 1064 && SPARC_SIMM13_P (INTVAL (op))) 1065#if HOST_BITS_PER_WIDE_INT != 64 1066 || (GET_CODE (op) == CONST_DOUBLE 1067 && SPARC_SIMM13_P (CONST_DOUBLE_LOW (op)) 1068 && (CONST_DOUBLE_HIGH (op) == 1069 ((CONST_DOUBLE_LOW (op) & 0x80000000) != 0 ? 1070 (HOST_WIDE_INT)-1 : 0))) 1071#endif 1072 ); 1073} 1074 1075/* The same, but only for sethi instructions. */ 1076int 1077const64_high_operand (op, mode) 1078 rtx op; 1079 enum machine_mode mode; 1080{ 1081 return ((GET_CODE (op) == CONST_INT 1082 && (INTVAL (op) & ~(HOST_WIDE_INT)0x3ff) != 0 1083 && SPARC_SETHI_P (INTVAL (op) & GET_MODE_MASK (mode)) 1084 ) 1085 || (GET_CODE (op) == CONST_DOUBLE 1086 && CONST_DOUBLE_HIGH (op) == 0 1087 && (CONST_DOUBLE_LOW (op) & ~(HOST_WIDE_INT)0x3ff) != 0 1088 && SPARC_SETHI_P (CONST_DOUBLE_LOW (op)))); 1089} 1090 1091/* Return true if OP is a register, or is a CONST_INT that can fit in a 1092 signed 11 bit immediate field. This is an acceptable SImode operand for 1093 the movcc instructions. */ 1094 1095int 1096arith11_operand (op, mode) 1097 rtx op; 1098 enum machine_mode mode; 1099{ 1100 return (register_operand (op, mode) 1101 || (GET_CODE (op) == CONST_INT && SPARC_SIMM11_P (INTVAL (op)))); 1102} 1103 1104/* Return true if OP is a register, or is a CONST_INT that can fit in a 1105 signed 10 bit immediate field. This is an acceptable SImode operand for 1106 the movrcc instructions. */ 1107 1108int 1109arith10_operand (op, mode) 1110 rtx op; 1111 enum machine_mode mode; 1112{ 1113 return (register_operand (op, mode) 1114 || (GET_CODE (op) == CONST_INT && SPARC_SIMM10_P (INTVAL (op)))); 1115} 1116 1117/* Return true if OP is a register, is a CONST_INT that fits in a 13 bit 1118 immediate field, or is a CONST_DOUBLE whose both parts fit in a 13 bit 1119 immediate field. 1120 v9: Return true if OP is a register, or is a CONST_INT or CONST_DOUBLE that 1121 can fit in a 13 bit immediate field. This is an acceptable DImode operand 1122 for most 3 address instructions. */ 1123 1124int 1125arith_double_operand (op, mode) 1126 rtx op; 1127 enum machine_mode mode; 1128{ 1129 return (register_operand (op, mode) 1130 || (GET_CODE (op) == CONST_INT && SMALL_INT (op)) 1131 || (! TARGET_ARCH64 1132 && GET_CODE (op) == CONST_DOUBLE 1133 && (unsigned HOST_WIDE_INT) (CONST_DOUBLE_LOW (op) + 0x1000) < 0x2000 1134 && (unsigned HOST_WIDE_INT) (CONST_DOUBLE_HIGH (op) + 0x1000) < 0x2000) 1135 || (TARGET_ARCH64 1136 && GET_CODE (op) == CONST_DOUBLE 1137 && (unsigned HOST_WIDE_INT) (CONST_DOUBLE_LOW (op) + 0x1000) < 0x2000 1138 && ((CONST_DOUBLE_HIGH (op) == -1 1139 && (CONST_DOUBLE_LOW (op) & 0x1000) == 0x1000) 1140 || (CONST_DOUBLE_HIGH (op) == 0 1141 && (CONST_DOUBLE_LOW (op) & 0x1000) == 0)))); 1142} 1143 1144/* Return true if OP is a constant 4096 for DImode on ARCH64 */ 1145 1146int 1147arith_double_4096_operand (op, mode) 1148 rtx op; 1149 enum machine_mode mode ATTRIBUTE_UNUSED; 1150{ 1151 return (TARGET_ARCH64 && 1152 ((GET_CODE (op) == CONST_INT && INTVAL (op) == 4096) || 1153 (GET_CODE (op) == CONST_DOUBLE && 1154 CONST_DOUBLE_LOW (op) == 4096 && 1155 CONST_DOUBLE_HIGH (op) == 0))); 1156} 1157 1158/* Return true if OP is suitable as second operand for add/sub in DImode */ 1159 1160int 1161arith_double_add_operand (op, mode) 1162 rtx op; 1163 enum machine_mode mode; 1164{ 1165 return arith_double_operand (op, mode) || arith_double_4096_operand (op, mode); 1166} 1167 1168/* Return true if OP is a register, or is a CONST_INT or CONST_DOUBLE that 1169 can fit in an 11 bit immediate field. This is an acceptable DImode 1170 operand for the movcc instructions. */ 1171/* ??? Replace with arith11_operand? */ 1172 1173int 1174arith11_double_operand (op, mode) 1175 rtx op; 1176 enum machine_mode mode; 1177{ 1178 return (register_operand (op, mode) 1179 || (GET_CODE (op) == CONST_DOUBLE 1180 && (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode) 1181 && (unsigned HOST_WIDE_INT) (CONST_DOUBLE_LOW (op) + 0x400) < 0x800 1182 && ((CONST_DOUBLE_HIGH (op) == -1 1183 && (CONST_DOUBLE_LOW (op) & 0x400) == 0x400) 1184 || (CONST_DOUBLE_HIGH (op) == 0 1185 && (CONST_DOUBLE_LOW (op) & 0x400) == 0))) 1186 || (GET_CODE (op) == CONST_INT 1187 && (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode) 1188 && (unsigned HOST_WIDE_INT) (INTVAL (op) + 0x400) < 0x800)); 1189} 1190 1191/* Return true if OP is a register, or is a CONST_INT or CONST_DOUBLE that 1192 can fit in an 10 bit immediate field. This is an acceptable DImode 1193 operand for the movrcc instructions. */ 1194/* ??? Replace with arith10_operand? */ 1195 1196int 1197arith10_double_operand (op, mode) 1198 rtx op; 1199 enum machine_mode mode; 1200{ 1201 return (register_operand (op, mode) 1202 || (GET_CODE (op) == CONST_DOUBLE 1203 && (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode) 1204 && (unsigned) (CONST_DOUBLE_LOW (op) + 0x200) < 0x400 1205 && ((CONST_DOUBLE_HIGH (op) == -1 1206 && (CONST_DOUBLE_LOW (op) & 0x200) == 0x200) 1207 || (CONST_DOUBLE_HIGH (op) == 0 1208 && (CONST_DOUBLE_LOW (op) & 0x200) == 0))) 1209 || (GET_CODE (op) == CONST_INT 1210 && (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode) 1211 && (unsigned HOST_WIDE_INT) (INTVAL (op) + 0x200) < 0x400)); 1212} 1213 1214/* Return truth value of whether OP is an integer which fits the 1215 range constraining immediate operands in most three-address insns, 1216 which have a 13 bit immediate field. */ 1217 1218int 1219small_int (op, mode) 1220 rtx op; 1221 enum machine_mode mode ATTRIBUTE_UNUSED; 1222{ 1223 return (GET_CODE (op) == CONST_INT && SMALL_INT (op)); 1224} 1225 1226int 1227small_int_or_double (op, mode) 1228 rtx op; 1229 enum machine_mode mode ATTRIBUTE_UNUSED; 1230{ 1231 return ((GET_CODE (op) == CONST_INT && SMALL_INT (op)) 1232 || (GET_CODE (op) == CONST_DOUBLE 1233 && CONST_DOUBLE_HIGH (op) == 0 1234 && SPARC_SIMM13_P (CONST_DOUBLE_LOW (op)))); 1235} 1236 1237/* Recognize operand values for the umul instruction. That instruction sign 1238 extends immediate values just like all other sparc instructions, but 1239 interprets the extended result as an unsigned number. */ 1240 1241int 1242uns_small_int (op, mode) 1243 rtx op; 1244 enum machine_mode mode ATTRIBUTE_UNUSED; 1245{ 1246#if HOST_BITS_PER_WIDE_INT > 32 1247 /* All allowed constants will fit a CONST_INT. */ 1248 return (GET_CODE (op) == CONST_INT 1249 && ((INTVAL (op) >= 0 && INTVAL (op) < 0x1000) 1250 || (INTVAL (op) >= 0xFFFFF000 1251 && INTVAL (op) <= 0xFFFFFFFF))); 1252#else 1253 return ((GET_CODE (op) == CONST_INT && (unsigned) INTVAL (op) < 0x1000) 1254 || (GET_CODE (op) == CONST_DOUBLE 1255 && CONST_DOUBLE_HIGH (op) == 0 1256 && (unsigned) CONST_DOUBLE_LOW (op) - 0xFFFFF000 < 0x1000)); 1257#endif 1258} 1259 1260int 1261uns_arith_operand (op, mode) 1262 rtx op; 1263 enum machine_mode mode; 1264{ 1265 return register_operand (op, mode) || uns_small_int (op, mode); 1266} 1267 1268/* Return truth value of statement that OP is a call-clobbered register. */ 1269int 1270clobbered_register (op, mode) 1271 rtx op; 1272 enum machine_mode mode ATTRIBUTE_UNUSED; 1273{ 1274 return (GET_CODE (op) == REG && call_used_regs[REGNO (op)]); 1275} 1276 1277/* Return 1 if OP is a valid operand for the source of a move insn. */ 1278 1279int 1280input_operand (op, mode) 1281 rtx op; 1282 enum machine_mode mode; 1283{ 1284 /* If both modes are non-void they must be the same. */ 1285 if (mode != VOIDmode && GET_MODE (op) != VOIDmode && mode != GET_MODE (op)) 1286 return 0; 1287 1288 /* Only a tiny bit of handling for CONSTANT_P_RTX is necessary. */ 1289 if (GET_CODE (op) == CONST && GET_CODE (XEXP (op, 0)) == CONSTANT_P_RTX) 1290 return 1; 1291 1292 /* Allow any one instruction integer constant, and all CONST_INT 1293 variants when we are working in DImode and !arch64. */ 1294 if (GET_MODE_CLASS (mode) == MODE_INT 1295 && ((GET_CODE (op) == CONST_INT 1296 && (SPARC_SETHI_P (INTVAL (op) & GET_MODE_MASK (mode)) 1297 || SPARC_SIMM13_P (INTVAL (op)) 1298 || (mode == DImode 1299 && ! TARGET_ARCH64))) 1300 || (TARGET_ARCH64 1301 && GET_CODE (op) == CONST_DOUBLE 1302 && ((CONST_DOUBLE_HIGH (op) == 0 1303 && SPARC_SETHI_P (CONST_DOUBLE_LOW (op))) 1304 || 1305#if HOST_BITS_PER_WIDE_INT == 64 1306 (CONST_DOUBLE_HIGH (op) == 0 1307 && SPARC_SIMM13_P (CONST_DOUBLE_LOW (op))) 1308#else 1309 (SPARC_SIMM13_P (CONST_DOUBLE_LOW (op)) 1310 && (((CONST_DOUBLE_LOW (op) & 0x80000000) == 0 1311 && CONST_DOUBLE_HIGH (op) == 0) 1312 || (CONST_DOUBLE_HIGH (op) == -1 1313 && CONST_DOUBLE_LOW (op) & 0x80000000) != 0)) 1314#endif 1315 )))) 1316 return 1; 1317 1318 /* If !arch64 and this is a DImode const, allow it so that 1319 the splits can be generated. */ 1320 if (! TARGET_ARCH64 1321 && mode == DImode 1322 && GET_CODE (op) == CONST_DOUBLE) 1323 return 1; 1324 1325 if (register_operand (op, mode)) 1326 return 1; 1327 1328 if (GET_MODE_CLASS (mode) == MODE_FLOAT 1329 && GET_CODE (op) == CONST_DOUBLE) 1330 return 1; 1331 1332 /* If this is a SUBREG, look inside so that we handle 1333 paradoxical ones. */ 1334 if (GET_CODE (op) == SUBREG) 1335 op = SUBREG_REG (op); 1336 1337 /* Check for valid MEM forms. */ 1338 if (GET_CODE (op) == MEM) 1339 { 1340 rtx inside = XEXP (op, 0); 1341 1342 if (GET_CODE (inside) == LO_SUM) 1343 { 1344 /* We can't allow these because all of the splits 1345 (eventually as they trickle down into DFmode 1346 splits) require offsettable memory references. */ 1347 if (! TARGET_V9 1348 && GET_MODE (op) == TFmode) 1349 return 0; 1350 1351 return (register_operand (XEXP (inside, 0), Pmode) 1352 && CONSTANT_P (XEXP (inside, 1))); 1353 } 1354 return memory_address_p (mode, inside); 1355 } 1356 1357 return 0; 1358} 1359 1360 1361/* We know it can't be done in one insn when we get here, 1362 the movsi expander guarentees this. */ 1363void 1364sparc_emit_set_const32 (op0, op1) 1365 rtx op0; 1366 rtx op1; 1367{ 1368 enum machine_mode mode = GET_MODE (op0); 1369 rtx temp; 1370 1371 if (GET_CODE (op1) == CONST_INT) 1372 { 1373 HOST_WIDE_INT value = INTVAL (op1); 1374 1375 if (SPARC_SETHI_P (value & GET_MODE_MASK (mode)) 1376 || SPARC_SIMM13_P (value)) 1377 abort (); 1378 } 1379 1380 /* Full 2-insn decomposition is needed. */ 1381 if (reload_in_progress || reload_completed) 1382 temp = op0; 1383 else 1384 temp = gen_reg_rtx (mode); 1385 1386 if (GET_CODE (op1) == CONST_INT) 1387 { 1388 /* Emit them as real moves instead of a HIGH/LO_SUM, 1389 this way CSE can see everything and reuse intermediate 1390 values if it wants. */ 1391 if (TARGET_ARCH64 1392 && HOST_BITS_PER_WIDE_INT != 64 1393 && (INTVAL (op1) & 0x80000000) != 0) 1394 emit_insn (gen_rtx_SET 1395 (VOIDmode, temp, 1396 immed_double_const (INTVAL (op1) & ~(HOST_WIDE_INT)0x3ff, 1397 0, DImode))); 1398 else 1399 emit_insn (gen_rtx_SET (VOIDmode, temp, 1400 GEN_INT (INTVAL (op1) 1401 & ~(HOST_WIDE_INT)0x3ff))); 1402 1403 emit_insn (gen_rtx_SET (VOIDmode, 1404 op0, 1405 gen_rtx_IOR (mode, temp, 1406 GEN_INT (INTVAL (op1) & 0x3ff)))); 1407 } 1408 else 1409 { 1410 /* A symbol, emit in the traditional way. */ 1411 emit_insn (gen_rtx_SET (VOIDmode, temp, 1412 gen_rtx_HIGH (mode, op1))); 1413 emit_insn (gen_rtx_SET (VOIDmode, 1414 op0, gen_rtx_LO_SUM (mode, temp, op1))); 1415 1416 } 1417} 1418 1419 1420/* SPARC-v9 code-model support. */ 1421void 1422sparc_emit_set_symbolic_const64 (op0, op1, temp1) 1423 rtx op0; 1424 rtx op1; 1425 rtx temp1; 1426{ 1427 rtx ti_temp1 = 0; 1428 1429 if (temp1 && GET_MODE (temp1) == TImode) 1430 { 1431 ti_temp1 = temp1; 1432 temp1 = gen_rtx_REG (DImode, REGNO (temp1)); 1433 } 1434 1435 switch (sparc_cmodel) 1436 { 1437 case CM_MEDLOW: 1438 /* The range spanned by all instructions in the object is less 1439 than 2^31 bytes (2GB) and the distance from any instruction 1440 to the location of the label _GLOBAL_OFFSET_TABLE_ is less 1441 than 2^31 bytes (2GB). 1442 1443 The executable must be in the low 4TB of the virtual address 1444 space. 1445 1446 sethi %hi(symbol), %temp 1447 or %temp, %lo(symbol), %reg */ 1448 emit_insn (gen_rtx_SET (VOIDmode, temp1, gen_rtx_HIGH (DImode, op1))); 1449 emit_insn (gen_rtx_SET (VOIDmode, op0, gen_rtx_LO_SUM (DImode, temp1, op1))); 1450 break; 1451 1452 case CM_MEDMID: 1453 /* The range spanned by all instructions in the object is less 1454 than 2^31 bytes (2GB) and the distance from any instruction 1455 to the location of the label _GLOBAL_OFFSET_TABLE_ is less 1456 than 2^31 bytes (2GB). 1457 1458 The executable must be in the low 16TB of the virtual address 1459 space. 1460 1461 sethi %h44(symbol), %temp1 1462 or %temp1, %m44(symbol), %temp2 1463 sllx %temp2, 12, %temp3 1464 or %temp3, %l44(symbol), %reg */ 1465 emit_insn (gen_seth44 (op0, op1)); 1466 emit_insn (gen_setm44 (op0, op0, op1)); 1467 emit_insn (gen_rtx_SET (VOIDmode, temp1, 1468 gen_rtx_ASHIFT (DImode, op0, GEN_INT (12)))); 1469 emit_insn (gen_setl44 (op0, temp1, op1)); 1470 break; 1471 1472 case CM_MEDANY: 1473 /* The range spanned by all instructions in the object is less 1474 than 2^31 bytes (2GB) and the distance from any instruction 1475 to the location of the label _GLOBAL_OFFSET_TABLE_ is less 1476 than 2^31 bytes (2GB). 1477 1478 The executable can be placed anywhere in the virtual address 1479 space. 1480 1481 sethi %hh(symbol), %temp1 1482 sethi %lm(symbol), %temp2 1483 or %temp1, %hm(symbol), %temp3 1484 or %temp2, %lo(symbol), %temp4 1485 sllx %temp3, 32, %temp5 1486 or %temp4, %temp5, %reg */ 1487 1488 /* It is possible that one of the registers we got for operands[2] 1489 might coincide with that of operands[0] (which is why we made 1490 it TImode). Pick the other one to use as our scratch. */ 1491 if (rtx_equal_p (temp1, op0)) 1492 { 1493 if (ti_temp1) 1494 temp1 = gen_rtx_REG (DImode, REGNO (temp1) + 1); 1495 else 1496 abort(); 1497 } 1498 1499 emit_insn (gen_sethh (op0, op1)); 1500 emit_insn (gen_setlm (temp1, op1)); 1501 emit_insn (gen_sethm (op0, op0, op1)); 1502 emit_insn (gen_rtx_SET (VOIDmode, op0, 1503 gen_rtx_ASHIFT (DImode, op0, GEN_INT (32)))); 1504 emit_insn (gen_rtx_SET (VOIDmode, op0, 1505 gen_rtx_PLUS (DImode, op0, temp1))); 1506 emit_insn (gen_setlo (op0, op0, op1)); 1507 break; 1508 1509 case CM_EMBMEDANY: 1510 /* Old old old backwards compatibility kruft here. 1511 Essentially it is MEDLOW with a fixed 64-bit 1512 virtual base added to all data segment addresses. 1513 Text-segment stuff is computed like MEDANY, we can't 1514 reuse the code above because the relocation knobs 1515 look different. 1516 1517 Data segment: sethi %hi(symbol), %temp1 1518 or %temp1, %lo(symbol), %temp2 1519 add %temp2, EMBMEDANY_BASE_REG, %reg 1520 1521 Text segment: sethi %uhi(symbol), %temp1 1522 sethi %hi(symbol), %temp2 1523 or %temp1, %ulo(symbol), %temp3 1524 or %temp2, %lo(symbol), %temp4 1525 sllx %temp3, 32, %temp5 1526 or %temp4, %temp5, %reg */ 1527 if (data_segment_operand (op1, GET_MODE (op1))) 1528 { 1529 emit_insn (gen_embmedany_sethi (temp1, op1)); 1530 emit_insn (gen_embmedany_brsum (op0, temp1)); 1531 emit_insn (gen_embmedany_losum (op0, op0, op1)); 1532 } 1533 else 1534 { 1535 /* It is possible that one of the registers we got for operands[2] 1536 might coincide with that of operands[0] (which is why we made 1537 it TImode). Pick the other one to use as our scratch. */ 1538 if (rtx_equal_p (temp1, op0)) 1539 { 1540 if (ti_temp1) 1541 temp1 = gen_rtx_REG (DImode, REGNO (temp1) + 1); 1542 else 1543 abort(); 1544 } 1545 1546 emit_insn (gen_embmedany_textuhi (op0, op1)); 1547 emit_insn (gen_embmedany_texthi (temp1, op1)); 1548 emit_insn (gen_embmedany_textulo (op0, op0, op1)); 1549 emit_insn (gen_rtx_SET (VOIDmode, op0, 1550 gen_rtx_ASHIFT (DImode, op0, GEN_INT (32)))); 1551 emit_insn (gen_rtx_SET (VOIDmode, op0, 1552 gen_rtx_PLUS (DImode, op0, temp1))); 1553 emit_insn (gen_embmedany_textlo (op0, op0, op1)); 1554 } 1555 break; 1556 1557 default: 1558 abort(); 1559 } 1560} 1561 1562/* These avoid problems when cross compiling. If we do not 1563 go through all this hair then the optimizer will see 1564 invalid REG_EQUAL notes or in some cases none at all. */ 1565static void sparc_emit_set_safe_HIGH64 PARAMS ((rtx, HOST_WIDE_INT)); 1566static rtx gen_safe_SET64 PARAMS ((rtx, HOST_WIDE_INT)); 1567static rtx gen_safe_OR64 PARAMS ((rtx, HOST_WIDE_INT)); 1568static rtx gen_safe_XOR64 PARAMS ((rtx, HOST_WIDE_INT)); 1569 1570#if HOST_BITS_PER_WIDE_INT == 64 1571#define GEN_HIGHINT64(__x) GEN_INT ((__x) & ~(HOST_WIDE_INT)0x3ff) 1572#define GEN_INT64(__x) GEN_INT (__x) 1573#else 1574#define GEN_HIGHINT64(__x) \ 1575 immed_double_const ((__x) & ~(HOST_WIDE_INT)0x3ff, 0, DImode) 1576#define GEN_INT64(__x) \ 1577 immed_double_const ((__x) & 0xffffffff, \ 1578 ((__x) & 0x80000000 ? -1 : 0), DImode) 1579#endif 1580 1581/* The optimizer is not to assume anything about exactly 1582 which bits are set for a HIGH, they are unspecified. 1583 Unfortunately this leads to many missed optimizations 1584 during CSE. We mask out the non-HIGH bits, and matches 1585 a plain movdi, to alleviate this problem. */ 1586static void 1587sparc_emit_set_safe_HIGH64 (dest, val) 1588 rtx dest; 1589 HOST_WIDE_INT val; 1590{ 1591 emit_insn (gen_rtx_SET (VOIDmode, dest, GEN_HIGHINT64 (val))); 1592} 1593 1594static rtx 1595gen_safe_SET64 (dest, val) 1596 rtx dest; 1597 HOST_WIDE_INT val; 1598{ 1599 return gen_rtx_SET (VOIDmode, dest, GEN_INT64 (val)); 1600} 1601 1602static rtx 1603gen_safe_OR64 (src, val) 1604 rtx src; 1605 HOST_WIDE_INT val; 1606{ 1607 return gen_rtx_IOR (DImode, src, GEN_INT64 (val)); 1608} 1609 1610static rtx 1611gen_safe_XOR64 (src, val) 1612 rtx src; 1613 HOST_WIDE_INT val; 1614{ 1615 return gen_rtx_XOR (DImode, src, GEN_INT64 (val)); 1616} 1617 1618/* Worker routines for 64-bit constant formation on arch64. 1619 One of the key things to be doing in these emissions is 1620 to create as many temp REGs as possible. This makes it 1621 possible for half-built constants to be used later when 1622 such values are similar to something required later on. 1623 Without doing this, the optimizer cannot see such 1624 opportunities. */ 1625 1626static void sparc_emit_set_const64_quick1 1627 PARAMS ((rtx, rtx, unsigned HOST_WIDE_INT, int)); 1628 1629static void 1630sparc_emit_set_const64_quick1 (op0, temp, low_bits, is_neg) 1631 rtx op0; 1632 rtx temp; 1633 unsigned HOST_WIDE_INT low_bits; 1634 int is_neg; 1635{ 1636 unsigned HOST_WIDE_INT high_bits; 1637 1638 if (is_neg) 1639 high_bits = (~low_bits) & 0xffffffff; 1640 else 1641 high_bits = low_bits; 1642 1643 sparc_emit_set_safe_HIGH64 (temp, high_bits); 1644 if (!is_neg) 1645 { 1646 emit_insn (gen_rtx_SET (VOIDmode, op0, 1647 gen_safe_OR64 (temp, (high_bits & 0x3ff)))); 1648 } 1649 else 1650 { 1651 /* If we are XOR'ing with -1, then we should emit a one's complement 1652 instead. This way the combiner will notice logical operations 1653 such as ANDN later on and substitute. */ 1654 if ((low_bits & 0x3ff) == 0x3ff) 1655 { 1656 emit_insn (gen_rtx_SET (VOIDmode, op0, 1657 gen_rtx_NOT (DImode, temp))); 1658 } 1659 else 1660 { 1661 emit_insn (gen_rtx_SET (VOIDmode, op0, 1662 gen_safe_XOR64 (temp, 1663 (-(HOST_WIDE_INT)0x400 1664 | (low_bits & 0x3ff))))); 1665 } 1666 } 1667} 1668 1669static void sparc_emit_set_const64_quick2 1670 PARAMS ((rtx, rtx, unsigned HOST_WIDE_INT, 1671 unsigned HOST_WIDE_INT, int)); 1672 1673static void 1674sparc_emit_set_const64_quick2 (op0, temp, high_bits, low_immediate, shift_count) 1675 rtx op0; 1676 rtx temp; 1677 unsigned HOST_WIDE_INT high_bits; 1678 unsigned HOST_WIDE_INT low_immediate; 1679 int shift_count; 1680{ 1681 rtx temp2 = op0; 1682 1683 if ((high_bits & 0xfffffc00) != 0) 1684 { 1685 sparc_emit_set_safe_HIGH64 (temp, high_bits); 1686 if ((high_bits & ~0xfffffc00) != 0) 1687 emit_insn (gen_rtx_SET (VOIDmode, op0, 1688 gen_safe_OR64 (temp, (high_bits & 0x3ff)))); 1689 else 1690 temp2 = temp; 1691 } 1692 else 1693 { 1694 emit_insn (gen_safe_SET64 (temp, high_bits)); 1695 temp2 = temp; 1696 } 1697 1698 /* Now shift it up into place. */ 1699 emit_insn (gen_rtx_SET (VOIDmode, op0, 1700 gen_rtx_ASHIFT (DImode, temp2, 1701 GEN_INT (shift_count)))); 1702 1703 /* If there is a low immediate part piece, finish up by 1704 putting that in as well. */ 1705 if (low_immediate != 0) 1706 emit_insn (gen_rtx_SET (VOIDmode, op0, 1707 gen_safe_OR64 (op0, low_immediate))); 1708} 1709 1710static void sparc_emit_set_const64_longway 1711 PARAMS ((rtx, rtx, unsigned HOST_WIDE_INT, unsigned HOST_WIDE_INT)); 1712 1713/* Full 64-bit constant decomposition. Even though this is the 1714 'worst' case, we still optimize a few things away. */ 1715static void 1716sparc_emit_set_const64_longway (op0, temp, high_bits, low_bits) 1717 rtx op0; 1718 rtx temp; 1719 unsigned HOST_WIDE_INT high_bits; 1720 unsigned HOST_WIDE_INT low_bits; 1721{ 1722 rtx sub_temp; 1723 1724 if (reload_in_progress || reload_completed) 1725 sub_temp = op0; 1726 else 1727 sub_temp = gen_reg_rtx (DImode); 1728 1729 if ((high_bits & 0xfffffc00) != 0) 1730 { 1731 sparc_emit_set_safe_HIGH64 (temp, high_bits); 1732 if ((high_bits & ~0xfffffc00) != 0) 1733 emit_insn (gen_rtx_SET (VOIDmode, 1734 sub_temp, 1735 gen_safe_OR64 (temp, (high_bits & 0x3ff)))); 1736 else 1737 sub_temp = temp; 1738 } 1739 else 1740 { 1741 emit_insn (gen_safe_SET64 (temp, high_bits)); 1742 sub_temp = temp; 1743 } 1744 1745 if (!reload_in_progress && !reload_completed) 1746 { 1747 rtx temp2 = gen_reg_rtx (DImode); 1748 rtx temp3 = gen_reg_rtx (DImode); 1749 rtx temp4 = gen_reg_rtx (DImode); 1750 1751 emit_insn (gen_rtx_SET (VOIDmode, temp4, 1752 gen_rtx_ASHIFT (DImode, sub_temp, 1753 GEN_INT (32)))); 1754 1755 sparc_emit_set_safe_HIGH64 (temp2, low_bits); 1756 if ((low_bits & ~0xfffffc00) != 0) 1757 { 1758 emit_insn (gen_rtx_SET (VOIDmode, temp3, 1759 gen_safe_OR64 (temp2, (low_bits & 0x3ff)))); 1760 emit_insn (gen_rtx_SET (VOIDmode, op0, 1761 gen_rtx_PLUS (DImode, temp4, temp3))); 1762 } 1763 else 1764 { 1765 emit_insn (gen_rtx_SET (VOIDmode, op0, 1766 gen_rtx_PLUS (DImode, temp4, temp2))); 1767 } 1768 } 1769 else 1770 { 1771 rtx low1 = GEN_INT ((low_bits >> (32 - 12)) & 0xfff); 1772 rtx low2 = GEN_INT ((low_bits >> (32 - 12 - 12)) & 0xfff); 1773 rtx low3 = GEN_INT ((low_bits >> (32 - 12 - 12 - 8)) & 0x0ff); 1774 int to_shift = 12; 1775 1776 /* We are in the middle of reload, so this is really 1777 painful. However we do still make an attempt to 1778 avoid emitting truly stupid code. */ 1779 if (low1 != const0_rtx) 1780 { 1781 emit_insn (gen_rtx_SET (VOIDmode, op0, 1782 gen_rtx_ASHIFT (DImode, sub_temp, 1783 GEN_INT (to_shift)))); 1784 emit_insn (gen_rtx_SET (VOIDmode, op0, 1785 gen_rtx_IOR (DImode, op0, low1))); 1786 sub_temp = op0; 1787 to_shift = 12; 1788 } 1789 else 1790 { 1791 to_shift += 12; 1792 } 1793 if (low2 != const0_rtx) 1794 { 1795 emit_insn (gen_rtx_SET (VOIDmode, op0, 1796 gen_rtx_ASHIFT (DImode, sub_temp, 1797 GEN_INT (to_shift)))); 1798 emit_insn (gen_rtx_SET (VOIDmode, op0, 1799 gen_rtx_IOR (DImode, op0, low2))); 1800 sub_temp = op0; 1801 to_shift = 8; 1802 } 1803 else 1804 { 1805 to_shift += 8; 1806 } 1807 emit_insn (gen_rtx_SET (VOIDmode, op0, 1808 gen_rtx_ASHIFT (DImode, sub_temp, 1809 GEN_INT (to_shift)))); 1810 if (low3 != const0_rtx) 1811 emit_insn (gen_rtx_SET (VOIDmode, op0, 1812 gen_rtx_IOR (DImode, op0, low3))); 1813 /* phew... */ 1814 } 1815} 1816 1817/* Analyze a 64-bit constant for certain properties. */ 1818static void analyze_64bit_constant 1819 PARAMS ((unsigned HOST_WIDE_INT, 1820 unsigned HOST_WIDE_INT, 1821 int *, int *, int *)); 1822 1823static void 1824analyze_64bit_constant (high_bits, low_bits, hbsp, lbsp, abbasp) 1825 unsigned HOST_WIDE_INT high_bits, low_bits; 1826 int *hbsp, *lbsp, *abbasp; 1827{ 1828 int lowest_bit_set, highest_bit_set, all_bits_between_are_set; 1829 int i; 1830 1831 lowest_bit_set = highest_bit_set = -1; 1832 i = 0; 1833 do 1834 { 1835 if ((lowest_bit_set == -1) 1836 && ((low_bits >> i) & 1)) 1837 lowest_bit_set = i; 1838 if ((highest_bit_set == -1) 1839 && ((high_bits >> (32 - i - 1)) & 1)) 1840 highest_bit_set = (64 - i - 1); 1841 } 1842 while (++i < 32 1843 && ((highest_bit_set == -1) 1844 || (lowest_bit_set == -1))); 1845 if (i == 32) 1846 { 1847 i = 0; 1848 do 1849 { 1850 if ((lowest_bit_set == -1) 1851 && ((high_bits >> i) & 1)) 1852 lowest_bit_set = i + 32; 1853 if ((highest_bit_set == -1) 1854 && ((low_bits >> (32 - i - 1)) & 1)) 1855 highest_bit_set = 32 - i - 1; 1856 } 1857 while (++i < 32 1858 && ((highest_bit_set == -1) 1859 || (lowest_bit_set == -1))); 1860 } 1861 /* If there are no bits set this should have gone out 1862 as one instruction! */ 1863 if (lowest_bit_set == -1 1864 || highest_bit_set == -1) 1865 abort (); 1866 all_bits_between_are_set = 1; 1867 for (i = lowest_bit_set; i <= highest_bit_set; i++) 1868 { 1869 if (i < 32) 1870 { 1871 if ((low_bits & (1 << i)) != 0) 1872 continue; 1873 } 1874 else 1875 { 1876 if ((high_bits & (1 << (i - 32))) != 0) 1877 continue; 1878 } 1879 all_bits_between_are_set = 0; 1880 break; 1881 } 1882 *hbsp = highest_bit_set; 1883 *lbsp = lowest_bit_set; 1884 *abbasp = all_bits_between_are_set; 1885} 1886 1887static int const64_is_2insns 1888 PARAMS ((unsigned HOST_WIDE_INT, unsigned HOST_WIDE_INT)); 1889 1890static int 1891const64_is_2insns (high_bits, low_bits) 1892 unsigned HOST_WIDE_INT high_bits, low_bits; 1893{ 1894 int highest_bit_set, lowest_bit_set, all_bits_between_are_set; 1895 1896 if (high_bits == 0 1897 || high_bits == 0xffffffff) 1898 return 1; 1899 1900 analyze_64bit_constant (high_bits, low_bits, 1901 &highest_bit_set, &lowest_bit_set, 1902 &all_bits_between_are_set); 1903 1904 if ((highest_bit_set == 63 1905 || lowest_bit_set == 0) 1906 && all_bits_between_are_set != 0) 1907 return 1; 1908 1909 if ((highest_bit_set - lowest_bit_set) < 21) 1910 return 1; 1911 1912 return 0; 1913} 1914 1915static unsigned HOST_WIDE_INT create_simple_focus_bits 1916 PARAMS ((unsigned HOST_WIDE_INT, unsigned HOST_WIDE_INT, 1917 int, int)); 1918 1919static unsigned HOST_WIDE_INT 1920create_simple_focus_bits (high_bits, low_bits, lowest_bit_set, shift) 1921 unsigned HOST_WIDE_INT high_bits, low_bits; 1922 int lowest_bit_set, shift; 1923{ 1924 HOST_WIDE_INT hi, lo; 1925 1926 if (lowest_bit_set < 32) 1927 { 1928 lo = (low_bits >> lowest_bit_set) << shift; 1929 hi = ((high_bits << (32 - lowest_bit_set)) << shift); 1930 } 1931 else 1932 { 1933 lo = 0; 1934 hi = ((high_bits >> (lowest_bit_set - 32)) << shift); 1935 } 1936 if (hi & lo) 1937 abort (); 1938 return (hi | lo); 1939} 1940 1941/* Here we are sure to be arch64 and this is an integer constant 1942 being loaded into a register. Emit the most efficient 1943 insn sequence possible. Detection of all the 1-insn cases 1944 has been done already. */ 1945void 1946sparc_emit_set_const64 (op0, op1) 1947 rtx op0; 1948 rtx op1; 1949{ 1950 unsigned HOST_WIDE_INT high_bits, low_bits; 1951 int lowest_bit_set, highest_bit_set; 1952 int all_bits_between_are_set; 1953 rtx temp; 1954 1955 /* Sanity check that we know what we are working with. */ 1956 if (! TARGET_ARCH64) 1957 abort (); 1958 1959 if (GET_CODE (op0) != SUBREG) 1960 { 1961 if (GET_CODE (op0) != REG 1962 || (REGNO (op0) >= SPARC_FIRST_FP_REG 1963 && REGNO (op0) <= SPARC_LAST_V9_FP_REG)) 1964 abort (); 1965 } 1966 1967 if (reload_in_progress || reload_completed) 1968 temp = op0; 1969 else 1970 temp = gen_reg_rtx (DImode); 1971 1972 if (GET_CODE (op1) != CONST_DOUBLE 1973 && GET_CODE (op1) != CONST_INT) 1974 { 1975 sparc_emit_set_symbolic_const64 (op0, op1, temp); 1976 return; 1977 } 1978 1979 if (GET_CODE (op1) == CONST_DOUBLE) 1980 { 1981#if HOST_BITS_PER_WIDE_INT == 64 1982 high_bits = (CONST_DOUBLE_LOW (op1) >> 32) & 0xffffffff; 1983 low_bits = CONST_DOUBLE_LOW (op1) & 0xffffffff; 1984#else 1985 high_bits = CONST_DOUBLE_HIGH (op1); 1986 low_bits = CONST_DOUBLE_LOW (op1); 1987#endif 1988 } 1989 else 1990 { 1991#if HOST_BITS_PER_WIDE_INT == 64 1992 high_bits = ((INTVAL (op1) >> 32) & 0xffffffff); 1993 low_bits = (INTVAL (op1) & 0xffffffff); 1994#else 1995 high_bits = ((INTVAL (op1) < 0) ? 1996 0xffffffff : 1997 0x00000000); 1998 low_bits = INTVAL (op1); 1999#endif 2000 } 2001 2002 /* low_bits bits 0 --> 31 2003 high_bits bits 32 --> 63 */ 2004 2005 analyze_64bit_constant (high_bits, low_bits, 2006 &highest_bit_set, &lowest_bit_set, 2007 &all_bits_between_are_set); 2008 2009 /* First try for a 2-insn sequence. */ 2010 2011 /* These situations are preferred because the optimizer can 2012 * do more things with them: 2013 * 1) mov -1, %reg 2014 * sllx %reg, shift, %reg 2015 * 2) mov -1, %reg 2016 * srlx %reg, shift, %reg 2017 * 3) mov some_small_const, %reg 2018 * sllx %reg, shift, %reg 2019 */ 2020 if (((highest_bit_set == 63 2021 || lowest_bit_set == 0) 2022 && all_bits_between_are_set != 0) 2023 || ((highest_bit_set - lowest_bit_set) < 12)) 2024 { 2025 HOST_WIDE_INT the_const = -1; 2026 int shift = lowest_bit_set; 2027 2028 if ((highest_bit_set != 63 2029 && lowest_bit_set != 0) 2030 || all_bits_between_are_set == 0) 2031 { 2032 the_const = 2033 create_simple_focus_bits (high_bits, low_bits, 2034 lowest_bit_set, 0); 2035 } 2036 else if (lowest_bit_set == 0) 2037 shift = -(63 - highest_bit_set); 2038 2039 if (! SPARC_SIMM13_P (the_const)) 2040 abort (); 2041 2042 emit_insn (gen_safe_SET64 (temp, the_const)); 2043 if (shift > 0) 2044 emit_insn (gen_rtx_SET (VOIDmode, 2045 op0, 2046 gen_rtx_ASHIFT (DImode, 2047 temp, 2048 GEN_INT (shift)))); 2049 else if (shift < 0) 2050 emit_insn (gen_rtx_SET (VOIDmode, 2051 op0, 2052 gen_rtx_LSHIFTRT (DImode, 2053 temp, 2054 GEN_INT (-shift)))); 2055 else 2056 abort (); 2057 return; 2058 } 2059 2060 /* Now a range of 22 or less bits set somewhere. 2061 * 1) sethi %hi(focus_bits), %reg 2062 * sllx %reg, shift, %reg 2063 * 2) sethi %hi(focus_bits), %reg 2064 * srlx %reg, shift, %reg 2065 */ 2066 if ((highest_bit_set - lowest_bit_set) < 21) 2067 { 2068 unsigned HOST_WIDE_INT focus_bits = 2069 create_simple_focus_bits (high_bits, low_bits, 2070 lowest_bit_set, 10); 2071 2072 if (! SPARC_SETHI_P (focus_bits)) 2073 abort (); 2074 2075 sparc_emit_set_safe_HIGH64 (temp, focus_bits); 2076 2077 /* If lowest_bit_set == 10 then a sethi alone could have done it. */ 2078 if (lowest_bit_set < 10) 2079 emit_insn (gen_rtx_SET (VOIDmode, 2080 op0, 2081 gen_rtx_LSHIFTRT (DImode, temp, 2082 GEN_INT (10 - lowest_bit_set)))); 2083 else if (lowest_bit_set > 10) 2084 emit_insn (gen_rtx_SET (VOIDmode, 2085 op0, 2086 gen_rtx_ASHIFT (DImode, temp, 2087 GEN_INT (lowest_bit_set - 10)))); 2088 else 2089 abort (); 2090 return; 2091 } 2092 2093 /* 1) sethi %hi(low_bits), %reg 2094 * or %reg, %lo(low_bits), %reg 2095 * 2) sethi %hi(~low_bits), %reg 2096 * xor %reg, %lo(-0x400 | (low_bits & 0x3ff)), %reg 2097 */ 2098 if (high_bits == 0 2099 || high_bits == 0xffffffff) 2100 { 2101 sparc_emit_set_const64_quick1 (op0, temp, low_bits, 2102 (high_bits == 0xffffffff)); 2103 return; 2104 } 2105 2106 /* Now, try 3-insn sequences. */ 2107 2108 /* 1) sethi %hi(high_bits), %reg 2109 * or %reg, %lo(high_bits), %reg 2110 * sllx %reg, 32, %reg 2111 */ 2112 if (low_bits == 0) 2113 { 2114 sparc_emit_set_const64_quick2 (op0, temp, high_bits, 0, 32); 2115 return; 2116 } 2117 2118 /* We may be able to do something quick 2119 when the constant is negated, so try that. */ 2120 if (const64_is_2insns ((~high_bits) & 0xffffffff, 2121 (~low_bits) & 0xfffffc00)) 2122 { 2123 /* NOTE: The trailing bits get XOR'd so we need the 2124 non-negated bits, not the negated ones. */ 2125 unsigned HOST_WIDE_INT trailing_bits = low_bits & 0x3ff; 2126 2127 if ((((~high_bits) & 0xffffffff) == 0 2128 && ((~low_bits) & 0x80000000) == 0) 2129 || (((~high_bits) & 0xffffffff) == 0xffffffff 2130 && ((~low_bits) & 0x80000000) != 0)) 2131 { 2132 int fast_int = (~low_bits & 0xffffffff); 2133 2134 if ((SPARC_SETHI_P (fast_int) 2135 && (~high_bits & 0xffffffff) == 0) 2136 || SPARC_SIMM13_P (fast_int)) 2137 emit_insn (gen_safe_SET64 (temp, fast_int)); 2138 else 2139 sparc_emit_set_const64 (temp, GEN_INT64 (fast_int)); 2140 } 2141 else 2142 { 2143 rtx negated_const; 2144#if HOST_BITS_PER_WIDE_INT == 64 2145 negated_const = GEN_INT (((~low_bits) & 0xfffffc00) | 2146 (((HOST_WIDE_INT)((~high_bits) & 0xffffffff))<<32)); 2147#else 2148 negated_const = immed_double_const ((~low_bits) & 0xfffffc00, 2149 (~high_bits) & 0xffffffff, 2150 DImode); 2151#endif 2152 sparc_emit_set_const64 (temp, negated_const); 2153 } 2154 2155 /* If we are XOR'ing with -1, then we should emit a one's complement 2156 instead. This way the combiner will notice logical operations 2157 such as ANDN later on and substitute. */ 2158 if (trailing_bits == 0x3ff) 2159 { 2160 emit_insn (gen_rtx_SET (VOIDmode, op0, 2161 gen_rtx_NOT (DImode, temp))); 2162 } 2163 else 2164 { 2165 emit_insn (gen_rtx_SET (VOIDmode, 2166 op0, 2167 gen_safe_XOR64 (temp, 2168 (-0x400 | trailing_bits)))); 2169 } 2170 return; 2171 } 2172 2173 /* 1) sethi %hi(xxx), %reg 2174 * or %reg, %lo(xxx), %reg 2175 * sllx %reg, yyy, %reg 2176 * 2177 * ??? This is just a generalized version of the low_bits==0 2178 * thing above, FIXME... 2179 */ 2180 if ((highest_bit_set - lowest_bit_set) < 32) 2181 { 2182 unsigned HOST_WIDE_INT focus_bits = 2183 create_simple_focus_bits (high_bits, low_bits, 2184 lowest_bit_set, 0); 2185 2186 /* We can't get here in this state. */ 2187 if (highest_bit_set < 32 2188 || lowest_bit_set >= 32) 2189 abort (); 2190 2191 /* So what we know is that the set bits straddle the 2192 middle of the 64-bit word. */ 2193 sparc_emit_set_const64_quick2 (op0, temp, 2194 focus_bits, 0, 2195 lowest_bit_set); 2196 return; 2197 } 2198 2199 /* 1) sethi %hi(high_bits), %reg 2200 * or %reg, %lo(high_bits), %reg 2201 * sllx %reg, 32, %reg 2202 * or %reg, low_bits, %reg 2203 */ 2204 if (SPARC_SIMM13_P(low_bits) 2205 && ((int)low_bits > 0)) 2206 { 2207 sparc_emit_set_const64_quick2 (op0, temp, high_bits, low_bits, 32); 2208 return; 2209 } 2210 2211 /* The easiest way when all else fails, is full decomposition. */ 2212#if 0 2213 printf ("sparc_emit_set_const64: Hard constant [%08lx%08lx] neg[%08lx%08lx]\n", 2214 high_bits, low_bits, ~high_bits, ~low_bits); 2215#endif 2216 sparc_emit_set_const64_longway (op0, temp, high_bits, low_bits); 2217} 2218 2219/* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE, 2220 return the mode to be used for the comparison. For floating-point, 2221 CCFP[E]mode is used. CC_NOOVmode should be used when the first operand 2222 is a PLUS, MINUS, NEG, or ASHIFT. CCmode should be used when no special 2223 processing is needed. */ 2224 2225enum machine_mode 2226select_cc_mode (op, x, y) 2227 enum rtx_code op; 2228 rtx x; 2229 rtx y ATTRIBUTE_UNUSED; 2230{ 2231 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT) 2232 { 2233 switch (op) 2234 { 2235 case EQ: 2236 case NE: 2237 case UNORDERED: 2238 case ORDERED: 2239 case UNLT: 2240 case UNLE: 2241 case UNGT: 2242 case UNGE: 2243 case UNEQ: 2244 case LTGT: 2245 return CCFPmode; 2246 2247 case LT: 2248 case LE: 2249 case GT: 2250 case GE: 2251 return CCFPEmode; 2252 2253 default: 2254 abort (); 2255 } 2256 } 2257 else if (GET_CODE (x) == PLUS || GET_CODE (x) == MINUS 2258 || GET_CODE (x) == NEG || GET_CODE (x) == ASHIFT) 2259 { 2260 if (TARGET_ARCH64 && GET_MODE (x) == DImode) 2261 return CCX_NOOVmode; 2262 else 2263 return CC_NOOVmode; 2264 } 2265 else 2266 { 2267 if (TARGET_ARCH64 && GET_MODE (x) == DImode) 2268 return CCXmode; 2269 else 2270 return CCmode; 2271 } 2272} 2273 2274/* X and Y are two things to compare using CODE. Emit the compare insn and 2275 return the rtx for the cc reg in the proper mode. */ 2276 2277rtx 2278gen_compare_reg (code, x, y) 2279 enum rtx_code code; 2280 rtx x, y; 2281{ 2282 enum machine_mode mode = SELECT_CC_MODE (code, x, y); 2283 rtx cc_reg; 2284 2285 /* ??? We don't have movcc patterns so we cannot generate pseudo regs for the 2286 fcc regs (cse can't tell they're really call clobbered regs and will 2287 remove a duplicate comparison even if there is an intervening function 2288 call - it will then try to reload the cc reg via an int reg which is why 2289 we need the movcc patterns). It is possible to provide the movcc 2290 patterns by using the ldxfsr/stxfsr v9 insns. I tried it: you need two 2291 registers (say %g1,%g5) and it takes about 6 insns. A better fix would be 2292 to tell cse that CCFPE mode registers (even pseudos) are call 2293 clobbered. */ 2294 2295 /* ??? This is an experiment. Rather than making changes to cse which may 2296 or may not be easy/clean, we do our own cse. This is possible because 2297 we will generate hard registers. Cse knows they're call clobbered (it 2298 doesn't know the same thing about pseudos). If we guess wrong, no big 2299 deal, but if we win, great! */ 2300 2301 if (TARGET_V9 && GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT) 2302#if 1 /* experiment */ 2303 { 2304 int reg; 2305 /* We cycle through the registers to ensure they're all exercised. */ 2306 static int next_fcc_reg = 0; 2307 /* Previous x,y for each fcc reg. */ 2308 static rtx prev_args[4][2]; 2309 2310 /* Scan prev_args for x,y. */ 2311 for (reg = 0; reg < 4; reg++) 2312 if (prev_args[reg][0] == x && prev_args[reg][1] == y) 2313 break; 2314 if (reg == 4) 2315 { 2316 reg = next_fcc_reg; 2317 prev_args[reg][0] = x; 2318 prev_args[reg][1] = y; 2319 next_fcc_reg = (next_fcc_reg + 1) & 3; 2320 } 2321 cc_reg = gen_rtx_REG (mode, reg + SPARC_FIRST_V9_FCC_REG); 2322 } 2323#else 2324 cc_reg = gen_reg_rtx (mode); 2325#endif /* ! experiment */ 2326 else if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT) 2327 cc_reg = gen_rtx_REG (mode, SPARC_FCC_REG); 2328 else 2329 cc_reg = gen_rtx_REG (mode, SPARC_ICC_REG); 2330 2331 emit_insn (gen_rtx_SET (VOIDmode, cc_reg, 2332 gen_rtx_COMPARE (mode, x, y))); 2333 2334 return cc_reg; 2335} 2336 2337/* This function is used for v9 only. 2338 CODE is the code for an Scc's comparison. 2339 OPERANDS[0] is the target of the Scc insn. 2340 OPERANDS[1] is the value we compare against const0_rtx (which hasn't 2341 been generated yet). 2342 2343 This function is needed to turn 2344 2345 (set (reg:SI 110) 2346 (gt (reg:CCX 100 %icc) 2347 (const_int 0))) 2348 into 2349 (set (reg:SI 110) 2350 (gt:DI (reg:CCX 100 %icc) 2351 (const_int 0))) 2352 2353 IE: The instruction recognizer needs to see the mode of the comparison to 2354 find the right instruction. We could use "gt:DI" right in the 2355 define_expand, but leaving it out allows us to handle DI, SI, etc. 2356 2357 We refer to the global sparc compare operands sparc_compare_op0 and 2358 sparc_compare_op1. */ 2359 2360int 2361gen_v9_scc (compare_code, operands) 2362 enum rtx_code compare_code; 2363 register rtx *operands; 2364{ 2365 rtx temp, op0, op1; 2366 2367 if (! TARGET_ARCH64 2368 && (GET_MODE (sparc_compare_op0) == DImode 2369 || GET_MODE (operands[0]) == DImode)) 2370 return 0; 2371 2372 op0 = sparc_compare_op0; 2373 op1 = sparc_compare_op1; 2374 2375 /* Try to use the movrCC insns. */ 2376 if (TARGET_ARCH64 2377 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT 2378 && op1 == const0_rtx 2379 && v9_regcmp_p (compare_code)) 2380 { 2381 /* Special case for op0 != 0. This can be done with one instruction if 2382 operands[0] == sparc_compare_op0. */ 2383 2384 if (compare_code == NE 2385 && GET_MODE (operands[0]) == DImode 2386 && rtx_equal_p (op0, operands[0])) 2387 { 2388 emit_insn (gen_rtx_SET (VOIDmode, operands[0], 2389 gen_rtx_IF_THEN_ELSE (DImode, 2390 gen_rtx_fmt_ee (compare_code, DImode, 2391 op0, const0_rtx), 2392 const1_rtx, 2393 operands[0]))); 2394 return 1; 2395 } 2396 2397 if (reg_overlap_mentioned_p (operands[0], op0)) 2398 { 2399 /* Handle the case where operands[0] == sparc_compare_op0. 2400 We "early clobber" the result. */ 2401 op0 = gen_reg_rtx (GET_MODE (sparc_compare_op0)); 2402 emit_move_insn (op0, sparc_compare_op0); 2403 } 2404 2405 emit_insn (gen_rtx_SET (VOIDmode, operands[0], const0_rtx)); 2406 if (GET_MODE (op0) != DImode) 2407 { 2408 temp = gen_reg_rtx (DImode); 2409 convert_move (temp, op0, 0); 2410 } 2411 else 2412 temp = op0; 2413 emit_insn (gen_rtx_SET (VOIDmode, operands[0], 2414 gen_rtx_IF_THEN_ELSE (GET_MODE (operands[0]), 2415 gen_rtx_fmt_ee (compare_code, DImode, 2416 temp, const0_rtx), 2417 const1_rtx, 2418 operands[0]))); 2419 return 1; 2420 } 2421 else 2422 { 2423 operands[1] = gen_compare_reg (compare_code, op0, op1); 2424 2425 switch (GET_MODE (operands[1])) 2426 { 2427 case CCmode : 2428 case CCXmode : 2429 case CCFPEmode : 2430 case CCFPmode : 2431 break; 2432 default : 2433 abort (); 2434 } 2435 emit_insn (gen_rtx_SET (VOIDmode, operands[0], const0_rtx)); 2436 emit_insn (gen_rtx_SET (VOIDmode, operands[0], 2437 gen_rtx_IF_THEN_ELSE (GET_MODE (operands[0]), 2438 gen_rtx_fmt_ee (compare_code, 2439 GET_MODE (operands[1]), 2440 operands[1], const0_rtx), 2441 const1_rtx, operands[0]))); 2442 return 1; 2443 } 2444} 2445 2446/* Emit a conditional jump insn for the v9 architecture using comparison code 2447 CODE and jump target LABEL. 2448 This function exists to take advantage of the v9 brxx insns. */ 2449 2450void 2451emit_v9_brxx_insn (code, op0, label) 2452 enum rtx_code code; 2453 rtx op0, label; 2454{ 2455 emit_jump_insn (gen_rtx_SET (VOIDmode, 2456 pc_rtx, 2457 gen_rtx_IF_THEN_ELSE (VOIDmode, 2458 gen_rtx_fmt_ee (code, GET_MODE (op0), 2459 op0, const0_rtx), 2460 gen_rtx_LABEL_REF (VOIDmode, label), 2461 pc_rtx))); 2462} 2463 2464/* Generate a DFmode part of a hard TFmode register. 2465 REG is the TFmode hard register, LOW is 1 for the 2466 low 64bit of the register and 0 otherwise. 2467 */ 2468rtx 2469gen_df_reg (reg, low) 2470 rtx reg; 2471 int low; 2472{ 2473 int regno = REGNO (reg); 2474 2475 if ((WORDS_BIG_ENDIAN == 0) ^ (low != 0)) 2476 regno += (TARGET_ARCH64 && regno < 32) ? 1 : 2; 2477 return gen_rtx_REG (DFmode, regno); 2478} 2479 2480/* Generate a call to FUNC with OPERANDS. Operand 0 is the return value. 2481 Unlike normal calls, TFmode operands are passed by reference. It is 2482 assumed that no more than 3 operands are required. */ 2483 2484static void 2485emit_soft_tfmode_libcall (func_name, nargs, operands) 2486 const char *func_name; 2487 int nargs; 2488 rtx *operands; 2489{ 2490 rtx ret_slot = NULL, arg[3], func_sym; 2491 int i; 2492 2493 /* We only expect to be called for conversions, unary, and binary ops. */ 2494 if (nargs < 2 || nargs > 3) 2495 abort (); 2496 2497 for (i = 0; i < nargs; ++i) 2498 { 2499 rtx this_arg = operands[i]; 2500 rtx this_slot; 2501 2502 /* TFmode arguments and return values are passed by reference. */ 2503 if (GET_MODE (this_arg) == TFmode) 2504 { 2505 int force_stack_temp; 2506 2507 force_stack_temp = 0; 2508 if (TARGET_BUGGY_QP_LIB && i == 0) 2509 force_stack_temp = 1; 2510 2511 if (GET_CODE (this_arg) == MEM 2512 && ! force_stack_temp) 2513 this_arg = XEXP (this_arg, 0); 2514 else if (CONSTANT_P (this_arg) 2515 && ! force_stack_temp) 2516 { 2517 this_slot = force_const_mem (TFmode, this_arg); 2518 this_arg = XEXP (this_slot, 0); 2519 } 2520 else 2521 { 2522 this_slot = assign_stack_temp (TFmode, GET_MODE_SIZE (TFmode), 0); 2523 2524 /* Operand 0 is the return value. We'll copy it out later. */ 2525 if (i > 0) 2526 emit_move_insn (this_slot, this_arg); 2527 else 2528 ret_slot = this_slot; 2529 2530 this_arg = XEXP (this_slot, 0); 2531 } 2532 } 2533 2534 arg[i] = this_arg; 2535 } 2536 2537 func_sym = gen_rtx_SYMBOL_REF (Pmode, func_name); 2538 2539 if (GET_MODE (operands[0]) == TFmode) 2540 { 2541 if (nargs == 2) 2542 emit_library_call (func_sym, LCT_NORMAL, VOIDmode, 2, 2543 arg[0], GET_MODE (arg[0]), 2544 arg[1], GET_MODE (arg[1])); 2545 else 2546 emit_library_call (func_sym, LCT_NORMAL, VOIDmode, 3, 2547 arg[0], GET_MODE (arg[0]), 2548 arg[1], GET_MODE (arg[1]), 2549 arg[2], GET_MODE (arg[2])); 2550 2551 if (ret_slot) 2552 emit_move_insn (operands[0], ret_slot); 2553 } 2554 else 2555 { 2556 rtx ret; 2557 2558 if (nargs != 2) 2559 abort (); 2560 2561 ret = emit_library_call_value (func_sym, operands[0], LCT_NORMAL, 2562 GET_MODE (operands[0]), 1, 2563 arg[1], GET_MODE (arg[1])); 2564 2565 if (ret != operands[0]) 2566 emit_move_insn (operands[0], ret); 2567 } 2568} 2569 2570/* Expand soft-float TFmode calls to sparc abi routines. */ 2571 2572static void 2573emit_soft_tfmode_binop (code, operands) 2574 enum rtx_code code; 2575 rtx *operands; 2576{ 2577 const char *func; 2578 2579 switch (code) 2580 { 2581 case PLUS: 2582 func = "_Qp_add"; 2583 break; 2584 case MINUS: 2585 func = "_Qp_sub"; 2586 break; 2587 case MULT: 2588 func = "_Qp_mul"; 2589 break; 2590 case DIV: 2591 func = "_Qp_div"; 2592 break; 2593 default: 2594 abort (); 2595 } 2596 2597 emit_soft_tfmode_libcall (func, 3, operands); 2598} 2599 2600static void 2601emit_soft_tfmode_unop (code, operands) 2602 enum rtx_code code; 2603 rtx *operands; 2604{ 2605 const char *func; 2606 2607 switch (code) 2608 { 2609 case SQRT: 2610 func = "_Qp_sqrt"; 2611 break; 2612 default: 2613 abort (); 2614 } 2615 2616 emit_soft_tfmode_libcall (func, 2, operands); 2617} 2618 2619static void 2620emit_soft_tfmode_cvt (code, operands) 2621 enum rtx_code code; 2622 rtx *operands; 2623{ 2624 const char *func; 2625 2626 switch (code) 2627 { 2628 case FLOAT_EXTEND: 2629 switch (GET_MODE (operands[1])) 2630 { 2631 case SFmode: 2632 func = "_Qp_stoq"; 2633 break; 2634 case DFmode: 2635 func = "_Qp_dtoq"; 2636 break; 2637 default: 2638 abort (); 2639 } 2640 break; 2641 2642 case FLOAT_TRUNCATE: 2643 switch (GET_MODE (operands[0])) 2644 { 2645 case SFmode: 2646 func = "_Qp_qtos"; 2647 break; 2648 case DFmode: 2649 func = "_Qp_qtod"; 2650 break; 2651 default: 2652 abort (); 2653 } 2654 break; 2655 2656 case FLOAT: 2657 switch (GET_MODE (operands[1])) 2658 { 2659 case SImode: 2660 func = "_Qp_itoq"; 2661 break; 2662 case DImode: 2663 func = "_Qp_xtoq"; 2664 break; 2665 default: 2666 abort (); 2667 } 2668 break; 2669 2670 case UNSIGNED_FLOAT: 2671 switch (GET_MODE (operands[1])) 2672 { 2673 case SImode: 2674 func = "_Qp_uitoq"; 2675 break; 2676 case DImode: 2677 func = "_Qp_uxtoq"; 2678 break; 2679 default: 2680 abort (); 2681 } 2682 break; 2683 2684 case FIX: 2685 switch (GET_MODE (operands[0])) 2686 { 2687 case SImode: 2688 func = "_Qp_qtoi"; 2689 break; 2690 case DImode: 2691 func = "_Qp_qtox"; 2692 break; 2693 default: 2694 abort (); 2695 } 2696 break; 2697 2698 case UNSIGNED_FIX: 2699 switch (GET_MODE (operands[0])) 2700 { 2701 case SImode: 2702 func = "_Qp_qtoui"; 2703 break; 2704 case DImode: 2705 func = "_Qp_qtoux"; 2706 break; 2707 default: 2708 abort (); 2709 } 2710 break; 2711 2712 default: 2713 abort (); 2714 } 2715 2716 emit_soft_tfmode_libcall (func, 2, operands); 2717} 2718 2719/* Expand a hard-float tfmode operation. All arguments must be in 2720 registers. */ 2721 2722static void 2723emit_hard_tfmode_operation (code, operands) 2724 enum rtx_code code; 2725 rtx *operands; 2726{ 2727 rtx op, dest; 2728 2729 if (GET_RTX_CLASS (code) == '1') 2730 { 2731 operands[1] = force_reg (GET_MODE (operands[1]), operands[1]); 2732 op = gen_rtx_fmt_e (code, GET_MODE (operands[0]), operands[1]); 2733 } 2734 else 2735 { 2736 operands[1] = force_reg (GET_MODE (operands[1]), operands[1]); 2737 operands[2] = force_reg (GET_MODE (operands[2]), operands[2]); 2738 op = gen_rtx_fmt_ee (code, GET_MODE (operands[0]), 2739 operands[1], operands[2]); 2740 } 2741 2742 if (register_operand (operands[0], VOIDmode)) 2743 dest = operands[0]; 2744 else 2745 dest = gen_reg_rtx (GET_MODE (operands[0])); 2746 2747 emit_insn (gen_rtx_SET (VOIDmode, dest, op)); 2748 2749 if (dest != operands[0]) 2750 emit_move_insn (operands[0], dest); 2751} 2752 2753void 2754emit_tfmode_binop (code, operands) 2755 enum rtx_code code; 2756 rtx *operands; 2757{ 2758 if (TARGET_HARD_QUAD) 2759 emit_hard_tfmode_operation (code, operands); 2760 else 2761 emit_soft_tfmode_binop (code, operands); 2762} 2763 2764void 2765emit_tfmode_unop (code, operands) 2766 enum rtx_code code; 2767 rtx *operands; 2768{ 2769 if (TARGET_HARD_QUAD) 2770 emit_hard_tfmode_operation (code, operands); 2771 else 2772 emit_soft_tfmode_unop (code, operands); 2773} 2774 2775void 2776emit_tfmode_cvt (code, operands) 2777 enum rtx_code code; 2778 rtx *operands; 2779{ 2780 if (TARGET_HARD_QUAD) 2781 emit_hard_tfmode_operation (code, operands); 2782 else 2783 emit_soft_tfmode_cvt (code, operands); 2784} 2785 2786/* Return nonzero if a return peephole merging return with 2787 setting of output register is ok. */ 2788int 2789leaf_return_peephole_ok () 2790{ 2791 return (actual_fsize == 0); 2792} 2793 2794/* Return nonzero if a branch/jump/call instruction will be emitting 2795 nop into its delay slot. */ 2796 2797int 2798empty_delay_slot (insn) 2799 rtx insn; 2800{ 2801 rtx seq; 2802 2803 /* If no previous instruction (should not happen), return true. */ 2804 if (PREV_INSN (insn) == NULL) 2805 return 1; 2806 2807 seq = NEXT_INSN (PREV_INSN (insn)); 2808 if (GET_CODE (PATTERN (seq)) == SEQUENCE) 2809 return 0; 2810 2811 return 1; 2812} 2813 2814/* Return nonzero if TRIAL can go into the function epilogue's 2815 delay slot. SLOT is the slot we are trying to fill. */ 2816 2817int 2818eligible_for_epilogue_delay (trial, slot) 2819 rtx trial; 2820 int slot; 2821{ 2822 rtx pat, src; 2823 2824 if (slot >= 1) 2825 return 0; 2826 2827 if (GET_CODE (trial) != INSN || GET_CODE (PATTERN (trial)) != SET) 2828 return 0; 2829 2830 if (get_attr_length (trial) != 1) 2831 return 0; 2832 2833 /* If there are any call-saved registers, we should scan TRIAL if it 2834 does not reference them. For now just make it easy. */ 2835 if (num_gfregs) 2836 return 0; 2837 2838 /* If the function uses __builtin_eh_return, the eh_return machinery 2839 occupies the delay slot. */ 2840 if (current_function_calls_eh_return) 2841 return 0; 2842 2843 /* In the case of a true leaf function, anything can go into the delay slot. 2844 A delay slot only exists however if the frame size is zero, otherwise 2845 we will put an insn to adjust the stack after the return. */ 2846 if (current_function_uses_only_leaf_regs) 2847 { 2848 if (leaf_return_peephole_ok ()) 2849 return ((get_attr_in_uncond_branch_delay (trial) 2850 == IN_BRANCH_DELAY_TRUE)); 2851 return 0; 2852 } 2853 2854 pat = PATTERN (trial); 2855 2856 /* Otherwise, only operations which can be done in tandem with 2857 a `restore' or `return' insn can go into the delay slot. */ 2858 if (GET_CODE (SET_DEST (pat)) != REG 2859 || REGNO (SET_DEST (pat)) < 24) 2860 return 0; 2861 2862 /* If this instruction sets up floating point register and we have a return 2863 instruction, it can probably go in. But restore will not work 2864 with FP_REGS. */ 2865 if (REGNO (SET_DEST (pat)) >= 32) 2866 { 2867 if (TARGET_V9 && ! epilogue_renumber (&pat, 1) 2868 && (get_attr_in_uncond_branch_delay (trial) == IN_BRANCH_DELAY_TRUE)) 2869 return 1; 2870 return 0; 2871 } 2872 2873 /* The set of insns matched here must agree precisely with the set of 2874 patterns paired with a RETURN in sparc.md. */ 2875 2876 src = SET_SRC (pat); 2877 2878 /* This matches "*return_[qhs]i" or even "*return_di" on TARGET_ARCH64. */ 2879 if (GET_MODE_CLASS (GET_MODE (src)) != MODE_FLOAT 2880 && arith_operand (src, GET_MODE (src))) 2881 { 2882 if (TARGET_ARCH64) 2883 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (DImode); 2884 else 2885 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (SImode); 2886 } 2887 2888 /* This matches "*return_di". */ 2889 else if (GET_MODE_CLASS (GET_MODE (src)) != MODE_FLOAT 2890 && arith_double_operand (src, GET_MODE (src))) 2891 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (DImode); 2892 2893 /* This matches "*return_sf_no_fpu". */ 2894 else if (! TARGET_FPU && restore_operand (SET_DEST (pat), SFmode) 2895 && register_operand (src, SFmode)) 2896 return 1; 2897 2898 /* If we have return instruction, anything that does not use 2899 local or output registers and can go into a delay slot wins. */ 2900 else if (TARGET_V9 && ! epilogue_renumber (&pat, 1) 2901 && (get_attr_in_uncond_branch_delay (trial) == IN_BRANCH_DELAY_TRUE)) 2902 return 1; 2903 2904 /* This matches "*return_addsi". */ 2905 else if (GET_CODE (src) == PLUS 2906 && arith_operand (XEXP (src, 0), SImode) 2907 && arith_operand (XEXP (src, 1), SImode) 2908 && (register_operand (XEXP (src, 0), SImode) 2909 || register_operand (XEXP (src, 1), SImode))) 2910 return 1; 2911 2912 /* This matches "*return_adddi". */ 2913 else if (GET_CODE (src) == PLUS 2914 && arith_double_operand (XEXP (src, 0), DImode) 2915 && arith_double_operand (XEXP (src, 1), DImode) 2916 && (register_operand (XEXP (src, 0), DImode) 2917 || register_operand (XEXP (src, 1), DImode))) 2918 return 1; 2919 2920 /* This can match "*return_losum_[sd]i". 2921 Catch only some cases, so that return_losum* don't have 2922 to be too big. */ 2923 else if (GET_CODE (src) == LO_SUM 2924 && ! TARGET_CM_MEDMID 2925 && ((register_operand (XEXP (src, 0), SImode) 2926 && immediate_operand (XEXP (src, 1), SImode)) 2927 || (TARGET_ARCH64 2928 && register_operand (XEXP (src, 0), DImode) 2929 && immediate_operand (XEXP (src, 1), DImode)))) 2930 return 1; 2931 2932 /* sll{,x} reg,1,reg2 is add reg,reg,reg2 as well. */ 2933 else if (GET_CODE (src) == ASHIFT 2934 && (register_operand (XEXP (src, 0), SImode) 2935 || register_operand (XEXP (src, 0), DImode)) 2936 && XEXP (src, 1) == const1_rtx) 2937 return 1; 2938 2939 return 0; 2940} 2941 2942/* Return nonzero if TRIAL can go into the sibling call 2943 delay slot. */ 2944 2945int 2946eligible_for_sibcall_delay (trial) 2947 rtx trial; 2948{ 2949 rtx pat, src; 2950 2951 if (GET_CODE (trial) != INSN || GET_CODE (PATTERN (trial)) != SET) 2952 return 0; 2953 2954 if (get_attr_length (trial) != 1) 2955 return 0; 2956 2957 pat = PATTERN (trial); 2958 2959 if (current_function_uses_only_leaf_regs) 2960 { 2961 /* If the tail call is done using the call instruction, 2962 we have to restore %o7 in the delay slot. */ 2963 if ((TARGET_ARCH64 && ! TARGET_CM_MEDLOW) || flag_pic) 2964 return 0; 2965 2966 /* %g1 is used to build the function address */ 2967 if (reg_mentioned_p (gen_rtx_REG (Pmode, 1), pat)) 2968 return 0; 2969 2970 return 1; 2971 } 2972 2973 /* Otherwise, only operations which can be done in tandem with 2974 a `restore' insn can go into the delay slot. */ 2975 if (GET_CODE (SET_DEST (pat)) != REG 2976 || REGNO (SET_DEST (pat)) < 24 2977 || REGNO (SET_DEST (pat)) >= 32) 2978 return 0; 2979 2980 /* If it mentions %o7, it can't go in, because sibcall will clobber it 2981 in most cases. */ 2982 if (reg_mentioned_p (gen_rtx_REG (Pmode, 15), pat)) 2983 return 0; 2984 2985 src = SET_SRC (pat); 2986 2987 if (GET_MODE_CLASS (GET_MODE (src)) != MODE_FLOAT 2988 && arith_operand (src, GET_MODE (src))) 2989 { 2990 if (TARGET_ARCH64) 2991 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (DImode); 2992 else 2993 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (SImode); 2994 } 2995 2996 else if (GET_MODE_CLASS (GET_MODE (src)) != MODE_FLOAT 2997 && arith_double_operand (src, GET_MODE (src))) 2998 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (DImode); 2999 3000 else if (! TARGET_FPU && restore_operand (SET_DEST (pat), SFmode) 3001 && register_operand (src, SFmode)) 3002 return 1; 3003 3004 else if (GET_CODE (src) == PLUS 3005 && arith_operand (XEXP (src, 0), SImode) 3006 && arith_operand (XEXP (src, 1), SImode) 3007 && (register_operand (XEXP (src, 0), SImode) 3008 || register_operand (XEXP (src, 1), SImode))) 3009 return 1; 3010 3011 else if (GET_CODE (src) == PLUS 3012 && arith_double_operand (XEXP (src, 0), DImode) 3013 && arith_double_operand (XEXP (src, 1), DImode) 3014 && (register_operand (XEXP (src, 0), DImode) 3015 || register_operand (XEXP (src, 1), DImode))) 3016 return 1; 3017 3018 else if (GET_CODE (src) == LO_SUM 3019 && ! TARGET_CM_MEDMID 3020 && ((register_operand (XEXP (src, 0), SImode) 3021 && immediate_operand (XEXP (src, 1), SImode)) 3022 || (TARGET_ARCH64 3023 && register_operand (XEXP (src, 0), DImode) 3024 && immediate_operand (XEXP (src, 1), DImode)))) 3025 return 1; 3026 3027 else if (GET_CODE (src) == ASHIFT 3028 && (register_operand (XEXP (src, 0), SImode) 3029 || register_operand (XEXP (src, 0), DImode)) 3030 && XEXP (src, 1) == const1_rtx) 3031 return 1; 3032 3033 return 0; 3034} 3035 3036static int 3037check_return_regs (x) 3038 rtx x; 3039{ 3040 switch (GET_CODE (x)) 3041 { 3042 case REG: 3043 return IN_OR_GLOBAL_P (x); 3044 3045 case CONST_INT: 3046 case CONST_DOUBLE: 3047 case CONST: 3048 case SYMBOL_REF: 3049 case LABEL_REF: 3050 return 1; 3051 3052 case SET: 3053 case IOR: 3054 case AND: 3055 case XOR: 3056 case PLUS: 3057 case MINUS: 3058 if (check_return_regs (XEXP (x, 1)) == 0) 3059 return 0; 3060 case NOT: 3061 case NEG: 3062 case MEM: 3063 return check_return_regs (XEXP (x, 0)); 3064 3065 default: 3066 return 0; 3067 } 3068 3069} 3070 3071int 3072short_branch (uid1, uid2) 3073 int uid1, uid2; 3074{ 3075 int delta = INSN_ADDRESSES (uid1) - INSN_ADDRESSES (uid2); 3076 3077 /* Leave a few words of "slop". */ 3078 if (delta >= -1023 && delta <= 1022) 3079 return 1; 3080 3081 return 0; 3082} 3083 3084/* Return nonzero if REG is not used after INSN. 3085 We assume REG is a reload reg, and therefore does 3086 not live past labels or calls or jumps. */ 3087int 3088reg_unused_after (reg, insn) 3089 rtx reg; 3090 rtx insn; 3091{ 3092 enum rtx_code code, prev_code = UNKNOWN; 3093 3094 while ((insn = NEXT_INSN (insn))) 3095 { 3096 if (prev_code == CALL_INSN && call_used_regs[REGNO (reg)]) 3097 return 1; 3098 3099 code = GET_CODE (insn); 3100 if (GET_CODE (insn) == CODE_LABEL) 3101 return 1; 3102 3103 if (GET_RTX_CLASS (code) == 'i') 3104 { 3105 rtx set = single_set (insn); 3106 int in_src = set && reg_overlap_mentioned_p (reg, SET_SRC (set)); 3107 if (set && in_src) 3108 return 0; 3109 if (set && reg_overlap_mentioned_p (reg, SET_DEST (set))) 3110 return 1; 3111 if (set == 0 && reg_overlap_mentioned_p (reg, PATTERN (insn))) 3112 return 0; 3113 } 3114 prev_code = code; 3115 } 3116 return 1; 3117} 3118 3119/* The table we use to reference PIC data. */ 3120static GTY(()) rtx global_offset_table; 3121 3122/* The function we use to get at it. */ 3123static GTY(()) rtx get_pc_symbol; 3124static char get_pc_symbol_name[256]; 3125 3126/* Ensure that we are not using patterns that are not OK with PIC. */ 3127 3128int 3129check_pic (i) 3130 int i; 3131{ 3132 switch (flag_pic) 3133 { 3134 case 1: 3135 if (GET_CODE (recog_data.operand[i]) == SYMBOL_REF 3136 || (GET_CODE (recog_data.operand[i]) == CONST 3137 && ! (GET_CODE (XEXP (recog_data.operand[i], 0)) == MINUS 3138 && (XEXP (XEXP (recog_data.operand[i], 0), 0) 3139 == global_offset_table) 3140 && (GET_CODE (XEXP (XEXP (recog_data.operand[i], 0), 1)) 3141 == CONST)))) 3142 abort (); 3143 case 2: 3144 default: 3145 return 1; 3146 } 3147} 3148 3149/* Return true if X is an address which needs a temporary register when 3150 reloaded while generating PIC code. */ 3151 3152int 3153pic_address_needs_scratch (x) 3154 rtx x; 3155{ 3156 /* An address which is a symbolic plus a non SMALL_INT needs a temp reg. */ 3157 if (GET_CODE (x) == CONST && GET_CODE (XEXP (x, 0)) == PLUS 3158 && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF 3159 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT 3160 && ! SMALL_INT (XEXP (XEXP (x, 0), 1))) 3161 return 1; 3162 3163 return 0; 3164} 3165 3166/* Legitimize PIC addresses. If the address is already position-independent, 3167 we return ORIG. Newly generated position-independent addresses go into a 3168 reg. This is REG if nonzero, otherwise we allocate register(s) as 3169 necessary. */ 3170 3171rtx 3172legitimize_pic_address (orig, mode, reg) 3173 rtx orig; 3174 enum machine_mode mode ATTRIBUTE_UNUSED; 3175 rtx reg; 3176{ 3177 if (GET_CODE (orig) == SYMBOL_REF) 3178 { 3179 rtx pic_ref, address; 3180 rtx insn; 3181 3182 if (reg == 0) 3183 { 3184 if (reload_in_progress || reload_completed) 3185 abort (); 3186 else 3187 reg = gen_reg_rtx (Pmode); 3188 } 3189 3190 if (flag_pic == 2) 3191 { 3192 /* If not during reload, allocate another temp reg here for loading 3193 in the address, so that these instructions can be optimized 3194 properly. */ 3195 rtx temp_reg = ((reload_in_progress || reload_completed) 3196 ? reg : gen_reg_rtx (Pmode)); 3197 3198 /* Must put the SYMBOL_REF inside an UNSPEC here so that cse 3199 won't get confused into thinking that these two instructions 3200 are loading in the true address of the symbol. If in the 3201 future a PIC rtx exists, that should be used instead. */ 3202 if (Pmode == SImode) 3203 { 3204 emit_insn (gen_movsi_high_pic (temp_reg, orig)); 3205 emit_insn (gen_movsi_lo_sum_pic (temp_reg, temp_reg, orig)); 3206 } 3207 else 3208 { 3209 emit_insn (gen_movdi_high_pic (temp_reg, orig)); 3210 emit_insn (gen_movdi_lo_sum_pic (temp_reg, temp_reg, orig)); 3211 } 3212 address = temp_reg; 3213 } 3214 else 3215 address = orig; 3216 3217 pic_ref = gen_rtx_MEM (Pmode, 3218 gen_rtx_PLUS (Pmode, 3219 pic_offset_table_rtx, address)); 3220 current_function_uses_pic_offset_table = 1; 3221 RTX_UNCHANGING_P (pic_ref) = 1; 3222 insn = emit_move_insn (reg, pic_ref); 3223 /* Put a REG_EQUAL note on this insn, so that it can be optimized 3224 by loop. */ 3225 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUAL, orig, 3226 REG_NOTES (insn)); 3227 return reg; 3228 } 3229 else if (GET_CODE (orig) == CONST) 3230 { 3231 rtx base, offset; 3232 3233 if (GET_CODE (XEXP (orig, 0)) == PLUS 3234 && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx) 3235 return orig; 3236 3237 if (reg == 0) 3238 { 3239 if (reload_in_progress || reload_completed) 3240 abort (); 3241 else 3242 reg = gen_reg_rtx (Pmode); 3243 } 3244 3245 if (GET_CODE (XEXP (orig, 0)) == PLUS) 3246 { 3247 base = legitimize_pic_address (XEXP (XEXP (orig, 0), 0), Pmode, reg); 3248 offset = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode, 3249 base == reg ? 0 : reg); 3250 } 3251 else 3252 abort (); 3253 3254 if (GET_CODE (offset) == CONST_INT) 3255 { 3256 if (SMALL_INT (offset)) 3257 return plus_constant (base, INTVAL (offset)); 3258 else if (! reload_in_progress && ! reload_completed) 3259 offset = force_reg (Pmode, offset); 3260 else 3261 /* If we reach here, then something is seriously wrong. */ 3262 abort (); 3263 } 3264 return gen_rtx_PLUS (Pmode, base, offset); 3265 } 3266 else if (GET_CODE (orig) == LABEL_REF) 3267 /* ??? Why do we do this? */ 3268 /* Now movsi_pic_label_ref uses it, but we ought to be checking that 3269 the register is live instead, in case it is eliminated. */ 3270 current_function_uses_pic_offset_table = 1; 3271 3272 return orig; 3273} 3274 3275/* Emit special PIC prologues. */ 3276 3277void 3278load_pic_register () 3279{ 3280 /* Labels to get the PC in the prologue of this function. */ 3281 int orig_flag_pic = flag_pic; 3282 3283 if (! flag_pic) 3284 abort (); 3285 3286 /* If we haven't emitted the special get_pc helper function, do so now. */ 3287 if (get_pc_symbol_name[0] == 0) 3288 { 3289 int align; 3290 3291 ASM_GENERATE_INTERNAL_LABEL (get_pc_symbol_name, "LGETPC", 0); 3292 text_section (); 3293 3294 align = floor_log2 (FUNCTION_BOUNDARY / BITS_PER_UNIT); 3295 if (align > 0) 3296 ASM_OUTPUT_ALIGN (asm_out_file, align); 3297 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "LGETPC", 0); 3298 fputs ("\tretl\n\tadd\t%o7, %l7, %l7\n", asm_out_file); 3299 } 3300 3301 /* Initialize every time through, since we can't easily 3302 know this to be permanent. */ 3303 global_offset_table = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_"); 3304 get_pc_symbol = gen_rtx_SYMBOL_REF (Pmode, get_pc_symbol_name); 3305 flag_pic = 0; 3306 3307 emit_insn (gen_get_pc (pic_offset_table_rtx, global_offset_table, 3308 get_pc_symbol)); 3309 3310 flag_pic = orig_flag_pic; 3311 3312 /* Need to emit this whether or not we obey regdecls, 3313 since setjmp/longjmp can cause life info to screw up. 3314 ??? In the case where we don't obey regdecls, this is not sufficient 3315 since we may not fall out the bottom. */ 3316 emit_insn (gen_rtx_USE (VOIDmode, pic_offset_table_rtx)); 3317} 3318 3319/* Return 1 if RTX is a MEM which is known to be aligned to at 3320 least a DESIRED byte boundary. */ 3321 3322int 3323mem_min_alignment (mem, desired) 3324 rtx mem; 3325 int desired; 3326{ 3327 rtx addr, base, offset; 3328 3329 /* If it's not a MEM we can't accept it. */ 3330 if (GET_CODE (mem) != MEM) 3331 return 0; 3332 3333 addr = XEXP (mem, 0); 3334 base = offset = NULL_RTX; 3335 if (GET_CODE (addr) == PLUS) 3336 { 3337 if (GET_CODE (XEXP (addr, 0)) == REG) 3338 { 3339 base = XEXP (addr, 0); 3340 3341 /* What we are saying here is that if the base 3342 REG is aligned properly, the compiler will make 3343 sure any REG based index upon it will be so 3344 as well. */ 3345 if (GET_CODE (XEXP (addr, 1)) == CONST_INT) 3346 offset = XEXP (addr, 1); 3347 else 3348 offset = const0_rtx; 3349 } 3350 } 3351 else if (GET_CODE (addr) == REG) 3352 { 3353 base = addr; 3354 offset = const0_rtx; 3355 } 3356 3357 if (base != NULL_RTX) 3358 { 3359 int regno = REGNO (base); 3360 3361 if (regno != HARD_FRAME_POINTER_REGNUM && regno != STACK_POINTER_REGNUM) 3362 { 3363 /* Check if the compiler has recorded some information 3364 about the alignment of the base REG. If reload has 3365 completed, we already matched with proper alignments. 3366 If not running global_alloc, reload might give us 3367 unaligned pointer to local stack though. */ 3368 if (((cfun != 0 3369 && REGNO_POINTER_ALIGN (regno) >= desired * BITS_PER_UNIT) 3370 || (optimize && reload_completed)) 3371 && (INTVAL (offset) & (desired - 1)) == 0) 3372 return 1; 3373 } 3374 else 3375 { 3376 if (((INTVAL (offset) - SPARC_STACK_BIAS) & (desired - 1)) == 0) 3377 return 1; 3378 } 3379 } 3380 else if (! TARGET_UNALIGNED_DOUBLES 3381 || CONSTANT_P (addr) 3382 || GET_CODE (addr) == LO_SUM) 3383 { 3384 /* Anything else we know is properly aligned unless TARGET_UNALIGNED_DOUBLES 3385 is true, in which case we can only assume that an access is aligned if 3386 it is to a constant address, or the address involves a LO_SUM. */ 3387 return 1; 3388 } 3389 3390 /* An obviously unaligned address. */ 3391 return 0; 3392} 3393 3394 3395/* Vectors to keep interesting information about registers where it can easily 3396 be got. We used to use the actual mode value as the bit number, but there 3397 are more than 32 modes now. Instead we use two tables: one indexed by 3398 hard register number, and one indexed by mode. */ 3399 3400/* The purpose of sparc_mode_class is to shrink the range of modes so that 3401 they all fit (as bit numbers) in a 32 bit word (again). Each real mode is 3402 mapped into one sparc_mode_class mode. */ 3403 3404enum sparc_mode_class { 3405 S_MODE, D_MODE, T_MODE, O_MODE, 3406 SF_MODE, DF_MODE, TF_MODE, OF_MODE, 3407 CC_MODE, CCFP_MODE 3408}; 3409 3410/* Modes for single-word and smaller quantities. */ 3411#define S_MODES ((1 << (int) S_MODE) | (1 << (int) SF_MODE)) 3412 3413/* Modes for double-word and smaller quantities. */ 3414#define D_MODES (S_MODES | (1 << (int) D_MODE) | (1 << DF_MODE)) 3415 3416/* Modes for quad-word and smaller quantities. */ 3417#define T_MODES (D_MODES | (1 << (int) T_MODE) | (1 << (int) TF_MODE)) 3418 3419/* Modes for 8-word and smaller quantities. */ 3420#define O_MODES (T_MODES | (1 << (int) O_MODE) | (1 << (int) OF_MODE)) 3421 3422/* Modes for single-float quantities. We must allow any single word or 3423 smaller quantity. This is because the fix/float conversion instructions 3424 take integer inputs/outputs from the float registers. */ 3425#define SF_MODES (S_MODES) 3426 3427/* Modes for double-float and smaller quantities. */ 3428#define DF_MODES (S_MODES | D_MODES) 3429 3430/* Modes for double-float only quantities. */ 3431#define DF_MODES_NO_S ((1 << (int) D_MODE) | (1 << (int) DF_MODE)) 3432 3433/* Modes for quad-float only quantities. */ 3434#define TF_ONLY_MODES (1 << (int) TF_MODE) 3435 3436/* Modes for quad-float and smaller quantities. */ 3437#define TF_MODES (DF_MODES | TF_ONLY_MODES) 3438 3439/* Modes for quad-float and double-float quantities. */ 3440#define TF_MODES_NO_S (DF_MODES_NO_S | TF_ONLY_MODES) 3441 3442/* Modes for quad-float pair only quantities. */ 3443#define OF_ONLY_MODES (1 << (int) OF_MODE) 3444 3445/* Modes for quad-float pairs and smaller quantities. */ 3446#define OF_MODES (TF_MODES | OF_ONLY_MODES) 3447 3448#define OF_MODES_NO_S (TF_MODES_NO_S | OF_ONLY_MODES) 3449 3450/* Modes for condition codes. */ 3451#define CC_MODES (1 << (int) CC_MODE) 3452#define CCFP_MODES (1 << (int) CCFP_MODE) 3453 3454/* Value is 1 if register/mode pair is acceptable on sparc. 3455 The funny mixture of D and T modes is because integer operations 3456 do not specially operate on tetra quantities, so non-quad-aligned 3457 registers can hold quadword quantities (except %o4 and %i4 because 3458 they cross fixed registers). */ 3459 3460/* This points to either the 32 bit or the 64 bit version. */ 3461const int *hard_regno_mode_classes; 3462 3463static const int hard_32bit_mode_classes[] = { 3464 S_MODES, S_MODES, T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES, 3465 T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES, D_MODES, S_MODES, 3466 T_MODES, S_MODES, T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES, 3467 T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES, D_MODES, S_MODES, 3468 3469 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES, 3470 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES, 3471 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES, 3472 OF_MODES, SF_MODES, DF_MODES, SF_MODES, TF_MODES, SF_MODES, DF_MODES, SF_MODES, 3473 3474 /* FP regs f32 to f63. Only the even numbered registers actually exist, 3475 and none can hold SFmode/SImode values. */ 3476 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, 3477 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, 3478 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, 3479 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, TF_MODES_NO_S, 0, DF_MODES_NO_S, 0, 3480 3481 /* %fcc[0123] */ 3482 CCFP_MODES, CCFP_MODES, CCFP_MODES, CCFP_MODES, 3483 3484 /* %icc */ 3485 CC_MODES 3486}; 3487 3488static const int hard_64bit_mode_classes[] = { 3489 D_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, 3490 O_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, 3491 T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, 3492 O_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, 3493 3494 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES, 3495 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES, 3496 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES, 3497 OF_MODES, SF_MODES, DF_MODES, SF_MODES, TF_MODES, SF_MODES, DF_MODES, SF_MODES, 3498 3499 /* FP regs f32 to f63. Only the even numbered registers actually exist, 3500 and none can hold SFmode/SImode values. */ 3501 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, 3502 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, 3503 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, 3504 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, TF_MODES_NO_S, 0, DF_MODES_NO_S, 0, 3505 3506 /* %fcc[0123] */ 3507 CCFP_MODES, CCFP_MODES, CCFP_MODES, CCFP_MODES, 3508 3509 /* %icc */ 3510 CC_MODES 3511}; 3512 3513int sparc_mode_class [NUM_MACHINE_MODES]; 3514 3515enum reg_class sparc_regno_reg_class[FIRST_PSEUDO_REGISTER]; 3516 3517static void 3518sparc_init_modes () 3519{ 3520 int i; 3521 3522 for (i = 0; i < NUM_MACHINE_MODES; i++) 3523 { 3524 switch (GET_MODE_CLASS (i)) 3525 { 3526 case MODE_INT: 3527 case MODE_PARTIAL_INT: 3528 case MODE_COMPLEX_INT: 3529 if (GET_MODE_SIZE (i) <= 4) 3530 sparc_mode_class[i] = 1 << (int) S_MODE; 3531 else if (GET_MODE_SIZE (i) == 8) 3532 sparc_mode_class[i] = 1 << (int) D_MODE; 3533 else if (GET_MODE_SIZE (i) == 16) 3534 sparc_mode_class[i] = 1 << (int) T_MODE; 3535 else if (GET_MODE_SIZE (i) == 32) 3536 sparc_mode_class[i] = 1 << (int) O_MODE; 3537 else 3538 sparc_mode_class[i] = 0; 3539 break; 3540 case MODE_FLOAT: 3541 case MODE_COMPLEX_FLOAT: 3542 if (GET_MODE_SIZE (i) <= 4) 3543 sparc_mode_class[i] = 1 << (int) SF_MODE; 3544 else if (GET_MODE_SIZE (i) == 8) 3545 sparc_mode_class[i] = 1 << (int) DF_MODE; 3546 else if (GET_MODE_SIZE (i) == 16) 3547 sparc_mode_class[i] = 1 << (int) TF_MODE; 3548 else if (GET_MODE_SIZE (i) == 32) 3549 sparc_mode_class[i] = 1 << (int) OF_MODE; 3550 else 3551 sparc_mode_class[i] = 0; 3552 break; 3553 case MODE_CC: 3554 default: 3555 /* mode_class hasn't been initialized yet for EXTRA_CC_MODES, so 3556 we must explicitly check for them here. */ 3557 if (i == (int) CCFPmode || i == (int) CCFPEmode) 3558 sparc_mode_class[i] = 1 << (int) CCFP_MODE; 3559 else if (i == (int) CCmode || i == (int) CC_NOOVmode 3560 || i == (int) CCXmode || i == (int) CCX_NOOVmode) 3561 sparc_mode_class[i] = 1 << (int) CC_MODE; 3562 else 3563 sparc_mode_class[i] = 0; 3564 break; 3565 } 3566 } 3567 3568 if (TARGET_ARCH64) 3569 hard_regno_mode_classes = hard_64bit_mode_classes; 3570 else 3571 hard_regno_mode_classes = hard_32bit_mode_classes; 3572 3573 /* Initialize the array used by REGNO_REG_CLASS. */ 3574 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) 3575 { 3576 if (i < 16 && TARGET_V8PLUS) 3577 sparc_regno_reg_class[i] = I64_REGS; 3578 else if (i < 32 || i == FRAME_POINTER_REGNUM) 3579 sparc_regno_reg_class[i] = GENERAL_REGS; 3580 else if (i < 64) 3581 sparc_regno_reg_class[i] = FP_REGS; 3582 else if (i < 96) 3583 sparc_regno_reg_class[i] = EXTRA_FP_REGS; 3584 else if (i < 100) 3585 sparc_regno_reg_class[i] = FPCC_REGS; 3586 else 3587 sparc_regno_reg_class[i] = NO_REGS; 3588 } 3589} 3590 3591/* Save non call used registers from LOW to HIGH at BASE+OFFSET. 3592 N_REGS is the number of 4-byte regs saved thus far. This applies even to 3593 v9 int regs as it simplifies the code. */ 3594 3595static int 3596save_regs (file, low, high, base, offset, n_regs, real_offset) 3597 FILE *file; 3598 int low, high; 3599 const char *base; 3600 int offset; 3601 int n_regs; 3602 int real_offset; 3603{ 3604 int i; 3605 3606 if (TARGET_ARCH64 && high <= 32) 3607 { 3608 for (i = low; i < high; i++) 3609 { 3610 if (regs_ever_live[i] && ! call_used_regs[i]) 3611 { 3612 fprintf (file, "\tstx\t%s, [%s+%d]\n", 3613 reg_names[i], base, offset + 4 * n_regs); 3614 if (dwarf2out_do_frame ()) 3615 dwarf2out_reg_save ("", i, real_offset + 4 * n_regs); 3616 n_regs += 2; 3617 } 3618 } 3619 } 3620 else 3621 { 3622 for (i = low; i < high; i += 2) 3623 { 3624 if (regs_ever_live[i] && ! call_used_regs[i]) 3625 { 3626 if (regs_ever_live[i+1] && ! call_used_regs[i+1]) 3627 { 3628 fprintf (file, "\tstd\t%s, [%s+%d]\n", 3629 reg_names[i], base, offset + 4 * n_regs); 3630 if (dwarf2out_do_frame ()) 3631 { 3632 char *l = dwarf2out_cfi_label (); 3633 dwarf2out_reg_save (l, i, real_offset + 4 * n_regs); 3634 dwarf2out_reg_save (l, i+1, real_offset + 4 * n_regs + 4); 3635 } 3636 n_regs += 2; 3637 } 3638 else 3639 { 3640 fprintf (file, "\tst\t%s, [%s+%d]\n", 3641 reg_names[i], base, offset + 4 * n_regs); 3642 if (dwarf2out_do_frame ()) 3643 dwarf2out_reg_save ("", i, real_offset + 4 * n_regs); 3644 n_regs += 2; 3645 } 3646 } 3647 else 3648 { 3649 if (regs_ever_live[i+1] && ! call_used_regs[i+1]) 3650 { 3651 fprintf (file, "\tst\t%s, [%s+%d]\n", 3652 reg_names[i+1], base, offset + 4 * n_regs + 4); 3653 if (dwarf2out_do_frame ()) 3654 dwarf2out_reg_save ("", i + 1, real_offset + 4 * n_regs + 4); 3655 n_regs += 2; 3656 } 3657 } 3658 } 3659 } 3660 return n_regs; 3661} 3662 3663/* Restore non call used registers from LOW to HIGH at BASE+OFFSET. 3664 3665 N_REGS is the number of 4-byte regs saved thus far. This applies even to 3666 v9 int regs as it simplifies the code. */ 3667 3668static int 3669restore_regs (file, low, high, base, offset, n_regs) 3670 FILE *file; 3671 int low, high; 3672 const char *base; 3673 int offset; 3674 int n_regs; 3675{ 3676 int i; 3677 3678 if (TARGET_ARCH64 && high <= 32) 3679 { 3680 for (i = low; i < high; i++) 3681 { 3682 if (regs_ever_live[i] && ! call_used_regs[i]) 3683 fprintf (file, "\tldx\t[%s+%d], %s\n", 3684 base, offset + 4 * n_regs, reg_names[i]), 3685 n_regs += 2; 3686 } 3687 } 3688 else 3689 { 3690 for (i = low; i < high; i += 2) 3691 { 3692 if (regs_ever_live[i] && ! call_used_regs[i]) 3693 if (regs_ever_live[i+1] && ! call_used_regs[i+1]) 3694 fprintf (file, "\tldd\t[%s+%d], %s\n", 3695 base, offset + 4 * n_regs, reg_names[i]), 3696 n_regs += 2; 3697 else 3698 fprintf (file, "\tld\t[%s+%d], %s\n", 3699 base, offset + 4 * n_regs, reg_names[i]), 3700 n_regs += 2; 3701 else if (regs_ever_live[i+1] && ! call_used_regs[i+1]) 3702 fprintf (file, "\tld\t[%s+%d], %s\n", 3703 base, offset + 4 * n_regs + 4, reg_names[i+1]), 3704 n_regs += 2; 3705 } 3706 } 3707 return n_regs; 3708} 3709 3710/* Compute the frame size required by the function. This function is called 3711 during the reload pass and also by output_function_prologue(). */ 3712 3713int 3714compute_frame_size (size, leaf_function) 3715 int size; 3716 int leaf_function; 3717{ 3718 int n_regs = 0, i; 3719 int outgoing_args_size = (current_function_outgoing_args_size 3720 + REG_PARM_STACK_SPACE (current_function_decl)); 3721 3722 /* N_REGS is the number of 4-byte regs saved thus far. This applies 3723 even to v9 int regs to be consistent with save_regs/restore_regs. */ 3724 3725 if (TARGET_ARCH64) 3726 { 3727 for (i = 0; i < 8; i++) 3728 if (regs_ever_live[i] && ! call_used_regs[i]) 3729 n_regs += 2; 3730 } 3731 else 3732 { 3733 for (i = 0; i < 8; i += 2) 3734 if ((regs_ever_live[i] && ! call_used_regs[i]) 3735 || (regs_ever_live[i+1] && ! call_used_regs[i+1])) 3736 n_regs += 2; 3737 } 3738 3739 for (i = 32; i < (TARGET_V9 ? 96 : 64); i += 2) 3740 if ((regs_ever_live[i] && ! call_used_regs[i]) 3741 || (regs_ever_live[i+1] && ! call_used_regs[i+1])) 3742 n_regs += 2; 3743 3744 /* Set up values for use in `function_epilogue'. */ 3745 num_gfregs = n_regs; 3746 3747 if (leaf_function && n_regs == 0 3748 && size == 0 && current_function_outgoing_args_size == 0) 3749 { 3750 actual_fsize = apparent_fsize = 0; 3751 } 3752 else 3753 { 3754 /* We subtract STARTING_FRAME_OFFSET, remember it's negative. */ 3755 apparent_fsize = (size - STARTING_FRAME_OFFSET + 7) & -8; 3756 apparent_fsize += n_regs * 4; 3757 actual_fsize = apparent_fsize + ((outgoing_args_size + 7) & -8); 3758 } 3759 3760 /* Make sure nothing can clobber our register windows. 3761 If a SAVE must be done, or there is a stack-local variable, 3762 the register window area must be allocated. 3763 ??? For v8 we apparently need an additional 8 bytes of reserved space. */ 3764 if (leaf_function == 0 || size > 0) 3765 actual_fsize += (16 * UNITS_PER_WORD) + (TARGET_ARCH64 ? 0 : 8); 3766 3767 return SPARC_STACK_ALIGN (actual_fsize); 3768} 3769 3770/* Build a (32 bit) big number in a register. */ 3771/* ??? We may be able to use the set macro here too. */ 3772 3773static void 3774build_big_number (file, num, reg) 3775 FILE *file; 3776 int num; 3777 const char *reg; 3778{ 3779 if (num >= 0 || ! TARGET_ARCH64) 3780 { 3781 fprintf (file, "\tsethi\t%%hi(%d), %s\n", num, reg); 3782 if ((num & 0x3ff) != 0) 3783 fprintf (file, "\tor\t%s, %%lo(%d), %s\n", reg, num, reg); 3784 } 3785 else /* num < 0 && TARGET_ARCH64 */ 3786 { 3787 /* Sethi does not sign extend, so we must use a little trickery 3788 to use it for negative numbers. Invert the constant before 3789 loading it in, then use xor immediate to invert the loaded bits 3790 (along with the upper 32 bits) to the desired constant. This 3791 works because the sethi and immediate fields overlap. */ 3792 int asize = num; 3793 int inv = ~asize; 3794 int low = -0x400 + (asize & 0x3FF); 3795 3796 fprintf (file, "\tsethi\t%%hi(%d), %s\n\txor\t%s, %d, %s\n", 3797 inv, reg, reg, low, reg); 3798 } 3799} 3800 3801/* Output any necessary .register pseudo-ops. */ 3802void 3803sparc_output_scratch_registers (file) 3804 FILE *file ATTRIBUTE_UNUSED; 3805{ 3806#ifdef HAVE_AS_REGISTER_PSEUDO_OP 3807 int i; 3808 3809 if (TARGET_ARCH32) 3810 return; 3811 3812 /* Check if %g[2367] were used without 3813 .register being printed for them already. */ 3814 for (i = 2; i < 8; i++) 3815 { 3816 if (regs_ever_live [i] 3817 && ! sparc_hard_reg_printed [i]) 3818 { 3819 sparc_hard_reg_printed [i] = 1; 3820 fprintf (file, "\t.register\t%%g%d, #scratch\n", i); 3821 } 3822 if (i == 3) i = 5; 3823 } 3824#endif 3825} 3826 3827/* This function generates the assembly code for function entry. 3828 FILE is a stdio stream to output the code to. 3829 SIZE is an int: how many units of temporary storage to allocate. 3830 Refer to the array `regs_ever_live' to determine which registers 3831 to save; `regs_ever_live[I]' is nonzero if register number I 3832 is ever used in the function. This macro is responsible for 3833 knowing which registers should not be saved even if used. */ 3834 3835/* On SPARC, move-double insns between fpu and cpu need an 8-byte block 3836 of memory. If any fpu reg is used in the function, we allocate 3837 such a block here, at the bottom of the frame, just in case it's needed. 3838 3839 If this function is a leaf procedure, then we may choose not 3840 to do a "save" insn. The decision about whether or not 3841 to do this is made in regclass.c. */ 3842 3843static void 3844sparc_output_function_prologue (file, size) 3845 FILE *file; 3846 HOST_WIDE_INT size; 3847{ 3848 if (TARGET_FLAT) 3849 sparc_flat_function_prologue (file, size); 3850 else 3851 sparc_nonflat_function_prologue (file, size, 3852 current_function_uses_only_leaf_regs); 3853} 3854 3855/* Output code for the function prologue. */ 3856 3857static void 3858sparc_nonflat_function_prologue (file, size, leaf_function) 3859 FILE *file; 3860 HOST_WIDE_INT size; 3861 int leaf_function; 3862{ 3863 sparc_output_scratch_registers (file); 3864 3865 /* Need to use actual_fsize, since we are also allocating 3866 space for our callee (and our own register save area). */ 3867 actual_fsize = compute_frame_size (size, leaf_function); 3868 3869 if (leaf_function) 3870 { 3871 frame_base_name = "%sp"; 3872 frame_base_offset = actual_fsize + SPARC_STACK_BIAS; 3873 } 3874 else 3875 { 3876 frame_base_name = "%fp"; 3877 frame_base_offset = SPARC_STACK_BIAS; 3878 } 3879 3880 /* This is only for the human reader. */ 3881 fprintf (file, "\t%s#PROLOGUE# 0\n", ASM_COMMENT_START); 3882 3883 if (actual_fsize == 0) 3884 /* do nothing. */ ; 3885 else if (! leaf_function) 3886 { 3887 if (actual_fsize <= 4096) 3888 fprintf (file, "\tsave\t%%sp, -%d, %%sp\n", actual_fsize); 3889 else if (actual_fsize <= 8192) 3890 { 3891 fprintf (file, "\tsave\t%%sp, -4096, %%sp\n"); 3892 fprintf (file, "\tadd\t%%sp, -%d, %%sp\n", actual_fsize - 4096); 3893 } 3894 else 3895 { 3896 build_big_number (file, -actual_fsize, "%g1"); 3897 fprintf (file, "\tsave\t%%sp, %%g1, %%sp\n"); 3898 } 3899 } 3900 else /* leaf function */ 3901 { 3902 if (actual_fsize <= 4096) 3903 fprintf (file, "\tadd\t%%sp, -%d, %%sp\n", actual_fsize); 3904 else if (actual_fsize <= 8192) 3905 { 3906 fprintf (file, "\tadd\t%%sp, -4096, %%sp\n"); 3907 fprintf (file, "\tadd\t%%sp, -%d, %%sp\n", actual_fsize - 4096); 3908 } 3909 else 3910 { 3911 build_big_number (file, -actual_fsize, "%g1"); 3912 fprintf (file, "\tadd\t%%sp, %%g1, %%sp\n"); 3913 } 3914 } 3915 3916 if (dwarf2out_do_frame () && actual_fsize) 3917 { 3918 char *label = dwarf2out_cfi_label (); 3919 3920 /* The canonical frame address refers to the top of the frame. */ 3921 dwarf2out_def_cfa (label, (leaf_function ? STACK_POINTER_REGNUM 3922 : HARD_FRAME_POINTER_REGNUM), 3923 frame_base_offset); 3924 3925 if (! leaf_function) 3926 { 3927 /* Note the register window save. This tells the unwinder that 3928 it needs to restore the window registers from the previous 3929 frame's window save area at 0(cfa). */ 3930 dwarf2out_window_save (label); 3931 3932 /* The return address (-8) is now in %i7. */ 3933 dwarf2out_return_reg (label, 31); 3934 } 3935 } 3936 3937 /* If doing anything with PIC, do it now. */ 3938 if (! flag_pic) 3939 fprintf (file, "\t%s#PROLOGUE# 1\n", ASM_COMMENT_START); 3940 3941 /* Call saved registers are saved just above the outgoing argument area. */ 3942 if (num_gfregs) 3943 { 3944 int offset, real_offset, n_regs; 3945 const char *base; 3946 3947 real_offset = -apparent_fsize; 3948 offset = -apparent_fsize + frame_base_offset; 3949 if (offset < -4096 || offset + num_gfregs * 4 > 4096) 3950 { 3951 /* ??? This might be optimized a little as %g1 might already have a 3952 value close enough that a single add insn will do. */ 3953 /* ??? Although, all of this is probably only a temporary fix 3954 because if %g1 can hold a function result, then 3955 output_function_epilogue will lose (the result will get 3956 clobbered). */ 3957 build_big_number (file, offset, "%g1"); 3958 fprintf (file, "\tadd\t%s, %%g1, %%g1\n", frame_base_name); 3959 base = "%g1"; 3960 offset = 0; 3961 } 3962 else 3963 { 3964 base = frame_base_name; 3965 } 3966 3967 n_regs = save_regs (file, 0, 8, base, offset, 0, real_offset); 3968 save_regs (file, 32, TARGET_V9 ? 96 : 64, base, offset, n_regs, 3969 real_offset); 3970 } 3971} 3972 3973/* Output code to restore any call saved registers. */ 3974 3975static void 3976output_restore_regs (file, leaf_function) 3977 FILE *file; 3978 int leaf_function ATTRIBUTE_UNUSED; 3979{ 3980 int offset, n_regs; 3981 const char *base; 3982 3983 offset = -apparent_fsize + frame_base_offset; 3984 if (offset < -4096 || offset + num_gfregs * 4 > 4096 - 8 /*double*/) 3985 { 3986 build_big_number (file, offset, "%g1"); 3987 fprintf (file, "\tadd\t%s, %%g1, %%g1\n", frame_base_name); 3988 base = "%g1"; 3989 offset = 0; 3990 } 3991 else 3992 { 3993 base = frame_base_name; 3994 } 3995 3996 n_regs = restore_regs (file, 0, 8, base, offset, 0); 3997 restore_regs (file, 32, TARGET_V9 ? 96 : 64, base, offset, n_regs); 3998} 3999 4000/* This function generates the assembly code for function exit, 4001 on machines that need it. 4002 4003 The function epilogue should not depend on the current stack pointer! 4004 It should use the frame pointer only. This is mandatory because 4005 of alloca; we also take advantage of it to omit stack adjustments 4006 before returning. */ 4007 4008static void 4009sparc_output_function_epilogue (file, size) 4010 FILE *file; 4011 HOST_WIDE_INT size; 4012{ 4013 if (TARGET_FLAT) 4014 sparc_flat_function_epilogue (file, size); 4015 else 4016 sparc_nonflat_function_epilogue (file, size, 4017 current_function_uses_only_leaf_regs); 4018} 4019 4020/* Output code for the function epilogue. */ 4021 4022static void 4023sparc_nonflat_function_epilogue (file, size, leaf_function) 4024 FILE *file; 4025 HOST_WIDE_INT size ATTRIBUTE_UNUSED; 4026 int leaf_function; 4027{ 4028 const char *ret; 4029 4030 if (current_function_epilogue_delay_list == 0) 4031 { 4032 /* If code does not drop into the epilogue, we need 4033 do nothing except output pending case vectors. 4034 4035 We have to still output a dummy nop for the sake of 4036 sane backtraces. Otherwise, if the last two instructions 4037 of a function were call foo; dslot; this can make the return 4038 PC of foo (ie. address of call instruction plus 8) point to 4039 the first instruction in the next function. */ 4040 rtx insn; 4041 4042 fputs("\tnop\n", file); 4043 4044 insn = get_last_insn (); 4045 if (GET_CODE (insn) == NOTE) 4046 insn = prev_nonnote_insn (insn); 4047 if (insn && GET_CODE (insn) == BARRIER) 4048 goto output_vectors; 4049 } 4050 4051 if (num_gfregs) 4052 output_restore_regs (file, leaf_function); 4053 4054 /* Work out how to skip the caller's unimp instruction if required. */ 4055 if (leaf_function) 4056 ret = (SKIP_CALLERS_UNIMP_P ? "jmp\t%o7+12" : "retl"); 4057 else 4058 ret = (SKIP_CALLERS_UNIMP_P ? "jmp\t%i7+12" : "ret"); 4059 4060 if (! leaf_function) 4061 { 4062 if (current_function_calls_eh_return) 4063 { 4064 if (current_function_epilogue_delay_list) 4065 abort (); 4066 if (SKIP_CALLERS_UNIMP_P) 4067 abort (); 4068 4069 fputs ("\trestore\n\tretl\n\tadd\t%sp, %g1, %sp\n", file); 4070 } 4071 /* If we wound up with things in our delay slot, flush them here. */ 4072 else if (current_function_epilogue_delay_list) 4073 { 4074 rtx delay = PATTERN (XEXP (current_function_epilogue_delay_list, 0)); 4075 4076 if (TARGET_V9 && ! epilogue_renumber (&delay, 1)) 4077 { 4078 epilogue_renumber (&delay, 0); 4079 fputs (SKIP_CALLERS_UNIMP_P 4080 ? "\treturn\t%i7+12\n" 4081 : "\treturn\t%i7+8\n", file); 4082 final_scan_insn (XEXP (current_function_epilogue_delay_list, 0), 4083 file, 1, 0, 0); 4084 } 4085 else 4086 { 4087 rtx insn, src; 4088 4089 if (GET_CODE (delay) != SET) 4090 abort(); 4091 4092 src = SET_SRC (delay); 4093 if (GET_CODE (src) == ASHIFT) 4094 { 4095 if (XEXP (src, 1) != const1_rtx) 4096 abort(); 4097 SET_SRC (delay) 4098 = gen_rtx_PLUS (GET_MODE (src), XEXP (src, 0), 4099 XEXP (src, 0)); 4100 } 4101 4102 insn = gen_rtx_PARALLEL (VOIDmode, 4103 gen_rtvec (2, delay, 4104 gen_rtx_RETURN (VOIDmode))); 4105 insn = emit_jump_insn (insn); 4106 4107 sparc_emitting_epilogue = true; 4108 final_scan_insn (insn, file, 1, 0, 1); 4109 sparc_emitting_epilogue = false; 4110 } 4111 } 4112 else if (TARGET_V9 && ! SKIP_CALLERS_UNIMP_P) 4113 fputs ("\treturn\t%i7+8\n\tnop\n", file); 4114 else 4115 fprintf (file, "\t%s\n\trestore\n", ret); 4116 } 4117 /* All of the following cases are for leaf functions. */ 4118 else if (current_function_calls_eh_return) 4119 abort (); 4120 else if (current_function_epilogue_delay_list) 4121 { 4122 /* eligible_for_epilogue_delay_slot ensures that if this is a 4123 leaf function, then we will only have insn in the delay slot 4124 if the frame size is zero, thus no adjust for the stack is 4125 needed here. */ 4126 if (actual_fsize != 0) 4127 abort (); 4128 fprintf (file, "\t%s\n", ret); 4129 final_scan_insn (XEXP (current_function_epilogue_delay_list, 0), 4130 file, 1, 0, 1); 4131 } 4132 /* Output 'nop' instead of 'sub %sp,-0,%sp' when no frame, so as to 4133 avoid generating confusing assembly language output. */ 4134 else if (actual_fsize == 0) 4135 fprintf (file, "\t%s\n\tnop\n", ret); 4136 else if (actual_fsize <= 4096) 4137 fprintf (file, "\t%s\n\tsub\t%%sp, -%d, %%sp\n", ret, actual_fsize); 4138 else if (actual_fsize <= 8192) 4139 fprintf (file, "\tsub\t%%sp, -4096, %%sp\n\t%s\n\tsub\t%%sp, -%d, %%sp\n", 4140 ret, actual_fsize - 4096); 4141 else if ((actual_fsize & 0x3ff) == 0) 4142 fprintf (file, "\tsethi\t%%hi(%d), %%g1\n\t%s\n\tadd\t%%sp, %%g1, %%sp\n", 4143 actual_fsize, ret); 4144 else 4145 fprintf (file, "\tsethi\t%%hi(%d), %%g1\n\tor\t%%g1, %%lo(%d), %%g1\n\t%s\n\tadd\t%%sp, %%g1, %%sp\n", 4146 actual_fsize, actual_fsize, ret); 4147 4148 output_vectors: 4149 sparc_output_deferred_case_vectors (); 4150} 4151 4152/* Output a sibling call. */ 4153 4154const char * 4155output_sibcall (insn, call_operand) 4156 rtx insn, call_operand; 4157{ 4158 int leaf_regs = current_function_uses_only_leaf_regs; 4159 rtx operands[3]; 4160 int delay_slot = dbr_sequence_length () > 0; 4161 4162 if (num_gfregs) 4163 { 4164 /* Call to restore global regs might clobber 4165 the delay slot. Instead of checking for this 4166 output the delay slot now. */ 4167 if (delay_slot) 4168 { 4169 rtx delay = NEXT_INSN (insn); 4170 4171 if (! delay) 4172 abort (); 4173 4174 final_scan_insn (delay, asm_out_file, 1, 0, 1); 4175 PATTERN (delay) = gen_blockage (); 4176 INSN_CODE (delay) = -1; 4177 delay_slot = 0; 4178 } 4179 output_restore_regs (asm_out_file, leaf_regs); 4180 } 4181 4182 operands[0] = call_operand; 4183 4184 if (leaf_regs) 4185 { 4186#ifdef HAVE_AS_RELAX_OPTION 4187 /* If as and ld are relaxing tail call insns into branch always, 4188 use or %o7,%g0,X; call Y; or X,%g0,%o7 always, so that it can 4189 be optimized. With sethi/jmpl as nor ld has no easy way how to 4190 find out if somebody does not branch between the sethi and jmpl. */ 4191 int spare_slot = 0; 4192#else 4193 int spare_slot = ((TARGET_ARCH32 || TARGET_CM_MEDLOW) && ! flag_pic); 4194#endif 4195 int size = 0; 4196 4197 if ((actual_fsize || ! spare_slot) && delay_slot) 4198 { 4199 rtx delay = NEXT_INSN (insn); 4200 4201 if (! delay) 4202 abort (); 4203 4204 final_scan_insn (delay, asm_out_file, 1, 0, 1); 4205 PATTERN (delay) = gen_blockage (); 4206 INSN_CODE (delay) = -1; 4207 delay_slot = 0; 4208 } 4209 if (actual_fsize) 4210 { 4211 if (actual_fsize <= 4096) 4212 size = actual_fsize; 4213 else if (actual_fsize <= 8192) 4214 { 4215 fputs ("\tsub\t%sp, -4096, %sp\n", asm_out_file); 4216 size = actual_fsize - 4096; 4217 } 4218 else if ((actual_fsize & 0x3ff) == 0) 4219 fprintf (asm_out_file, 4220 "\tsethi\t%%hi(%d), %%g1\n\tadd\t%%sp, %%g1, %%sp\n", 4221 actual_fsize); 4222 else 4223 { 4224 fprintf (asm_out_file, 4225 "\tsethi\t%%hi(%d), %%g1\n\tor\t%%g1, %%lo(%d), %%g1\n", 4226 actual_fsize, actual_fsize); 4227 fputs ("\tadd\t%%sp, %%g1, %%sp\n", asm_out_file); 4228 } 4229 } 4230 if (spare_slot) 4231 { 4232 output_asm_insn ("sethi\t%%hi(%a0), %%g1", operands); 4233 output_asm_insn ("jmpl\t%%g1 + %%lo(%a0), %%g0", operands); 4234 if (size) 4235 fprintf (asm_out_file, "\t sub\t%%sp, -%d, %%sp\n", size); 4236 else if (! delay_slot) 4237 fputs ("\t nop\n", asm_out_file); 4238 } 4239 else 4240 { 4241 if (size) 4242 fprintf (asm_out_file, "\tsub\t%%sp, -%d, %%sp\n", size); 4243 /* Use or with rs2 %%g0 instead of mov, so that as/ld can optimize 4244 it into branch if possible. */ 4245 output_asm_insn ("or\t%%o7, %%g0, %%g1", operands); 4246 output_asm_insn ("call\t%a0, 0", operands); 4247 output_asm_insn (" or\t%%g1, %%g0, %%o7", operands); 4248 } 4249 return ""; 4250 } 4251 4252 output_asm_insn ("call\t%a0, 0", operands); 4253 if (delay_slot) 4254 { 4255 rtx delay = NEXT_INSN (insn), pat; 4256 4257 if (! delay) 4258 abort (); 4259 4260 pat = PATTERN (delay); 4261 if (GET_CODE (pat) != SET) 4262 abort (); 4263 4264 operands[0] = SET_DEST (pat); 4265 pat = SET_SRC (pat); 4266 switch (GET_CODE (pat)) 4267 { 4268 case PLUS: 4269 operands[1] = XEXP (pat, 0); 4270 operands[2] = XEXP (pat, 1); 4271 output_asm_insn (" restore %r1, %2, %Y0", operands); 4272 break; 4273 case LO_SUM: 4274 operands[1] = XEXP (pat, 0); 4275 operands[2] = XEXP (pat, 1); 4276 output_asm_insn (" restore %r1, %%lo(%a2), %Y0", operands); 4277 break; 4278 case ASHIFT: 4279 operands[1] = XEXP (pat, 0); 4280 output_asm_insn (" restore %r1, %r1, %Y0", operands); 4281 break; 4282 default: 4283 operands[1] = pat; 4284 output_asm_insn (" restore %%g0, %1, %Y0", operands); 4285 break; 4286 } 4287 PATTERN (delay) = gen_blockage (); 4288 INSN_CODE (delay) = -1; 4289 } 4290 else 4291 fputs ("\t restore\n", asm_out_file); 4292 return ""; 4293} 4294 4295/* Functions for handling argument passing. 4296 4297 For v8 the first six args are normally in registers and the rest are 4298 pushed. Any arg that starts within the first 6 words is at least 4299 partially passed in a register unless its data type forbids. 4300 4301 For v9, the argument registers are laid out as an array of 16 elements 4302 and arguments are added sequentially. The first 6 int args and up to the 4303 first 16 fp args (depending on size) are passed in regs. 4304 4305 Slot Stack Integral Float Float in structure Double Long Double 4306 ---- ----- -------- ----- ------------------ ------ ----------- 4307 15 [SP+248] %f31 %f30,%f31 %d30 4308 14 [SP+240] %f29 %f28,%f29 %d28 %q28 4309 13 [SP+232] %f27 %f26,%f27 %d26 4310 12 [SP+224] %f25 %f24,%f25 %d24 %q24 4311 11 [SP+216] %f23 %f22,%f23 %d22 4312 10 [SP+208] %f21 %f20,%f21 %d20 %q20 4313 9 [SP+200] %f19 %f18,%f19 %d18 4314 8 [SP+192] %f17 %f16,%f17 %d16 %q16 4315 7 [SP+184] %f15 %f14,%f15 %d14 4316 6 [SP+176] %f13 %f12,%f13 %d12 %q12 4317 5 [SP+168] %o5 %f11 %f10,%f11 %d10 4318 4 [SP+160] %o4 %f9 %f8,%f9 %d8 %q8 4319 3 [SP+152] %o3 %f7 %f6,%f7 %d6 4320 2 [SP+144] %o2 %f5 %f4,%f5 %d4 %q4 4321 1 [SP+136] %o1 %f3 %f2,%f3 %d2 4322 0 [SP+128] %o0 %f1 %f0,%f1 %d0 %q0 4323 4324 Here SP = %sp if -mno-stack-bias or %sp+stack_bias otherwise. 4325 4326 Integral arguments are always passed as 64 bit quantities appropriately 4327 extended. 4328 4329 Passing of floating point values is handled as follows. 4330 If a prototype is in scope: 4331 If the value is in a named argument (i.e. not a stdarg function or a 4332 value not part of the `...') then the value is passed in the appropriate 4333 fp reg. 4334 If the value is part of the `...' and is passed in one of the first 6 4335 slots then the value is passed in the appropriate int reg. 4336 If the value is part of the `...' and is not passed in one of the first 6 4337 slots then the value is passed in memory. 4338 If a prototype is not in scope: 4339 If the value is one of the first 6 arguments the value is passed in the 4340 appropriate integer reg and the appropriate fp reg. 4341 If the value is not one of the first 6 arguments the value is passed in 4342 the appropriate fp reg and in memory. 4343 */ 4344 4345/* Maximum number of int regs for args. */ 4346#define SPARC_INT_ARG_MAX 6 4347/* Maximum number of fp regs for args. */ 4348#define SPARC_FP_ARG_MAX 16 4349 4350#define ROUND_ADVANCE(SIZE) (((SIZE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) 4351 4352/* Handle the INIT_CUMULATIVE_ARGS macro. 4353 Initialize a variable CUM of type CUMULATIVE_ARGS 4354 for a call to a function whose data type is FNTYPE. 4355 For a library call, FNTYPE is 0. */ 4356 4357void 4358init_cumulative_args (cum, fntype, libname, indirect) 4359 CUMULATIVE_ARGS *cum; 4360 tree fntype; 4361 rtx libname ATTRIBUTE_UNUSED; 4362 int indirect ATTRIBUTE_UNUSED; 4363{ 4364 cum->words = 0; 4365 cum->prototype_p = fntype && TYPE_ARG_TYPES (fntype); 4366 cum->libcall_p = fntype == 0; 4367} 4368 4369/* Compute the slot number to pass an argument in. 4370 Returns the slot number or -1 if passing on the stack. 4371 4372 CUM is a variable of type CUMULATIVE_ARGS which gives info about 4373 the preceding args and about the function being called. 4374 MODE is the argument's machine mode. 4375 TYPE is the data type of the argument (as a tree). 4376 This is null for libcalls where that information may 4377 not be available. 4378 NAMED is nonzero if this argument is a named parameter 4379 (otherwise it is an extra parameter matching an ellipsis). 4380 INCOMING_P is zero for FUNCTION_ARG, nonzero for FUNCTION_INCOMING_ARG. 4381 *PREGNO records the register number to use if scalar type. 4382 *PPADDING records the amount of padding needed in words. */ 4383 4384static int 4385function_arg_slotno (cum, mode, type, named, incoming_p, pregno, ppadding) 4386 const CUMULATIVE_ARGS *cum; 4387 enum machine_mode mode; 4388 tree type; 4389 int named; 4390 int incoming_p; 4391 int *pregno; 4392 int *ppadding; 4393{ 4394 int regbase = (incoming_p 4395 ? SPARC_INCOMING_INT_ARG_FIRST 4396 : SPARC_OUTGOING_INT_ARG_FIRST); 4397 int slotno = cum->words; 4398 int regno; 4399 4400 *ppadding = 0; 4401 4402 if (type != 0 && TREE_ADDRESSABLE (type)) 4403 return -1; 4404 if (TARGET_ARCH32 4405 && type != 0 && mode == BLKmode 4406 && TYPE_ALIGN (type) % PARM_BOUNDARY != 0) 4407 return -1; 4408 4409 switch (mode) 4410 { 4411 case VOIDmode : 4412 /* MODE is VOIDmode when generating the actual call. 4413 See emit_call_1. */ 4414 return -1; 4415 4416 case QImode : case CQImode : 4417 case HImode : case CHImode : 4418 case SImode : case CSImode : 4419 case DImode : case CDImode : 4420 case TImode : case CTImode : 4421 if (slotno >= SPARC_INT_ARG_MAX) 4422 return -1; 4423 regno = regbase + slotno; 4424 break; 4425 4426 case SFmode : case SCmode : 4427 case DFmode : case DCmode : 4428 case TFmode : case TCmode : 4429 if (TARGET_ARCH32) 4430 { 4431 if (slotno >= SPARC_INT_ARG_MAX) 4432 return -1; 4433 regno = regbase + slotno; 4434 } 4435 else 4436 { 4437 if ((mode == TFmode || mode == TCmode) 4438 && (slotno & 1) != 0) 4439 slotno++, *ppadding = 1; 4440 if (TARGET_FPU && named) 4441 { 4442 if (slotno >= SPARC_FP_ARG_MAX) 4443 return -1; 4444 regno = SPARC_FP_ARG_FIRST + slotno * 2; 4445 if (mode == SFmode) 4446 regno++; 4447 } 4448 else 4449 { 4450 if (slotno >= SPARC_INT_ARG_MAX) 4451 return -1; 4452 regno = regbase + slotno; 4453 } 4454 } 4455 break; 4456 4457 case BLKmode : 4458 /* For sparc64, objects requiring 16 byte alignment get it. */ 4459 if (TARGET_ARCH64) 4460 { 4461 if (type && TYPE_ALIGN (type) == 128 && (slotno & 1) != 0) 4462 slotno++, *ppadding = 1; 4463 } 4464 4465 if (TARGET_ARCH32 4466 || (type && TREE_CODE (type) == UNION_TYPE)) 4467 { 4468 if (slotno >= SPARC_INT_ARG_MAX) 4469 return -1; 4470 regno = regbase + slotno; 4471 } 4472 else 4473 { 4474 tree field; 4475 int intregs_p = 0, fpregs_p = 0; 4476 /* The ABI obviously doesn't specify how packed 4477 structures are passed. These are defined to be passed 4478 in int regs if possible, otherwise memory. */ 4479 int packed_p = 0; 4480 4481 /* First see what kinds of registers we need. */ 4482 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field)) 4483 { 4484 if (TREE_CODE (field) == FIELD_DECL) 4485 { 4486 if (TREE_CODE (TREE_TYPE (field)) == REAL_TYPE 4487 && TARGET_FPU) 4488 fpregs_p = 1; 4489 else 4490 intregs_p = 1; 4491 if (DECL_PACKED (field)) 4492 packed_p = 1; 4493 } 4494 } 4495 if (packed_p || !named) 4496 fpregs_p = 0, intregs_p = 1; 4497 4498 /* If all arg slots are filled, then must pass on stack. */ 4499 if (fpregs_p && slotno >= SPARC_FP_ARG_MAX) 4500 return -1; 4501 /* If there are only int args and all int arg slots are filled, 4502 then must pass on stack. */ 4503 if (!fpregs_p && intregs_p && slotno >= SPARC_INT_ARG_MAX) 4504 return -1; 4505 /* Note that even if all int arg slots are filled, fp members may 4506 still be passed in regs if such regs are available. 4507 *PREGNO isn't set because there may be more than one, it's up 4508 to the caller to compute them. */ 4509 return slotno; 4510 } 4511 break; 4512 4513 default : 4514 abort (); 4515 } 4516 4517 *pregno = regno; 4518 return slotno; 4519} 4520 4521/* Handle recursive register counting for structure field layout. */ 4522 4523struct function_arg_record_value_parms 4524{ 4525 rtx ret; /* return expression being built. */ 4526 int slotno; /* slot number of the argument. */ 4527 int named; /* whether the argument is named. */ 4528 int regbase; /* regno of the base register. */ 4529 int stack; /* 1 if part of the argument is on the stack. */ 4530 int intoffset; /* offset of the pending integer field. */ 4531 unsigned int nregs; /* number of words passed in registers. */ 4532}; 4533 4534static void function_arg_record_value_3 4535 PARAMS ((HOST_WIDE_INT, struct function_arg_record_value_parms *)); 4536static void function_arg_record_value_2 4537 PARAMS ((tree, HOST_WIDE_INT, 4538 struct function_arg_record_value_parms *)); 4539static void function_arg_record_value_1 4540 PARAMS ((tree, HOST_WIDE_INT, 4541 struct function_arg_record_value_parms *)); 4542static rtx function_arg_record_value 4543 PARAMS ((tree, enum machine_mode, int, int, int)); 4544 4545/* A subroutine of function_arg_record_value. Traverse the structure 4546 recusively and determine how many registers will be required. */ 4547 4548static void 4549function_arg_record_value_1 (type, startbitpos, parms) 4550 tree type; 4551 HOST_WIDE_INT startbitpos; 4552 struct function_arg_record_value_parms *parms; 4553{ 4554 tree field; 4555 4556 /* The ABI obviously doesn't specify how packed structures are 4557 passed. These are defined to be passed in int regs if possible, 4558 otherwise memory. */ 4559 int packed_p = 0; 4560 4561 /* We need to compute how many registers are needed so we can 4562 allocate the PARALLEL but before we can do that we need to know 4563 whether there are any packed fields. If there are, int regs are 4564 used regardless of whether there are fp values present. */ 4565 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field)) 4566 { 4567 if (TREE_CODE (field) == FIELD_DECL && DECL_PACKED (field)) 4568 { 4569 packed_p = 1; 4570 break; 4571 } 4572 } 4573 4574 /* Compute how many registers we need. */ 4575 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field)) 4576 { 4577 if (TREE_CODE (field) == FIELD_DECL) 4578 { 4579 HOST_WIDE_INT bitpos = startbitpos; 4580 4581 if (DECL_SIZE (field) != 0 4582 && host_integerp (bit_position (field), 1)) 4583 bitpos += int_bit_position (field); 4584 4585 /* ??? FIXME: else assume zero offset. */ 4586 4587 if (TREE_CODE (TREE_TYPE (field)) == RECORD_TYPE) 4588 function_arg_record_value_1 (TREE_TYPE (field), bitpos, parms); 4589 else if ((TREE_CODE (TREE_TYPE (field)) == REAL_TYPE 4590 || (TREE_CODE (TREE_TYPE (field)) == COMPLEX_TYPE 4591 && (TREE_CODE (TREE_TYPE (TREE_TYPE (field))) 4592 == REAL_TYPE))) 4593 && TARGET_FPU 4594 && ! packed_p 4595 && parms->named) 4596 { 4597 if (parms->intoffset != -1) 4598 { 4599 int intslots, this_slotno; 4600 4601 intslots = (bitpos - parms->intoffset + BITS_PER_WORD - 1) 4602 / BITS_PER_WORD; 4603 this_slotno = parms->slotno + parms->intoffset 4604 / BITS_PER_WORD; 4605 4606 if (intslots > 0 && intslots > SPARC_INT_ARG_MAX - this_slotno) 4607 { 4608 intslots = MAX (0, SPARC_INT_ARG_MAX - this_slotno); 4609 /* We need to pass this field on the stack. */ 4610 parms->stack = 1; 4611 } 4612 4613 parms->nregs += intslots; 4614 parms->intoffset = -1; 4615 } 4616 4617 /* There's no need to check this_slotno < SPARC_FP_ARG MAX. 4618 If it wasn't true we wouldn't be here. */ 4619 parms->nregs += 1; 4620 if (TREE_CODE (TREE_TYPE (field)) == COMPLEX_TYPE) 4621 parms->nregs += 1; 4622 } 4623 else 4624 { 4625 if (parms->intoffset == -1) 4626 parms->intoffset = bitpos; 4627 } 4628 } 4629 } 4630} 4631 4632/* A subroutine of function_arg_record_value. Assign the bits of the 4633 structure between parms->intoffset and bitpos to integer registers. */ 4634 4635static void 4636function_arg_record_value_3 (bitpos, parms) 4637 HOST_WIDE_INT bitpos; 4638 struct function_arg_record_value_parms *parms; 4639{ 4640 enum machine_mode mode; 4641 unsigned int regno; 4642 unsigned int startbit, endbit; 4643 int this_slotno, intslots, intoffset; 4644 rtx reg; 4645 4646 if (parms->intoffset == -1) 4647 return; 4648 4649 intoffset = parms->intoffset; 4650 parms->intoffset = -1; 4651 4652 startbit = intoffset & -BITS_PER_WORD; 4653 endbit = (bitpos + BITS_PER_WORD - 1) & -BITS_PER_WORD; 4654 intslots = (endbit - startbit) / BITS_PER_WORD; 4655 this_slotno = parms->slotno + intoffset / BITS_PER_WORD; 4656 4657 intslots = MIN (intslots, SPARC_INT_ARG_MAX - this_slotno); 4658 if (intslots <= 0) 4659 return; 4660 4661 /* If this is the trailing part of a word, only load that much into 4662 the register. Otherwise load the whole register. Note that in 4663 the latter case we may pick up unwanted bits. It's not a problem 4664 at the moment but may wish to revisit. */ 4665 4666 if (intoffset % BITS_PER_WORD != 0) 4667 mode = mode_for_size (BITS_PER_WORD - intoffset % BITS_PER_WORD, 4668 MODE_INT, 0); 4669 else 4670 mode = word_mode; 4671 4672 intoffset /= BITS_PER_UNIT; 4673 do 4674 { 4675 regno = parms->regbase + this_slotno; 4676 reg = gen_rtx_REG (mode, regno); 4677 XVECEXP (parms->ret, 0, parms->stack + parms->nregs) 4678 = gen_rtx_EXPR_LIST (VOIDmode, reg, GEN_INT (intoffset)); 4679 4680 this_slotno += 1; 4681 intoffset = (intoffset | (UNITS_PER_WORD-1)) + 1; 4682 parms->nregs += 1; 4683 intslots -= 1; 4684 } 4685 while (intslots > 0); 4686} 4687 4688/* A subroutine of function_arg_record_value. Traverse the structure 4689 recursively and assign bits to floating point registers. Track which 4690 bits in between need integer registers; invoke function_arg_record_value_3 4691 to make that happen. */ 4692 4693static void 4694function_arg_record_value_2 (type, startbitpos, parms) 4695 tree type; 4696 HOST_WIDE_INT startbitpos; 4697 struct function_arg_record_value_parms *parms; 4698{ 4699 tree field; 4700 int packed_p = 0; 4701 4702 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field)) 4703 { 4704 if (TREE_CODE (field) == FIELD_DECL && DECL_PACKED (field)) 4705 { 4706 packed_p = 1; 4707 break; 4708 } 4709 } 4710 4711 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field)) 4712 { 4713 if (TREE_CODE (field) == FIELD_DECL) 4714 { 4715 HOST_WIDE_INT bitpos = startbitpos; 4716 4717 if (DECL_SIZE (field) != 0 4718 && host_integerp (bit_position (field), 1)) 4719 bitpos += int_bit_position (field); 4720 4721 /* ??? FIXME: else assume zero offset. */ 4722 4723 if (TREE_CODE (TREE_TYPE (field)) == RECORD_TYPE) 4724 function_arg_record_value_2 (TREE_TYPE (field), bitpos, parms); 4725 else if ((TREE_CODE (TREE_TYPE (field)) == REAL_TYPE 4726 || (TREE_CODE (TREE_TYPE (field)) == COMPLEX_TYPE 4727 && (TREE_CODE (TREE_TYPE (TREE_TYPE (field))) 4728 == REAL_TYPE))) 4729 && TARGET_FPU 4730 && ! packed_p 4731 && parms->named) 4732 { 4733 int this_slotno = parms->slotno + bitpos / BITS_PER_WORD; 4734 int regno; 4735 enum machine_mode mode = DECL_MODE (field); 4736 rtx reg; 4737 4738 function_arg_record_value_3 (bitpos, parms); 4739 regno = SPARC_FP_ARG_FIRST + this_slotno * 2 4740 + ((mode == SFmode || mode == SCmode) 4741 && (bitpos & 32) != 0); 4742 switch (mode) 4743 { 4744 case SCmode: mode = SFmode; break; 4745 case DCmode: mode = DFmode; break; 4746 case TCmode: mode = TFmode; break; 4747 default: break; 4748 } 4749 reg = gen_rtx_REG (mode, regno); 4750 XVECEXP (parms->ret, 0, parms->stack + parms->nregs) 4751 = gen_rtx_EXPR_LIST (VOIDmode, reg, 4752 GEN_INT (bitpos / BITS_PER_UNIT)); 4753 parms->nregs += 1; 4754 if (TREE_CODE (TREE_TYPE (field)) == COMPLEX_TYPE) 4755 { 4756 regno += GET_MODE_SIZE (mode) / 4; 4757 reg = gen_rtx_REG (mode, regno); 4758 XVECEXP (parms->ret, 0, parms->stack + parms->nregs) 4759 = gen_rtx_EXPR_LIST (VOIDmode, reg, 4760 GEN_INT ((bitpos + GET_MODE_BITSIZE (mode)) 4761 / BITS_PER_UNIT)); 4762 parms->nregs += 1; 4763 } 4764 } 4765 else 4766 { 4767 if (parms->intoffset == -1) 4768 parms->intoffset = bitpos; 4769 } 4770 } 4771 } 4772} 4773 4774/* Used by function_arg and function_value to implement the complex 4775 conventions of the 64-bit ABI for passing and returning structures. 4776 Return an expression valid as a return value for the two macros 4777 FUNCTION_ARG and FUNCTION_VALUE. 4778 4779 TYPE is the data type of the argument (as a tree). 4780 This is null for libcalls where that information may 4781 not be available. 4782 MODE is the argument's machine mode. 4783 SLOTNO is the index number of the argument's slot in the parameter array. 4784 NAMED is nonzero if this argument is a named parameter 4785 (otherwise it is an extra parameter matching an ellipsis). 4786 REGBASE is the regno of the base register for the parameter array. */ 4787 4788static rtx 4789function_arg_record_value (type, mode, slotno, named, regbase) 4790 tree type; 4791 enum machine_mode mode; 4792 int slotno, named, regbase; 4793{ 4794 HOST_WIDE_INT typesize = int_size_in_bytes (type); 4795 struct function_arg_record_value_parms parms; 4796 unsigned int nregs; 4797 4798 parms.ret = NULL_RTX; 4799 parms.slotno = slotno; 4800 parms.named = named; 4801 parms.regbase = regbase; 4802 parms.stack = 0; 4803 4804 /* Compute how many registers we need. */ 4805 parms.nregs = 0; 4806 parms.intoffset = 0; 4807 function_arg_record_value_1 (type, 0, &parms); 4808 4809 if (parms.intoffset != -1) 4810 { 4811 unsigned int startbit, endbit; 4812 int intslots, this_slotno; 4813 4814 startbit = parms.intoffset & -BITS_PER_WORD; 4815 endbit = (typesize*BITS_PER_UNIT + BITS_PER_WORD - 1) & -BITS_PER_WORD; 4816 intslots = (endbit - startbit) / BITS_PER_WORD; 4817 this_slotno = slotno + parms.intoffset / BITS_PER_WORD; 4818 4819 if (intslots > 0 && intslots > SPARC_INT_ARG_MAX - this_slotno) 4820 { 4821 intslots = MAX (0, SPARC_INT_ARG_MAX - this_slotno); 4822 /* We need to pass this field on the stack. */ 4823 parms.stack = 1; 4824 } 4825 4826 parms.nregs += intslots; 4827 } 4828 nregs = parms.nregs; 4829 4830 /* Allocate the vector and handle some annoying special cases. */ 4831 if (nregs == 0) 4832 { 4833 /* ??? Empty structure has no value? Duh? */ 4834 if (typesize <= 0) 4835 { 4836 /* Though there's nothing really to store, return a word register 4837 anyway so the rest of gcc doesn't go nuts. Returning a PARALLEL 4838 leads to breakage due to the fact that there are zero bytes to 4839 load. */ 4840 return gen_rtx_REG (mode, regbase); 4841 } 4842 else 4843 { 4844 /* ??? C++ has structures with no fields, and yet a size. Give up 4845 for now and pass everything back in integer registers. */ 4846 nregs = (typesize + UNITS_PER_WORD - 1) / UNITS_PER_WORD; 4847 } 4848 if (nregs + slotno > SPARC_INT_ARG_MAX) 4849 nregs = SPARC_INT_ARG_MAX - slotno; 4850 } 4851 if (nregs == 0) 4852 abort (); 4853 4854 parms.ret = gen_rtx_PARALLEL (mode, rtvec_alloc (parms.stack + nregs)); 4855 4856 /* If at least one field must be passed on the stack, generate 4857 (parallel [(expr_list (nil) ...) ...]) so that all fields will 4858 also be passed on the stack. We can't do much better because the 4859 semantics of FUNCTION_ARG_PARTIAL_NREGS doesn't handle the case 4860 of structures for which the fields passed exclusively in registers 4861 are not at the beginning of the structure. */ 4862 if (parms.stack) 4863 XVECEXP (parms.ret, 0, 0) 4864 = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx); 4865 4866 /* Fill in the entries. */ 4867 parms.nregs = 0; 4868 parms.intoffset = 0; 4869 function_arg_record_value_2 (type, 0, &parms); 4870 function_arg_record_value_3 (typesize * BITS_PER_UNIT, &parms); 4871 4872 if (parms.nregs != nregs) 4873 abort (); 4874 4875 return parms.ret; 4876} 4877 4878/* Handle the FUNCTION_ARG macro. 4879 Determine where to put an argument to a function. 4880 Value is zero to push the argument on the stack, 4881 or a hard register in which to store the argument. 4882 4883 CUM is a variable of type CUMULATIVE_ARGS which gives info about 4884 the preceding args and about the function being called. 4885 MODE is the argument's machine mode. 4886 TYPE is the data type of the argument (as a tree). 4887 This is null for libcalls where that information may 4888 not be available. 4889 NAMED is nonzero if this argument is a named parameter 4890 (otherwise it is an extra parameter matching an ellipsis). 4891 INCOMING_P is zero for FUNCTION_ARG, nonzero for FUNCTION_INCOMING_ARG. */ 4892 4893rtx 4894function_arg (cum, mode, type, named, incoming_p) 4895 const CUMULATIVE_ARGS *cum; 4896 enum machine_mode mode; 4897 tree type; 4898 int named; 4899 int incoming_p; 4900{ 4901 int regbase = (incoming_p 4902 ? SPARC_INCOMING_INT_ARG_FIRST 4903 : SPARC_OUTGOING_INT_ARG_FIRST); 4904 int slotno, regno, padding; 4905 rtx reg; 4906 4907 slotno = function_arg_slotno (cum, mode, type, named, incoming_p, 4908 ®no, &padding); 4909 4910 if (slotno == -1) 4911 return 0; 4912 4913 if (TARGET_ARCH32) 4914 { 4915 reg = gen_rtx_REG (mode, regno); 4916 return reg; 4917 } 4918 4919 /* v9 fp args in reg slots beyond the int reg slots get passed in regs 4920 but also have the slot allocated for them. 4921 If no prototype is in scope fp values in register slots get passed 4922 in two places, either fp regs and int regs or fp regs and memory. */ 4923 if ((GET_MODE_CLASS (mode) == MODE_FLOAT 4924 || GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT) 4925 && SPARC_FP_REG_P (regno)) 4926 { 4927 reg = gen_rtx_REG (mode, regno); 4928 if (cum->prototype_p || cum->libcall_p) 4929 { 4930 /* "* 2" because fp reg numbers are recorded in 4 byte 4931 quantities. */ 4932#if 0 4933 /* ??? This will cause the value to be passed in the fp reg and 4934 in the stack. When a prototype exists we want to pass the 4935 value in the reg but reserve space on the stack. That's an 4936 optimization, and is deferred [for a bit]. */ 4937 if ((regno - SPARC_FP_ARG_FIRST) >= SPARC_INT_ARG_MAX * 2) 4938 return gen_rtx_PARALLEL (mode, 4939 gen_rtvec (2, 4940 gen_rtx_EXPR_LIST (VOIDmode, 4941 NULL_RTX, const0_rtx), 4942 gen_rtx_EXPR_LIST (VOIDmode, 4943 reg, const0_rtx))); 4944 else 4945#else 4946 /* ??? It seems that passing back a register even when past 4947 the area declared by REG_PARM_STACK_SPACE will allocate 4948 space appropriately, and will not copy the data onto the 4949 stack, exactly as we desire. 4950 4951 This is due to locate_and_pad_parm being called in 4952 expand_call whenever reg_parm_stack_space > 0, which 4953 while benefical to our example here, would seem to be 4954 in error from what had been intended. Ho hum... -- r~ */ 4955#endif 4956 return reg; 4957 } 4958 else 4959 { 4960 rtx v0, v1; 4961 4962 if ((regno - SPARC_FP_ARG_FIRST) < SPARC_INT_ARG_MAX * 2) 4963 { 4964 int intreg; 4965 4966 /* On incoming, we don't need to know that the value 4967 is passed in %f0 and %i0, and it confuses other parts 4968 causing needless spillage even on the simplest cases. */ 4969 if (incoming_p) 4970 return reg; 4971 4972 intreg = (SPARC_OUTGOING_INT_ARG_FIRST 4973 + (regno - SPARC_FP_ARG_FIRST) / 2); 4974 4975 v0 = gen_rtx_EXPR_LIST (VOIDmode, reg, const0_rtx); 4976 v1 = gen_rtx_EXPR_LIST (VOIDmode, gen_rtx_REG (mode, intreg), 4977 const0_rtx); 4978 return gen_rtx_PARALLEL (mode, gen_rtvec (2, v0, v1)); 4979 } 4980 else 4981 { 4982 v0 = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx); 4983 v1 = gen_rtx_EXPR_LIST (VOIDmode, reg, const0_rtx); 4984 return gen_rtx_PARALLEL (mode, gen_rtvec (2, v0, v1)); 4985 } 4986 } 4987 } 4988 else if (type && TREE_CODE (type) == RECORD_TYPE) 4989 { 4990 /* Structures up to 16 bytes in size are passed in arg slots on the 4991 stack and are promoted to registers where possible. */ 4992 4993 if (int_size_in_bytes (type) > 16) 4994 abort (); /* shouldn't get here */ 4995 4996 return function_arg_record_value (type, mode, slotno, named, regbase); 4997 } 4998 else if (type && TREE_CODE (type) == UNION_TYPE) 4999 { 5000 enum machine_mode mode; 5001 int bytes = int_size_in_bytes (type); 5002 5003 if (bytes > 16) 5004 abort (); 5005 5006 mode = mode_for_size (bytes * BITS_PER_UNIT, MODE_INT, 0); 5007 reg = gen_rtx_REG (mode, regno); 5008 } 5009 else 5010 { 5011 /* Scalar or complex int. */ 5012 reg = gen_rtx_REG (mode, regno); 5013 } 5014 5015 return reg; 5016} 5017 5018/* Handle the FUNCTION_ARG_PARTIAL_NREGS macro. 5019 For an arg passed partly in registers and partly in memory, 5020 this is the number of registers used. 5021 For args passed entirely in registers or entirely in memory, zero. 5022 5023 Any arg that starts in the first 6 regs but won't entirely fit in them 5024 needs partial registers on v8. On v9, structures with integer 5025 values in arg slots 5,6 will be passed in %o5 and SP+176, and complex fp 5026 values that begin in the last fp reg [where "last fp reg" varies with the 5027 mode] will be split between that reg and memory. */ 5028 5029int 5030function_arg_partial_nregs (cum, mode, type, named) 5031 const CUMULATIVE_ARGS *cum; 5032 enum machine_mode mode; 5033 tree type; 5034 int named; 5035{ 5036 int slotno, regno, padding; 5037 5038 /* We pass 0 for incoming_p here, it doesn't matter. */ 5039 slotno = function_arg_slotno (cum, mode, type, named, 0, ®no, &padding); 5040 5041 if (slotno == -1) 5042 return 0; 5043 5044 if (TARGET_ARCH32) 5045 { 5046 if ((slotno + (mode == BLKmode 5047 ? ROUND_ADVANCE (int_size_in_bytes (type)) 5048 : ROUND_ADVANCE (GET_MODE_SIZE (mode)))) 5049 > NPARM_REGS (SImode)) 5050 return NPARM_REGS (SImode) - slotno; 5051 return 0; 5052 } 5053 else 5054 { 5055 if (type && AGGREGATE_TYPE_P (type)) 5056 { 5057 int size = int_size_in_bytes (type); 5058 int align = TYPE_ALIGN (type); 5059 5060 if (align == 16) 5061 slotno += slotno & 1; 5062 if (size > 8 && size <= 16 5063 && slotno == SPARC_INT_ARG_MAX - 1) 5064 return 1; 5065 } 5066 else if (GET_MODE_CLASS (mode) == MODE_COMPLEX_INT 5067 || (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT 5068 && ! TARGET_FPU)) 5069 { 5070 if (GET_MODE_ALIGNMENT (mode) == 128) 5071 { 5072 slotno += slotno & 1; 5073 if (slotno == SPARC_INT_ARG_MAX - 2) 5074 return 1; 5075 } 5076 else 5077 { 5078 if (slotno == SPARC_INT_ARG_MAX - 1) 5079 return 1; 5080 } 5081 } 5082 else if (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT) 5083 { 5084 if (GET_MODE_ALIGNMENT (mode) == 128) 5085 slotno += slotno & 1; 5086 if ((slotno + GET_MODE_SIZE (mode) / UNITS_PER_WORD) 5087 > SPARC_FP_ARG_MAX) 5088 return 1; 5089 } 5090 return 0; 5091 } 5092} 5093 5094/* Handle the FUNCTION_ARG_PASS_BY_REFERENCE macro. 5095 !v9: The SPARC ABI stipulates passing struct arguments (of any size) and 5096 quad-precision floats by invisible reference. 5097 v9: Aggregates greater than 16 bytes are passed by reference. 5098 For Pascal, also pass arrays by reference. */ 5099 5100int 5101function_arg_pass_by_reference (cum, mode, type, named) 5102 const CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED; 5103 enum machine_mode mode; 5104 tree type; 5105 int named ATTRIBUTE_UNUSED; 5106{ 5107 if (TARGET_ARCH32) 5108 { 5109 return ((type && AGGREGATE_TYPE_P (type)) 5110 || mode == TFmode || mode == TCmode); 5111 } 5112 else 5113 { 5114 return ((type && TREE_CODE (type) == ARRAY_TYPE) 5115 /* Consider complex values as aggregates, so care for TCmode. */ 5116 || GET_MODE_SIZE (mode) > 16 5117 || (type 5118 && AGGREGATE_TYPE_P (type) 5119 && (unsigned HOST_WIDE_INT) int_size_in_bytes (type) > 16)); 5120 } 5121} 5122 5123/* Handle the FUNCTION_ARG_ADVANCE macro. 5124 Update the data in CUM to advance over an argument 5125 of mode MODE and data type TYPE. 5126 TYPE is null for libcalls where that information may not be available. */ 5127 5128void 5129function_arg_advance (cum, mode, type, named) 5130 CUMULATIVE_ARGS *cum; 5131 enum machine_mode mode; 5132 tree type; 5133 int named; 5134{ 5135 int slotno, regno, padding; 5136 5137 /* We pass 0 for incoming_p here, it doesn't matter. */ 5138 slotno = function_arg_slotno (cum, mode, type, named, 0, ®no, &padding); 5139 5140 /* If register required leading padding, add it. */ 5141 if (slotno != -1) 5142 cum->words += padding; 5143 5144 if (TARGET_ARCH32) 5145 { 5146 cum->words += (mode != BLKmode 5147 ? ROUND_ADVANCE (GET_MODE_SIZE (mode)) 5148 : ROUND_ADVANCE (int_size_in_bytes (type))); 5149 } 5150 else 5151 { 5152 if (type && AGGREGATE_TYPE_P (type)) 5153 { 5154 int size = int_size_in_bytes (type); 5155 5156 if (size <= 8) 5157 ++cum->words; 5158 else if (size <= 16) 5159 cum->words += 2; 5160 else /* passed by reference */ 5161 ++cum->words; 5162 } 5163 else if (GET_MODE_CLASS (mode) == MODE_COMPLEX_INT) 5164 { 5165 cum->words += 2; 5166 } 5167 else if (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT) 5168 { 5169 cum->words += GET_MODE_SIZE (mode) / UNITS_PER_WORD; 5170 } 5171 else 5172 { 5173 cum->words += (mode != BLKmode 5174 ? ROUND_ADVANCE (GET_MODE_SIZE (mode)) 5175 : ROUND_ADVANCE (int_size_in_bytes (type))); 5176 } 5177 } 5178} 5179 5180/* Handle the FUNCTION_ARG_PADDING macro. 5181 For the 64 bit ABI structs are always stored left shifted in their 5182 argument slot. */ 5183 5184enum direction 5185function_arg_padding (mode, type) 5186 enum machine_mode mode; 5187 tree type; 5188{ 5189 if (TARGET_ARCH64 && type != 0 && AGGREGATE_TYPE_P (type)) 5190 return upward; 5191 5192 /* This is the default definition. */ 5193 return (! BYTES_BIG_ENDIAN 5194 ? upward 5195 : ((mode == BLKmode 5196 ? (type && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST 5197 && int_size_in_bytes (type) < (PARM_BOUNDARY / BITS_PER_UNIT)) 5198 : GET_MODE_BITSIZE (mode) < PARM_BOUNDARY) 5199 ? downward : upward)); 5200} 5201 5202/* Handle FUNCTION_VALUE, FUNCTION_OUTGOING_VALUE, and LIBCALL_VALUE macros. 5203 For v9, function return values are subject to the same rules as arguments, 5204 except that up to 32-bytes may be returned in registers. */ 5205 5206rtx 5207function_value (type, mode, incoming_p) 5208 tree type; 5209 enum machine_mode mode; 5210 int incoming_p; 5211{ 5212 int regno; 5213 int regbase = (incoming_p 5214 ? SPARC_OUTGOING_INT_ARG_FIRST 5215 : SPARC_INCOMING_INT_ARG_FIRST); 5216 5217 if (TARGET_ARCH64 && type) 5218 { 5219 if (TREE_CODE (type) == RECORD_TYPE) 5220 { 5221 /* Structures up to 32 bytes in size are passed in registers, 5222 promoted to fp registers where possible. */ 5223 5224 if (int_size_in_bytes (type) > 32) 5225 abort (); /* shouldn't get here */ 5226 5227 return function_arg_record_value (type, mode, 0, 1, regbase); 5228 } 5229 else if (AGGREGATE_TYPE_P (type)) 5230 { 5231 /* All other aggregate types are passed in an integer register 5232 in a mode corresponding to the size of the type. */ 5233 HOST_WIDE_INT bytes = int_size_in_bytes (type); 5234 5235 if (bytes > 32) 5236 abort (); 5237 5238 mode = mode_for_size (bytes * BITS_PER_UNIT, MODE_INT, 0); 5239 } 5240 } 5241 5242 if (TARGET_ARCH64 5243 && GET_MODE_CLASS (mode) == MODE_INT 5244 && GET_MODE_SIZE (mode) < UNITS_PER_WORD 5245 && type && ! AGGREGATE_TYPE_P (type)) 5246 mode = DImode; 5247 5248 if (incoming_p) 5249 regno = BASE_RETURN_VALUE_REG (mode); 5250 else 5251 regno = BASE_OUTGOING_VALUE_REG (mode); 5252 5253 return gen_rtx_REG (mode, regno); 5254} 5255 5256/* Do what is necessary for `va_start'. We look at the current function 5257 to determine if stdarg or varargs is used and return the address of 5258 the first unnamed parameter. */ 5259 5260rtx 5261sparc_builtin_saveregs () 5262{ 5263 int first_reg = current_function_args_info.words; 5264 rtx address; 5265 int regno; 5266 5267 for (regno = first_reg; regno < NPARM_REGS (word_mode); regno++) 5268 emit_move_insn (gen_rtx_MEM (word_mode, 5269 gen_rtx_PLUS (Pmode, 5270 frame_pointer_rtx, 5271 GEN_INT (FIRST_PARM_OFFSET (0) 5272 + (UNITS_PER_WORD 5273 * regno)))), 5274 gen_rtx_REG (word_mode, 5275 BASE_INCOMING_ARG_REG (word_mode) + regno)); 5276 5277 address = gen_rtx_PLUS (Pmode, 5278 frame_pointer_rtx, 5279 GEN_INT (FIRST_PARM_OFFSET (0) 5280 + UNITS_PER_WORD * first_reg)); 5281 5282 return address; 5283} 5284 5285/* Implement `va_start' for varargs and stdarg. */ 5286 5287void 5288sparc_va_start (valist, nextarg) 5289 tree valist; 5290 rtx nextarg; 5291{ 5292 nextarg = expand_builtin_saveregs (); 5293 std_expand_builtin_va_start (valist, nextarg); 5294} 5295 5296/* Implement `va_arg'. */ 5297 5298rtx 5299sparc_va_arg (valist, type) 5300 tree valist, type; 5301{ 5302 HOST_WIDE_INT size, rsize, align; 5303 tree addr, incr; 5304 rtx addr_rtx; 5305 int indirect = 0; 5306 5307 /* Round up sizeof(type) to a word. */ 5308 size = int_size_in_bytes (type); 5309 rsize = (size + UNITS_PER_WORD - 1) & -UNITS_PER_WORD; 5310 align = 0; 5311 5312 if (TARGET_ARCH64) 5313 { 5314 if (TYPE_ALIGN (type) >= 2 * (unsigned) BITS_PER_WORD) 5315 align = 2 * UNITS_PER_WORD; 5316 5317 if (AGGREGATE_TYPE_P (type)) 5318 { 5319 if ((unsigned HOST_WIDE_INT) size > 16) 5320 { 5321 indirect = 1; 5322 size = rsize = UNITS_PER_WORD; 5323 } 5324 /* SPARC v9 ABI states that structures up to 8 bytes in size are 5325 given one 8 byte slot. */ 5326 else if (size == 0) 5327 size = rsize = UNITS_PER_WORD; 5328 else 5329 size = rsize; 5330 } 5331 } 5332 else 5333 { 5334 if (AGGREGATE_TYPE_P (type) 5335 || TYPE_MODE (type) == TFmode 5336 || TYPE_MODE (type) == TCmode) 5337 { 5338 indirect = 1; 5339 size = rsize = UNITS_PER_WORD; 5340 } 5341 } 5342 5343 incr = valist; 5344 if (align) 5345 { 5346 incr = fold (build (PLUS_EXPR, ptr_type_node, incr, 5347 build_int_2 (align - 1, 0))); 5348 incr = fold (build (BIT_AND_EXPR, ptr_type_node, incr, 5349 build_int_2 (-align, -1))); 5350 } 5351 5352 addr = incr = save_expr (incr); 5353 if (BYTES_BIG_ENDIAN && size < rsize) 5354 { 5355 addr = fold (build (PLUS_EXPR, ptr_type_node, incr, 5356 build_int_2 (rsize - size, 0))); 5357 } 5358 incr = fold (build (PLUS_EXPR, ptr_type_node, incr, 5359 build_int_2 (rsize, 0))); 5360 5361 incr = build (MODIFY_EXPR, ptr_type_node, valist, incr); 5362 TREE_SIDE_EFFECTS (incr) = 1; 5363 expand_expr (incr, const0_rtx, VOIDmode, EXPAND_NORMAL); 5364 5365 addr_rtx = expand_expr (addr, NULL, Pmode, EXPAND_NORMAL); 5366 5367 /* If the address isn't aligned properly for the type, 5368 we may need to copy to a temporary. 5369 FIXME: This is inefficient. Usually we can do this 5370 in registers. */ 5371 if (align == 0 5372 && TYPE_ALIGN (type) > BITS_PER_WORD 5373 && !indirect) 5374 { 5375 /* FIXME: We really need to specify that the temporary is live 5376 for the whole function because expand_builtin_va_arg wants 5377 the alias set to be get_varargs_alias_set (), but in this 5378 case the alias set is that for TYPE and if the memory gets 5379 reused it will be reused with alias set TYPE. */ 5380 rtx tmp = assign_temp (type, 0, 1, 0); 5381 rtx dest_addr; 5382 5383 addr_rtx = force_reg (Pmode, addr_rtx); 5384 addr_rtx = gen_rtx_MEM (BLKmode, addr_rtx); 5385 set_mem_alias_set (addr_rtx, get_varargs_alias_set ()); 5386 set_mem_align (addr_rtx, BITS_PER_WORD); 5387 tmp = shallow_copy_rtx (tmp); 5388 PUT_MODE (tmp, BLKmode); 5389 set_mem_alias_set (tmp, 0); 5390 5391 dest_addr = emit_block_move (tmp, addr_rtx, GEN_INT (rsize), 5392 BLOCK_OP_NORMAL); 5393 if (dest_addr != NULL_RTX) 5394 addr_rtx = dest_addr; 5395 else 5396 addr_rtx = XCEXP (tmp, 0, MEM); 5397 } 5398 5399 if (indirect) 5400 { 5401 addr_rtx = force_reg (Pmode, addr_rtx); 5402 addr_rtx = gen_rtx_MEM (Pmode, addr_rtx); 5403 set_mem_alias_set (addr_rtx, get_varargs_alias_set ()); 5404 } 5405 5406 return addr_rtx; 5407} 5408 5409/* Return the string to output a conditional branch to LABEL, which is 5410 the operand number of the label. OP is the conditional expression. 5411 XEXP (OP, 0) is assumed to be a condition code register (integer or 5412 floating point) and its mode specifies what kind of comparison we made. 5413 5414 REVERSED is nonzero if we should reverse the sense of the comparison. 5415 5416 ANNUL is nonzero if we should generate an annulling branch. 5417 5418 NOOP is nonzero if we have to follow this branch by a noop. 5419 5420 INSN, if set, is the insn. */ 5421 5422char * 5423output_cbranch (op, dest, label, reversed, annul, noop, insn) 5424 rtx op, dest; 5425 int label; 5426 int reversed, annul, noop; 5427 rtx insn; 5428{ 5429 static char string[50]; 5430 enum rtx_code code = GET_CODE (op); 5431 rtx cc_reg = XEXP (op, 0); 5432 enum machine_mode mode = GET_MODE (cc_reg); 5433 const char *labelno, *branch; 5434 int spaces = 8, far; 5435 char *p; 5436 5437 /* v9 branches are limited to +-1MB. If it is too far away, 5438 change 5439 5440 bne,pt %xcc, .LC30 5441 5442 to 5443 5444 be,pn %xcc, .+12 5445 nop 5446 ba .LC30 5447 5448 and 5449 5450 fbne,a,pn %fcc2, .LC29 5451 5452 to 5453 5454 fbe,pt %fcc2, .+16 5455 nop 5456 ba .LC29 */ 5457 5458 far = get_attr_length (insn) >= 3; 5459 if (reversed ^ far) 5460 { 5461 /* Reversal of FP compares takes care -- an ordered compare 5462 becomes an unordered compare and vice versa. */ 5463 if (mode == CCFPmode || mode == CCFPEmode) 5464 code = reverse_condition_maybe_unordered (code); 5465 else 5466 code = reverse_condition (code); 5467 } 5468 5469 /* Start by writing the branch condition. */ 5470 if (mode == CCFPmode || mode == CCFPEmode) 5471 { 5472 switch (code) 5473 { 5474 case NE: 5475 branch = "fbne"; 5476 break; 5477 case EQ: 5478 branch = "fbe"; 5479 break; 5480 case GE: 5481 branch = "fbge"; 5482 break; 5483 case GT: 5484 branch = "fbg"; 5485 break; 5486 case LE: 5487 branch = "fble"; 5488 break; 5489 case LT: 5490 branch = "fbl"; 5491 break; 5492 case UNORDERED: 5493 branch = "fbu"; 5494 break; 5495 case ORDERED: 5496 branch = "fbo"; 5497 break; 5498 case UNGT: 5499 branch = "fbug"; 5500 break; 5501 case UNLT: 5502 branch = "fbul"; 5503 break; 5504 case UNEQ: 5505 branch = "fbue"; 5506 break; 5507 case UNGE: 5508 branch = "fbuge"; 5509 break; 5510 case UNLE: 5511 branch = "fbule"; 5512 break; 5513 case LTGT: 5514 branch = "fblg"; 5515 break; 5516 5517 default: 5518 abort (); 5519 } 5520 5521 /* ??? !v9: FP branches cannot be preceded by another floating point 5522 insn. Because there is currently no concept of pre-delay slots, 5523 we can fix this only by always emitting a nop before a floating 5524 point branch. */ 5525 5526 string[0] = '\0'; 5527 if (! TARGET_V9) 5528 strcpy (string, "nop\n\t"); 5529 strcat (string, branch); 5530 } 5531 else 5532 { 5533 switch (code) 5534 { 5535 case NE: 5536 branch = "bne"; 5537 break; 5538 case EQ: 5539 branch = "be"; 5540 break; 5541 case GE: 5542 if (mode == CC_NOOVmode || mode == CCX_NOOVmode) 5543 branch = "bpos"; 5544 else 5545 branch = "bge"; 5546 break; 5547 case GT: 5548 branch = "bg"; 5549 break; 5550 case LE: 5551 branch = "ble"; 5552 break; 5553 case LT: 5554 if (mode == CC_NOOVmode || mode == CCX_NOOVmode) 5555 branch = "bneg"; 5556 else 5557 branch = "bl"; 5558 break; 5559 case GEU: 5560 branch = "bgeu"; 5561 break; 5562 case GTU: 5563 branch = "bgu"; 5564 break; 5565 case LEU: 5566 branch = "bleu"; 5567 break; 5568 case LTU: 5569 branch = "blu"; 5570 break; 5571 5572 default: 5573 abort (); 5574 } 5575 strcpy (string, branch); 5576 } 5577 spaces -= strlen (branch); 5578 p = strchr (string, '\0'); 5579 5580 /* Now add the annulling, the label, and a possible noop. */ 5581 if (annul && ! far) 5582 { 5583 strcpy (p, ",a"); 5584 p += 2; 5585 spaces -= 2; 5586 } 5587 5588 if (! TARGET_V9) 5589 labelno = ""; 5590 else 5591 { 5592 rtx note; 5593 int v8 = 0; 5594 5595 if (! far && insn && INSN_ADDRESSES_SET_P ()) 5596 { 5597 int delta = (INSN_ADDRESSES (INSN_UID (dest)) 5598 - INSN_ADDRESSES (INSN_UID (insn))); 5599 /* Leave some instructions for "slop". */ 5600 if (delta < -260000 || delta >= 260000) 5601 v8 = 1; 5602 } 5603 5604 if (mode == CCFPmode || mode == CCFPEmode) 5605 { 5606 static char v9_fcc_labelno[] = "%%fccX, "; 5607 /* Set the char indicating the number of the fcc reg to use. */ 5608 v9_fcc_labelno[5] = REGNO (cc_reg) - SPARC_FIRST_V9_FCC_REG + '0'; 5609 labelno = v9_fcc_labelno; 5610 if (v8) 5611 { 5612 if (REGNO (cc_reg) == SPARC_FCC_REG) 5613 labelno = ""; 5614 else 5615 abort (); 5616 } 5617 } 5618 else if (mode == CCXmode || mode == CCX_NOOVmode) 5619 { 5620 labelno = "%%xcc, "; 5621 if (v8) 5622 abort (); 5623 } 5624 else 5625 { 5626 labelno = "%%icc, "; 5627 if (v8) 5628 labelno = ""; 5629 } 5630 5631 if (*labelno && insn && (note = find_reg_note (insn, REG_BR_PROB, NULL_RTX))) 5632 { 5633 strcpy (p, 5634 ((INTVAL (XEXP (note, 0)) >= REG_BR_PROB_BASE / 2) ^ far) 5635 ? ",pt" : ",pn"); 5636 p += 3; 5637 spaces -= 3; 5638 } 5639 } 5640 if (spaces > 0) 5641 *p++ = '\t'; 5642 else 5643 *p++ = ' '; 5644 strcpy (p, labelno); 5645 p = strchr (p, '\0'); 5646 if (far) 5647 { 5648 strcpy (p, ".+12\n\tnop\n\tb\t"); 5649 if (annul || noop) 5650 p[3] = '6'; 5651 p += 13; 5652 } 5653 *p++ = '%'; 5654 *p++ = 'l'; 5655 /* Set the char indicating the number of the operand containing the 5656 label_ref. */ 5657 *p++ = label + '0'; 5658 *p = '\0'; 5659 if (noop) 5660 strcpy (p, "\n\tnop"); 5661 5662 return string; 5663} 5664 5665/* Emit a library call comparison between floating point X and Y. 5666 COMPARISON is the rtl operator to compare with (EQ, NE, GT, etc.). 5667 TARGET_ARCH64 uses _Qp_* functions, which use pointers to TFmode 5668 values as arguments instead of the TFmode registers themselves, 5669 that's why we cannot call emit_float_lib_cmp. */ 5670void 5671sparc_emit_float_lib_cmp (x, y, comparison) 5672 rtx x, y; 5673 enum rtx_code comparison; 5674{ 5675 const char *qpfunc; 5676 rtx slot0, slot1, result, tem, tem2; 5677 enum machine_mode mode; 5678 5679 switch (comparison) 5680 { 5681 case EQ: 5682 qpfunc = (TARGET_ARCH64) ? "_Qp_feq" : "_Q_feq"; 5683 break; 5684 5685 case NE: 5686 qpfunc = (TARGET_ARCH64) ? "_Qp_fne" : "_Q_fne"; 5687 break; 5688 5689 case GT: 5690 qpfunc = (TARGET_ARCH64) ? "_Qp_fgt" : "_Q_fgt"; 5691 break; 5692 5693 case GE: 5694 qpfunc = (TARGET_ARCH64) ? "_Qp_fge" : "_Q_fge"; 5695 break; 5696 5697 case LT: 5698 qpfunc = (TARGET_ARCH64) ? "_Qp_flt" : "_Q_flt"; 5699 break; 5700 5701 case LE: 5702 qpfunc = (TARGET_ARCH64) ? "_Qp_fle" : "_Q_fle"; 5703 break; 5704 5705 case ORDERED: 5706 case UNORDERED: 5707 case UNGT: 5708 case UNLT: 5709 case UNEQ: 5710 case UNGE: 5711 case UNLE: 5712 case LTGT: 5713 qpfunc = (TARGET_ARCH64) ? "_Qp_cmp" : "_Q_cmp"; 5714 break; 5715 5716 default: 5717 abort(); 5718 break; 5719 } 5720 5721 if (TARGET_ARCH64) 5722 { 5723 if (GET_CODE (x) != MEM) 5724 { 5725 slot0 = assign_stack_temp (TFmode, GET_MODE_SIZE(TFmode), 0); 5726 emit_insn (gen_rtx_SET (VOIDmode, slot0, x)); 5727 } 5728 else 5729 slot0 = x; 5730 5731 if (GET_CODE (y) != MEM) 5732 { 5733 slot1 = assign_stack_temp (TFmode, GET_MODE_SIZE(TFmode), 0); 5734 emit_insn (gen_rtx_SET (VOIDmode, slot1, y)); 5735 } 5736 else 5737 slot1 = y; 5738 5739 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, qpfunc), LCT_NORMAL, 5740 DImode, 2, 5741 XEXP (slot0, 0), Pmode, 5742 XEXP (slot1, 0), Pmode); 5743 5744 mode = DImode; 5745 } 5746 else 5747 { 5748 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, qpfunc), LCT_NORMAL, 5749 SImode, 2, 5750 x, TFmode, y, TFmode); 5751 5752 mode = SImode; 5753 } 5754 5755 5756 /* Immediately move the result of the libcall into a pseudo 5757 register so reload doesn't clobber the value if it needs 5758 the return register for a spill reg. */ 5759 result = gen_reg_rtx (mode); 5760 emit_move_insn (result, hard_libcall_value (mode)); 5761 5762 switch (comparison) 5763 { 5764 default: 5765 emit_cmp_insn (result, const0_rtx, NE, NULL_RTX, mode, 0); 5766 break; 5767 case ORDERED: 5768 case UNORDERED: 5769 emit_cmp_insn (result, GEN_INT(3), comparison == UNORDERED ? EQ : NE, 5770 NULL_RTX, mode, 0); 5771 break; 5772 case UNGT: 5773 case UNGE: 5774 emit_cmp_insn (result, const1_rtx, 5775 comparison == UNGT ? GT : NE, NULL_RTX, mode, 0); 5776 break; 5777 case UNLE: 5778 emit_cmp_insn (result, const2_rtx, NE, NULL_RTX, mode, 0); 5779 break; 5780 case UNLT: 5781 tem = gen_reg_rtx (mode); 5782 if (TARGET_ARCH32) 5783 emit_insn (gen_andsi3 (tem, result, const1_rtx)); 5784 else 5785 emit_insn (gen_anddi3 (tem, result, const1_rtx)); 5786 emit_cmp_insn (tem, const0_rtx, NE, NULL_RTX, mode, 0); 5787 break; 5788 case UNEQ: 5789 case LTGT: 5790 tem = gen_reg_rtx (mode); 5791 if (TARGET_ARCH32) 5792 emit_insn (gen_addsi3 (tem, result, const1_rtx)); 5793 else 5794 emit_insn (gen_adddi3 (tem, result, const1_rtx)); 5795 tem2 = gen_reg_rtx (mode); 5796 if (TARGET_ARCH32) 5797 emit_insn (gen_andsi3 (tem2, tem, const2_rtx)); 5798 else 5799 emit_insn (gen_anddi3 (tem2, tem, const2_rtx)); 5800 emit_cmp_insn (tem2, const0_rtx, comparison == UNEQ ? EQ : NE, 5801 NULL_RTX, mode, 0); 5802 break; 5803 } 5804} 5805 5806/* Generate an unsigned DImode to FP conversion. This is the same code 5807 optabs would emit if we didn't have TFmode patterns. */ 5808 5809void 5810sparc_emit_floatunsdi (operands) 5811 rtx operands[2]; 5812{ 5813 rtx neglab, donelab, i0, i1, f0, in, out; 5814 enum machine_mode mode; 5815 5816 out = operands[0]; 5817 in = force_reg (DImode, operands[1]); 5818 mode = GET_MODE (out); 5819 neglab = gen_label_rtx (); 5820 donelab = gen_label_rtx (); 5821 i0 = gen_reg_rtx (DImode); 5822 i1 = gen_reg_rtx (DImode); 5823 f0 = gen_reg_rtx (mode); 5824 5825 emit_cmp_and_jump_insns (in, const0_rtx, LT, const0_rtx, DImode, 0, neglab); 5826 5827 emit_insn (gen_rtx_SET (VOIDmode, out, gen_rtx_FLOAT (mode, in))); 5828 emit_jump_insn (gen_jump (donelab)); 5829 emit_barrier (); 5830 5831 emit_label (neglab); 5832 5833 emit_insn (gen_lshrdi3 (i0, in, const1_rtx)); 5834 emit_insn (gen_anddi3 (i1, in, const1_rtx)); 5835 emit_insn (gen_iordi3 (i0, i0, i1)); 5836 emit_insn (gen_rtx_SET (VOIDmode, f0, gen_rtx_FLOAT (mode, i0))); 5837 emit_insn (gen_rtx_SET (VOIDmode, out, gen_rtx_PLUS (mode, f0, f0))); 5838 5839 emit_label (donelab); 5840} 5841 5842/* Return the string to output a conditional branch to LABEL, testing 5843 register REG. LABEL is the operand number of the label; REG is the 5844 operand number of the reg. OP is the conditional expression. The mode 5845 of REG says what kind of comparison we made. 5846 5847 REVERSED is nonzero if we should reverse the sense of the comparison. 5848 5849 ANNUL is nonzero if we should generate an annulling branch. 5850 5851 NOOP is nonzero if we have to follow this branch by a noop. */ 5852 5853char * 5854output_v9branch (op, dest, reg, label, reversed, annul, noop, insn) 5855 rtx op, dest; 5856 int reg, label; 5857 int reversed, annul, noop; 5858 rtx insn; 5859{ 5860 static char string[50]; 5861 enum rtx_code code = GET_CODE (op); 5862 enum machine_mode mode = GET_MODE (XEXP (op, 0)); 5863 rtx note; 5864 int far; 5865 char *p; 5866 5867 /* branch on register are limited to +-128KB. If it is too far away, 5868 change 5869 5870 brnz,pt %g1, .LC30 5871 5872 to 5873 5874 brz,pn %g1, .+12 5875 nop 5876 ba,pt %xcc, .LC30 5877 5878 and 5879 5880 brgez,a,pn %o1, .LC29 5881 5882 to 5883 5884 brlz,pt %o1, .+16 5885 nop 5886 ba,pt %xcc, .LC29 */ 5887 5888 far = get_attr_length (insn) >= 3; 5889 5890 /* If not floating-point or if EQ or NE, we can just reverse the code. */ 5891 if (reversed ^ far) 5892 code = reverse_condition (code); 5893 5894 /* Only 64 bit versions of these instructions exist. */ 5895 if (mode != DImode) 5896 abort (); 5897 5898 /* Start by writing the branch condition. */ 5899 5900 switch (code) 5901 { 5902 case NE: 5903 strcpy (string, "brnz"); 5904 break; 5905 5906 case EQ: 5907 strcpy (string, "brz"); 5908 break; 5909 5910 case GE: 5911 strcpy (string, "brgez"); 5912 break; 5913 5914 case LT: 5915 strcpy (string, "brlz"); 5916 break; 5917 5918 case LE: 5919 strcpy (string, "brlez"); 5920 break; 5921 5922 case GT: 5923 strcpy (string, "brgz"); 5924 break; 5925 5926 default: 5927 abort (); 5928 } 5929 5930 p = strchr (string, '\0'); 5931 5932 /* Now add the annulling, reg, label, and nop. */ 5933 if (annul && ! far) 5934 { 5935 strcpy (p, ",a"); 5936 p += 2; 5937 } 5938 5939 if (insn && (note = find_reg_note (insn, REG_BR_PROB, NULL_RTX))) 5940 { 5941 strcpy (p, 5942 ((INTVAL (XEXP (note, 0)) >= REG_BR_PROB_BASE / 2) ^ far) 5943 ? ",pt" : ",pn"); 5944 p += 3; 5945 } 5946 5947 *p = p < string + 8 ? '\t' : ' '; 5948 p++; 5949 *p++ = '%'; 5950 *p++ = '0' + reg; 5951 *p++ = ','; 5952 *p++ = ' '; 5953 if (far) 5954 { 5955 int veryfar = 1, delta; 5956 5957 if (INSN_ADDRESSES_SET_P ()) 5958 { 5959 delta = (INSN_ADDRESSES (INSN_UID (dest)) 5960 - INSN_ADDRESSES (INSN_UID (insn))); 5961 /* Leave some instructions for "slop". */ 5962 if (delta >= -260000 && delta < 260000) 5963 veryfar = 0; 5964 } 5965 5966 strcpy (p, ".+12\n\tnop\n\t"); 5967 if (annul || noop) 5968 p[3] = '6'; 5969 p += 11; 5970 if (veryfar) 5971 { 5972 strcpy (p, "b\t"); 5973 p += 2; 5974 } 5975 else 5976 { 5977 strcpy (p, "ba,pt\t%%xcc, "); 5978 p += 13; 5979 } 5980 } 5981 *p++ = '%'; 5982 *p++ = 'l'; 5983 *p++ = '0' + label; 5984 *p = '\0'; 5985 5986 if (noop) 5987 strcpy (p, "\n\tnop"); 5988 5989 return string; 5990} 5991 5992/* Return 1, if any of the registers of the instruction are %l[0-7] or %o[0-7]. 5993 Such instructions cannot be used in the delay slot of return insn on v9. 5994 If TEST is 0, also rename all %i[0-7] registers to their %o[0-7] counterparts. 5995 */ 5996 5997static int 5998epilogue_renumber (where, test) 5999 register rtx *where; 6000 int test; 6001{ 6002 register const char *fmt; 6003 register int i; 6004 register enum rtx_code code; 6005 6006 if (*where == 0) 6007 return 0; 6008 6009 code = GET_CODE (*where); 6010 6011 switch (code) 6012 { 6013 case REG: 6014 if (REGNO (*where) >= 8 && REGNO (*where) < 24) /* oX or lX */ 6015 return 1; 6016 if (! test && REGNO (*where) >= 24 && REGNO (*where) < 32) 6017 *where = gen_rtx (REG, GET_MODE (*where), OUTGOING_REGNO (REGNO(*where))); 6018 case SCRATCH: 6019 case CC0: 6020 case PC: 6021 case CONST_INT: 6022 case CONST_DOUBLE: 6023 return 0; 6024 6025 /* Do not replace the frame pointer with the stack pointer because 6026 it can cause the delayed instruction to load below the stack. 6027 This occurs when instructions like: 6028 6029 (set (reg/i:SI 24 %i0) 6030 (mem/f:SI (plus:SI (reg/f:SI 30 %fp) 6031 (const_int -20 [0xffffffec])) 0)) 6032 6033 are in the return delayed slot. */ 6034 case PLUS: 6035 if (GET_CODE (XEXP (*where, 0)) == REG 6036 && REGNO (XEXP (*where, 0)) == HARD_FRAME_POINTER_REGNUM 6037 && (GET_CODE (XEXP (*where, 1)) != CONST_INT 6038 || INTVAL (XEXP (*where, 1)) < SPARC_STACK_BIAS)) 6039 return 1; 6040 break; 6041 6042 case MEM: 6043 if (SPARC_STACK_BIAS 6044 && GET_CODE (XEXP (*where, 0)) == REG 6045 && REGNO (XEXP (*where, 0)) == HARD_FRAME_POINTER_REGNUM) 6046 return 1; 6047 break; 6048 6049 default: 6050 break; 6051 } 6052 6053 fmt = GET_RTX_FORMAT (code); 6054 6055 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) 6056 { 6057 if (fmt[i] == 'E') 6058 { 6059 register int j; 6060 for (j = XVECLEN (*where, i) - 1; j >= 0; j--) 6061 if (epilogue_renumber (&(XVECEXP (*where, i, j)), test)) 6062 return 1; 6063 } 6064 else if (fmt[i] == 'e' 6065 && epilogue_renumber (&(XEXP (*where, i)), test)) 6066 return 1; 6067 } 6068 return 0; 6069} 6070 6071/* Leaf functions and non-leaf functions have different needs. */ 6072 6073static const int 6074reg_leaf_alloc_order[] = REG_LEAF_ALLOC_ORDER; 6075 6076static const int 6077reg_nonleaf_alloc_order[] = REG_ALLOC_ORDER; 6078 6079static const int *const reg_alloc_orders[] = { 6080 reg_leaf_alloc_order, 6081 reg_nonleaf_alloc_order}; 6082 6083void 6084order_regs_for_local_alloc () 6085{ 6086 static int last_order_nonleaf = 1; 6087 6088 if (regs_ever_live[15] != last_order_nonleaf) 6089 { 6090 last_order_nonleaf = !last_order_nonleaf; 6091 memcpy ((char *) reg_alloc_order, 6092 (const char *) reg_alloc_orders[last_order_nonleaf], 6093 FIRST_PSEUDO_REGISTER * sizeof (int)); 6094 } 6095} 6096 6097/* Return 1 if REG and MEM are legitimate enough to allow the various 6098 mem<-->reg splits to be run. */ 6099 6100int 6101sparc_splitdi_legitimate (reg, mem) 6102 rtx reg; 6103 rtx mem; 6104{ 6105 /* Punt if we are here by mistake. */ 6106 if (! reload_completed) 6107 abort (); 6108 6109 /* We must have an offsettable memory reference. */ 6110 if (! offsettable_memref_p (mem)) 6111 return 0; 6112 6113 /* If we have legitimate args for ldd/std, we do not want 6114 the split to happen. */ 6115 if ((REGNO (reg) % 2) == 0 6116 && mem_min_alignment (mem, 8)) 6117 return 0; 6118 6119 /* Success. */ 6120 return 1; 6121} 6122 6123/* Return 1 if x and y are some kind of REG and they refer to 6124 different hard registers. This test is guarenteed to be 6125 run after reload. */ 6126 6127int 6128sparc_absnegfloat_split_legitimate (x, y) 6129 rtx x, y; 6130{ 6131 if (GET_CODE (x) != REG) 6132 return 0; 6133 if (GET_CODE (y) != REG) 6134 return 0; 6135 if (REGNO (x) == REGNO (y)) 6136 return 0; 6137 return 1; 6138} 6139 6140/* Return 1 if REGNO (reg1) is even and REGNO (reg1) == REGNO (reg2) - 1. 6141 This makes them candidates for using ldd and std insns. 6142 6143 Note reg1 and reg2 *must* be hard registers. */ 6144 6145int 6146registers_ok_for_ldd_peep (reg1, reg2) 6147 rtx reg1, reg2; 6148{ 6149 /* We might have been passed a SUBREG. */ 6150 if (GET_CODE (reg1) != REG || GET_CODE (reg2) != REG) 6151 return 0; 6152 6153 if (REGNO (reg1) % 2 != 0) 6154 return 0; 6155 6156 /* Integer ldd is deprecated in SPARC V9 */ 6157 if (TARGET_V9 && REGNO (reg1) < 32) 6158 return 0; 6159 6160 return (REGNO (reg1) == REGNO (reg2) - 1); 6161} 6162 6163/* Return 1 if the addresses in mem1 and mem2 are suitable for use in 6164 an ldd or std insn. 6165 6166 This can only happen when addr1 and addr2, the addresses in mem1 6167 and mem2, are consecutive memory locations (addr1 + 4 == addr2). 6168 addr1 must also be aligned on a 64-bit boundary. 6169 6170 Also iff dependent_reg_rtx is not null it should not be used to 6171 compute the address for mem1, i.e. we cannot optimize a sequence 6172 like: 6173 ld [%o0], %o0 6174 ld [%o0 + 4], %o1 6175 to 6176 ldd [%o0], %o0 6177 nor: 6178 ld [%g3 + 4], %g3 6179 ld [%g3], %g2 6180 to 6181 ldd [%g3], %g2 6182 6183 But, note that the transformation from: 6184 ld [%g2 + 4], %g3 6185 ld [%g2], %g2 6186 to 6187 ldd [%g2], %g2 6188 is perfectly fine. Thus, the peephole2 patterns always pass us 6189 the destination register of the first load, never the second one. 6190 6191 For stores we don't have a similar problem, so dependent_reg_rtx is 6192 NULL_RTX. */ 6193 6194int 6195mems_ok_for_ldd_peep (mem1, mem2, dependent_reg_rtx) 6196 rtx mem1, mem2, dependent_reg_rtx; 6197{ 6198 rtx addr1, addr2; 6199 unsigned int reg1; 6200 int offset1; 6201 6202 /* The mems cannot be volatile. */ 6203 if (MEM_VOLATILE_P (mem1) || MEM_VOLATILE_P (mem2)) 6204 return 0; 6205 6206 /* MEM1 should be aligned on a 64-bit boundary. */ 6207 if (MEM_ALIGN (mem1) < 64) 6208 return 0; 6209 6210 addr1 = XEXP (mem1, 0); 6211 addr2 = XEXP (mem2, 0); 6212 6213 /* Extract a register number and offset (if used) from the first addr. */ 6214 if (GET_CODE (addr1) == PLUS) 6215 { 6216 /* If not a REG, return zero. */ 6217 if (GET_CODE (XEXP (addr1, 0)) != REG) 6218 return 0; 6219 else 6220 { 6221 reg1 = REGNO (XEXP (addr1, 0)); 6222 /* The offset must be constant! */ 6223 if (GET_CODE (XEXP (addr1, 1)) != CONST_INT) 6224 return 0; 6225 offset1 = INTVAL (XEXP (addr1, 1)); 6226 } 6227 } 6228 else if (GET_CODE (addr1) != REG) 6229 return 0; 6230 else 6231 { 6232 reg1 = REGNO (addr1); 6233 /* This was a simple (mem (reg)) expression. Offset is 0. */ 6234 offset1 = 0; 6235 } 6236 6237 /* Make sure the second address is a (mem (plus (reg) (const_int). */ 6238 if (GET_CODE (addr2) != PLUS) 6239 return 0; 6240 6241 if (GET_CODE (XEXP (addr2, 0)) != REG 6242 || GET_CODE (XEXP (addr2, 1)) != CONST_INT) 6243 return 0; 6244 6245 if (reg1 != REGNO (XEXP (addr2, 0))) 6246 return 0; 6247 6248 if (dependent_reg_rtx != NULL_RTX && reg1 == REGNO (dependent_reg_rtx)) 6249 return 0; 6250 6251 /* The first offset must be evenly divisible by 8 to ensure the 6252 address is 64 bit aligned. */ 6253 if (offset1 % 8 != 0) 6254 return 0; 6255 6256 /* The offset for the second addr must be 4 more than the first addr. */ 6257 if (INTVAL (XEXP (addr2, 1)) != offset1 + 4) 6258 return 0; 6259 6260 /* All the tests passed. addr1 and addr2 are valid for ldd and std 6261 instructions. */ 6262 return 1; 6263} 6264 6265/* Return 1 if reg is a pseudo, or is the first register in 6266 a hard register pair. This makes it a candidate for use in 6267 ldd and std insns. */ 6268 6269int 6270register_ok_for_ldd (reg) 6271 rtx reg; 6272{ 6273 /* We might have been passed a SUBREG. */ 6274 if (GET_CODE (reg) != REG) 6275 return 0; 6276 6277 if (REGNO (reg) < FIRST_PSEUDO_REGISTER) 6278 return (REGNO (reg) % 2 == 0); 6279 else 6280 return 1; 6281} 6282 6283/* Print operand X (an rtx) in assembler syntax to file FILE. 6284 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified. 6285 For `%' followed by punctuation, CODE is the punctuation and X is null. */ 6286 6287void 6288print_operand (file, x, code) 6289 FILE *file; 6290 rtx x; 6291 int code; 6292{ 6293 switch (code) 6294 { 6295 case '#': 6296 /* Output a 'nop' if there's nothing for the delay slot. */ 6297 if (dbr_sequence_length () == 0) 6298 fputs ("\n\t nop", file); 6299 return; 6300 case '*': 6301 /* Output an annul flag if there's nothing for the delay slot and we 6302 are optimizing. This is always used with '(' below. */ 6303 /* Sun OS 4.1.1 dbx can't handle an annulled unconditional branch; 6304 this is a dbx bug. So, we only do this when optimizing. */ 6305 /* On UltraSPARC, a branch in a delay slot causes a pipeline flush. 6306 Always emit a nop in case the next instruction is a branch. */ 6307 if (dbr_sequence_length () == 0 6308 && (optimize && (int)sparc_cpu < PROCESSOR_V9)) 6309 fputs (",a", file); 6310 return; 6311 case '(': 6312 /* Output a 'nop' if there's nothing for the delay slot and we are 6313 not optimizing. This is always used with '*' above. */ 6314 if (dbr_sequence_length () == 0 6315 && ! (optimize && (int)sparc_cpu < PROCESSOR_V9)) 6316 fputs ("\n\t nop", file); 6317 return; 6318 case '_': 6319 /* Output the Embedded Medium/Anywhere code model base register. */ 6320 fputs (EMBMEDANY_BASE_REG, file); 6321 return; 6322 case '@': 6323 /* Print out what we are using as the frame pointer. This might 6324 be %fp, or might be %sp+offset. */ 6325 /* ??? What if offset is too big? Perhaps the caller knows it isn't? */ 6326 fprintf (file, "%s+%d", frame_base_name, frame_base_offset); 6327 return; 6328 case 'Y': 6329 /* Adjust the operand to take into account a RESTORE operation. */ 6330 if (GET_CODE (x) == CONST_INT) 6331 break; 6332 else if (GET_CODE (x) != REG) 6333 output_operand_lossage ("invalid %%Y operand"); 6334 else if (REGNO (x) < 8) 6335 fputs (reg_names[REGNO (x)], file); 6336 else if (REGNO (x) >= 24 && REGNO (x) < 32) 6337 fputs (reg_names[REGNO (x)-16], file); 6338 else 6339 output_operand_lossage ("invalid %%Y operand"); 6340 return; 6341 case 'L': 6342 /* Print out the low order register name of a register pair. */ 6343 if (WORDS_BIG_ENDIAN) 6344 fputs (reg_names[REGNO (x)+1], file); 6345 else 6346 fputs (reg_names[REGNO (x)], file); 6347 return; 6348 case 'H': 6349 /* Print out the high order register name of a register pair. */ 6350 if (WORDS_BIG_ENDIAN) 6351 fputs (reg_names[REGNO (x)], file); 6352 else 6353 fputs (reg_names[REGNO (x)+1], file); 6354 return; 6355 case 'R': 6356 /* Print out the second register name of a register pair or quad. 6357 I.e., R (%o0) => %o1. */ 6358 fputs (reg_names[REGNO (x)+1], file); 6359 return; 6360 case 'S': 6361 /* Print out the third register name of a register quad. 6362 I.e., S (%o0) => %o2. */ 6363 fputs (reg_names[REGNO (x)+2], file); 6364 return; 6365 case 'T': 6366 /* Print out the fourth register name of a register quad. 6367 I.e., T (%o0) => %o3. */ 6368 fputs (reg_names[REGNO (x)+3], file); 6369 return; 6370 case 'x': 6371 /* Print a condition code register. */ 6372 if (REGNO (x) == SPARC_ICC_REG) 6373 { 6374 /* We don't handle CC[X]_NOOVmode because they're not supposed 6375 to occur here. */ 6376 if (GET_MODE (x) == CCmode) 6377 fputs ("%icc", file); 6378 else if (GET_MODE (x) == CCXmode) 6379 fputs ("%xcc", file); 6380 else 6381 abort (); 6382 } 6383 else 6384 /* %fccN register */ 6385 fputs (reg_names[REGNO (x)], file); 6386 return; 6387 case 'm': 6388 /* Print the operand's address only. */ 6389 output_address (XEXP (x, 0)); 6390 return; 6391 case 'r': 6392 /* In this case we need a register. Use %g0 if the 6393 operand is const0_rtx. */ 6394 if (x == const0_rtx 6395 || (GET_MODE (x) != VOIDmode && x == CONST0_RTX (GET_MODE (x)))) 6396 { 6397 fputs ("%g0", file); 6398 return; 6399 } 6400 else 6401 break; 6402 6403 case 'A': 6404 switch (GET_CODE (x)) 6405 { 6406 case IOR: fputs ("or", file); break; 6407 case AND: fputs ("and", file); break; 6408 case XOR: fputs ("xor", file); break; 6409 default: output_operand_lossage ("invalid %%A operand"); 6410 } 6411 return; 6412 6413 case 'B': 6414 switch (GET_CODE (x)) 6415 { 6416 case IOR: fputs ("orn", file); break; 6417 case AND: fputs ("andn", file); break; 6418 case XOR: fputs ("xnor", file); break; 6419 default: output_operand_lossage ("invalid %%B operand"); 6420 } 6421 return; 6422 6423 /* These are used by the conditional move instructions. */ 6424 case 'c' : 6425 case 'C': 6426 { 6427 enum rtx_code rc = GET_CODE (x); 6428 6429 if (code == 'c') 6430 { 6431 enum machine_mode mode = GET_MODE (XEXP (x, 0)); 6432 if (mode == CCFPmode || mode == CCFPEmode) 6433 rc = reverse_condition_maybe_unordered (GET_CODE (x)); 6434 else 6435 rc = reverse_condition (GET_CODE (x)); 6436 } 6437 switch (rc) 6438 { 6439 case NE: fputs ("ne", file); break; 6440 case EQ: fputs ("e", file); break; 6441 case GE: fputs ("ge", file); break; 6442 case GT: fputs ("g", file); break; 6443 case LE: fputs ("le", file); break; 6444 case LT: fputs ("l", file); break; 6445 case GEU: fputs ("geu", file); break; 6446 case GTU: fputs ("gu", file); break; 6447 case LEU: fputs ("leu", file); break; 6448 case LTU: fputs ("lu", file); break; 6449 case LTGT: fputs ("lg", file); break; 6450 case UNORDERED: fputs ("u", file); break; 6451 case ORDERED: fputs ("o", file); break; 6452 case UNLT: fputs ("ul", file); break; 6453 case UNLE: fputs ("ule", file); break; 6454 case UNGT: fputs ("ug", file); break; 6455 case UNGE: fputs ("uge", file); break; 6456 case UNEQ: fputs ("ue", file); break; 6457 default: output_operand_lossage (code == 'c' 6458 ? "invalid %%c operand" 6459 : "invalid %%C operand"); 6460 } 6461 return; 6462 } 6463 6464 /* These are used by the movr instruction pattern. */ 6465 case 'd': 6466 case 'D': 6467 { 6468 enum rtx_code rc = (code == 'd' 6469 ? reverse_condition (GET_CODE (x)) 6470 : GET_CODE (x)); 6471 switch (rc) 6472 { 6473 case NE: fputs ("ne", file); break; 6474 case EQ: fputs ("e", file); break; 6475 case GE: fputs ("gez", file); break; 6476 case LT: fputs ("lz", file); break; 6477 case LE: fputs ("lez", file); break; 6478 case GT: fputs ("gz", file); break; 6479 default: output_operand_lossage (code == 'd' 6480 ? "invalid %%d operand" 6481 : "invalid %%D operand"); 6482 } 6483 return; 6484 } 6485 6486 case 'b': 6487 { 6488 /* Print a sign-extended character. */ 6489 int i = trunc_int_for_mode (INTVAL (x), QImode); 6490 fprintf (file, "%d", i); 6491 return; 6492 } 6493 6494 case 'f': 6495 /* Operand must be a MEM; write its address. */ 6496 if (GET_CODE (x) != MEM) 6497 output_operand_lossage ("invalid %%f operand"); 6498 output_address (XEXP (x, 0)); 6499 return; 6500 6501 case 's': 6502 { 6503 /* Print a sign-extended 32-bit value. */ 6504 HOST_WIDE_INT i; 6505 if (GET_CODE(x) == CONST_INT) 6506 i = INTVAL (x); 6507 else if (GET_CODE(x) == CONST_DOUBLE) 6508 i = CONST_DOUBLE_LOW (x); 6509 else 6510 { 6511 output_operand_lossage ("invalid %%s operand"); 6512 return; 6513 } 6514 i = trunc_int_for_mode (i, SImode); 6515 fprintf (file, HOST_WIDE_INT_PRINT_DEC, i); 6516 return; 6517 } 6518 6519 case 0: 6520 /* Do nothing special. */ 6521 break; 6522 6523 default: 6524 /* Undocumented flag. */ 6525 output_operand_lossage ("invalid operand output code"); 6526 } 6527 6528 if (GET_CODE (x) == REG) 6529 fputs (reg_names[REGNO (x)], file); 6530 else if (GET_CODE (x) == MEM) 6531 { 6532 fputc ('[', file); 6533 /* Poor Sun assembler doesn't understand absolute addressing. */ 6534 if (CONSTANT_P (XEXP (x, 0))) 6535 fputs ("%g0+", file); 6536 output_address (XEXP (x, 0)); 6537 fputc (']', file); 6538 } 6539 else if (GET_CODE (x) == HIGH) 6540 { 6541 fputs ("%hi(", file); 6542 output_addr_const (file, XEXP (x, 0)); 6543 fputc (')', file); 6544 } 6545 else if (GET_CODE (x) == LO_SUM) 6546 { 6547 print_operand (file, XEXP (x, 0), 0); 6548 if (TARGET_CM_MEDMID) 6549 fputs ("+%l44(", file); 6550 else 6551 fputs ("+%lo(", file); 6552 output_addr_const (file, XEXP (x, 1)); 6553 fputc (')', file); 6554 } 6555 else if (GET_CODE (x) == CONST_DOUBLE 6556 && (GET_MODE (x) == VOIDmode 6557 || GET_MODE_CLASS (GET_MODE (x)) == MODE_INT)) 6558 { 6559 if (CONST_DOUBLE_HIGH (x) == 0) 6560 fprintf (file, "%u", (unsigned int) CONST_DOUBLE_LOW (x)); 6561 else if (CONST_DOUBLE_HIGH (x) == -1 6562 && CONST_DOUBLE_LOW (x) < 0) 6563 fprintf (file, "%d", (int) CONST_DOUBLE_LOW (x)); 6564 else 6565 output_operand_lossage ("long long constant not a valid immediate operand"); 6566 } 6567 else if (GET_CODE (x) == CONST_DOUBLE) 6568 output_operand_lossage ("floating point constant not a valid immediate operand"); 6569 else { output_addr_const (file, x); } 6570} 6571 6572/* Target hook for assembling integer objects. The sparc version has 6573 special handling for aligned DI-mode objects. */ 6574 6575static bool 6576sparc_assemble_integer (x, size, aligned_p) 6577 rtx x; 6578 unsigned int size; 6579 int aligned_p; 6580{ 6581 /* ??? We only output .xword's for symbols and only then in environments 6582 where the assembler can handle them. */ 6583 if (aligned_p && size == 8 6584 && (GET_CODE (x) != CONST_INT && GET_CODE (x) != CONST_DOUBLE)) 6585 { 6586 if (TARGET_V9) 6587 { 6588 assemble_integer_with_op ("\t.xword\t", x); 6589 return true; 6590 } 6591 else 6592 { 6593 assemble_aligned_integer (4, const0_rtx); 6594 assemble_aligned_integer (4, x); 6595 return true; 6596 } 6597 } 6598 return default_assemble_integer (x, size, aligned_p); 6599} 6600 6601/* Return the value of a code used in the .proc pseudo-op that says 6602 what kind of result this function returns. For non-C types, we pick 6603 the closest C type. */ 6604 6605#ifndef SHORT_TYPE_SIZE 6606#define SHORT_TYPE_SIZE (BITS_PER_UNIT * 2) 6607#endif 6608 6609#ifndef INT_TYPE_SIZE 6610#define INT_TYPE_SIZE BITS_PER_WORD 6611#endif 6612 6613#ifndef LONG_TYPE_SIZE 6614#define LONG_TYPE_SIZE BITS_PER_WORD 6615#endif 6616 6617#ifndef LONG_LONG_TYPE_SIZE 6618#define LONG_LONG_TYPE_SIZE (BITS_PER_WORD * 2) 6619#endif 6620 6621#ifndef FLOAT_TYPE_SIZE 6622#define FLOAT_TYPE_SIZE BITS_PER_WORD 6623#endif 6624 6625#ifndef DOUBLE_TYPE_SIZE 6626#define DOUBLE_TYPE_SIZE (BITS_PER_WORD * 2) 6627#endif 6628 6629#ifndef LONG_DOUBLE_TYPE_SIZE 6630#define LONG_DOUBLE_TYPE_SIZE (BITS_PER_WORD * 2) 6631#endif 6632 6633unsigned long 6634sparc_type_code (type) 6635 register tree type; 6636{ 6637 register unsigned long qualifiers = 0; 6638 register unsigned shift; 6639 6640 /* Only the first 30 bits of the qualifier are valid. We must refrain from 6641 setting more, since some assemblers will give an error for this. Also, 6642 we must be careful to avoid shifts of 32 bits or more to avoid getting 6643 unpredictable results. */ 6644 6645 for (shift = 6; shift < 30; shift += 2, type = TREE_TYPE (type)) 6646 { 6647 switch (TREE_CODE (type)) 6648 { 6649 case ERROR_MARK: 6650 return qualifiers; 6651 6652 case ARRAY_TYPE: 6653 qualifiers |= (3 << shift); 6654 break; 6655 6656 case FUNCTION_TYPE: 6657 case METHOD_TYPE: 6658 qualifiers |= (2 << shift); 6659 break; 6660 6661 case POINTER_TYPE: 6662 case REFERENCE_TYPE: 6663 case OFFSET_TYPE: 6664 qualifiers |= (1 << shift); 6665 break; 6666 6667 case RECORD_TYPE: 6668 return (qualifiers | 8); 6669 6670 case UNION_TYPE: 6671 case QUAL_UNION_TYPE: 6672 return (qualifiers | 9); 6673 6674 case ENUMERAL_TYPE: 6675 return (qualifiers | 10); 6676 6677 case VOID_TYPE: 6678 return (qualifiers | 16); 6679 6680 case INTEGER_TYPE: 6681 /* If this is a range type, consider it to be the underlying 6682 type. */ 6683 if (TREE_TYPE (type) != 0) 6684 break; 6685 6686 /* Carefully distinguish all the standard types of C, 6687 without messing up if the language is not C. We do this by 6688 testing TYPE_PRECISION and TREE_UNSIGNED. The old code used to 6689 look at both the names and the above fields, but that's redundant. 6690 Any type whose size is between two C types will be considered 6691 to be the wider of the two types. Also, we do not have a 6692 special code to use for "long long", so anything wider than 6693 long is treated the same. Note that we can't distinguish 6694 between "int" and "long" in this code if they are the same 6695 size, but that's fine, since neither can the assembler. */ 6696 6697 if (TYPE_PRECISION (type) <= CHAR_TYPE_SIZE) 6698 return (qualifiers | (TREE_UNSIGNED (type) ? 12 : 2)); 6699 6700 else if (TYPE_PRECISION (type) <= SHORT_TYPE_SIZE) 6701 return (qualifiers | (TREE_UNSIGNED (type) ? 13 : 3)); 6702 6703 else if (TYPE_PRECISION (type) <= INT_TYPE_SIZE) 6704 return (qualifiers | (TREE_UNSIGNED (type) ? 14 : 4)); 6705 6706 else 6707 return (qualifiers | (TREE_UNSIGNED (type) ? 15 : 5)); 6708 6709 case REAL_TYPE: 6710 /* If this is a range type, consider it to be the underlying 6711 type. */ 6712 if (TREE_TYPE (type) != 0) 6713 break; 6714 6715 /* Carefully distinguish all the standard types of C, 6716 without messing up if the language is not C. */ 6717 6718 if (TYPE_PRECISION (type) == FLOAT_TYPE_SIZE) 6719 return (qualifiers | 6); 6720 6721 else 6722 return (qualifiers | 7); 6723 6724 case COMPLEX_TYPE: /* GNU Fortran COMPLEX type. */ 6725 /* ??? We need to distinguish between double and float complex types, 6726 but I don't know how yet because I can't reach this code from 6727 existing front-ends. */ 6728 return (qualifiers | 7); /* Who knows? */ 6729 6730 case CHAR_TYPE: /* GNU Pascal CHAR type. Not used in C. */ 6731 case BOOLEAN_TYPE: /* GNU Fortran BOOLEAN type. */ 6732 case FILE_TYPE: /* GNU Pascal FILE type. */ 6733 case SET_TYPE: /* GNU Pascal SET type. */ 6734 case LANG_TYPE: /* ? */ 6735 return qualifiers; 6736 6737 default: 6738 abort (); /* Not a type! */ 6739 } 6740 } 6741 6742 return qualifiers; 6743} 6744 6745/* Nested function support. */ 6746 6747/* Emit RTL insns to initialize the variable parts of a trampoline. 6748 FNADDR is an RTX for the address of the function's pure code. 6749 CXT is an RTX for the static chain value for the function. 6750 6751 This takes 16 insns: 2 shifts & 2 ands (to split up addresses), 4 sethi 6752 (to load in opcodes), 4 iors (to merge address and opcodes), and 4 writes 6753 (to store insns). This is a bit excessive. Perhaps a different 6754 mechanism would be better here. 6755 6756 Emit enough FLUSH insns to synchronize the data and instruction caches. */ 6757 6758void 6759sparc_initialize_trampoline (tramp, fnaddr, cxt) 6760 rtx tramp, fnaddr, cxt; 6761{ 6762 /* SPARC 32 bit trampoline: 6763 6764 sethi %hi(fn), %g1 6765 sethi %hi(static), %g2 6766 jmp %g1+%lo(fn) 6767 or %g2, %lo(static), %g2 6768 6769 SETHI i,r = 00rr rrr1 00ii iiii iiii iiii iiii iiii 6770 JMPL r+i,d = 10dd ddd1 1100 0rrr rr1i iiii iiii iiii 6771 */ 6772#ifdef TRANSFER_FROM_TRAMPOLINE 6773 emit_library_call (gen_rtx (SYMBOL_REF, Pmode, "__enable_execute_stack"), 6774 LCT_NORMAL, VOIDmode, 1, tramp, Pmode); 6775#endif 6776 6777 emit_move_insn 6778 (gen_rtx_MEM (SImode, plus_constant (tramp, 0)), 6779 expand_binop (SImode, ior_optab, 6780 expand_shift (RSHIFT_EXPR, SImode, fnaddr, 6781 size_int (10), 0, 1), 6782 GEN_INT (trunc_int_for_mode (0x03000000, SImode)), 6783 NULL_RTX, 1, OPTAB_DIRECT)); 6784 6785 emit_move_insn 6786 (gen_rtx_MEM (SImode, plus_constant (tramp, 4)), 6787 expand_binop (SImode, ior_optab, 6788 expand_shift (RSHIFT_EXPR, SImode, cxt, 6789 size_int (10), 0, 1), 6790 GEN_INT (trunc_int_for_mode (0x05000000, SImode)), 6791 NULL_RTX, 1, OPTAB_DIRECT)); 6792 6793 emit_move_insn 6794 (gen_rtx_MEM (SImode, plus_constant (tramp, 8)), 6795 expand_binop (SImode, ior_optab, 6796 expand_and (SImode, fnaddr, GEN_INT (0x3ff), NULL_RTX), 6797 GEN_INT (trunc_int_for_mode (0x81c06000, SImode)), 6798 NULL_RTX, 1, OPTAB_DIRECT)); 6799 6800 emit_move_insn 6801 (gen_rtx_MEM (SImode, plus_constant (tramp, 12)), 6802 expand_binop (SImode, ior_optab, 6803 expand_and (SImode, cxt, GEN_INT (0x3ff), NULL_RTX), 6804 GEN_INT (trunc_int_for_mode (0x8410a000, SImode)), 6805 NULL_RTX, 1, OPTAB_DIRECT)); 6806 6807 /* On UltraSPARC a flush flushes an entire cache line. The trampoline is 6808 aligned on a 16 byte boundary so one flush clears it all. */ 6809 emit_insn (gen_flush (validize_mem (gen_rtx_MEM (SImode, tramp)))); 6810 if (sparc_cpu != PROCESSOR_ULTRASPARC 6811 && sparc_cpu != PROCESSOR_ULTRASPARC3) 6812 emit_insn (gen_flush (validize_mem (gen_rtx_MEM (SImode, 6813 plus_constant (tramp, 8))))); 6814} 6815 6816/* The 64 bit version is simpler because it makes more sense to load the 6817 values as "immediate" data out of the trampoline. It's also easier since 6818 we can read the PC without clobbering a register. */ 6819 6820void 6821sparc64_initialize_trampoline (tramp, fnaddr, cxt) 6822 rtx tramp, fnaddr, cxt; 6823{ 6824#ifdef TRANSFER_FROM_TRAMPOLINE 6825 emit_library_call (gen_rtx (SYMBOL_REF, Pmode, "__enable_execute_stack"), 6826 LCT_NORMAL, VOIDmode, 1, tramp, Pmode); 6827#endif 6828 6829 /* 6830 rd %pc, %g1 6831 ldx [%g1+24], %g5 6832 jmp %g5 6833 ldx [%g1+16], %g5 6834 +16 bytes data 6835 */ 6836 6837 emit_move_insn (gen_rtx_MEM (SImode, tramp), 6838 GEN_INT (trunc_int_for_mode (0x83414000, SImode))); 6839 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 4)), 6840 GEN_INT (trunc_int_for_mode (0xca586018, SImode))); 6841 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 8)), 6842 GEN_INT (trunc_int_for_mode (0x81c14000, SImode))); 6843 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 12)), 6844 GEN_INT (trunc_int_for_mode (0xca586010, SImode))); 6845 emit_move_insn (gen_rtx_MEM (DImode, plus_constant (tramp, 16)), cxt); 6846 emit_move_insn (gen_rtx_MEM (DImode, plus_constant (tramp, 24)), fnaddr); 6847 emit_insn (gen_flushdi (validize_mem (gen_rtx_MEM (DImode, tramp)))); 6848 6849 if (sparc_cpu != PROCESSOR_ULTRASPARC 6850 && sparc_cpu != PROCESSOR_ULTRASPARC3) 6851 emit_insn (gen_flushdi (validize_mem (gen_rtx_MEM (DImode, plus_constant (tramp, 8))))); 6852} 6853 6854/* Subroutines to support a flat (single) register window calling 6855 convention. */ 6856 6857/* Single-register window sparc stack frames look like: 6858 6859 Before call After call 6860 +-----------------------+ +-----------------------+ 6861 high | | | | 6862 mem | caller's temps. | | caller's temps. | 6863 | | | | 6864 +-----------------------+ +-----------------------+ 6865 | | | | 6866 | arguments on stack. | | arguments on stack. | 6867 | | | | 6868 +-----------------------+FP+92->+-----------------------+ 6869 | 6 words to save | | 6 words to save | 6870 | arguments passed | | arguments passed | 6871 | in registers, even | | in registers, even | 6872 | if not passed. | | if not passed. | 6873 SP+68->+-----------------------+FP+68->+-----------------------+ 6874 | 1 word struct addr | | 1 word struct addr | 6875 +-----------------------+FP+64->+-----------------------+ 6876 | | | | 6877 | 16 word reg save area | | 16 word reg save area | 6878 | | | | 6879 SP->+-----------------------+ FP->+-----------------------+ 6880 | 4 word area for | 6881 | fp/alu reg moves | 6882 FP-16->+-----------------------+ 6883 | | 6884 | local variables | 6885 | | 6886 +-----------------------+ 6887 | | 6888 | fp register save | 6889 | | 6890 +-----------------------+ 6891 | | 6892 | gp register save | 6893 | | 6894 +-----------------------+ 6895 | | 6896 | alloca allocations | 6897 | | 6898 +-----------------------+ 6899 | | 6900 | arguments on stack | 6901 | | 6902 SP+92->+-----------------------+ 6903 | 6 words to save | 6904 | arguments passed | 6905 | in registers, even | 6906 low | if not passed. | 6907 memory SP+68->+-----------------------+ 6908 | 1 word struct addr | 6909 SP+64->+-----------------------+ 6910 | | 6911 I 16 word reg save area | 6912 | | 6913 SP->+-----------------------+ */ 6914 6915/* Structure to be filled in by sparc_flat_compute_frame_size with register 6916 save masks, and offsets for the current function. */ 6917 6918struct sparc_frame_info 6919{ 6920 unsigned long total_size; /* # bytes that the entire frame takes up. */ 6921 unsigned long var_size; /* # bytes that variables take up. */ 6922 unsigned long args_size; /* # bytes that outgoing arguments take up. */ 6923 unsigned long extra_size; /* # bytes of extra gunk. */ 6924 unsigned int gp_reg_size; /* # bytes needed to store gp regs. */ 6925 unsigned int fp_reg_size; /* # bytes needed to store fp regs. */ 6926 unsigned long gmask; /* Mask of saved gp registers. */ 6927 unsigned long fmask; /* Mask of saved fp registers. */ 6928 unsigned long reg_offset; /* Offset from new sp to store regs. */ 6929 int initialized; /* Nonzero if frame size already calculated. */ 6930}; 6931 6932/* Current frame information calculated by sparc_flat_compute_frame_size. */ 6933struct sparc_frame_info current_frame_info; 6934 6935/* Zero structure to initialize current_frame_info. */ 6936struct sparc_frame_info zero_frame_info; 6937 6938/* Tell prologue and epilogue if register REGNO should be saved / restored. */ 6939 6940#define RETURN_ADDR_REGNUM 15 6941#define HARD_FRAME_POINTER_MASK (1 << (HARD_FRAME_POINTER_REGNUM)) 6942#define RETURN_ADDR_MASK (1 << (RETURN_ADDR_REGNUM)) 6943 6944#define MUST_SAVE_REGISTER(regno) \ 6945 ((regs_ever_live[regno] && !call_used_regs[regno]) \ 6946 || (regno == HARD_FRAME_POINTER_REGNUM && frame_pointer_needed) \ 6947 || (regno == RETURN_ADDR_REGNUM && regs_ever_live[RETURN_ADDR_REGNUM])) 6948 6949/* Return the bytes needed to compute the frame pointer from the current 6950 stack pointer. */ 6951 6952unsigned long 6953sparc_flat_compute_frame_size (size) 6954 int size; /* # of var. bytes allocated. */ 6955{ 6956 int regno; 6957 unsigned long total_size; /* # bytes that the entire frame takes up. */ 6958 unsigned long var_size; /* # bytes that variables take up. */ 6959 unsigned long args_size; /* # bytes that outgoing arguments take up. */ 6960 unsigned long extra_size; /* # extra bytes. */ 6961 unsigned int gp_reg_size; /* # bytes needed to store gp regs. */ 6962 unsigned int fp_reg_size; /* # bytes needed to store fp regs. */ 6963 unsigned long gmask; /* Mask of saved gp registers. */ 6964 unsigned long fmask; /* Mask of saved fp registers. */ 6965 unsigned long reg_offset; /* Offset to register save area. */ 6966 int need_aligned_p; /* 1 if need the save area 8 byte aligned. */ 6967 6968 /* This is the size of the 16 word reg save area, 1 word struct addr 6969 area, and 4 word fp/alu register copy area. */ 6970 extra_size = -STARTING_FRAME_OFFSET + FIRST_PARM_OFFSET(0); 6971 var_size = size; 6972 gp_reg_size = 0; 6973 fp_reg_size = 0; 6974 gmask = 0; 6975 fmask = 0; 6976 reg_offset = 0; 6977 need_aligned_p = 0; 6978 6979 args_size = 0; 6980 if (!leaf_function_p ()) 6981 { 6982 /* Also include the size needed for the 6 parameter registers. */ 6983 args_size = current_function_outgoing_args_size + 24; 6984 } 6985 total_size = var_size + args_size; 6986 6987 /* Calculate space needed for gp registers. */ 6988 for (regno = 1; regno <= 31; regno++) 6989 { 6990 if (MUST_SAVE_REGISTER (regno)) 6991 { 6992 /* If we need to save two regs in a row, ensure there's room to bump 6993 up the address to align it to a doubleword boundary. */ 6994 if ((regno & 0x1) == 0 && MUST_SAVE_REGISTER (regno+1)) 6995 { 6996 if (gp_reg_size % 8 != 0) 6997 gp_reg_size += 4; 6998 gp_reg_size += 2 * UNITS_PER_WORD; 6999 gmask |= 3 << regno; 7000 regno++; 7001 need_aligned_p = 1; 7002 } 7003 else 7004 { 7005 gp_reg_size += UNITS_PER_WORD; 7006 gmask |= 1 << regno; 7007 } 7008 } 7009 } 7010 7011 /* Calculate space needed for fp registers. */ 7012 for (regno = 32; regno <= 63; regno++) 7013 { 7014 if (regs_ever_live[regno] && !call_used_regs[regno]) 7015 { 7016 fp_reg_size += UNITS_PER_WORD; 7017 fmask |= 1 << (regno - 32); 7018 } 7019 } 7020 7021 if (gmask || fmask) 7022 { 7023 int n; 7024 reg_offset = FIRST_PARM_OFFSET(0) + args_size; 7025 /* Ensure save area is 8 byte aligned if we need it. */ 7026 n = reg_offset % 8; 7027 if (need_aligned_p && n != 0) 7028 { 7029 total_size += 8 - n; 7030 reg_offset += 8 - n; 7031 } 7032 total_size += gp_reg_size + fp_reg_size; 7033 } 7034 7035 /* If we must allocate a stack frame at all, we must also allocate 7036 room for register window spillage, so as to be binary compatible 7037 with libraries and operating systems that do not use -mflat. */ 7038 if (total_size > 0) 7039 total_size += extra_size; 7040 else 7041 extra_size = 0; 7042 7043 total_size = SPARC_STACK_ALIGN (total_size); 7044 7045 /* Save other computed information. */ 7046 current_frame_info.total_size = total_size; 7047 current_frame_info.var_size = var_size; 7048 current_frame_info.args_size = args_size; 7049 current_frame_info.extra_size = extra_size; 7050 current_frame_info.gp_reg_size = gp_reg_size; 7051 current_frame_info.fp_reg_size = fp_reg_size; 7052 current_frame_info.gmask = gmask; 7053 current_frame_info.fmask = fmask; 7054 current_frame_info.reg_offset = reg_offset; 7055 current_frame_info.initialized = reload_completed; 7056 7057 /* Ok, we're done. */ 7058 return total_size; 7059} 7060 7061/* Save/restore registers in GMASK and FMASK at register BASE_REG plus offset 7062 OFFSET. 7063 7064 BASE_REG must be 8 byte aligned. This allows us to test OFFSET for 7065 appropriate alignment and use DOUBLEWORD_OP when we can. We assume 7066 [BASE_REG+OFFSET] will always be a valid address. 7067 7068 WORD_OP is either "st" for save, "ld" for restore. 7069 DOUBLEWORD_OP is either "std" for save, "ldd" for restore. */ 7070 7071void 7072sparc_flat_save_restore (file, base_reg, offset, gmask, fmask, word_op, 7073 doubleword_op, base_offset) 7074 FILE *file; 7075 const char *base_reg; 7076 unsigned int offset; 7077 unsigned long gmask; 7078 unsigned long fmask; 7079 const char *word_op; 7080 const char *doubleword_op; 7081 unsigned long base_offset; 7082{ 7083 int regno; 7084 7085 if (gmask == 0 && fmask == 0) 7086 return; 7087 7088 /* Save registers starting from high to low. We've already saved the 7089 previous frame pointer and previous return address for the debugger's 7090 sake. The debugger allows us to not need a nop in the epilog if at least 7091 one register is reloaded in addition to return address. */ 7092 7093 if (gmask) 7094 { 7095 for (regno = 1; regno <= 31; regno++) 7096 { 7097 if ((gmask & (1L << regno)) != 0) 7098 { 7099 if ((regno & 0x1) == 0 && ((gmask & (1L << (regno+1))) != 0)) 7100 { 7101 /* We can save two registers in a row. If we're not at a 7102 double word boundary, move to one. 7103 sparc_flat_compute_frame_size ensures there's room to do 7104 this. */ 7105 if (offset % 8 != 0) 7106 offset += UNITS_PER_WORD; 7107 7108 if (word_op[0] == 's') 7109 { 7110 fprintf (file, "\t%s\t%s, [%s+%d]\n", 7111 doubleword_op, reg_names[regno], 7112 base_reg, offset); 7113 if (dwarf2out_do_frame ()) 7114 { 7115 char *l = dwarf2out_cfi_label (); 7116 dwarf2out_reg_save (l, regno, offset + base_offset); 7117 dwarf2out_reg_save 7118 (l, regno+1, offset+base_offset + UNITS_PER_WORD); 7119 } 7120 } 7121 else 7122 fprintf (file, "\t%s\t[%s+%d], %s\n", 7123 doubleword_op, base_reg, offset, 7124 reg_names[regno]); 7125 7126 offset += 2 * UNITS_PER_WORD; 7127 regno++; 7128 } 7129 else 7130 { 7131 if (word_op[0] == 's') 7132 { 7133 fprintf (file, "\t%s\t%s, [%s+%d]\n", 7134 word_op, reg_names[regno], 7135 base_reg, offset); 7136 if (dwarf2out_do_frame ()) 7137 dwarf2out_reg_save ("", regno, offset + base_offset); 7138 } 7139 else 7140 fprintf (file, "\t%s\t[%s+%d], %s\n", 7141 word_op, base_reg, offset, reg_names[regno]); 7142 7143 offset += UNITS_PER_WORD; 7144 } 7145 } 7146 } 7147 } 7148 7149 if (fmask) 7150 { 7151 for (regno = 32; regno <= 63; regno++) 7152 { 7153 if ((fmask & (1L << (regno - 32))) != 0) 7154 { 7155 if (word_op[0] == 's') 7156 { 7157 fprintf (file, "\t%s\t%s, [%s+%d]\n", 7158 word_op, reg_names[regno], 7159 base_reg, offset); 7160 if (dwarf2out_do_frame ()) 7161 dwarf2out_reg_save ("", regno, offset + base_offset); 7162 } 7163 else 7164 fprintf (file, "\t%s\t[%s+%d], %s\n", 7165 word_op, base_reg, offset, reg_names[regno]); 7166 7167 offset += UNITS_PER_WORD; 7168 } 7169 } 7170 } 7171} 7172 7173/* Set up the stack and frame (if desired) for the function. */ 7174 7175static void 7176sparc_flat_function_prologue (file, size) 7177 FILE *file; 7178 HOST_WIDE_INT size; 7179{ 7180 const char *sp_str = reg_names[STACK_POINTER_REGNUM]; 7181 unsigned long gmask = current_frame_info.gmask; 7182 7183 sparc_output_scratch_registers (file); 7184 7185 /* This is only for the human reader. */ 7186 fprintf (file, "\t%s#PROLOGUE# 0\n", ASM_COMMENT_START); 7187 fprintf (file, "\t%s# vars= %ld, regs= %d/%d, args= %d, extra= %ld\n", 7188 ASM_COMMENT_START, 7189 current_frame_info.var_size, 7190 current_frame_info.gp_reg_size / 4, 7191 current_frame_info.fp_reg_size / 4, 7192 current_function_outgoing_args_size, 7193 current_frame_info.extra_size); 7194 7195 size = SPARC_STACK_ALIGN (size); 7196 size = (! current_frame_info.initialized 7197 ? sparc_flat_compute_frame_size (size) 7198 : current_frame_info.total_size); 7199 7200 /* These cases shouldn't happen. Catch them now. */ 7201 if (size == 0 && (gmask || current_frame_info.fmask)) 7202 abort (); 7203 7204 /* Allocate our stack frame by decrementing %sp. 7205 At present, the only algorithm gdb can use to determine if this is a 7206 flat frame is if we always set %i7 if we set %sp. This can be optimized 7207 in the future by putting in some sort of debugging information that says 7208 this is a `flat' function. However, there is still the case of debugging 7209 code without such debugging information (including cases where most fns 7210 have such info, but there is one that doesn't). So, always do this now 7211 so we don't get a lot of code out there that gdb can't handle. 7212 If the frame pointer isn't needn't then that's ok - gdb won't be able to 7213 distinguish us from a non-flat function but there won't (and shouldn't) 7214 be any differences anyway. The return pc is saved (if necessary) right 7215 after %i7 so gdb won't have to look too far to find it. */ 7216 if (size > 0) 7217 { 7218 unsigned int reg_offset = current_frame_info.reg_offset; 7219 const char *const fp_str = reg_names[HARD_FRAME_POINTER_REGNUM]; 7220 static const char *const t1_str = "%g1"; 7221 7222 /* Things get a little tricky if local variables take up more than ~4096 7223 bytes and outgoing arguments take up more than ~4096 bytes. When that 7224 happens, the register save area can't be accessed from either end of 7225 the frame. Handle this by decrementing %sp to the start of the gp 7226 register save area, save the regs, update %i7, and then set %sp to its 7227 final value. Given that we only have one scratch register to play 7228 with it is the cheapest solution, and it helps gdb out as it won't 7229 slow down recognition of flat functions. 7230 Don't change the order of insns emitted here without checking with 7231 the gdb folk first. */ 7232 7233 /* Is the entire register save area offsettable from %sp? */ 7234 if (reg_offset < 4096 - 64 * (unsigned) UNITS_PER_WORD) 7235 { 7236 if (size <= 4096) 7237 { 7238 fprintf (file, "\tadd\t%s, %d, %s\n", 7239 sp_str, (int) -size, sp_str); 7240 if (gmask & HARD_FRAME_POINTER_MASK) 7241 { 7242 fprintf (file, "\tst\t%s, [%s+%d]\n", 7243 fp_str, sp_str, reg_offset); 7244 fprintf (file, "\tsub\t%s, %d, %s\t%s# set up frame pointer\n", 7245 sp_str, (int) -size, fp_str, ASM_COMMENT_START); 7246 reg_offset += 4; 7247 } 7248 } 7249 else 7250 { 7251 fprintf (file, "\tset\t"); 7252 fprintf (file, HOST_WIDE_INT_PRINT_DEC, size); 7253 fprintf (file, ", %s\n\tsub\t%s, %s, %s\n", 7254 t1_str, sp_str, t1_str, sp_str); 7255 if (gmask & HARD_FRAME_POINTER_MASK) 7256 { 7257 fprintf (file, "\tst\t%s, [%s+%d]\n", 7258 fp_str, sp_str, reg_offset); 7259 fprintf (file, "\tadd\t%s, %s, %s\t%s# set up frame pointer\n", 7260 sp_str, t1_str, fp_str, ASM_COMMENT_START); 7261 reg_offset += 4; 7262 } 7263 } 7264 if (dwarf2out_do_frame ()) 7265 { 7266 char *l = dwarf2out_cfi_label (); 7267 if (gmask & HARD_FRAME_POINTER_MASK) 7268 { 7269 dwarf2out_reg_save (l, HARD_FRAME_POINTER_REGNUM, 7270 reg_offset - 4 - size); 7271 dwarf2out_def_cfa (l, HARD_FRAME_POINTER_REGNUM, 0); 7272 } 7273 else 7274 dwarf2out_def_cfa (l, STACK_POINTER_REGNUM, size); 7275 } 7276 if (gmask & RETURN_ADDR_MASK) 7277 { 7278 fprintf (file, "\tst\t%s, [%s+%d]\n", 7279 reg_names[RETURN_ADDR_REGNUM], sp_str, reg_offset); 7280 if (dwarf2out_do_frame ()) 7281 dwarf2out_return_save ("", reg_offset - size); 7282 reg_offset += 4; 7283 } 7284 sparc_flat_save_restore (file, sp_str, reg_offset, 7285 gmask & ~(HARD_FRAME_POINTER_MASK | RETURN_ADDR_MASK), 7286 current_frame_info.fmask, 7287 "st", "std", -size); 7288 } 7289 else 7290 { 7291 /* Subtract %sp in two steps, but make sure there is always a 7292 64 byte register save area, and %sp is properly aligned. */ 7293 /* Amount to decrement %sp by, the first time. */ 7294 unsigned HOST_WIDE_INT size1 = ((size - reg_offset + 64) + 15) & -16; 7295 /* Offset to register save area from %sp. */ 7296 unsigned HOST_WIDE_INT offset = size1 - (size - reg_offset); 7297 7298 if (size1 <= 4096) 7299 { 7300 fprintf (file, "\tadd\t%s, %d, %s\n", 7301 sp_str, (int) -size1, sp_str); 7302 if (gmask & HARD_FRAME_POINTER_MASK) 7303 { 7304 fprintf (file, "\tst\t%s, [%s+%d]\n\tsub\t%s, %d, %s\t%s# set up frame pointer\n", 7305 fp_str, sp_str, (int) offset, sp_str, (int) -size1, 7306 fp_str, ASM_COMMENT_START); 7307 offset += 4; 7308 } 7309 } 7310 else 7311 { 7312 fprintf (file, "\tset\t"); 7313 fprintf (file, HOST_WIDE_INT_PRINT_DEC, size1); 7314 fprintf (file, ", %s\n\tsub\t%s, %s, %s\n", 7315 t1_str, sp_str, t1_str, sp_str); 7316 if (gmask & HARD_FRAME_POINTER_MASK) 7317 { 7318 fprintf (file, "\tst\t%s, [%s+%d]\n\tadd\t%s, %s, %s\t%s# set up frame pointer\n", 7319 fp_str, sp_str, (int) offset, sp_str, t1_str, 7320 fp_str, ASM_COMMENT_START); 7321 offset += 4; 7322 } 7323 } 7324 if (dwarf2out_do_frame ()) 7325 { 7326 char *l = dwarf2out_cfi_label (); 7327 if (gmask & HARD_FRAME_POINTER_MASK) 7328 { 7329 dwarf2out_reg_save (l, HARD_FRAME_POINTER_REGNUM, 7330 offset - 4 - size1); 7331 dwarf2out_def_cfa (l, HARD_FRAME_POINTER_REGNUM, 0); 7332 } 7333 else 7334 dwarf2out_def_cfa (l, STACK_POINTER_REGNUM, size1); 7335 } 7336 if (gmask & RETURN_ADDR_MASK) 7337 { 7338 fprintf (file, "\tst\t%s, [%s+%d]\n", 7339 reg_names[RETURN_ADDR_REGNUM], sp_str, (int) offset); 7340 if (dwarf2out_do_frame ()) 7341 /* offset - size1 == reg_offset - size 7342 if reg_offset were updated above like offset. */ 7343 dwarf2out_return_save ("", offset - size1); 7344 offset += 4; 7345 } 7346 sparc_flat_save_restore (file, sp_str, offset, 7347 gmask & ~(HARD_FRAME_POINTER_MASK | RETURN_ADDR_MASK), 7348 current_frame_info.fmask, 7349 "st", "std", -size1); 7350 fprintf (file, "\tset\t"); 7351 fprintf (file, HOST_WIDE_INT_PRINT_DEC, size - size1); 7352 fprintf (file, ", %s\n\tsub\t%s, %s, %s\n", 7353 t1_str, sp_str, t1_str, sp_str); 7354 if (dwarf2out_do_frame ()) 7355 if (! (gmask & HARD_FRAME_POINTER_MASK)) 7356 dwarf2out_def_cfa ("", STACK_POINTER_REGNUM, size); 7357 } 7358 } 7359 7360 fprintf (file, "\t%s#PROLOGUE# 1\n", ASM_COMMENT_START); 7361} 7362 7363/* Do any necessary cleanup after a function to restore stack, frame, 7364 and regs. */ 7365 7366static void 7367sparc_flat_function_epilogue (file, size) 7368 FILE *file; 7369 HOST_WIDE_INT size; 7370{ 7371 rtx epilogue_delay = current_function_epilogue_delay_list; 7372 int noepilogue = FALSE; 7373 7374 /* This is only for the human reader. */ 7375 fprintf (file, "\t%s#EPILOGUE#\n", ASM_COMMENT_START); 7376 7377 /* The epilogue does not depend on any registers, but the stack 7378 registers, so we assume that if we have 1 pending nop, it can be 7379 ignored, and 2 it must be filled (2 nops occur for integer 7380 multiply and divide). */ 7381 7382 size = SPARC_STACK_ALIGN (size); 7383 size = (!current_frame_info.initialized 7384 ? sparc_flat_compute_frame_size (size) 7385 : current_frame_info.total_size); 7386 7387 if (size == 0 && epilogue_delay == 0) 7388 { 7389 rtx insn = get_last_insn (); 7390 7391 /* If the last insn was a BARRIER, we don't have to write any code 7392 because a jump (aka return) was put there. */ 7393 if (GET_CODE (insn) == NOTE) 7394 insn = prev_nonnote_insn (insn); 7395 if (insn && GET_CODE (insn) == BARRIER) 7396 noepilogue = TRUE; 7397 } 7398 7399 if (!noepilogue) 7400 { 7401 unsigned HOST_WIDE_INT reg_offset = current_frame_info.reg_offset; 7402 unsigned HOST_WIDE_INT size1; 7403 const char *const sp_str = reg_names[STACK_POINTER_REGNUM]; 7404 const char *const fp_str = reg_names[HARD_FRAME_POINTER_REGNUM]; 7405 static const char *const t1_str = "%g1"; 7406 7407 /* In the reload sequence, we don't need to fill the load delay 7408 slots for most of the loads, also see if we can fill the final 7409 delay slot if not otherwise filled by the reload sequence. */ 7410 7411 if (size > 4095) 7412 { 7413 fprintf (file, "\tset\t"); 7414 fprintf (file, HOST_WIDE_INT_PRINT_DEC, size); 7415 fprintf (file, ", %s\n", t1_str); 7416 } 7417 7418 if (frame_pointer_needed) 7419 { 7420 if (size > 4095) 7421 fprintf (file,"\tsub\t%s, %s, %s\t\t%s# sp not trusted here\n", 7422 fp_str, t1_str, sp_str, ASM_COMMENT_START); 7423 else 7424 fprintf (file,"\tsub\t%s, %d, %s\t\t%s# sp not trusted here\n", 7425 fp_str, (int) size, sp_str, ASM_COMMENT_START); 7426 } 7427 7428 /* Is the entire register save area offsettable from %sp? */ 7429 if (reg_offset < 4096 - 64 * (unsigned) UNITS_PER_WORD) 7430 { 7431 size1 = 0; 7432 } 7433 else 7434 { 7435 /* Restore %sp in two steps, but make sure there is always a 7436 64 byte register save area, and %sp is properly aligned. */ 7437 /* Amount to increment %sp by, the first time. */ 7438 size1 = ((reg_offset - 64 - 16) + 15) & -16; 7439 /* Offset to register save area from %sp. */ 7440 reg_offset = size1 - reg_offset; 7441 7442 fprintf (file, "\tset\t"); 7443 fprintf (file, HOST_WIDE_INT_PRINT_DEC, size1); 7444 fprintf (file, ", %s\n\tadd\t%s, %s, %s\n", 7445 t1_str, sp_str, t1_str, sp_str); 7446 } 7447 7448 /* We must restore the frame pointer and return address reg first 7449 because they are treated specially by the prologue output code. */ 7450 if (current_frame_info.gmask & HARD_FRAME_POINTER_MASK) 7451 { 7452 fprintf (file, "\tld\t[%s+%d], %s\n", 7453 sp_str, (int) reg_offset, fp_str); 7454 reg_offset += 4; 7455 } 7456 if (current_frame_info.gmask & RETURN_ADDR_MASK) 7457 { 7458 fprintf (file, "\tld\t[%s+%d], %s\n", 7459 sp_str, (int) reg_offset, reg_names[RETURN_ADDR_REGNUM]); 7460 reg_offset += 4; 7461 } 7462 7463 /* Restore any remaining saved registers. */ 7464 sparc_flat_save_restore (file, sp_str, reg_offset, 7465 current_frame_info.gmask & ~(HARD_FRAME_POINTER_MASK | RETURN_ADDR_MASK), 7466 current_frame_info.fmask, 7467 "ld", "ldd", 0); 7468 7469 /* If we had to increment %sp in two steps, record it so the second 7470 restoration in the epilogue finishes up. */ 7471 if (size1 > 0) 7472 { 7473 size -= size1; 7474 if (size > 4095) 7475 { 7476 fprintf (file, "\tset\t"); 7477 fprintf (file, HOST_WIDE_INT_PRINT_DEC, size); 7478 fprintf (file, ", %s\n", t1_str); 7479 } 7480 } 7481 7482 if (current_function_returns_struct) 7483 fprintf (file, "\tjmp\t%%o7+12\n"); 7484 else 7485 fprintf (file, "\tretl\n"); 7486 7487 /* If the only register saved is the return address, we need a 7488 nop, unless we have an instruction to put into it. Otherwise 7489 we don't since reloading multiple registers doesn't reference 7490 the register being loaded. */ 7491 7492 if (epilogue_delay) 7493 { 7494 if (size) 7495 abort (); 7496 final_scan_insn (XEXP (epilogue_delay, 0), file, 1, -2, 1); 7497 } 7498 7499 else if (size > 4095) 7500 fprintf (file, "\tadd\t%s, %s, %s\n", sp_str, t1_str, sp_str); 7501 7502 else if (size > 0) 7503 fprintf (file, "\tadd\t%s, %d, %s\n", sp_str, (int) size, sp_str); 7504 7505 else 7506 fprintf (file, "\tnop\n"); 7507 } 7508 7509 /* Reset state info for each function. */ 7510 current_frame_info = zero_frame_info; 7511 7512 sparc_output_deferred_case_vectors (); 7513} 7514 7515/* Define the number of delay slots needed for the function epilogue. 7516 7517 On the sparc, we need a slot if either no stack has been allocated, 7518 or the only register saved is the return register. */ 7519 7520int 7521sparc_flat_epilogue_delay_slots () 7522{ 7523 if (!current_frame_info.initialized) 7524 (void) sparc_flat_compute_frame_size (get_frame_size ()); 7525 7526 if (current_frame_info.total_size == 0) 7527 return 1; 7528 7529 return 0; 7530} 7531 7532/* Return true if TRIAL is a valid insn for the epilogue delay slot. 7533 Any single length instruction which doesn't reference the stack or frame 7534 pointer is OK. */ 7535 7536int 7537sparc_flat_eligible_for_epilogue_delay (trial, slot) 7538 rtx trial; 7539 int slot ATTRIBUTE_UNUSED; 7540{ 7541 rtx pat = PATTERN (trial); 7542 7543 if (get_attr_length (trial) != 1) 7544 return 0; 7545 7546 if (! reg_mentioned_p (stack_pointer_rtx, pat) 7547 && ! reg_mentioned_p (frame_pointer_rtx, pat)) 7548 return 1; 7549 7550 return 0; 7551} 7552 7553/* Adjust the cost of a scheduling dependency. Return the new cost of 7554 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */ 7555 7556static int 7557supersparc_adjust_cost (insn, link, dep_insn, cost) 7558 rtx insn; 7559 rtx link; 7560 rtx dep_insn; 7561 int cost; 7562{ 7563 enum attr_type insn_type; 7564 7565 if (! recog_memoized (insn)) 7566 return 0; 7567 7568 insn_type = get_attr_type (insn); 7569 7570 if (REG_NOTE_KIND (link) == 0) 7571 { 7572 /* Data dependency; DEP_INSN writes a register that INSN reads some 7573 cycles later. */ 7574 7575 /* if a load, then the dependence must be on the memory address; 7576 add an extra "cycle". Note that the cost could be two cycles 7577 if the reg was written late in an instruction group; we ca not tell 7578 here. */ 7579 if (insn_type == TYPE_LOAD || insn_type == TYPE_FPLOAD) 7580 return cost + 3; 7581 7582 /* Get the delay only if the address of the store is the dependence. */ 7583 if (insn_type == TYPE_STORE || insn_type == TYPE_FPSTORE) 7584 { 7585 rtx pat = PATTERN(insn); 7586 rtx dep_pat = PATTERN (dep_insn); 7587 7588 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET) 7589 return cost; /* This should not happen! */ 7590 7591 /* The dependency between the two instructions was on the data that 7592 is being stored. Assume that this implies that the address of the 7593 store is not dependent. */ 7594 if (rtx_equal_p (SET_DEST (dep_pat), SET_SRC (pat))) 7595 return cost; 7596 7597 return cost + 3; /* An approximation. */ 7598 } 7599 7600 /* A shift instruction cannot receive its data from an instruction 7601 in the same cycle; add a one cycle penalty. */ 7602 if (insn_type == TYPE_SHIFT) 7603 return cost + 3; /* Split before cascade into shift. */ 7604 } 7605 else 7606 { 7607 /* Anti- or output- dependency; DEP_INSN reads/writes a register that 7608 INSN writes some cycles later. */ 7609 7610 /* These are only significant for the fpu unit; writing a fp reg before 7611 the fpu has finished with it stalls the processor. */ 7612 7613 /* Reusing an integer register causes no problems. */ 7614 if (insn_type == TYPE_IALU || insn_type == TYPE_SHIFT) 7615 return 0; 7616 } 7617 7618 return cost; 7619} 7620 7621static int 7622hypersparc_adjust_cost (insn, link, dep_insn, cost) 7623 rtx insn; 7624 rtx link; 7625 rtx dep_insn; 7626 int cost; 7627{ 7628 enum attr_type insn_type, dep_type; 7629 rtx pat = PATTERN(insn); 7630 rtx dep_pat = PATTERN (dep_insn); 7631 7632 if (recog_memoized (insn) < 0 || recog_memoized (dep_insn) < 0) 7633 return cost; 7634 7635 insn_type = get_attr_type (insn); 7636 dep_type = get_attr_type (dep_insn); 7637 7638 switch (REG_NOTE_KIND (link)) 7639 { 7640 case 0: 7641 /* Data dependency; DEP_INSN writes a register that INSN reads some 7642 cycles later. */ 7643 7644 switch (insn_type) 7645 { 7646 case TYPE_STORE: 7647 case TYPE_FPSTORE: 7648 /* Get the delay iff the address of the store is the dependence. */ 7649 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET) 7650 return cost; 7651 7652 if (rtx_equal_p (SET_DEST (dep_pat), SET_SRC (pat))) 7653 return cost; 7654 return cost + 3; 7655 7656 case TYPE_LOAD: 7657 case TYPE_SLOAD: 7658 case TYPE_FPLOAD: 7659 /* If a load, then the dependence must be on the memory address. If 7660 the addresses aren't equal, then it might be a false dependency */ 7661 if (dep_type == TYPE_STORE || dep_type == TYPE_FPSTORE) 7662 { 7663 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET 7664 || GET_CODE (SET_DEST (dep_pat)) != MEM 7665 || GET_CODE (SET_SRC (pat)) != MEM 7666 || ! rtx_equal_p (XEXP (SET_DEST (dep_pat), 0), 7667 XEXP (SET_SRC (pat), 0))) 7668 return cost + 2; 7669 7670 return cost + 8; 7671 } 7672 break; 7673 7674 case TYPE_BRANCH: 7675 /* Compare to branch latency is 0. There is no benefit from 7676 separating compare and branch. */ 7677 if (dep_type == TYPE_COMPARE) 7678 return 0; 7679 /* Floating point compare to branch latency is less than 7680 compare to conditional move. */ 7681 if (dep_type == TYPE_FPCMP) 7682 return cost - 1; 7683 break; 7684 default: 7685 break; 7686 } 7687 break; 7688 7689 case REG_DEP_ANTI: 7690 /* Anti-dependencies only penalize the fpu unit. */ 7691 if (insn_type == TYPE_IALU || insn_type == TYPE_SHIFT) 7692 return 0; 7693 break; 7694 7695 default: 7696 break; 7697 } 7698 7699 return cost; 7700} 7701 7702static int 7703sparc_adjust_cost(insn, link, dep, cost) 7704 rtx insn; 7705 rtx link; 7706 rtx dep; 7707 int cost; 7708{ 7709 switch (sparc_cpu) 7710 { 7711 case PROCESSOR_SUPERSPARC: 7712 cost = supersparc_adjust_cost (insn, link, dep, cost); 7713 break; 7714 case PROCESSOR_HYPERSPARC: 7715 case PROCESSOR_SPARCLITE86X: 7716 cost = hypersparc_adjust_cost (insn, link, dep, cost); 7717 break; 7718 default: 7719 break; 7720 } 7721 return cost; 7722} 7723 7724static void 7725sparc_sched_init (dump, sched_verbose, max_ready) 7726 FILE *dump ATTRIBUTE_UNUSED; 7727 int sched_verbose ATTRIBUTE_UNUSED; 7728 int max_ready ATTRIBUTE_UNUSED; 7729{ 7730} 7731 7732static int 7733sparc_use_dfa_pipeline_interface () 7734{ 7735 if ((1 << sparc_cpu) & 7736 ((1 << PROCESSOR_ULTRASPARC) | (1 << PROCESSOR_CYPRESS) | 7737 (1 << PROCESSOR_SUPERSPARC) | (1 << PROCESSOR_HYPERSPARC) | 7738 (1 << PROCESSOR_SPARCLITE86X) | (1 << PROCESSOR_TSC701) | 7739 (1 << PROCESSOR_ULTRASPARC3))) 7740 return 1; 7741 return 0; 7742} 7743 7744static int 7745sparc_use_sched_lookahead () 7746{ 7747 if (sparc_cpu == PROCESSOR_ULTRASPARC 7748 || sparc_cpu == PROCESSOR_ULTRASPARC3) 7749 return 4; 7750 if ((1 << sparc_cpu) & 7751 ((1 << PROCESSOR_SUPERSPARC) | (1 << PROCESSOR_HYPERSPARC) | 7752 (1 << PROCESSOR_SPARCLITE86X))) 7753 return 3; 7754 return 0; 7755} 7756 7757static int 7758sparc_issue_rate () 7759{ 7760 switch (sparc_cpu) 7761 { 7762 default: 7763 return 1; 7764 case PROCESSOR_V9: 7765 /* Assume V9 processors are capable of at least dual-issue. */ 7766 return 2; 7767 case PROCESSOR_SUPERSPARC: 7768 return 3; 7769 case PROCESSOR_HYPERSPARC: 7770 case PROCESSOR_SPARCLITE86X: 7771 return 2; 7772 case PROCESSOR_ULTRASPARC: 7773 case PROCESSOR_ULTRASPARC3: 7774 return 4; 7775 } 7776} 7777 7778static int 7779set_extends (insn) 7780 rtx insn; 7781{ 7782 register rtx pat = PATTERN (insn); 7783 7784 switch (GET_CODE (SET_SRC (pat))) 7785 { 7786 /* Load and some shift instructions zero extend. */ 7787 case MEM: 7788 case ZERO_EXTEND: 7789 /* sethi clears the high bits */ 7790 case HIGH: 7791 /* LO_SUM is used with sethi. sethi cleared the high 7792 bits and the values used with lo_sum are positive */ 7793 case LO_SUM: 7794 /* Store flag stores 0 or 1 */ 7795 case LT: case LTU: 7796 case GT: case GTU: 7797 case LE: case LEU: 7798 case GE: case GEU: 7799 case EQ: 7800 case NE: 7801 return 1; 7802 case AND: 7803 { 7804 rtx op0 = XEXP (SET_SRC (pat), 0); 7805 rtx op1 = XEXP (SET_SRC (pat), 1); 7806 if (GET_CODE (op1) == CONST_INT) 7807 return INTVAL (op1) >= 0; 7808 if (GET_CODE (op0) != REG) 7809 return 0; 7810 if (sparc_check_64 (op0, insn) == 1) 7811 return 1; 7812 return (GET_CODE (op1) == REG && sparc_check_64 (op1, insn) == 1); 7813 } 7814 case IOR: 7815 case XOR: 7816 { 7817 rtx op0 = XEXP (SET_SRC (pat), 0); 7818 rtx op1 = XEXP (SET_SRC (pat), 1); 7819 if (GET_CODE (op0) != REG || sparc_check_64 (op0, insn) <= 0) 7820 return 0; 7821 if (GET_CODE (op1) == CONST_INT) 7822 return INTVAL (op1) >= 0; 7823 return (GET_CODE (op1) == REG && sparc_check_64 (op1, insn) == 1); 7824 } 7825 case LSHIFTRT: 7826 return GET_MODE (SET_SRC (pat)) == SImode; 7827 /* Positive integers leave the high bits zero. */ 7828 case CONST_DOUBLE: 7829 return ! (CONST_DOUBLE_LOW (SET_SRC (pat)) & 0x80000000); 7830 case CONST_INT: 7831 return ! (INTVAL (SET_SRC (pat)) & 0x80000000); 7832 case ASHIFTRT: 7833 case SIGN_EXTEND: 7834 return - (GET_MODE (SET_SRC (pat)) == SImode); 7835 case REG: 7836 return sparc_check_64 (SET_SRC (pat), insn); 7837 default: 7838 return 0; 7839 } 7840} 7841 7842/* We _ought_ to have only one kind per function, but... */ 7843static GTY(()) rtx sparc_addr_diff_list; 7844static GTY(()) rtx sparc_addr_list; 7845 7846void 7847sparc_defer_case_vector (lab, vec, diff) 7848 rtx lab, vec; 7849 int diff; 7850{ 7851 vec = gen_rtx_EXPR_LIST (VOIDmode, lab, vec); 7852 if (diff) 7853 sparc_addr_diff_list 7854 = gen_rtx_EXPR_LIST (VOIDmode, vec, sparc_addr_diff_list); 7855 else 7856 sparc_addr_list = gen_rtx_EXPR_LIST (VOIDmode, vec, sparc_addr_list); 7857} 7858 7859static void 7860sparc_output_addr_vec (vec) 7861 rtx vec; 7862{ 7863 rtx lab = XEXP (vec, 0), body = XEXP (vec, 1); 7864 int idx, vlen = XVECLEN (body, 0); 7865 7866#ifdef ASM_OUTPUT_ADDR_VEC_START 7867 ASM_OUTPUT_ADDR_VEC_START (asm_out_file); 7868#endif 7869 7870#ifdef ASM_OUTPUT_CASE_LABEL 7871 ASM_OUTPUT_CASE_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (lab), 7872 NEXT_INSN (lab)); 7873#else 7874 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (lab)); 7875#endif 7876 7877 for (idx = 0; idx < vlen; idx++) 7878 { 7879 ASM_OUTPUT_ADDR_VEC_ELT 7880 (asm_out_file, CODE_LABEL_NUMBER (XEXP (XVECEXP (body, 0, idx), 0))); 7881 } 7882 7883#ifdef ASM_OUTPUT_ADDR_VEC_END 7884 ASM_OUTPUT_ADDR_VEC_END (asm_out_file); 7885#endif 7886} 7887 7888static void 7889sparc_output_addr_diff_vec (vec) 7890 rtx vec; 7891{ 7892 rtx lab = XEXP (vec, 0), body = XEXP (vec, 1); 7893 rtx base = XEXP (XEXP (body, 0), 0); 7894 int idx, vlen = XVECLEN (body, 1); 7895 7896#ifdef ASM_OUTPUT_ADDR_VEC_START 7897 ASM_OUTPUT_ADDR_VEC_START (asm_out_file); 7898#endif 7899 7900#ifdef ASM_OUTPUT_CASE_LABEL 7901 ASM_OUTPUT_CASE_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (lab), 7902 NEXT_INSN (lab)); 7903#else 7904 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (lab)); 7905#endif 7906 7907 for (idx = 0; idx < vlen; idx++) 7908 { 7909 ASM_OUTPUT_ADDR_DIFF_ELT 7910 (asm_out_file, 7911 body, 7912 CODE_LABEL_NUMBER (XEXP (XVECEXP (body, 1, idx), 0)), 7913 CODE_LABEL_NUMBER (base)); 7914 } 7915 7916#ifdef ASM_OUTPUT_ADDR_VEC_END 7917 ASM_OUTPUT_ADDR_VEC_END (asm_out_file); 7918#endif 7919} 7920 7921static void 7922sparc_output_deferred_case_vectors () 7923{ 7924 rtx t; 7925 int align; 7926 7927 if (sparc_addr_list == NULL_RTX 7928 && sparc_addr_diff_list == NULL_RTX) 7929 return; 7930 7931 /* Align to cache line in the function's code section. */ 7932 function_section (current_function_decl); 7933 7934 align = floor_log2 (FUNCTION_BOUNDARY / BITS_PER_UNIT); 7935 if (align > 0) 7936 ASM_OUTPUT_ALIGN (asm_out_file, align); 7937 7938 for (t = sparc_addr_list; t ; t = XEXP (t, 1)) 7939 sparc_output_addr_vec (XEXP (t, 0)); 7940 for (t = sparc_addr_diff_list; t ; t = XEXP (t, 1)) 7941 sparc_output_addr_diff_vec (XEXP (t, 0)); 7942 7943 sparc_addr_list = sparc_addr_diff_list = NULL_RTX; 7944} 7945 7946/* Return 0 if the high 32 bits of X (the low word of X, if DImode) are 7947 unknown. Return 1 if the high bits are zero, -1 if the register is 7948 sign extended. */ 7949int 7950sparc_check_64 (x, insn) 7951 rtx x, insn; 7952{ 7953 /* If a register is set only once it is safe to ignore insns this 7954 code does not know how to handle. The loop will either recognize 7955 the single set and return the correct value or fail to recognize 7956 it and return 0. */ 7957 int set_once = 0; 7958 rtx y = x; 7959 7960 if (GET_CODE (x) != REG) 7961 abort (); 7962 7963 if (GET_MODE (x) == DImode) 7964 y = gen_rtx_REG (SImode, REGNO (x) + WORDS_BIG_ENDIAN); 7965 7966 if (flag_expensive_optimizations 7967 && REG_N_SETS (REGNO (y)) == 1) 7968 set_once = 1; 7969 7970 if (insn == 0) 7971 { 7972 if (set_once) 7973 insn = get_last_insn_anywhere (); 7974 else 7975 return 0; 7976 } 7977 7978 while ((insn = PREV_INSN (insn))) 7979 { 7980 switch (GET_CODE (insn)) 7981 { 7982 case JUMP_INSN: 7983 case NOTE: 7984 break; 7985 case CODE_LABEL: 7986 case CALL_INSN: 7987 default: 7988 if (! set_once) 7989 return 0; 7990 break; 7991 case INSN: 7992 { 7993 rtx pat = PATTERN (insn); 7994 if (GET_CODE (pat) != SET) 7995 return 0; 7996 if (rtx_equal_p (x, SET_DEST (pat))) 7997 return set_extends (insn); 7998 if (y && rtx_equal_p (y, SET_DEST (pat))) 7999 return set_extends (insn); 8000 if (reg_overlap_mentioned_p (SET_DEST (pat), y)) 8001 return 0; 8002 } 8003 } 8004 } 8005 return 0; 8006} 8007 8008/* Returns assembly code to perform a DImode shift using 8009 a 64-bit global or out register on SPARC-V8+. */ 8010char * 8011sparc_v8plus_shift (operands, insn, opcode) 8012 rtx *operands; 8013 rtx insn; 8014 const char *opcode; 8015{ 8016 static char asm_code[60]; 8017 8018 /* The scratch register is only required when the destination 8019 register is not a 64-bit global or out register. */ 8020 if (which_alternative != 2) 8021 operands[3] = operands[0]; 8022 8023 if (GET_CODE (operands[1]) == CONST_INT) 8024 { 8025 output_asm_insn ("mov\t%1, %3", operands); 8026 } 8027 else 8028 { 8029 output_asm_insn ("sllx\t%H1, 32, %3", operands); 8030 if (sparc_check_64 (operands[1], insn) <= 0) 8031 output_asm_insn ("srl\t%L1, 0, %L1", operands); 8032 output_asm_insn ("or\t%L1, %3, %3", operands); 8033 } 8034 8035 strcpy(asm_code, opcode); 8036 8037 if (which_alternative != 2) 8038 return strcat (asm_code, "\t%0, %2, %L0\n\tsrlx\t%L0, 32, %H0"); 8039 else 8040 return strcat (asm_code, "\t%3, %2, %3\n\tsrlx\t%3, 32, %H0\n\tmov\t%3, %L0"); 8041} 8042 8043/* Output rtl to increment the profiler label LABELNO 8044 for profiling a function entry. */ 8045 8046void 8047sparc_profile_hook (labelno) 8048 int labelno; 8049{ 8050 char buf[32]; 8051 rtx lab, fun; 8052 8053 ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno); 8054 lab = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf)); 8055 fun = gen_rtx_SYMBOL_REF (Pmode, MCOUNT_FUNCTION); 8056 8057 emit_library_call (fun, LCT_NORMAL, VOIDmode, 1, lab, Pmode); 8058} 8059 8060#ifdef OBJECT_FORMAT_ELF 8061static void 8062sparc_elf_asm_named_section (name, flags) 8063 const char *name; 8064 unsigned int flags; 8065{ 8066 if (flags & SECTION_MERGE) 8067 { 8068 /* entsize cannot be expressed in this section attributes 8069 encoding style. */ 8070 default_elf_asm_named_section (name, flags); 8071 return; 8072 } 8073 8074 fprintf (asm_out_file, "\t.section\t\"%s\"", name); 8075 8076 if (!(flags & SECTION_DEBUG)) 8077 fputs (",#alloc", asm_out_file); 8078 if (flags & SECTION_WRITE) 8079 fputs (",#write", asm_out_file); 8080 if (flags & SECTION_CODE) 8081 fputs (",#execinstr", asm_out_file); 8082 8083 /* ??? Handle SECTION_BSS. */ 8084 8085 fputc ('\n', asm_out_file); 8086} 8087#endif /* OBJECT_FORMAT_ELF */ 8088 8089/* ??? Similar to the standard section selection, but force reloc-y-ness 8090 if SUNOS4_SHARED_LIBRARIES. Unclear why this helps (as opposed to 8091 pretending PIC always on), but that's what the old code did. */ 8092 8093static void 8094sparc_aout_select_section (t, reloc, align) 8095 tree t; 8096 int reloc; 8097 unsigned HOST_WIDE_INT align; 8098{ 8099 default_select_section (t, reloc | SUNOS4_SHARED_LIBRARIES, align); 8100} 8101 8102/* Use text section for a constant unless we need more alignment than 8103 that offers. */ 8104 8105static void 8106sparc_aout_select_rtx_section (mode, x, align) 8107 enum machine_mode mode; 8108 rtx x; 8109 unsigned HOST_WIDE_INT align; 8110{ 8111 if (align <= MAX_TEXT_ALIGN 8112 && ! (flag_pic && (symbolic_operand (x, mode) 8113 || SUNOS4_SHARED_LIBRARIES))) 8114 readonly_data_section (); 8115 else 8116 data_section (); 8117} 8118 8119int 8120sparc_extra_constraint_check (op, c, strict) 8121 rtx op; 8122 int c; 8123 int strict; 8124{ 8125 int reload_ok_mem; 8126 8127 if (TARGET_ARCH64 8128 && (c == 'T' || c == 'U')) 8129 return 0; 8130 8131 switch (c) 8132 { 8133 case 'Q': 8134 return fp_sethi_p (op); 8135 8136 case 'R': 8137 return fp_mov_p (op); 8138 8139 case 'S': 8140 return fp_high_losum_p (op); 8141 8142 case 'U': 8143 if (! strict 8144 || (GET_CODE (op) == REG 8145 && (REGNO (op) < FIRST_PSEUDO_REGISTER 8146 || reg_renumber[REGNO (op)] >= 0))) 8147 return register_ok_for_ldd (op); 8148 8149 return 0; 8150 8151 case 'W': 8152 case 'T': 8153 break; 8154 8155 default: 8156 return 0; 8157 } 8158 8159 /* Our memory extra constraints have to emulate the 8160 behavior of 'm' and 'o' in order for reload to work 8161 correctly. */ 8162 if (GET_CODE (op) == MEM) 8163 { 8164 reload_ok_mem = 0; 8165 if ((TARGET_ARCH64 || mem_min_alignment (op, 8)) 8166 && (! strict 8167 || strict_memory_address_p (Pmode, XEXP (op, 0)))) 8168 reload_ok_mem = 1; 8169 } 8170 else 8171 { 8172 reload_ok_mem = (reload_in_progress 8173 && GET_CODE (op) == REG 8174 && REGNO (op) >= FIRST_PSEUDO_REGISTER 8175 && reg_renumber [REGNO (op)] < 0); 8176 } 8177 8178 return reload_ok_mem; 8179} 8180 8181/* ??? This duplicates information provided to the compiler by the 8182 ??? scheduler description. Some day, teach genautomata to output 8183 ??? the latencies and then CSE will just use that. */ 8184 8185int 8186sparc_rtx_costs (x, code, outer_code) 8187 rtx x; 8188 enum rtx_code code, outer_code; 8189{ 8190 switch (code) 8191 { 8192 case PLUS: case MINUS: case ABS: case NEG: 8193 case FLOAT: case UNSIGNED_FLOAT: 8194 case FIX: case UNSIGNED_FIX: 8195 case FLOAT_EXTEND: case FLOAT_TRUNCATE: 8196 if (FLOAT_MODE_P (GET_MODE (x))) 8197 { 8198 switch (sparc_cpu) 8199 { 8200 case PROCESSOR_ULTRASPARC: 8201 case PROCESSOR_ULTRASPARC3: 8202 return COSTS_N_INSNS (4); 8203 8204 case PROCESSOR_SUPERSPARC: 8205 return COSTS_N_INSNS (3); 8206 8207 case PROCESSOR_CYPRESS: 8208 return COSTS_N_INSNS (5); 8209 8210 case PROCESSOR_HYPERSPARC: 8211 case PROCESSOR_SPARCLITE86X: 8212 default: 8213 return COSTS_N_INSNS (1); 8214 } 8215 } 8216 8217 return COSTS_N_INSNS (1); 8218 8219 case SQRT: 8220 switch (sparc_cpu) 8221 { 8222 case PROCESSOR_ULTRASPARC: 8223 if (GET_MODE (x) == SFmode) 8224 return COSTS_N_INSNS (13); 8225 else 8226 return COSTS_N_INSNS (23); 8227 8228 case PROCESSOR_ULTRASPARC3: 8229 if (GET_MODE (x) == SFmode) 8230 return COSTS_N_INSNS (20); 8231 else 8232 return COSTS_N_INSNS (29); 8233 8234 case PROCESSOR_SUPERSPARC: 8235 return COSTS_N_INSNS (12); 8236 8237 case PROCESSOR_CYPRESS: 8238 return COSTS_N_INSNS (63); 8239 8240 case PROCESSOR_HYPERSPARC: 8241 case PROCESSOR_SPARCLITE86X: 8242 return COSTS_N_INSNS (17); 8243 8244 default: 8245 return COSTS_N_INSNS (30); 8246 } 8247 8248 case COMPARE: 8249 if (FLOAT_MODE_P (GET_MODE (x))) 8250 { 8251 switch (sparc_cpu) 8252 { 8253 case PROCESSOR_ULTRASPARC: 8254 case PROCESSOR_ULTRASPARC3: 8255 return COSTS_N_INSNS (1); 8256 8257 case PROCESSOR_SUPERSPARC: 8258 return COSTS_N_INSNS (3); 8259 8260 case PROCESSOR_CYPRESS: 8261 return COSTS_N_INSNS (5); 8262 8263 case PROCESSOR_HYPERSPARC: 8264 case PROCESSOR_SPARCLITE86X: 8265 default: 8266 return COSTS_N_INSNS (1); 8267 } 8268 } 8269 8270 /* ??? Maybe mark integer compares as zero cost on 8271 ??? all UltraSPARC processors because the result 8272 ??? can be bypassed to a branch in the same group. */ 8273 8274 return COSTS_N_INSNS (1); 8275 8276 case MULT: 8277 if (FLOAT_MODE_P (GET_MODE (x))) 8278 { 8279 switch (sparc_cpu) 8280 { 8281 case PROCESSOR_ULTRASPARC: 8282 case PROCESSOR_ULTRASPARC3: 8283 return COSTS_N_INSNS (4); 8284 8285 case PROCESSOR_SUPERSPARC: 8286 return COSTS_N_INSNS (3); 8287 8288 case PROCESSOR_CYPRESS: 8289 return COSTS_N_INSNS (7); 8290 8291 case PROCESSOR_HYPERSPARC: 8292 case PROCESSOR_SPARCLITE86X: 8293 return COSTS_N_INSNS (1); 8294 8295 default: 8296 return COSTS_N_INSNS (5); 8297 } 8298 } 8299 8300 /* The latency is actually variable for Ultra-I/II 8301 And if one of the inputs have a known constant 8302 value, we could calculate this precisely. 8303 8304 However, for that to be useful we would need to 8305 add some machine description changes which would 8306 make sure small constants ended up in rs1 of the 8307 multiply instruction. This is because the multiply 8308 latency is determined by the number of clear (or 8309 set if the value is negative) bits starting from 8310 the most significant bit of the first input. 8311 8312 The algorithm for computing num_cycles of a multiply 8313 on Ultra-I/II is: 8314 8315 if (rs1 < 0) 8316 highest_bit = highest_clear_bit(rs1); 8317 else 8318 highest_bit = highest_set_bit(rs1); 8319 if (num_bits < 3) 8320 highest_bit = 3; 8321 num_cycles = 4 + ((highest_bit - 3) / 2); 8322 8323 If we did that we would have to also consider register 8324 allocation issues that would result from forcing such 8325 a value into a register. 8326 8327 There are other similar tricks we could play if we 8328 knew, for example, that one input was an array index. 8329 8330 Since we do not play any such tricks currently the 8331 safest thing to do is report the worst case latency. */ 8332 if (sparc_cpu == PROCESSOR_ULTRASPARC) 8333 return (GET_MODE (x) == DImode ? 8334 COSTS_N_INSNS (34) : COSTS_N_INSNS (19)); 8335 8336 /* Multiply latency on Ultra-III, fortunately, is constant. */ 8337 if (sparc_cpu == PROCESSOR_ULTRASPARC3) 8338 return COSTS_N_INSNS (6); 8339 8340 if (sparc_cpu == PROCESSOR_HYPERSPARC 8341 || sparc_cpu == PROCESSOR_SPARCLITE86X) 8342 return COSTS_N_INSNS (17); 8343 8344 return (TARGET_HARD_MUL 8345 ? COSTS_N_INSNS (5) 8346 : COSTS_N_INSNS (25)); 8347 8348 case DIV: 8349 case UDIV: 8350 case MOD: 8351 case UMOD: 8352 if (FLOAT_MODE_P (GET_MODE (x))) 8353 { 8354 switch (sparc_cpu) 8355 { 8356 case PROCESSOR_ULTRASPARC: 8357 if (GET_MODE (x) == SFmode) 8358 return COSTS_N_INSNS (13); 8359 else 8360 return COSTS_N_INSNS (23); 8361 8362 case PROCESSOR_ULTRASPARC3: 8363 if (GET_MODE (x) == SFmode) 8364 return COSTS_N_INSNS (17); 8365 else 8366 return COSTS_N_INSNS (20); 8367 8368 case PROCESSOR_SUPERSPARC: 8369 if (GET_MODE (x) == SFmode) 8370 return COSTS_N_INSNS (6); 8371 else 8372 return COSTS_N_INSNS (9); 8373 8374 case PROCESSOR_HYPERSPARC: 8375 case PROCESSOR_SPARCLITE86X: 8376 if (GET_MODE (x) == SFmode) 8377 return COSTS_N_INSNS (8); 8378 else 8379 return COSTS_N_INSNS (12); 8380 8381 default: 8382 return COSTS_N_INSNS (7); 8383 } 8384 } 8385 8386 if (sparc_cpu == PROCESSOR_ULTRASPARC) 8387 return (GET_MODE (x) == DImode ? 8388 COSTS_N_INSNS (68) : COSTS_N_INSNS (37)); 8389 if (sparc_cpu == PROCESSOR_ULTRASPARC3) 8390 return (GET_MODE (x) == DImode ? 8391 COSTS_N_INSNS (71) : COSTS_N_INSNS (40)); 8392 return COSTS_N_INSNS (25); 8393 8394 case IF_THEN_ELSE: 8395 /* Conditional moves. */ 8396 switch (sparc_cpu) 8397 { 8398 case PROCESSOR_ULTRASPARC: 8399 return COSTS_N_INSNS (2); 8400 8401 case PROCESSOR_ULTRASPARC3: 8402 if (FLOAT_MODE_P (GET_MODE (x))) 8403 return COSTS_N_INSNS (3); 8404 else 8405 return COSTS_N_INSNS (2); 8406 8407 default: 8408 return COSTS_N_INSNS (1); 8409 } 8410 8411 case MEM: 8412 /* If outer-code is SIGN/ZERO extension we have to subtract 8413 out COSTS_N_INSNS (1) from whatever we return in determining 8414 the cost. */ 8415 switch (sparc_cpu) 8416 { 8417 case PROCESSOR_ULTRASPARC: 8418 if (outer_code == ZERO_EXTEND) 8419 return COSTS_N_INSNS (1); 8420 else 8421 return COSTS_N_INSNS (2); 8422 8423 case PROCESSOR_ULTRASPARC3: 8424 if (outer_code == ZERO_EXTEND) 8425 { 8426 if (GET_MODE (x) == QImode 8427 || GET_MODE (x) == HImode 8428 || outer_code == SIGN_EXTEND) 8429 return COSTS_N_INSNS (2); 8430 else 8431 return COSTS_N_INSNS (1); 8432 } 8433 else 8434 { 8435 /* This handles sign extension (3 cycles) 8436 and everything else (2 cycles). */ 8437 return COSTS_N_INSNS (2); 8438 } 8439 8440 case PROCESSOR_SUPERSPARC: 8441 if (FLOAT_MODE_P (GET_MODE (x)) 8442 || outer_code == ZERO_EXTEND 8443 || outer_code == SIGN_EXTEND) 8444 return COSTS_N_INSNS (0); 8445 else 8446 return COSTS_N_INSNS (1); 8447 8448 case PROCESSOR_TSC701: 8449 if (outer_code == ZERO_EXTEND 8450 || outer_code == SIGN_EXTEND) 8451 return COSTS_N_INSNS (2); 8452 else 8453 return COSTS_N_INSNS (3); 8454 8455 case PROCESSOR_CYPRESS: 8456 if (outer_code == ZERO_EXTEND 8457 || outer_code == SIGN_EXTEND) 8458 return COSTS_N_INSNS (1); 8459 else 8460 return COSTS_N_INSNS (2); 8461 8462 case PROCESSOR_HYPERSPARC: 8463 case PROCESSOR_SPARCLITE86X: 8464 default: 8465 if (outer_code == ZERO_EXTEND 8466 || outer_code == SIGN_EXTEND) 8467 return COSTS_N_INSNS (0); 8468 else 8469 return COSTS_N_INSNS (1); 8470 } 8471 8472 case CONST_INT: 8473 if (INTVAL (x) < 0x1000 && INTVAL (x) >= -0x1000) 8474 return 0; 8475 8476 /* fallthru */ 8477 case HIGH: 8478 return 2; 8479 8480 case CONST: 8481 case LABEL_REF: 8482 case SYMBOL_REF: 8483 return 4; 8484 8485 case CONST_DOUBLE: 8486 if (GET_MODE (x) == DImode) 8487 if ((XINT (x, 3) == 0 8488 && (unsigned) XINT (x, 2) < 0x1000) 8489 || (XINT (x, 3) == -1 8490 && XINT (x, 2) < 0 8491 && XINT (x, 2) >= -0x1000)) 8492 return 0; 8493 return 8; 8494 8495 default: 8496 abort(); 8497 }; 8498} 8499 8500/* If we are referencing a function make the SYMBOL_REF special. In 8501 the Embedded Medium/Anywhere code model, %g4 points to the data 8502 segment so we must not add it to function addresses. */ 8503 8504static void 8505sparc_encode_section_info (decl, first) 8506 tree decl; 8507 int first ATTRIBUTE_UNUSED; 8508{ 8509 if (TARGET_CM_EMBMEDANY && TREE_CODE (decl) == FUNCTION_DECL) 8510 SYMBOL_REF_FLAG (XEXP (DECL_RTL (decl), 0)) = 1; 8511} 8512 8513/* Output code to add DELTA to the first argument, and then jump to FUNCTION. 8514 Used for C++ multiple inheritance. */ 8515 8516static void 8517sparc_output_mi_thunk (file, thunk_fndecl, delta, vcall_offset, function) 8518 FILE *file; 8519 tree thunk_fndecl ATTRIBUTE_UNUSED; 8520 HOST_WIDE_INT delta; 8521 HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED; 8522 tree function; 8523{ 8524 rtx this, insn, funexp, delta_rtx, tmp; 8525 8526 reload_completed = 1; 8527 no_new_pseudos = 1; 8528 current_function_uses_only_leaf_regs = 1; 8529 8530 emit_note (NULL, NOTE_INSN_PROLOGUE_END); 8531 8532 /* Find the "this" pointer. Normally in %o0, but in ARCH64 if the function 8533 returns a structure, the structure return pointer is there instead. */ 8534 if (TARGET_ARCH64 && aggregate_value_p (TREE_TYPE (TREE_TYPE (function)))) 8535 this = gen_rtx_REG (Pmode, SPARC_INCOMING_INT_ARG_FIRST + 1); 8536 else 8537 this = gen_rtx_REG (Pmode, SPARC_INCOMING_INT_ARG_FIRST); 8538 8539 /* Add DELTA. When possible use a plain add, otherwise load it into 8540 a register first. */ 8541 delta_rtx = GEN_INT (delta); 8542 if (!SPARC_SIMM13_P (delta)) 8543 { 8544 rtx scratch = gen_rtx_REG (Pmode, 1); 8545 if (TARGET_ARCH64) 8546 sparc_emit_set_const64 (scratch, delta_rtx); 8547 else 8548 sparc_emit_set_const32 (scratch, delta_rtx); 8549 delta_rtx = scratch; 8550 } 8551 8552 tmp = gen_rtx_PLUS (Pmode, this, delta_rtx); 8553 emit_insn (gen_rtx_SET (VOIDmode, this, tmp)); 8554 8555 /* Generate a tail call to the target function. */ 8556 if (! TREE_USED (function)) 8557 { 8558 assemble_external (function); 8559 TREE_USED (function) = 1; 8560 } 8561 funexp = XEXP (DECL_RTL (function), 0); 8562 funexp = gen_rtx_MEM (FUNCTION_MODE, funexp); 8563 insn = emit_call_insn (gen_sibcall (funexp)); 8564 SIBLING_CALL_P (insn) = 1; 8565 emit_barrier (); 8566 8567 /* Run just enough of rest_of_compilation to get the insns emitted. 8568 There's not really enough bulk here to make other passes such as 8569 instruction scheduling worth while. Note that use_thunk calls 8570 assemble_start_function and assemble_end_function. */ 8571 insn = get_insns (); 8572 shorten_branches (insn); 8573 final_start_function (insn, file, 1); 8574 final (insn, file, 1, 0); 8575 final_end_function (); 8576 8577 reload_completed = 0; 8578 no_new_pseudos = 0; 8579} 8580 8581#include "gt-sparc.h" 8582